LM9800 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor General Description Features The LM9800 is a high performance integrated signal processor/digitizer for linear CCD image scanners. The LM9800 performs all the analog processing (correlated double sampling for black level and offset compensation, pixel-by-pixel gain adjust, and 8-bit analog-to-digital conversion) necessary to maximize the performance of a wide range of linear CCD sensors. The LM9800 can be digitally programmed to work with a wide variety of CCDs from different manufacturers. An internal configuration register sets CCD and sampling timing to maximize performance, simplifying the design and manufacturing processes. The LM9800 can be used with sequential or parallel output color CCDs. Coarse gain switching brings weak Blue signals up to Red/Green levels for best performance. For complementary voltage reference see the LM4041. n 2.5 million pixels/s conversion rate n Implements Correlated Double Sampling for minimum noise and offset error n Pixel-to-pixel gain correction for individual pixels maximizes dynamic range and resolution, even on “weak” pixels n Reference and signal sampling points digitally controlled in 25ns increments for maximum performance n Generates all necessary CCD clock signals n Compatible with a wide range of linear CCDs n TTL/CMOS input/output compatible Key Specifications n Resolution 8 Bits n Pixel Conversion Rate +5V ± 5% n Supply Voltage Applications n Color and Greyscale Flatbed and Sheetfed Scanners n General Purpose CCD Imaging 2.5MHz n Supply Voltage (Digital I/O) n Power Dissipation +3.3V ± 10% or +5V ± 5% 210 mW (typ) Connection Diagram DS012498-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. © 1997 National Semiconductor Corporation DS012498 www.national.com LM9800 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor September 1997 Block Diagram DS012498-3 Ordering Information Commercial (10˚C ≤ TA ≤ +70˚C) LM9800CCV www.national.com Package V52A 52 Pin Plastic Leaded Chip Carrier 2 Absolute Maximum Ratings Operating Ratings (Notes 1, 2) (Note 1) (Note 2) Operating Temperature Range LM9800CCV, LM9800CCVF VA Supply Voltage VD Supply Voltage VD(I/O) Supply Voltage |VA–VD| VA–VD(I/O) OS, REF IN Voltage Range CD0–CD6, MCLK, SYNC, SDI, SCLK, CS , RD Voltage Range Positive Supply Voltage (V+ = VA = VD = VD(I/O)) With Respect to GND = AGND = DGND = 6.5V DGND(I/O) Voltage On Any Input or Output Pin 0.3V to V+ +0.3V ± 25 mA Input Current at any pin (Note 3) ± 50 mA Package Input Current (Note 3) Package Dissipation at TA = 25˚C (Note 4) ESD Susceptibility (Note 5) Human Body Model 3000V Soldering Information Infrared, 10 seconds (Note 6) 300˚C Storage Temperature −65˚C to +150˚C TMIN ≤ TA ≤ TMAX 10˚C ≤ TA ≤ +70˚C +4.75V to +5.25V +4.75V to +5.25V +2.7V to +5.25V ≤100 mW ≥ −100 mV −0.05V to VA + 0.05V −0.05V to VD(I/O) + 0.05V Electrical Characteristics The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = +5.0VDC, VD(I/O) = +5.0V or +3.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, Rs = 25Ω. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C (Note 8) Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) CCD Source Requirements for Full Specified Accuracy and Dynamic Range (Note 12) VWHITE Maximum Peak CCD Differential Signal Range VGA Bypassed VGA On (VGAIN = 2.0V) Correctable Range of CCD Pixel-to-Pixel VWHITE Variation VRFT CCD Reset Feed Through Amplitude 1.1 V (min) 0.5 V (min) 6 dB (max) 2 V (max) ADC Characteristics Resolution with No Missing Codes 8 Bits (min) ±1 ±1 LSB (max) Monotonicity 7 bits (min) Gain Range 0 dB (min) 6 dB (max) 1.0 % (max) ±6 % (max) ILE Integral Linearity Error (Note 11) DNL Differential Non-Linearity ± 0.5 ± 0.5 LSB (max) PGA Characteristics Gain Error at any gain VGA Characteristics VGA Gain Error vs. Formula Coarse Offset Trim Characteristics Offset DAC LSB Size 1 LSB System Characteristics Full Channel Offset Error (Adjusted) Full Channel Gain Error Offset DAC, Offset Add Adjusted PGA Gain = 0 dB ±1 LSB (max) −5 % (min) +10 % (max) 20 nA (max) Reference and Analog Input Characteristics (Note 7) OS Input Capacitance OS Input Leakage Current RREF REF IN 5 Measured with OS = 2.45VDC ADC Reference Ladder (REF OUTHI to REF IN) Impedance 2 1000 Reference Voltage (Note 12) 1.225 3 pF 500 Ω (min) 2000 Ω (max) 1.19 V (min) 1.26 V (max) www.national.com DC and Logic Electrical Characteristics The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = +5.0VDC, VD(I/O) = +5.0 or +3.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, Rs = 25Ω. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) 2.0 V (min) CD0–CD6, MCLK, SYNC, SDI, SCLK, CS , RD Digital Input Characteristics VIN(1) Logical “1” Input Voltage VD(I/O) = 5.25V VIN(0) Logical “0” Input Voltage VD(I/O) = 3.6V VD(I/O) = 4.75V IIN Input Leakage Current VD(I/O) = 2.7V VIN = VD 0.1 µA VIN = DGND −0.1 µA 5 pF CIN Input Capacitance DD0–DD7, EOC , CCLK, SDO Digital Output Characteristics VOUT(1) Logical “1” Output Voltage VD(I/O) = 4.75V, IOUT = −360 µA VD(I/O) = 4.75V, IOUT = −10 µA VD(I/O) = 2.7V, IOUT = −360 µA VOUT(0) IOUT Logical “0” Output Voltage TRI-STATE ® Output Current (DD0–DD7 only) COUT VD(I/O) = 2.7V, IOUT = −10 µA VD(I/O) = 5.25V, IOUT = 1.6 mA VD(I/O) = 3.6V, IOUT = 1.6 mA VOUT = DGND VOUT = VD 2.0 V (min) 0.8 V (max) 0.7 V (max) 2.4 V (min) 4.4 V (min) 2.1 V (min) 2.5 V (min) 0.4 V (max) 0.4 V (max) 0.1 µA −0.1 µA 5 pF TRI-STATE Output Capacitance φ1, φ2, RS, TR Digital Output Characteristics VOUT(1) VOUT(0) Logical “1” Output Voltage Logical “0” Output Voltage VD = 4.75V, IOUT = −360 µA VD = 4.75V, IOUT = −10 µA VD = 5.25V, IOUT = 1.6 mA 2.4 V (min) 4.4 V (min) 0.4 V (max) 42 mA (max) 10 mA (max) 3.5 6 mA (max) 1.6 2 mA (max) Power Supply Characteristics IA Analog Supply Current ID Digital Supply Current ID(I/O) Digital I/O Supply Current Operating 32 Standby 20 Operating 6 Standby µA 4 Operating, VD(I/O) = 5.0V Operating, VD(I/O) = 3.0V Standby, VD(I/O) = 5.0V or 3.0V mA 0.5 mA AC Electrical Characteristics, MCLK Independent The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = VD(I/O) = +5.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, tMCLK = 1/fMCLK, tr = tf = 5ns, Rs = 25Ω, CL (databus loading) = 50 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol fMCLK Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) Maximum MCLK Frequency 20 MHz (min) Minimum MCLK Frequency 5 MHz (max) MCLK Duty Cycle 30 40 % (min) 70 60 % (max) ns (min) tA SYNC setup of MCLK 5 10 tCDSETUP Correction Data valid to CLK Setup 14 20 ns (min) tCDHOLD Correction Data valid to CLK Hold −12 0 ns (min) tD1H, tD0H RD High to DD0–DD7 TRI-STATE 7 15 ns (max) www.national.com 4 AC Electrical Characteristics, MCLK Independent (Continued) The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = VD(I/O) = +5.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, tMCLK = 1/fMCLK, tr = tf = 5ns, Rs = 25Ω, CL (databus loading) = 50 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) 20 40 ns (max) MHz (max) tDACC Access Time Delay from RD Low to DD0–DD7 Data Valid fSCLK Maximum SCLK Frequency 2.5 SCLK Duty Cycle 40 % (min) 60 % (max) tSDI SDI Set-Up Time from SCLK Rising Edge 3 10 ns (min) tHDI SDI Hold Time from SCLK Rising Edge 2 15 ns (min) tDDO Delay from SCLK Falling Edge to SDO Data Valid 35 55 ns (max) 21 55 ns (max) 5 ns (min) tHDO SDO Hold Time from SCLK RL = 3K, CL = 25 pF Falling Edge tDELAY DELAY from SCLK Falling Edge to CS Rising or Falling Edge 2 5 ns (min) tSETUP Set-Up Time of CS Rising or Falling Edge to SCLK Rising Edge −2 10 ns (min) tSACC Access Time Delay from CS Falling Edge to SDO Data Valid 20 40 ns (max) tS1H, tS0H Delay from CS Rising Edge to SDO TRI-STATE RL = 3K, CL = 50 pF 40 100 ns (max) SDO Rise Time, TRI-STATE to High RL = 3K, CL = 50 pF tRDO SDO Rise Time, Low to High tFDO SDO Fall Time, TRI-STATE to Low RL = 3K, CL = 50 pF SDO Fall Time, High to Low 5 20 ns 20 ns 20 ns 20 ns www.national.com AC Electrical Characteristics, MCLK Dependent The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = VD(I/O) = +5.0 VDC, REF IN = +1.225 VDC, fMCLK = 20MHz, tMCLK = 1/fMCLK, tr = tf = 5ns, Rs = 25Ω, CL (databus loading) = 50 pF/pin. Refer to Table 2 : Configuration Register Parameters for limits labelled C.R. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter tSTART MCLK to first φ1 high tφ φ1, φ2 Clock Period Conditions Typical Limits Units (Note 9) (Note 10) (Limits) tMCLK 50ns 1 Standard CCD Mode 400ns 8 tMCLK Even/Odd CCD Mode 800ns 16 tMCLK tTRWIDTH Transfer Pulse (TR) Width C.R. µs tGUARD φ1 to TR, TR to φ1 Guardband C.R. ns tRSWIDTH Reset Pulse (RS) Width C.R. ns tRS Falling Edge of φ1 to RS Standard CCD Mode C.R. ns Either Edge of φ1 to RS Even/Odd CCD Mode C.R. ns C.R. ns 50ns 1 tMCLK 100ns 2 tMCLK (min) 2 tMCLK (max) tS/HREF tS/HSIG tS/HWIDTH Falling Edge of φ1 to Ref. Sample Standard CCD Mode Either Edge of φ1 to Ref. Sample Even/Odd CCD Mode Falling Edge of φ1 to Sig. Sample Standard CCD Mode Either Edge of φ1 to Sig. Sample Even/Odd CCD Mode Sample Pulse Width (Acquisition Time) tSYNCLOW SYNC Low Between Lines tB SYNC Setup of φ1 to end line tCCLKWIDTH CCLK Pulse Width tDATAVALID Data Valid Time from EOC Low tEOCWIDTH EOC Pulse Width φ1 and φ2 Frequency 250ns 5 tMCLK 300 ns (min) 250ns 5 tMCLK Standard CCD Mode 2.5MHz fMCLK/8 Hz Even/Odd CCD Mode 1.25MHz fMCLK/16 Hz 50 % φ1 and φ2 Duty Cycle Electrical Characteristics (Notes) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = DGND(I/O) = 0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax–TA)/θJA. TJmax = 150˚C for this device. The typical thermal resistance θJA of this part when board mounted is 52˚C/W for the V52A PLCC package. Note 5: Human body model, 100 pF capacitor discharged through a 1.5Ω resistor. Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: A Zener diode clamps the OS analog input to AGND as shown below. This input protection, in combination with the external clamp capacitor and the output impedance of the CCD, prevents damage to the LM9800 from transients during power-up. DS012498-4 Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin. Note 9: Typicals are at TJ = TA = 25˚C, fMCLK = 20MHz, and represent most likely parametric norm. Note 10: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). www.national.com 6 Electrical Characteristics (Notes) (Continued) Note 11: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC. Note 12: VREF is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. VWHITE is defined as the peak CCD pixel output voltage for a white (full scale) image with respect to the reference level, VREF. VRFT is defined as the peak positive deviation above VREF of the reset feedthrough pulse. The maximum correctable range of pixel-to-pixel VWHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity variation, optics, etc.) that the LM9800 can correct for using its internal PGA. DS012498-5 Note 13: Reference voltages below 1.19V may decrease SNR. Reference voltages above 1.26V may cause clipping errors inside the LM9800. The LM4041EIM3-1.2 (SOT-23 package) or the LM4041EIZ-1.2 (TO-92 package) bandgap voltage references are recommended for this application. Typical Performance Characteristics φ1, φ2, RS, TR Rise and Fall Times Through a Series Resistance vs. Load Capacitance VGA Gain vs Voltage on GAIN Input DS012498-48 DS012498-49 Pin Descriptions REF IN Analog Inputs. These two pins are the system reference voltage inputs and should be tied together to a 1.225V voltage source and bypassed to AGND with a 0.1 µF monolithic capacitor. REF OUTHI Analog Output. This reference voltage is developed internally by the LM9800, and is equal to 3 times REF IN. It should be bypassed to AGND with a 0.1 µF monolithic capacitor. REF OUTMID Analog Output. This reference voltage is developed internally by the LM9800, and is equal to 2 times REF IN. It should be bypassed to AGND using a 0.1 µF monolithic capacitor. This pin can source up to 250 µA when used to power a voltage divider for setting the voltage at the GAIN input. ISET Analog Input. This input is used to set internal bias currents inside the LM9800. It should be connected to VA through a 75 kΩ resistor. CCD Driver Signals φ1 Digital Output. CCD clock signal, phase 1. φ2 Digital Output. CCD clock signal, phase 2. RS Digital Output. Reset pulse for the CCD. TR Digital Output. Transfer pulse for the CCD. Analog I/O OS Analog Input. This is the OS (Output Signal) from the CCD. The maximum peak signal that can be accurately digitized is equal to the voltage at REF IN, typically 1.225V. GAIN Analog Input. The voltage on this pin determines the gain of the VGA when the VGA is enabled. This input should be bypassed to AGND using a 0.1 µF monolithic capacitor. 7 www.national.com Pin Descriptions VTEST1, VTEST2 (Continued) Digital Output I/O Analog Inputs/Outputs. These pins are used for testing the device during manufacture and should be left unconnected. DD0 (LSB)– DD7 (MSB) Digital Outputs. Pixel Output Databus. This data bus outputs the 8-bit digital output data during line scan. EOC Digital Output. This is the End of Conversion signal from the ADC indicating that new pixel data is available. RD Digital Input. Taking this input low places the data stored in the output latch on the bus. When this input is high the DD0–DD7 bus is in TRI-STATE. VA This is the positive supply pin for the analog supply. It should be connected to a voltage source of +5V and bypassed to AGND with a 0.1 µF monolithic capacitor in parallel with a 10 µF tantalum capacitor. AGND This is the ground return for the analog supply. VD This is the positive supply pin for the digital supply. It should be connected to a voltage source of +5V and bypassed to DGND with a 0.1 µF monolithic capacitor. DGND This is the ground return for the digital supply. VD(I/O) This is the positive supply pin for the digital supply for the LM9800’s I/O. It should be connected to a voltage source of +3V to +5V and bypassed to DGND(I/O) with a 0.1 µF monolithic capacitor. If the supply for this pin is different than the supply for VA and VD, it should also be bypassed with a 10 µF tantalum capacitor. DGND(I/O) This is the ground return for the digital supply for the LM9800’s I/O. Configuration Register I/O SDI Digital Input. Serial Data Input pin. SDO Digital Output. Serial Data Output pin. SCLK Digital Input. This is the serial data clock, used to clock data in through SDI and out through SDO. SCLK is asynchronous to MCLK. Input data is latched and output data is changed on the rising edge of SCLK. CS Analog Power Digital Input. This is the Chip Select signal for writing to the Configuration Register through the serial interface. This input must be low in order to communicate with the Configuration Register. This pin is used for serial I/O only–it has no effect on any other section of the chip. Note: The SYNC pin must be high to read or write from the Configuration register. Digital Power General Digital I/O MCLK Digital Input. This is the 20 MHz (typical) master system clock. SYNC Digital Input. A low-to-high transition on this input begins a line scan operation. The line scan operation terminates when this input is taken low. A low-to-high transition on this input will also reset the serial I/O port to the Configuration Register. The SYNC pin must be high to read or write from the Configuration register. Digital Coefficient I/O CD0 (LSB)– CD6 (MSB) Digital Inputs. Correction Coefficient Databus. This is the 7-bit data path for the gain adjust PGA, used during line scan. CCLK Digital Output. This is the signal that is used to clock the Gain coefficients into the LM9800. Data is latched on the rising edge of CCLK. www.national.com 8 Timing Diagrams DS012498-6 FIGURE 1. Line Scan Timing Overview DS012498-7 FIGURE 2. Pixel Pipeline Timing Overview 9 www.national.com Timing Diagrams (Continued) DS012498-8 FIGURE 3. Timing for Start of Line Scan DS012498-9 FIGURE 4. Timing for End of Line/Start of Next Line DS012498-10 FIGURE 5. TR Pulse DS012498-11 FIGURE 6. RS Pulse Polarity www.national.com 10 Timing Diagrams (Continued) DS012498-12 Note: Clamp signal only active during optical black pixels at beginning of line. FIGURE 7. CCD Timing DS012498-13 Note: Clamp signal only active during optical black pixels at beginning of line. FIGURE 8. CCD Timing (Even/Odd CCDs) 11 www.national.com Timing Diagrams (Continued) DS012498-14 Note: j = value programmed in Optical Black Register. i = value programmed in Dummy Pixel Register - 1 (for example: dummy pixel register = 1 ≥ i = 0 ≥ no dummy pixels). FIGURE 9. Dummy Pixel and Optical Black Pixel Timing DS012498-15 FIGURE 10. Coefficient Data Timing DS012498-16 FIGURE 11. Output Data Timing www.national.com 12 Timing Diagrams (Continued) DS012498-17 FIGURE 12. Data Timing (Output and Coefficient Data Sharing Same Bus) DS012498-18 Note: VGA operation (on or off) for “a” pixels, “b” pixels, and “c” pixels is set in the configuration register. VGA is always off for first “a” pixel immediately following last optical black pixel. FIGURE 13. VGA Gain Switching 13 www.national.com Serial Configuration Register Timing Diagrams Note: SYNC pin must be held HIGH (+5V) to read from or write to configuration register. DS012498-19 FIGURE 14. Configuration Register Write Timing with CS Continuously Low (16-bit Word) DS012498-20 FIGURE 15. Configuration Register Write Timing with CS Continuously Low (Two 8-bit bytes) DS012498-21 FIGURE 16. Configuration Register Read Timing with CS Continuously Low (16-bit Word) DS012498-22 FIGURE 17. Configuration Register Read Timing with CS Continuously Low (Two 8-bit bytes) SDO Falling and Rising Edge SDO “TRI-STATE” Falling and Rising Edge DS012498-23 DS012498-24 FIGURE 18. SDO Timing www.national.com 14 Serial Configuration Register Timing Diagrams Note: SYNC pin must be held HIGH (+5V) to read from or write to configuration register. (Continued) DS012498-25 FIGURE 19. Configuration Register Write Timing using CS , Continuous SCLK (16-bit Word) DS012498-26 FIGURE 20. Configuration Register Write Timing using CS , Continuous SCLK (Two 8-bit bytes) DS012498-27 FIGURE 21. Configuration Register Read Timing using CS , Continuous SCLK (16-bit Word) DS012498-28 FIGURE 22. Configuration Register Read Timing using CS , Continuous SCLK (Two 8-bit bytes) 15 www.national.com EOC and CCLK Start of Line Timing Diagrams (See Section 2.4) RS Even RS Odd tEOC1 tEOC2 tCCLK1 tCCLK2 (MCLKs) (MCLKs) (MCLKs) (MCLKs) SR = 0 SR = 1 or 2 SR = 3 or 4 SR = 5 or 6 SR = 0 or 1 SR = 2 or 3 SR = 4 or 5 SR = 6 or 7 2 5 4 3 3 5 5 3 3 6 6 3 3 7 5 5 SR = 7 or 8 SR = 9 or 10 SR = 8 or 9 SR = 10 or 11 3 8 5 6 3 9 5 7 DS012498-29 RS Even, SR = 0 to 10: tEOC0 = 2 MCLKs, tCCLK0 = 3 MCLKs RS Odd, SR = 0 to 11: tEOC0 = 2.5 MCLKs, tCCLK0) = 3.5 MCLKs FIGURE 23. SR = 0 through 10 (RS Even), SR = 0 through 11 (RS Odd) DS012498-30 RS Even, SR = 11 or 12: tEOC0 = 2 MCLKs, tCCLK0 = 3 MCLKs RS Odd, SR = 12 or 13: tEOC0 = 2.5 MCLKs, tCCLK0 = 3.5 MCLKs FIGURE 24. SR = 11 or 12 (RS Even), SR = 12 or 13 (RS Odd) www.national.com 16 EOC and CCLK Start of Line Timing Diagrams (Continued) DS012498-31 RS Even, SR = 13 or 14: tEOC0 = 2 MCLKs, tCCLK0 = 3 MCLKs RS Odd, SR = 14 or 15: tEOC0 = 2.5 MCLKs, tCCLK0 = 3.5 MCLKs FIGURE 25. SR = 13 or 14 (RS Even), SR = 14 or 15 (RS Odd) DS012498-32 FIGURE 26. SR = 15 (RS Even) 17 www.national.com Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (tMCLK = 50ns). TABLE 1. Configuration Register Address Table A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Standard RS Pulse Width Mode or 0 0 0 Even/Odd RS Pulse Polarity RS Pulse Position (Minimum Value is 1) Mode MODE 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 www.national.com RSW1 RSW0 RSPOL RSPOS3 RSPOS2 Sample Reference Position RSPOS1 RSPOS0 Sample Signal Position SR3 SR2 SR1 SR0 φ1 φ2 RS TR Enable Enable Enable Enable φ1EN φ2EN RSEN TREN SS3 SS2 SS1 TR Guardband Polarity TRW0 TRGRD TRPOL BLS2 BLS1 BLS0 BLL1 BLL0 TR Pulse Width TRW1 SS0 TR–φ1 Dummy Pixels (Minimum Value is 1) BLS7 BLS6 BLS5 BLS4 BLS3 Optical Black Pixels (Minimum Value is 1) BLL7 BLL6 BLL5 BLL4 BLL3 BLL2 PGA Gain Coefficient 0 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 PGA Gain Test Power- Offset VGA VGA State VGA State VGA State Source Mode down Add On/Off Pixel c Pixel b Pixel a PGASRC 0 PD OFFADD VGA G3 G2 G1 Offset DAC Offset DAC Offset DAC Offset DAC Sign MSB ODSIGN VOS2 Test Modes LSB VOS1 VOS0 18 0 0 0 0 Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (tMCLK = 50ns). (Continued) TABLE 2. Configuration Register Parameters Parameter MODE Control Bits Result MODE Standard CCD (φ frequency = fMCLK/8) Even/Odd CCD (φ frequency = fMCLK/16) 0 1 RS Pulse Width (tRSWIDTH) RS Pulse Polarity RS1 RS0 0 0 1 tMCLK (50ns) 0 1 2 tMCLK (100ns) 1 0 3 tMCLK (150ns) 1 1 4 tMCLK (200ns) RSPOL 0 RS 1 RS Pulse Position (tRS) Note: Minimum Value is 1 Sample Reference Position (tS/HREF) RS RSPOS3 RSPOS2 RSPOS1 RSPOS0 0 0 0 0 Not Valid 0 0 0 1 0.5tMCLK (25 ns) 0 0 1 0 1.0tMCLK (50ns) 0 0 1 1 1.5tMCLK (75ns) 0 1 0 0 2.0tMCLK (100ns) 0 1 0 1 2.5tMCLK (125ns) 0 1 1 0 3.0tMCLK (150ns) 0 1 1 1 3.5tMCLK (175ns) 1 0 0 0 4.0tMCLK (200ns) 1 0 0 1 4.5tMCLK (225ns) 1 0 1 0 5.0tMCLK (250ns) 1 0 1 1 5.5tMCLK (275ns) 1 1 0 0 6.0tMCLK (300 ns) 1 1 0 1 6.5tMCLK (325 ns) 1 1 1 0 7.0tMCLK (350 ns) 1 1 1 1 7.5tMCLK (375 ns) SR3 SR2 SR1 SR0 0 0 0 0 0.0tMCLK (0 ns) 0 0 0 1 0.5tMCLK (25 ns) 0 0 1 0 1.0tMCLK (50 ns) 0 0 1 1 1.5tMCLK (75 ns) 0 1 0 0 2.0tMCLK (100 ns) 0 1 0 1 2.5tMCLK (125 ns) 0 1 1 0 3.0tMCLK (150 ns) 0 1 1 1 3.5tMCLK (175 ns) 1 0 0 0 4.0tMCLK (200 ns) 1 0 0 1 4.5tMCLK (225 ns) 1 0 1 0 5.0tMCLK (250 ns) 1 0 1 1 5.5tMCLK (275 ns) 1 1 0 0 6.0tMCLK (300 ns) 1 1 0 1 6.5tMCLK (325 ns) 1 1 1 0 7.0tMCLK (350 ns) 1 1 1 1 7.5tMCLK (375 ns) 19 www.national.com Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (tMCLK = 50ns). (Continued) TABLE 2. Configuration Register Parameters (Continued) Parameter Sample Signal Position (tS/HSIG) φ1 Enable φ2 Enable RS Enable TR Enable Control Bits SS3 SS2 0 0 0 0 0.0tMCLK (0 ns) 0 0 1 0.5tMCLK (25 ns) 0 0 1 0 1.0tMCLK (50 ns) 0 0 1 1 1.5tMCLK (75 ns) 0 1 0 0 2.0tMCLK (100 ns) 0 1 0 1 2.5tMCLK (125 ns) 0 1 1 0 3.0tMCLK (150 ns) 0 1 1 1 3.5tMCLK (175 ns) 1 0 0 0 4.0tMCLK (200 ns) 1 0 0 1 4.5tMCLK (225 ns) 1 0 1 0 5.0tMCLK (250 ns) 1 0 1 1 5.5tMCLK (275 ns) 1 1 0 0 6.0tMCLK (300 ns) 1 1 0 1 6.5tMCLK (325 ns) 1 1 1 0 7.0tMCLK (350 ns) 1 1 1 1 7.5tMCLK (375 ns) φ1EN 0 φ1 Output Off 1 φ1 Output On φ2EN 0 φ2 Output Off 1 φ2 Output On RSEN 0 RS Output Off 1 RS Output On TREN TR Output Off 1 TR-φ1 SS0 0 0 TR Pulse Width (tTRWIDTH) Result SS1 TRW1 TR Output On TRW0 0 0 20 tMCLK (1.0 µs) 0 1 30 tMCLK (1.5 µs) 1 0 40 tMCLK (2.0 µs) 1 1 50 tMCLK (2.5 µs) TRGRD Guardband 0 1 tMCLK (50 ns) (tGUARD) 1 2 tMCLK (100 ns) TR Polarity www.national.com TRPOL 0 TR 1 TR 20 Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (tMCLK = 50ns). (Continued) TABLE 2. Configuration Register Parameters (Continued) Parameter Dummy Pixels Note: Minimum Value is 1. Actual number of dummy pixels in CCD should be one less than number in this register. Optical Black Pixels Note: Minimum Value is 1 Internal PGA Gain Coefficient PGA Gain Coefficient Source Power Down Offset Add Master VGA Control VGA State for Pixel “c” VGA State for Pixel “b” Control Bits Result BLS7 BLS6 BLS5 BLS4 BLS3 BLS2 BLS1 BLS0 0 0 0 0 0 0 0 0 Not Valid 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 • • • 1 1 BLL7 0 0 0 • • • 1 1 BLL6 0 0 0 • • • 1 1 BLL5 0 0 0 • • • 1 1 BLL4 0 0 0 • • • 1 1 BLL3 0 0 0 • • • 1 1 BLL2 0 0 0 • • • 1 1 BLL1 0 0 1 • • • 0 1 BLL0 0 1 0 • • • 253 254 • • • 1 1 GAIN6 0 0 • • • 1 1 GAIN5 0 0 • • • 1 1 GAIN4 0 0 • • • 1 1 GAIN3 0 0 • • • 1 1 GAIN2 0 0 • • • 1 1 GAIN1 0 0 • • • 1 1 GAIN0 0 1 • • • 0 1 • • • 1 1 • • • 1 1 • • • 1 1 • • • 1 1 • • • 0 1 • • • • • • 1 1 1 1 PGASRC 0 1 PD 0 1 OFF ADD 0 1 VGA 0 1 VGAc 0 1 VGAb 0 1 Not Valid 1 2 • • • 254 255 0 [0 dB] 1 • • • 126 127 [6 dB] Internal External Operating Power Down Offset z0 LSB Offset z+1 LSB VGA Disabled VGA Enabled VGA bypassed VGA on VGA bypassed VGA on 21 www.national.com Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (tMCLK = 50ns). (Continued) TABLE 2. Configuration Register Parameters (Continued) Parameter VGA State for Pixel “a” Control Bits Result VGAa 0 VGA bypassed 1 Offset DAC VGA on Sign VOS1 VOS1 VOS0 Offset (LSB) 1 0 0 0 0 1 0 0 1 +1 1 0 1 0 +2 1 0 1 1 +3 1 1 0 0 +4 1 1 0 1 +5 1 1 1 0 +6 1 1 1 1 +7 0 0 0 0 0 0 0 0 1 −1 0 0 1 0 −2 0 0 1 1 −3 0 1 0 0 −4 0 1 0 1 −5 0 1 1 0 −6 0 1 1 1 −7 Block Diagram of LM9800-Based System DS012498-33 Note: Power supplies and bypass capacitors not shown for clarity. FIGURE 27. LM9800 System Block Diagram www.national.com 22 Finally, the output of the PGA is digitized by the ADC and made available on the DD0–DD7 bus. For a detailed explanation of the ADC, see section 4.9. Three reference voltages are used throughout the signal path: the externally supplied REF IN (1.225V), and the internally generated REF OUTMID (2.45V) and REF OUTHI (3.675V). Applications Information 1.0 THEORY OF OPERATION The LM9800 removes errors from and digitizes a linear CCD pixel stream, while providing all the necessary clock signals to drive the CCD. Offset and gain errors are removed at the pixel rate, for individual pixels. Offset errors are removed through correlated double sampling (CDS). Gain errors (which may come from any combination of PRNU, uneven illumination, cos4 effect, RGB filter mismatch, etc.) are removed through the use of a 7-bit PGA in front of the ADC. 1.2 The CCD Clocking Signals To maximize the flexibility of the LM9800, the CCD’s φ1, φ2, RS, and TR pulses are internally generated, with a wide range of options, compatible with most commercial linear CCDs. In most cases, these output signals can drive most CCD clock inputs directly, with only series resistors (for slew rate control) between the LM9800’s outputs and the CCD clock inputs. 1.1 The Analog Signal Path (See Block Diagram) The analog output signal from the CCD is connected to the OS Input of the LM9800 through a 0.001µF (typical, see section 4.2, Clamp Capacitor Selection ) DC blocking capacitor. During the CCD’s optical black pixel segment at the beginning of every line, this input is clamped to the REF OUTMID voltage (approximately 2.45V). This DC restore operation fixes the reference level of the CCD pixel stream at REF OUTMID. The signal is then buffered and fed to a voltage-controlled VGA (variable gain amplifier). The VGA can be used to compensate for peak white CCD outputs less than the 1.225V full-scale required by the LM9800 for maximum dynamic range. It can also be used to increase the gain of the Blue signal in a sequential-output RGB CCD, since the VGA can be switched in and out of the circuit at the pixel rate. When used with parallel output CCDs the VGA can be used (in conjunction with an external multiplexer) to fine-tune the amplitude of the red, green, and blue signals. For a detailed explanation of the VGA, see section 4.3, GAIN (VGA) Input. The output of the VGA goes into the CDS (Correlated Double Sampling) stage, consisting of two sample/hold amplifiers: S/H Ref (Reference) and S/H Signal. The Reference Level is sampled and held by the S/H Ref circuit and the active pixel data is sampled and held by the S/H Signal circuit. The output of S/H Ref is subtracted from the S/H Signal output and amplified by 2. The full-scale signal range at this point is approximately 2.45Vp-p. CDS reduces or eliminates many sources of noise, including reset noise, flicker noise, and both high and low frequency pixel-to-pixel offset variation. For more information on the CDS stage, see section 4.5, Correlated Double Sampler (CDS) . At this point an offset voltage can be injected by the 4-bit Offset DAC. This voltage is designed to compensate for any small fixed DC offset introduced by the CDS S/Hs and the x2 amplifier. The LSB size of the DAC is approximately 1 LSB (10mV).The adjustment range is ± 7 LSBs. For a detailed explanation of the Offset DAC, see section 4.6. 1.3 The Digital Interface There are three main sections to the digital interface of the LM9800: a serial interface to the Configuration Register, where all device programming is done, a 7 bit-wide input databus for gain correction coefficients with a synchronous clock output, and an 8-bit output databus for the final pixel output data with a synchronous EOC output signal and a RD input. Please note that CS affects only the serial I/O–it has no effect on the output databus, input coefficient bus, or any other section of the LM9800. 2.0 DIGITAL INTERFACE 2.1 Reading and Writing to the Configuration Register Communication with the Configuration Register is done through a standard MICROWIRE™ serial interface. This interface is compatible with the Motorola SPI standard and is simple enough to easily be implemented in custom hardware if needed. The serial interface timing is shown in Figures 14, 15, 16, 17 and Figures 19, 20, 21, 22. The SYNC pin must be pulled high to read or write to the configuration register. Taking SYNC high resets the internal serial counters. Data is sent serially, LSB first. Input data is latched on the rising edge of SCLK, and output data changes on the falling edge of SCLK. CS must be low to enable serial I/O. If SCLK is only clocked when sending or receiving data from the LM9800, and held low at all other times, then CS can be tied low permanently as shown in Figures 14, 15, 16, 17. If SCLK is continuous, then CS is used to determine the beginning and the end of a serial byte or word (see Figures 19, 20, 21, 22). Note that CS must make its high-to-low and low-to-high transitions when SCLK is low, otherwise the internal bit counter may receive an erroneous pulse, causing an error in the write or read operation. The next stage is the PGA. This is a programmable gain amplifier that changes the gain at the pixel rate to correct for gain errors due to PRNU, uneven illumination (such as cos4 effect), RGB filter mismatch, etc. The gain adjustment range is 0 to 6 dB (x1 to x2) with 7 bits of resolution. The gain data (correction coefficients) is provided on the CD0–CD6 bus. The gain may also be fixed at any value between 0 dB and 6 dB with the PGA Gain Coefficient configuration register. For further information on the PGA, see section 4.7. An approximately 1 LSB (10mV) offset can be added at the output of the PGA stage if necessary to ensure that the offset is zero or positive. This eliminates the possibility of a negative offset clipping the darkest output pixels. For more information on the Offset Add Bit, see section 4.8. Data may be transmitted and received in two 8-bit bytes (typical with microcontroller interfaces) or one 16-bit word (for custom serial controllers). The Configuration Register is programmed by sending a control byte to the serial port. This byte indicates whether this is a read or a write operation, and gives the 3-bit address of the register bank to be read from or written to. If this is a read operation, the next 8 SCLKs will output the data at the requested location on the SDO pin. If this is a write operation, the data to be sent to the specified location should be clocked in on the SDI input during the next 8 SCLKs. Data is sent and received using the LSB (Least Significant Bit) first format. 23 www.national.com Applications Information 2.6 SYNC This input signals the beginning of a line. When SYNC goes high, the LM9800 generates a TR pulse, then begins converting pixels until the SYNC line is brought low again. Since there is no pixel counter in the LM9800, it will work with CCDs of any length. SYNC must be high to read from or write to the Configuration Register. The rising edge of SYNC resets the serial I/O’s internal shift register, so any noise or sporadic signals on the SCLK input prior to SYNC going high will be ignored. (Continued) For maximum system reliability, each configuration register location can be read back and verified after a write. If the serial I/O to the configuration register falls out of sync for any reason, it can be reset by a rising edge on the SYNC pin input. 2.2 Writing Correction Coefficient Data on the CD0–CD6 Bus Correction coefficient data for each pixel is latched on the rising edge of the CCLK output signal (see Figure 10). Note that there is a 4 pixel latency between when the coefficient data is latched and when the output data is available. As Figure 2, Pixel Pipeline Timing Overview shows, coefficient data for pixel n is latched shortly before the output data for pixel n-2 becomes available on the output databus (DD0–DD7). Figures 23, 24, 25, 26 show the timing for coefficient data and output data at the beginning of each line. Note that there is no way to provide a correction coefficient for pixel 1, the first pixel in the CCD array. This is usually not a problem since the first several pixels of most CCDs are not used. The timing at the beginning of a line is discussed in detail in section 2.4. 3.0 DIGITAL CCD INTERFACE 3.1 Buffering φ1, φ2, RS, and TR The LM9800 can drive the φ1, φ2, RS, and TR inputs of many CCDs directly, without the need for external buffers between the LM9800 and the CCD. Most linear CCDs designed for scanner applications require 0V to 5V signal swings into 20pF to 500pF input loading. Series resistors are typically inserted between the driver and the CCD to control slew rate and isolate the driver from the large load capacitances. The values of these resistors are usually given in the CCD’s datasheet. 4.0 ANALOG INTERFACE 2.3 Reading Output Data on the DD0–DD7 Bus The corrected digital output data representing each pixel is available on the DD0–DD7 databus. The data is valid after the falling edge of the EOC output. The RD input takes the databus in and out of TRI-STATE. RD can be held low at all times if there are no other devices needing the bus, or it can be used to TRI-STATE the bus between pixels, allowing other devices access to the bus. Figure 12 shows how EOC can be tied to RD to automatically multiplex between coefficient data and conversion data. 4.1 Voltage Reference The two REF IN pins should be connected to a 1.225V ± 2% reference voltage capable of sinking between 2mA and 8mA of current coming from the 400Ω–900Ω resistor string between REF OUTHI and REF IN. The LM4041-1.2 1.225V bandgap reference is recommended for this application as shown in Figure 28. The inexpensive “E” grade meets all the requirements of the application and is available in a TO-92 (LM4041EIZ-1.2) package as well as a SOT-23 package (LM4041EIM3-1.2) to minimize board space. Due to the transient currents generated by the LM9800’s ADC, PGA, and CDS circuitry, the REF IN pins, the REF OUTMID pin and the REF OUTHI pin should all be bypassed to AGND with 0.1µF monolithic capacitors. 2.4 EOC and CCLK at Startup At the beginning of every line, the LM9800 internally synchronizes the EOC and CCLK signals with the user-programmed sample periods. The timing of EOC and CCLK during this adjustment period depends on the settings in the RS Pulse Position (RS) and Sample Reference Position (SR) registers, as shown in Figures 23, 24, 25, 26. The numbers inside the CCLK and EOC signals indicate the width (in MCLK periods) of that signal while it is in that state. The EOC and CCLK pulse train is synchronized with the position of the Sample Reference pulse. For most RS and SR combinations (shown in table and timing of Figure 23), increasing SR simply stretches out the second EOC and CCLK cycle. When SR is greater than 10 (typically with even/odd CCDs), the timing gets more complex, and should be considered when building any systems that rely on the EOC and/or CCLK signals for counting, or expect them to never be low simultaneously. 2.5 MCLK This is the master clock input that controls the LM9800. The pixel conversion rate is fixed at 1/8 of this frequency. Many of the timing parameters are also relative to the frequency of this clock. www.national.com DS012498-34 FIGURE 28. Voltage Reference Generation 4.2 Clamp Capacitor Selection The output signal of most CCDs rides on a large DC offset (typically 8V to 10V) which is incompatible with the LM9800’s 5V operation. To eliminate this offset without resorting to additional higher voltage components, the output of the CCD is AC coupled to the LM9800 through a DC blocking capacitor, CCLAMP (the CCD’s DOS output is not used). The value of this capacitor is determined by the leakage current of the 24 Applications Information the CCD’s output impedance, and the desired accuracy of the final clamp voltage and provides the maximum clamp capacitor value: (Continued) LM9800’s OS input and the output impedance of the CCD. The leakage through the OS input determines how quickly the capacitor value will drift from the clamp value of REF OUTMID, which then determines how many pixels can be processed before the droop causes errors in the conversion ( ± 0.1V is the recommended limit). The output impedance of the CCD determines how quickly the capacitor can be charged to the clamp value during the black reference period at the beginning of every line. Where n = the number of optical black pixels, tDARK is the amount of time (per pixel) that the clamp is on, ROUT is the output impedance of the CCD, and accuracy is the ratio of the worst-case initial capacitor voltage to the desired final capacitor voltage. For example, if a CCD has 18 black reference pixels, the output impedance of the CCD is 1000Ω, the LM9800 is configured to clamp for 300ns, the worst case initial voltage across the capaoitor is 10V, and the desired voltage after clamping is 0.05V (accuracy = 10/0.05 = 200), then: DS012498-53 FIGURE 29. OS Clamp Capacitor and Internal Clamp The minimum clamp capacitor value is determined by the maximum droop the LM9800 can tolerate while converting one CCD line. The following equation takes the maximum leakage current into the OS input, the maximum allowable droop (100mV), the number of pixels on the CCD, and the pixel conversion rate (fMCLK/8) and provides the minimum clamp capacitor value: The final value for CCLAMP should be equal to or slightly less than CCLAMP MAX, but no less than CCLAMP MIN. The LM9800 has been designed to work with most of the single output CCDs in use, but it is possible that some CCDs could have a combination of high output impedance and low optical black pixel count that would cause CCLAMP MIN to be greater than CCLAMP MAX. In this case the LM9800 can be “short cycled” as shown in Figure 30, by bringing the sync pin low and then high again shortly after clamping the black reference pixels. This starts the line over, effectively increasing the number of black reference pixels, giving the capacitor more time to charge up through the output impedance of the CCD. This “short cycling” can be repeated as many times as necessary in order to guarantee that the capacitor is charged up to the required accuracy. Short cycling, if needed at all, is only necessary on power up and at the beginning of new scans where the OS coupling capacitor may have drooped since the previous scan. If the SYNC input is continuously being cycled at the line rate, short cycling is usually not necessary. For example, if the OS input leakage current is 20nA worstcase, the CCD has 2200 active pixels, the conversion rate is 2.5MHz (fMCLK = 20MHz), and the max droop desired is 0.05V, the minimum clamp capacitor value is: The maximum size of the clamp capacitor is determined by the amount of time available to charge it to the desired value during the optical black portion of the CCD output. The internal clamp is on for each pixel from the rising edge of the S/H ref pulse to the falling edge of the S/H signal pulse (see Figures 7, 8 ). This time can be calculated using the values stored in the Sample Signal and Sample Reference configuration registers and the MCLK frequency. For normal CCDs: And for even/odd CCDs: DS012498-35 Where SS is the value in the Sample Signal Position register (0–15), SR is the value in the Sample Reference Position register (0–15), fMCLK is the MCLK frequency, and tDARK is the amount of time (per pixel) that the clamp is on. The following equation takes the number of optical black pixels, the amount of time (per pixel) that the clamp is closed, FIGURE 30. Example of Short Cycling 25 www.national.com Applications Information tude than the Red and Green signals. The LM9800 can compensate for this by allowing the VGA to be turned on and off at the pixel rate, allowing each pixel in a three pixel triad to have one of two different gains (see Figure 13, VGA Gain Switching). When the VGA is bypassed, the gain through the VGA stage is 1. When the VGA is activated, the gain through the VGA stage is determined by the external voltage on the GAIN input. The Configuration Register controls whether or not gain switching is implemented, and which pixels are routed through the VGA. Gain switching is controlled by the VGA On/Off bit and the three Pixel Gain bits in the Configuration Register. If the VGA On/Off bit is set to 0, then the VGA is bypassed (a gain of 1) for all pixels. If the VGA On/Off bit is set to 1, then the gain for each pixel inside every three pixel “triad” is set by the VGA State for Pixel “n” bits. For example, if the CCD output data is RGBRGBRGB, then the VGA state bits in the configuration register should be 001 (Pixel “a” = 0, Pixel “b” = 0, Pixel “c” = 1). The VGA would then be bypassed for the Red and Green pixels (for an effective gain of 1), and the Blue pixels would be routed through the VGA for amplification (as determined by the voltage on the GAIN input). Note that the VGA is always off (for an effective gain of 1) for the first pixel immediately following the last optical black pixel, regardless of the setting of the gain bit. Other color configurations are described in section 5.0. (Continued) 4.3 GAIN (VGA) Input The LM9800 has a VGA (Variable Gain Amplifier) that can be used to increase the amplitude of the CCD signal prior to sampling, correction, and digitization. In a greyscale system, the VGA can provide gain for all the pixels. The VGA is activated or bypassed by setting or resetting the VGA bit in the configuration register. For greyscale systems using the VGA, the VGA bit and all 3 Pixel Gain bits (VGAa, VGAb, and VGAc) should be set to “1”. The gain of the VGA is determined by the voltage on the GAIN input as given by the equation: Where VGAIN is the voltage at the GAIN input of the LM9800. A detailed graph of this function is provided in the Typical Performance Characteristics section of the datasheet. This equation is accurate for the VGAIN voltage range of 0.5V to 2.0V, corresponding to a gain range of x1.5 to x2.7 (typical). The voltage at the GAIN input may be supplied by a resistive divider between REF OUTHI and AGND or by a voltage output DAC. The divider provides a low cost fixed gain suitable for many applications. The DAC allows fine, closed-loop adjustment of the gain which can eliminate system-to-system CCD gain and light source intensity variations to maximize dynamic range. The DAC0854 has the ideal output voltage range for this application and requires no additional external components. 4.5 Correlated Double Sampler (CDS) Figure 33 shows the output stage of a typical CCD and the resulting output waveform: DS012498-39 DS012498-37 Note : 10 kΩ ≤ R1 + R2 ≤ 50 kΩ FIGURE 31. GAIN Control with Voltage Divider DS012498-40 FIGURE 33. CDS Capacitor C1 converts the electrons coming from the CCD’s shift register to an analog voltage. The source follower output stage (Q2) buffers this voltage before it leaves the CCD. Q1 resets the voltage across capacitor C1 in between every pixel at intervals 2 and 5. When Q1 is on, the output signal (OS) is at its maximum. After Q1 turns off (period 3), the OS level represents the residual voltage across C1 (VRESIDUAL). VRESIDUAL includes charge injection from Q1, thermal noise from the ON resistance of Q1, and other sources of error. When the shift register clock (φ1) makes a low to high transition (period 4), the electrons from the next pixel flow into C1. The charge across C1 now contains the voltage proportional to the number of electrons plus VRESIDUAL, an error DS012498-38 FIGURE 32. GAIN Control with DAC If the VGA is not going to be used, the GAIN input should be tied to AGND. 4.4 Color Gain Switching The VGA can also be used in color LM9800-based systems with sequential (serial) color CCD outputs (RGBRGBRGB. . .). Sequential RGB color CCDs typically have a Blue signal that is substantially lower (30%–70%) in ampliwww.national.com 26 Applications Information 5.0 COLOR There are several ways to apply the LM9800 in a color system: (Continued) term. If OS is sampled at the end of period 3 and that voltage is subtracted from the OS at the end of period 4, the VRESIDUAL term is canceled and the noise on the signal is reduced. ([VSIGNAL+VRESIDUAL]−VRESIDUAL = VSIGNAL). This is the principal of Correlated Double Sampling. 5.1 Sequential RGB Output CCD The LM9800 implements CDS with two switched-capacitor S/H amplifiers. The S/Hs acquire a signal within a 50 ns window which can be placed anywhere in the pixel period with 25 ns precision. See Figures 7, 8 for more detailed timing information. 4.6 Offset DAC The offset DAC is used to compensate for DC offsets due to the correlated double sampling stage. The offset can be corrected in 15 steps of 1 LSB size between −7 LSB and +7 LSB. Note that the DAC comes betore the PGA, so any offset errors at this stage are multiplied by the gain of the PGA. The calibration procedure described in section 6.0 demonstrates how to use the DAC to eliminate offset errors before scanning begins. Note that this DAC is programmed during LM9800 calibration/configuration and is not meant to compensate for pixel-to-pixel CCD offset errors. (CDS cancels the pixel-rate offset errors.) DS012498-41 FIGURE 34. Sequential RGB Output CCD The solution shown in Figure 34 provides a 2.5Mpixels/sec (830k RGB pixels/sec) pixel rate using a single LM9800 and no additional external components. It requires a sequential RGB output CCD, and provides inexpensive color at the expense of some resolution and registration. 5.2 Parallel Output CCD, One LM9800 4.7 Programmable Gain Amplifier (PGA) The PGA provides 7 bits of pixeI-to-pixel gain correction over a 0 dB to 6 dB (x1 to x2) range. After the input signal is sampled and held by the CDS stage, it is amplified by the gain indicated by the data (“PGA Code”) on the CD0–CD6 databus using the formula: 4.8 Offset Add Bit In addition to the Offset DAC, there is a bit in the configuration register which, when set, adds a positive 1 LSB offset at the output of the PGA. This offset ensures that any offset between the output of the PGA and the ADC is positive, so that no dark level information is lost due to negative offsets. The calibration procedure described in section 6.0 demonstrates how to set this bit. 4.9 ADC The ADC converts the normalized analog output signal to an 8-bit digital code. The EOC output goes from high to low to indicate that a new conversion is ready. ADC data can be latched by external memory on the rising edge of EOC . The RD input takes the ADC’s output buffer in and out of TRI-STATE. RD may be tied to EOC in many applications, putting the data on the bus only when EOC is low, and allowing other data on the bus (such as CD0–CD6 correction data) at other times. In this way the output data and correction coefficient data can share the same databus (see Figure 12). DS012498-42 FIGURE 35. Parallel Output CCD, One LM9800 Figure 35 gives an example of how to use a single LM9800 with a triple-output RGB CCD. In this case an entire line of red is digitized, followed by an entire line of green, then blue. This solution provides the same 2.5Mpixels/sec (for an effective 830k RGB pixels/sec after de-interleaving) pixel rate as the previous solution but uses a higher performance color CCD. The multiplexers select the color to be digitized and the resistor tap voltage corresponding to the desired gain for that color. The resistor ladder and its multiplexer can be replaced with a voltage output DAC (such as the DAC0854) for precision digital control of the gain for each color. Almost any multiplexer can be used since the multiplexer switches at the line rate, not the pixel rate, and goes into a high impedance input. The 74HC4052 is a good choice. 4.10 ISET Input This input is used to set internal bias currents inside the LM9800. It should be tied to VA through a 75kΩ resistor. 27 www.national.com Applications Information VADC2 = 2(VOS1 + VDAC1) + VOS2 + VDAC2 (PGA gain = x2) Solving for VOS1 and VOS2: VOS1 = (VADC2–VADC1)–VDAC1 VOS2 = (2VADC1–VADC2)–VDAC2 These equations were used to produce this procedure for cancelling the LM9800’s offset errors: (Continued) 5.3 Parallel Output CCD, Three LM9800s 1. 2. Turn off the VGA. Set the Offset DAC to +7 LSB. (This is done to ensure the total offset is positive and therefore measurable by the ADC.) 3. Set the Offset Add bit to 0. 4. Set the PGA Gain to x1 (PGA code = 0). 5. Digitize a black line. 6. 7. 8. 9. DS012498-43 FIGURE 36. Parallel Output CCD, Three LM9800s Figure 36 uses three LM9800s to achieve a 7.5Mpixel/sec (2.5M RGB pixels/sec) pixel rate. The three LM9800s are synchronized by applying the same MCLK and SYNC signals to all three devices. One LM9800 provides the clock signals required for the CCD. Since the coefficient data for all three LM9800s will be latched simultaneously on the rising edge of CCLK, the correction coefficient bus should either be at least 21 bits wide (7 correction coefficient bits by 3 LM9800s) or run at a 7.5MHz rate and latched into a buffer between the correction coefficient databus and each LM9800. Similarly, the output data for all three LM9800s will be available simultaneously at the 3 output databusses. 10. 11. Calculate the average (in ADC LSBs) of all the valid pixels in the black line and store that number as “B1” (equivalent to VADC1). Set the PGA Gain to x2 (PGA code = 127). Digitize a black line. Calculate the average (in ADC LSBs) of all the valid pixels in the black line and store that number as “B2” (equivalent to VADC2). Program the Offset DAC using the formula: Offset DAC code = 7+B1–B2. If 2B1 > B2, then set the Offset Add bit to 0. If 2B1 < B2, set the Offset Add bit to 1. 6.2 Coarse Gain Calibration The LM9800’s PGA corrects for up to 6 dB of varIation in the CCD output signal’s white level intensity. That 6 dB range has to be centered inside the 6 dB window of correction. 6.0 CALIBRATION To calibrate a LM9800-based system, follow these steps: 6.1 Offset Calibration This procedure corrects for offsets generated inside the LM9800. Because the LM9800 uses CDS to eliminate the pixel-to-pixel offset errors of the CCD, very good results can be obtained even if this procedure is not implemented. In this case the Offset DAC and Offset Add bit are simply set to 0. DS012498-44 FIGURE 38. CCD Input Signal In Range With the VGA off and the PGA set to a gain of 0 dB, the LM9800 expects the maximum CCD white level output to be below 1.2V (VREF IN) corresponding to strong pixels, and the minimum white level output voltage to be above 0.6V (VREF IN/2), corresponding to weaker CCD pixels or pixels further from the light source. If the variation for a white input is inside this range, as shown in Figure 38, the PGA can correct for it and linearize it. DS012498-54 If the maximum white level voltage (the voltage from the strongest pixels) is greater than 1.2V (Figure 39), the LM9800 will be unable to linearize the CCD’s output. FIGURE 37. Offset Calibration To use the Offset DAC and Offset Add bit for offset correction, the offset errors must first be determined. This is done be measuring the voltage at the PGA output, using the ADC. If this voltage is known with a PGA gain of x1 (0 dB) and x2 (6 dB), then the offset errors (VOS1 and VOS2) can be determined from the following two equations: VADC1 = 1(VOS1 + VDAC1) + VOS2 + VDAC2 (PGA gain = x1) www.national.com 28 Applications Information close to 6dB, should do this procedure for every system, either once during manufacture or as part of the calibration routine the scanner does on power-up or before a scan. 1. Set the PGA gain to 0dB. (Continued) 2. 3. 4. 5. DS012498-45 6. FIGURE 39. CCD Input Signal Too Strong In this case it is necessary to decrease the maximum amplitude of the CCD output. Typically this is done by reducing the light source intensity, or decreasing the light integration time of the CCD. If the minimum white level output voltage (the voltage from the weakest pixels) is less than 0.6V, then a similar situation occurs, as shown in Figure 40. 7. 8. DS012498-46 FIGURE 40. CCD Input Signal Too Weak In this case the amplitude for some of the weak pixels is too low, and cannot be corrected for by the 6 dB PGA alone. The amplitude of the CCD’s output signal must be increased. This can be accomplished by increasing the intensity of the light source, increasing the integration time of the CCD, or using the LM9800’s VGA feature to add gain to the signal prior to the PGA. If the minimum white level is less than 0.6V and the maximum white level is greater than 1.2V, then the LM9800 cannot correct for this amount of pixel-to-pixel variation — the variation is greater than 6dB (Figure 41). In this case the system should be examined and steps taken to bring the variation within a 6dB window. Typically this can be done by using more even illumination, higher quality CCDs, or better optics. 9. If using the VGA, turn it on and set the gain voltage to provide the approximate gain required. If not using the VGA, turn it off. Scan a reference line corresponding to the maximum white input the scanner should ever have to digitize. Find the minimum and the maximum (in ADC LSBs) of the valid pixels in the reference line. The reference line should correspond to a desired output code. For example, if the reference is 100% white, the desired output code might be 240 LSBs. If the reference was 80% white (light grey), then the desired output code might be (240)(0.8) = 192. If the maximum code obtained after scanning the reference line is less than the desired output code, and the minimum output code is greater than half the desired output code, the signal is in range. Go to section 6.3. If the maximum code obtained after scanning the reference line is greater than the desired output code, and the minimum output code is less than half the desired output code, then there is more than 6dB of variation on the input signal and the LM9800 will not be able to correct for the variations. The pixel-to-pixel variation must be reduced to less than 6dB before the LM9800 can correct for variations. If the maximum code obtained after scanning the reference line is greater than the desired output code for that reference, the CCD output is too large. Reduce the light intensity, shorten the integration time, or (if using the VGA) reduce the voltage on the GAIN input. Go back to Step 4. If the minimum code obtained after scanning the reference line is smaller than half the desired output code for that reference, the CCD output is too weak. Increase the light intensity, lengthen the integration time, or (if using the VGA) increase the voltage on the GAIN input. Go back to Step 4. 6.3 PGA Correction Coefficients (Shading Calibration) Once the input signal has been centered inside the range the LM9800 can correct for, correction coefficients must be generated for each pixel to compensate for the gain error of that pixel. 1. Set the PGA gain to 0dB. 2. If using the VGA, turn it on and set the gain voltage to provide the required gain (determined by the procedure in Section 6.2). 3. If not using the VGA, turn it off (set the VGA On/Off bit to “0”). Scan a reference line corresponding to all white or light grey and store it in memory. Calculate the required gain correction coefficients for each pixel using the formula: 4. 5. DS012498-47 FIGURE 41. CCD Input Signal Range Too Wide The coarse gain calibration procedure follows. In scanner systems with low unit-to-unit variations in light intensity and CCD efficiency, this calibration can be done once and fixed for all the systems. Other systems, where the light intensity varies from unit-to-unit or the pixel-to-pixel variation is very Where Uncorrected Coden is the ADC output code for pixel n with the PGA gain = 0dB, Desired Code is the number that corresponds to the desired output from the ADC with the given reference line input, and Correction Coefficientn is 29 www.national.com Applications Information usually given in the CCD’s datasheet. If the datasheet’s requirement is given as a particular rise/fall time, the resistor can be chosen using the graph of φ1, φ2, RS and TR Rise Times Through A Series Resistance vs. Load Capacitance graph in the Typical Performance Characteristics (Continued) the gain correction number that is sent to the CD0–CD6 correction databus to provide gain correction for pixel n when digitizing a line with the LM9800’s PGA gain correction operating. All the Correction Coefficients must be stored and sent to the LM9800 through the CD0–CD6 databus for every line scanned. 7.0 POWER SUPPLY CONSIDERATIONS 7.1 General The LM9800 should be powered by a single +5V source (unless 3V-compatible digital I/O is required — see section 7.2). The analog supplies (VA) and the digital supplies (VD and VD(I/O)) are brought out individually to allow separate bypassing for each supply input. They should not be powered by two or more different supplies. In systems with separate analog and digital +5V supplies, all the supply pins of the LM9800 should be powered by the cleaner analog +5V supply. Each supply input should be bypassed to its respective ground with a 0.1µF capacitor located as close as possible to the supply input pin. A single 10µF tantalum should be placed near the VA supply pin to provide low frequency bypassing. To minimize noise, keep the LM9800 and all analog components as far as possible from noise generators, such as switching power supplies and high frequency digital busses. If possible, isolate all the analog components and signals (OS, GAIN, reference inputs and outputs, VA, AGND, ISET) on an analog ground plane, separate from the digital ground plane. The two ground planes should be tied together at a single point, preferably the point where the power supply enters the PCB. DS012498-50 FIGURE 42. CCD Interface Example section. Given the required rise time and the input capacitance of the input being driven, the resistor value can be estimated from the graph. Table 3 shows the Configuration Register parameters recommended for use as a starting point for most even/odd CCDs. The Mode is set to Even/Odd, RS Pulse Width is set to its minimum value, and RS polarity is positive. The timing, shown in Figure 43, is determined by the RS, SR, and SS registers. The RS pulse position (RS) is set to 10, dividing the pixel period so that the signal portion is available for the first 5 MCLKs following a φ1 clock edge and the black reference portion appears during the last 2 MCLKs (following the 1 MCLK wide reset pulse). Sample Reference (SR) is set to 14, so it samples the black reference just before the next φ1 clock edge. Sample Signal (SS) is set to 8, so it samples the black reference just before the next reset pulse. These values can be adjusted to account for differences in CCDs, CCD data delays, settling time, etc., but this is often not necessary. 7.2 3V Compatible Digital I/O If 3V digital I/O operation is desired, the VD(I/O) pin may be powered by a separate 3V ± 10% or 3.3V ± 10% supply. In this case all the digital I/O pins (CD0–CD6, CCLK, MCLK, DD0–DD7, EOC , RD , SYNC, CS , SCLK, SDO, and SDI) will be 3V compatible. (The CCD clock signals (φ1, φ2, RS, and TR) remain 5V outputs, powered by VD.) In this case the VD(I/O) input should be bypassed to DGND(I/O) with a parallel combination of a 0.1µF capacitor and a 10µF tantalum capacitor. 7.3 Power Down Mode Setting the Power Down bit to a “1” puts the device in a low power standby mode. The CCD outputs (φ1, φ2, RS, and TR) are pulled low and the analog sections are turned off to conserve power. The digital logic will continue to operate if MCLK continues and SYNC is held high, so for minimum power dissipation MCLK should be stopped when the LM9800 enters the Power Down mode. Recovery from Power Down typically takes 50µs (the time required for the reference voltages to settle to 0.5 LSB accuracy). 8.0 TYPICAL APPLICATION Figure 42 shows the interface between the LM9800 and a typical even/odd output CCD, the TCD1250. The interface for most other CCDs will be similar, the only differences being the values for the clamp capacitor and the values for the series resistors, if needed. The clamp capacitor value is determined as shown in section 4.2. The resistor values are www.national.com DS012498-51 FIGURE 43. Typical Even/Odd Timing 30 Applications Information 9.0 HINTS AND COMMON SYSTEM DESIGN PROBLEMS (Continued) All 4 digital outputs (φ1, φ2, RS, and TR) are enabled. The TR pulse width is set to the minimum, 20 MCLKs, as is the guardband between φ1 and TR. Either of these settings can be increased if necessary. The TR polarity is positive, as is the RS polarity. Some CCDs may require one or both of these signals to be inverted, in which case the corresponding bit can be set to a “1”. If there is an inverting buffer between the LM9800 and the CCD, these bits can be also used to correct the output polarity at the CCD. Note that if φ1 and φ2 are inverted, then φ2 should be used as φ1 at the CCD, and φ1 should be used as φ2 at the CCD (Figure 44). 9.1 Reading and Writing to the Configuration Register The Configuration Register sends and receives data LSB (Least Significant Byte) first. Some microcontrollers send out data MSB (Most Significant Byte) first. The SYNC pin must be high to send/receive data to/from the Configuration Register. 9.2 Examine the CCLK and EOC Timing As explained earlier, this timing depends on the position of the Sample Reference (SR) pulse, and for some values of SR it is not what you would expect. Pay close attention to Timing Diagrams (Figures 23, 24, 25, 26). 9.3 Setting the Dummy and Optical Black Pixel Registers The minimum value in the Dummy Pixels register is 1. Note that the value in this register should be equal to 1 plus the actual number of dummy pixels in the CCD. For example, if the CCD being used with the LM9800 has 12 dummy pixels, this register should be set to 13. The minimum number in the Optical Black Pixels register is 1. DS012498-52 FIGURE 44. φ1 and φ2 After Inversion The number of dummy pixels and optical black reference pixels are given in the CCD’s datasheet. The dummy pixel register should be programmed with the number of dummy pixels in the CCD + 1 (for example, if the CCD has 16 dummy pixels then the register should contain 17). The optical black reference register should be programmed with the number of optical black pixels in the CCD. The PGA gain coefficient register and PGA Gain Source bit are used during calibration (see section 6.0). The Power Down bit should be set to 0 for normal operation. The Offset Add bit is also programmed durIng calibration. The VGA settings should be all zeros (0 0 0 0) if the VGA is not going to be used, or all ones (1 1 1 1) if the VGA will be used to provide additional input signal gain. If using a sequential color CCD, see section 4.4). The Offset DAC bits are programmed during calibration (section 6.0). The Test Mode bits should always be set to “0”. 31 www.national.com Applications Information (Continued) TABLE 3. Configuration Register Example Data A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Standard RS Pulse Width Mode or 0 0 0 Even/Odd RS Pulse Polarity RS Pulse Position (Minimum Value is 1) Mode 1 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 0 1 www.national.com 0 0 0 1 0 Sample Reference Position 1 0 Sample Signal Position 1 1 1 0 φ1 φ2 RS TR Enable Enable Enable Enable 1 1 1 1 1 0 TR Pulse Width 0 0 0 TR–φ1 TR Guardband Polarity 0 0 0 Dummy Pixels (Minimum Value is 1) Set to 1 + Number of Dummy Pixels Given in CCD Datasheet Optical Black Pixels (Minimum Value is 1) Set to Number of Optical Black Pixels Given in CCD Datasheet PGA Gain Coefficient 0 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 PGA Gain Test Power- Offset VGA VGA State VGA State VGA State Source Mode down Add On/Off Pixel c Pixel b Pixel a 0 0 0 0 1 1 1 1 PGASRC 0 0 OFFADD Offset DAC Offset DAC Offset DAC Offset DAC Sign MSB ODSIGN VOS2 Test Modes LSB VOS1 VOS0 32 0 0 0 0 33 LM9800 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor Physical Dimensions inches (millimeters) unless otherwise noted 52-Lead Plastic Leaded Chip Carrier (PLCC) Order Number LM9800CCV NS Package Number V52A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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