Very Low Power CMOS SRAM 512K X 8 bit BS62LV4006 Pb-Free and Green package materials are compliant to RoHS n FEATURES n DESCRIPTION Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption : VCC = 3.0V Operation current : 30mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 0.25uA (Typ.) at 25 OC VCC = 5.0V Operation current : 70mA (Max.) at 55ns 10mA (Max.) at 1MHz Standby current : 1.5uA (Typ.) at 25OC Ÿ High speed access time : -55 55ns (Max.) at VCC=3.0~5.5V -70 70ns (Max.) at VCC=2.7~5.5V Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE and OE options Ÿ Three state outputs and TTL compatible Ÿ Fully static operation Ÿ Data retention supply voltage as low as 1.5V The BS62LV4006 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.25uA at 3.0V/25OC and maximum access time of 55ns at 3.0V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62LV4006 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV4006 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 600mil Plastic DIP, 400 mil TSOP II, 8mmx13.4mm STSOP and 8mmx20mm TSOP package. n POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY STANDBY OPERATING TEMPERATURE VCC=5.0V BS62LV4006DC BS62LV4006EC BS62LV4006HC BS62LV4006PC BS62LV4006SC BS62LV4006STC BS62LV4006TC BS62LV4006EI BS62LV4006HI BS62LV4006PI BS62LV4006SI BS62LV4006STI BS62LV4006TI Operating (ICCSB1, Max) VCC=3.0V 1MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9mA 43mA 68mA 1.5mA 18mA 29mA Industrial -40OC to +85OC 20uA 4.0uA 10mA 45mA 70mA 2mA 20mA 30mA • BS62LV4006EC BS62LV4006EI BS62LV4006SC BS62LV4006SI BS62LV4006PC BS62LV4006PI VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 DICE TSOP II-32 BGA-36-0608 PDIP-32 SOP-32 STSOP-32 TSOP-32 TSOP II-32 BGA-36-0608 PDIP-32 SOP-32 STSOP-32 TSOP-32 n BLOCK DIAGRAM 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BS62LV4006TC BS62LV4006TI BS62LV4006STC BS62LV4006STI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 fMax. 2.0uA 1 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1MHz 10uA • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 fMax. VCC=3V 10MHz Commercial +0OC to +70OC n PIN CONFIGURATIONS A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 PKG TYPE (ICC, Max) VCC=5V 10MHz 2 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 3 4 A12 A14 A16 A18 A15 A17 A13 A8 A9 A11 Address 10 Input Decoder 5 A0 A1 NC A3 A6 A8 B DQ4 A2 WE A4 A7 DQ0 DQ5 DQ6 8 8 VSS NC A5 Data Input Buffer Data Output Buffer 8 Column I/O Write Driver Sense Amp 8 256 Column Decoder DQ7 DQ5 1024 x 4096 Buffer DQ1 DQ2 6 A D Memory Array 4096 DQ0 DQ3 DQ4 C 1024 Row DQ1 9 CE VCC WE E VCC F DQ6 G DQ7 H A9 VSS A18 A17 OE CE A16 A15 DQ3 A10 A11 A12 A13 A14 Control Address Input Buffer OE VCC DQ2 GND A7 A6 A5 A4 A3 A2 A1 A0 A0 36-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS62LV4006 1 Revision 1.4 May. 2006 BS62LV4006 n PIN DESCRIPTIONS Name Function A0-A18 Address Input These 19 address inputs select one of the 524,288 x 8-bit in the RAM CE Chip Enable Input CE is active LOW. Chip enable must be active when data read form or write to the device. If chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. DQ0-DQ7 Data Input/Output There 8 bi-directional ports are used to read data from or write data into the RAM. Ports VCC Power Supply GND Ground n TRUTH TABLE MODE CE WE OE I/O OPERATION VCC CURRENT Not selected (Power Down) H X X High Z ICCSB, ICCSB1 Output Disabled L H H High Z ICC Read L H L DOUT ICC Write L L X DIN ICC n ABSOLUTE MAXIMUM RATINGS TBIAS TSTG n OPERATING RANGE RATING UNITS RANG AMBIENT TEMPERATURE VCC Terminal Voltage with Respect to GND Temperature Under Bias -0.5(2) to 7.0 V Commercial 0OC to + 70OC 2.4V ~ 5.5V -40 to +125 O C Industrial -40OC to + 85OC 2.4V ~ 5.5V Storage Temperature -60 to +150 O C SYMBOL VTERM (1) PARAMETER PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA n CAPACITANCE O (TA = 25 C, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. R0201-BS62LV4006 (1) CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V 6 pF VI/O = 0V 8 pF 1. This parameter is guaranteed and not 100% tested. 2 Revision 1.4 May. 2006 BS62LV4006 O O n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNITS 2.4 -- 5.5 V VCC Power Supply VIL Input Low Voltage -0.5(2) -- 0.8 V VIH Input High Voltage 2.2 -- VCC+0.3(3) V IIL Input Leakage Current VCC = Max, VIN = 0V to VCC -- -- 1 UA ILO Output Leakage Current V CC = Max, CE= VIH, or OE = VIH, VI/O = 0V to V CC -- -- 1 UA VOL Output Low Voltage V CC = Max, IOL = 2.0mA -- -- 0.4 V VOH Output High Voltage V CC = Min, IOH = -1.0mA 2.4 -- -- V ICC(5) Operating Power Supply Current CE = VIL, IDQ = 0mA, f = FMAX(4) VCC=3.0V -- -- Operating Power Supply Current CE = VIL, IDQ = 0mA, f = 1MHz VCC=3.0V -- -- Standby Current – TTL CE = VIH, IDQ = 0mA VCC=3.0V -- -- Standby Current – CMOS CE≧VCC-0.2V, VIN≧V CC-0.2V or VIN≦0.2V VCC=3.0V ICC1 ICCSB ICCSB1(6) VCC=5.0V VCC=5.0V VCC=5.0V 1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. -- VCC=5.0V 30 mA 70 2 mA 10 0.5 1.0 0.25 4.0 1.5 20 mA uA 4. FMAX=1/tRC. 5. ICC (MAX.) is 29mA/68mA at VCC=3.0V/5.0V and TA=70OC. 6. ICCSB1(MAX.) is 2.0uA/10uA at VCC=3.0V/5.0V and TA=70OC. O O n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS VDR VCC for Data Retention CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V 1.5 -- -- V ICCDR(3) Data Retention Current CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V -- 0.1 1.5 uA tCDR Chip Deselect to Data Retention Time 0 -- -- ns tRC (2) -- -- ns tR See Retention Waveform Operation Recovery Time 1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCRD(Max.) is 1.0uA at TA=70OC. n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled) Data Retention Mode VCC VCC VDR≧1.5V tCDR CE R0201-BS62LV4006 VIH VCC tR CE≧VCC - 0.2V 3 VIH Revision 1.4 May. 2006 BS62LV4006 n AC TEST CONDITIONS n KEY TO SWITCHING WAVEFORMS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load WAVEFORM tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL Others CL = 30pF+1TTL ALL INPUT PULSES VCC 1 TTL Output 90% GND CL(1) 90% 10% 10% → ← Rise Time : 1V/ns → ← Fall Time : 1V/ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” WILL BE CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED CHANGE : STATE UNKNOW DOES NOT APPLY CENTER LINE IS HIGH INPEDANCE “OFF” STATE 1. Including jig and scope capacitance. O O n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. TYP. MAX. DESCRIPTION CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. MAX. UNITS tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns tE1LQV tACS Chip Select Access Time -- -- 55 -- -- 70 ns tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns tE1LQX tCLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output Low Z 5 -- -- 5 -- -- ns tE1HQZ tCHZ Chip Select to Output High Z -- -- 30 -- -- 35 ns tGHQZ tOHZ Output Enable to Output High Z -- -- 25 -- -- 30 ns tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns R0201-BS62LV4006 4 Revision 1.4 May. 2006 BS62LV4006 n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tAA tOH tOH DOUT READ CYCLE 2 (1,3,4) CE tACS tCLZ tCHZ (5) (5) DOUT READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOH tOE tOLZ CE tACS tCLZ (5) tOHZ tCHZ (5) (1,5) DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS62LV4006 5 Revision 1.4 May. 2006 BS62LV4006 O O n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION CYCLE TIME : 55ns (VCC = 3.0~5.5V) CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. UNITS tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns tE1LWH tCW Chip Select to End of Write 55 -- -- 70 -- -- ns tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns tWHAX tWR Write Recovery Time 0 -- -- 0 -- -- ns tWLQZ tWHZ Write to Output High Z -- -- 25 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns (CE, WE) n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR (3) OE tCW (11) (5) CE tAW WE tWP tAS tOHZ (2) (4,10) DOUT tDH tDW DIN R0201-BS62LV4006 6 Revision 1.4 May. 2006 BS62LV4006 WRITE CYCLE 2 (1,6) tWC ADDRESS tCW (5) CE (11) tAW tWP WE tAS tWHZ (2) (4,10) tOW (7) (8) DOUT tDW tDH (8,9) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE going low to the end of write. R0201-BS62LV4006 7 Revision 1.4 May. 2006 BS62LV4006 n ORDERING INFORMATION BS62LV4006 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE D: DICE E: TSOP II H: BGA-36-0608 P: PDIP S: SOP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n PACKAGE DIMENSIONS WITH PLATING c b c1 b1 BASE METAL SECTION A-A SOP -32 R0201-BS62LV4006 8 Revision 1.4 May. 2006 BS62LV4006 n PACKAGE DIMENSIONS (continued) STSOP - 32 TSOP - 32 R0201-BS62LV4006 9 Revision 1.4 May. 2006 BS62LV4006 n PACKAGE DIMENSIONS (continued) PDIP - 32 NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.2 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 36 mini-BGA (6 x 8mm) R0201-BS62LV4006 10 Revision 1.4 May. 2006 BS62LV4006 n PACKAGE DIMENSIONS (continued) DIMENSION (MM) 17 32 MIN. NOM. b T X 0.20 E1 -XE e 16 "X" Y Y 0.05 0.10 0.15 0.002 0.004 0.006 1.00 1.05 0.037 0.039 0.042 b 0.30 0.52 0.012 b1 0.30 0.45 0.012 c 0.12 0.21 0.005 c1 0.10 0.127 0.16 0.004 0.005 0.006 D 20.82 20.95 21.08 0.820 0.825 0.830 E 11.56 11.76 11.96 0.455 0.463 0.471 E1 10.03 10.16 10.29 0.394 0.400 0.405 0.40 0.50 0.60 0.016 A2 A R1 0.12 A1 Y 0.018 0.008 0.024 0.020 0.010 BASIC 0.8 REF 0.12 0.020 0.016 0.050 BASIC 0.25 BASIC R ZD 0.40 1.27 BASIC L2 SEATING PLANE MAX. 0.047 0.95 L1 Y NOM. A2 L D MIN. A1 e ZD MAX. 1.20 A 1 DIMENSION (INCH) 0.031 REF 0.25 0.005 0.010 0.005 0.95 REF 0.037 REF 0.10 0.004 0.44 REF -T- L1 L RAD R1 L2 0.44 REF 0°~8° c GAGE PLANE DETAIL "X" WITH PLATING c1 c b b1 RAD R BASE METAL NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS. 2. REFREENCE DOCUMENT : JEDEC MS-024 3. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE. 4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. SECTION Y-Y TSOP II - 32 R0201-BS62LV4006 11 Revision 1.4 May. 2006 BS62LV4006 n Revision History Revision No. History Draft Date 1.2 To add Icc1 characteristic parameter To improve Iccsb1 spec. I-grade from 60uA to 20uA at 5.0V 10uA to 4.0uA at 3.0V C-grade from 30uA to 10uA at 5.0V 5.0uA to 2.0uA at 3.0V Jan. 13, 2006 1.3 To Add 400 mil TSOP II package type March 20, 2006 1.4 Change I-grade operation temperature range - from –25OC to –40OC May. 25, 2006 R0201-BS62LV4006 12 Remark Revision 1.4 May. 2006