Renesas M5M5V5636GP-16 18874368-bit(524288-word by 36-bit) network sram Datasheet

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
January 14,
2003
MITSUBISHI LSIs
Rev.0.5
M5M5V5636GP –16,13
Preliminary
Notice: This is not final specification.
Some parametric limits are subject to change.
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DESCRIPTION
APPLICATION
The M5M5V5636GP is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Mitsubishi's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5V5636GP operates on 3.3V
power/ 2.5V I/O supply or a single 3.3V power supply and are
3.3V CMOS compatible.
High-end networking products that require high bandwidth, such
as switches and routers.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 167 MHz and 133MHz
• Fast access time: 3.8 ns and 4.2ns
• Single 3.3V -5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need
to control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Package
100pin TQFP
PART NAME TABLE
Part Name
Access
Cycle
Active Current
(max.)
Standby Current
(max.)
M5M5V5636GP - 16
3.8ns
6.0ns
380mA
30mA
M5M5V5636GP - 13
4.2ns
7.5ns
350mA
30mA
1/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
MCH
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
DQPa
100pin TQFP
M5M5V5636GP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A10
A11
A12
A13
A14
A15
A16
NC
NC
VDD
VSS
NC
NC
A0
A1
A2
A3
A4
A5
LBO#
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
MCH
VDD
MCH
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A9 81
A8 82
A17 83
A18 84
ADV 85
G# 86
CKE# 87
W# 88
CLK 89
VSS 90
VDD 91
E3# 92
BWa# 93
BWb# 94
BWc# 95
BWd# 96
E2 97
E1# 98
A7 99
A6 100
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
2/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
BLOCK DIAGRAM
VDD
A0
A1
A2~18
VDDQ
19
19
17
ADDRESS
REGISTER
A1'
A1
D1
LINEAR/
Q1
D0
INTERLEAVED
BURST
COUNTER
Q0
A0
A0'
LBO#
CLK
CKE#
19
WRITE ADDRESS
REGISTER1
WRITE ADDRESS
REGISTER2
19
ZZ
ADV
BYTE2
WRITE
DRIVERS
BYTE3
WRITE
DRIVERS
MEMORY
ARRAY
BYTE4
WRITE
DRIVERS
W#
36
G#
256Kx36
INPUT
INPUT
REGISTER1
REGISTER0
OUTPUT BUFFERS
AND
DATA COHERENCY
CONTROL LOGIC
OUTPUT SELECT
WRITE REGISTRY
OUTPUT REGISTERS
BWa#
BWb#
BWc#
BWd#
BYTE1
WRITE
DRIVERS
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
READ
LOGIC
E1#
E2
E3#
VSS
Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic.
Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
3/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PIN FUNCTION
Pin
Function
Name
A0~A18
Synchronous
Address
Inputs
These inputs are registered and must meet the setup and hold times around the rising edge of
CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
BWa#, BWb#,
BWc#, BWd#
Synchronous
Byte Write
Enables
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWs are associated with addresses and apply to
subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#
controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.
CLK
Clock Input
This signal registers the address, data, chip enables, byte write enables
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock's rising edge.
E1#
Synchronous
Chip Enable
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW).
E2
Synchronous
Chip Enable
This active High input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
E3#
Synchronous
Chip Enable
This active Low input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
G#
Output Enable
This active LOW asynchronous input enable the data I/O output drivers.
ADV
Synchronous
Address
Advance/Load
CKE#
Synchronous
Clock Enable
When HIGH, this input is used to advance the internal burst counter, controlling burst access after
the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new
address to be loaded at CLK rising edge.
This active LOW input permits CLK to propagate throughout the device. When HIGH, the device
ignores the CLK input and effectively internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
This active HIGH asynchronous input causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active, all other inputs are ignored. When this
pin is LOW or NC, the SRAM normally operates.
ZZ
Snooze
Enable
W#
Synchronous
Read/Write
This active input determines the cycle type when ADV is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
DQa,DQPa,DQb,DQPb
DQc,DQPc,DQd,DQPd
Synchronous
Data I/O
Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is
DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge.
Burst Mode
Control
This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is
HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input
leak current to this pin.
VDD
VDD
Core Power Supply
VSS
LBO#
VSS
Core Ground
VDDQ
VDDQ
I/O buffer Power supply
VSSQ
VSSQ
I/O buffer Ground
MCH
Must Connect High
These pins should be connected to HIGH
No Connect
These pins are not internally connected and may be connected to ground.
NC
4/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name
Input Status
LBO#
HIGH or NC
LOW
Operation
Interleaved Burst Sequence
Linear Burst Sequence
Note4. LBO# is DC operated pin.
Note5. NC means No Connection.
Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
A18~A2
First access, latch external address
Second access(first burst address)
Third access(second burst address)
Fourth access(third burst address)
A1,A0
A18~A2
latched A18~A2
latched A18~A2
latched A18~A2
0,1
0,0
1,1
1,0
0,0
0,1
1,0
1,1
1,0
1,1
0,0
0,1
1,1
1,0
0,1
0,0
Linear Burst Sequence (when LBO# = LOW)
Operation
A18~A2
A1,A0
First access, latch external address
A18~A2
0,0
0,1
1,0
1,1
Second access(first burst address)
latched A18~A2
0,1
1,0
1,1
0,0
Third access(second burst address)
latched A18~A2
1,0
1,1
0,0
0,1
Fourth access(third burst address)
latched A18~A2
1,1
0,0
0,1
1,0
Note7. The burst sequence wraps around to its initial state upon completion.
TRUTH TABLE
Address
E1#
E2
E3#
ZZ
ADV
W#
BWx#
G#
CKE#
CLK
DQ
H
X
X
X
L
X
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
L
L->H
High-Z
None
L->H
High-Z
None
L->H
High-Z
None
Deselect Cycle
Deselect Cycle
Deselect Cycle
X
X
X
L
H
X
X
X
L
L->H
High-Z
None
Continue Deselect Cycle
L
X
L
X
H
X
H
X
L
X
L
X
L
L
L
L
L
H
L
H
H
X
H
X
X
X
X
X
L
L
H
H
L
L
L
L
L->H
Q
External
L
X
L
X
H
X
H
X
L
X
L
X
L
L
L
L
L
H
L
H
L
X
L
X
L
L
H
H
X
X
X
X
L
L
L
L
X
X
X
L
X
X
X
X
H
used
L->H
Q
Next
L->H
High-Z
External
L->H
High-Z
Next
L->H
D
External
L->H
D
Next
L->H
High-Z
None
L->H
High-Z
Next
L->H
-
Current
Operation
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Dummy Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Ignore Clock edge, Stall
X
X
X
H
X
X
X
X
X
Snooze Mode
X
High-Z
None
Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL.
Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more
Synchronous Byte Write Enables are LOW.
Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
STATE DIAGRAM
F,L,X
Deselect
F,L,X
T,L,H
T,L,L
X,H,X
Read
Begin
Burst
T,L,H
X,H,X
T,L,H
Write
Begin
Burst
T,L,L
T,L,H
X,H,X
X,H,X
Read
Continue
Burst
T,L,L
Key
F,L,X
T,L,H
T,L,L
T,L,L
Write
Continue
Burst
X,H,X
Input Command Code
f
Current State
Transition
Next State
Note11. The notation "x , x , x" controlling the state transitions above indicate the state of inputs E, ADV and W# respectively.
Note12. If (E1# = L and E2 = H and E3# = L) then E="T" else E="F".
Note13. "H" = input VIH; "L" = input VIL; "X" = input VIH or VIL; "T" = input "true"; "F" = input "false".
6/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
WRITE TRUTH TABLE
W#
BWa#
BWb#
BWc#
BWd#
H
X
X
X
X
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Function
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write Abort/NOP
L
H
H
H
H
Note14. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL.
Note15. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VDDQ
VI
VO
PD
TOPR
TSTG(bias)
TSTG
Parameter
Conditions
Power Supply Voltage
I/O Buffer Power Supply Voltage
Input Voltage
Output Voltage
Maximum Power Dissipation (VDD)
Operating Temperature
Storage Temperature(bias)
With respect to VSS
Ratings
Unit
-1.0*~4.6
-1.0*~4.6
-1.0~VDDQ+1.0**
-1.0~VDDQ+1.0**
1180
0~70
-10~85
-65~150
V
Storage Temperature
Note16.* This is –1.0V when pulse width≤2ns, and –0.5V in case of DC.
** This is –1.0V~VDDQ+1.0V when pulse width≤2ns, and –0.5V~VDDQ+0.5V in case of DC.
V
V
V
mW
°C
°C
°C
7/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=3.135~3.465V, unless otherwise noted)
Limits
Symbol
Parameter
VDD
Power Supply Voltage
VDDQ
I/O Buffer Power Supply Voltage
VIH
VIL
Condition
Unit
Min
Max
3.135
3.465
VDDQ = 3.3V
3.135
3.465
VDDQ = 2.5V
2.375
2.625
VDDQ = 3.135~3.465V
2.0
VDDQ = 2.375~2.625V
1.7
High-level Input Voltage
VDDQ = 3.135~3.465V
-0.3*
Low-level Input Voltage
VDDQ = 2.375~2.625V
VDDQ+0.3*
0.8
0.7
VOH
High-level Output Voltage
IOH = -2.0mA
VOL
Low-level Output Voltage
IOL = 2.0mA
0.4
Input Leakage Current except ZZ
and LBO#
VI = 0V ~ VDDQ
10
Input Leakage Current of LBO#
VI = 0V ~ VDDQ
100
Input Leakage Current of ZZ
VI = 0V ~ VDDQ
100
Off-state Output Current
VI (G#) ≥ VIH, VO = 0V ~ VDDQ
Power Supply Current : Operating
Device selected;
Output Open
VI≤VIL or VI≥VIH
ZZ≤VIL
ILI
ILO
ICC1
ICC2
Power Supply Current : Deselected
ICC3
CMOS Standby Current
(CLK stopped standby mode)
ICC4
Snooze Mode Standby Current
ICC5
Stall Current
Device
deselected
VI≤VIL or VI≥VIH
ZZ≤VIL
VDDQ-0.4
V
V
V
V
V
10
6.0ns cycle(167MHz)
380
7.5ns cycle(133MHz)
350
6.0ns cycle(167MHz)
160
7.5ns cycle(167MHz)
130
V
µA
µA
mA
Device deselected; Output Open
VI≤VSS+0.2V or VI≥VDDQ-0.2V
CLK frequency=0Hz, All inputs static
Snooze mode
ZZ≥VDDQ-0.2V, LBO#≥VDD-0.2V
Device selected;
6.0ns cycle(167MHz)
Output Open
CKE#≥VIH
VI≤VSS+0.2V or
7.5ns cycle(133MHz)
VI≥VDDQ-0.2V
Note17.*VILmin is –1.0V and VIH max is VDDQ+1.0V in case of AC(Pulse width≤2ns).
Note18."Device Deselected" means device is in power-down mode as defined in the truth table.
mA
30
mA
30
mA
130
mA
120
8/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
CAPACITANCE
Symbol
Parameter
CI
CO
Limits
Conditions
Input Capacitance
Min
Typ
Unit
6
8
VI=GND, VI=25mVrms, f=1MHz
Input / Output(DQ) Capacitance
Note19.This parameter is sampled.
Max
VO=GND, VO=25mVrms, f=1MHz
pF
pF
THERMAL RESISTANCE
4-Layer PC board mounted (70x70x1.6mmT)
Symbol
Parameter
θJA
Limits
Conditions
Thermal Resistance Junction Ambient
Min
Typ
Max
28.18
20.33
6.64
Air velocity=0m/sec
Air velocity=2m/sec
θJC
Thermal Resistance Junction to Case
Note20.This parameter is sampled.
Unit
°C/W
°C/W
°C/W
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=3.135~3.465V, unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels ········································ VIH=VDDQ, VIL=0V
Input rise and fall times ······························· faster than or equal to 1V/ns
Input timing reference levels ······················· VIH=VIL=0.5*VDDQ
Output reference levels ·······························VIH=VIL=0.5*VDDQ
Output load ·················································· Fig.1
30pF
(Including wiring and JIG)
Q
ZO=50Ω
50Ω
VT=0.5*VDDQ
Fig.1 Output load
Input
Waveform
VDDQ / 2
toff
tplh
Output
Waveform
Input
Waveform
VDDQ / 2
VDDQ / 2
Fig.2 Tdly measurement
tphl
Vh
Output
Waveform
(toff)
Vl
ton
Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz))
Vz
0.2(Vz-Vl)
Vz-(0.2(Vz-Vl))
(ton)
Fig.3 Tri-State measurement
Note21.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform.
Input waveform should have a slew rate of faster than or equal to 1V/ns.
Note22.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%
from its initial to final Value VDDQ/2.
Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.
Note23. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%
from its initial Value VDDQ/2 to its final Value.
Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.
Note24.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns.
9/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(2)TIMING CHARACTERISTICS
Limits
Symbol
Parameter
Clock
tKHKH
Clock cycle time
tKHKL
Clock HIGH time
tKLKH
Clock LOW time
Output times
Clock HIGH to output valid
tKHQV
Clock HIGH to output invalid
tKHQX
Clock HIGH to output in LOW-Z
tKHQX1
Clock HIGH to output in High-Z
tKHQZ
G# to output valid
tGLQV
tGLQX1
G# to output in Low-Z
tGHQZ
G# to output in High-Z
Setup Times
tAVKH
Address valid to clock HIGH
tckeVKH
CKE# valid to clock HIGH
tadvVKH
ADV valid to clock HIGH
tWVKH
Write valid to clock HIGH
tBVKH
Byte write valid to clock HIGH (BWa#~BWd#)
tEVKH
Enable valid to clock HIGH (E1#,E2,E3#)
tDVKH
Data In valid clock HIGH
Hold Times
tKHAX
Clock HIGH to Address don’t care
tKHckeX
Clock HIGH to CKE# don’t care
tKHadvX
Clock HIGH to ADV don’t care
tKHWX
Clock HIGH to Write don’t care
tKHBX
tKHEX
tKHDX
ZZ
tZZS
tZZREC
Clock HIGH to Byte Write don’t care
(BWa#~BWb#)
Clock HIGH to Enable don’t care (E1#,E2,E3#)
Clock HIGH to Data In don’t care
167MHz
-16
Min
Max
133MHz
-13
Min
Max
6.0
2.7
2.7
7.5
3.0
3.0
3.8
1.5
1.5
1.5
3.8
3.8
0.0
ns
ns
ns
4.2
1.5
1.5
1.5
4.2
4.2
0.0
3.8
Unit
4.2
ns
ns
ns
ns
ns
ns
ns
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
0.5
0.5
ns
0.5
0.5
0.5
0.5
ns
ns
ZZ standby
2*tKHKH
ZZ recovery
2*tKHKH
Note25.All parameter except tZZS, tZZREC in this table are measured on condition that ZZ=LOW fix.
Note26.Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted.
Note27. tKHQX1, tKHQZ, tGLQX1, tGHQZ are sampled.
Note28.LBO# is static and must not change during normal operation.
2*tKHKH
2*tKHKH
ns
ns
10/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(3)READ TIMING
tKHKH
CLK
tKHKL
tKLKH
tckeVKH
tKHckeX
CKE#
tEVKH
tKHEX
E#
tadvVKH
tKHadvX
ADV
tWVKH
tKHWX
W#
BWx#
tAVKH
ADD
tKHAX
A1
A2
A3
tKHQX1
DQ
tGLQV
Q(A1)
tKHQV
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
tGHQZ
tKHQX
Q(A2)
Q(A3)
Q(A3+1)
tKHQZ
tGLQX1
G#
Read A1
Read A2
Burst Read
A2+1
Stall
Burst Read Burst Read Burst Read
A2+2
A2+3
A2
Deselect
Continue
Deselect
Read A3
Burst Read Burst Read Burst Read
A3+1
A3+2
A3+3
DON'T CARE
UNDEFINED
Note29.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note30. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note31.ZZ is fixed LOW.
11/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(4)WRITE TIMING
tKHKH
CLK
tKHKL
tKLKH
tckeVKH
tKHckeX
CKE#
tEVKH
tKHEX
E#
tadvVKH
tKHadvX
ADV
tWVKH
tKHWX
W#
tBVKH
tKHBX
BWx#
tAVKH
ADD
tKHAX
A1
A2
A3
A4
tDVKH
tKHDX
DQ
D(A1)
D(A2)
D(A2+1)
D(A2+3)
D(A2)
D(A3)
D(A4)
D(A4+1)
G#
Write A1
Write A2
Burst Write
A2+1
NOP
Burst Write
A2+3
Write A2
Write A3
NOP
Write A4
Burst Write
A4+1
Stall
Burst Write Burst Write
A4+2
A4+3
DON'T CARE
UNDEFINED
Note32.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note33. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note34.ZZ is fixed LOW.
12/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(5)READ/WRITE TIMING
tKHKH
CLK
tKHKL
tKLKH
tckeVKH
tKHckeX
CKE#
tEVKH
tKHEX
E#
tadvVKH
tKHadvX
ADV
tWVKH
tKHWX
W#
tBVKH
tKHBX
BWx#
tAVKH
ADD
tKHAX
A1
A2
A2
A3
A3
A4
A5
tDVKH
tKHQX1
tKHDX
DQ
Q(A1)
tKHQV
D(A2)
Q(A2)
D(A3)
D(A3+1)
Q(A3)
Q(A3+1)
D(A4)
Q(A5)
tKHQV
G#
Read A1
Write A2
Read A2
Write A3
Burst Write
A3+1
Read A3
Burst Read
A3+1
Deselect
Write A4
Stall
Read A5
DON'T CARE
Burst Read Burst Read
A5+1
A5+2
UNDEFINED
Note35.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note36. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note37.ZZ is fixed LOW.
13/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(6)SNOOZE MODE TIMING
CLK
tZZS
tZZREC
ZZ
All Inputs
(except ZZ)
DESELECT or READ only
Q
Snooze Mode
14/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PACKAGE OUTLINE
Plastic 100pin 14x20 mm body
22±0.2
*2
20±0.1
80
0.125+0.05
-0.02
51
50
100
31
1
30
A
*3
0.1
0.32+0.06
-0.07
0.13 M
0°~7°
0.125±0.075
0.65 Nom
(1.4)
1.6 MAX
*1
14±0.2
16±0.2
81
0.5±0.15
Detail A
Note38. Dimensions *1 and *2 don't include mold flash.
Note39 Dimension *3 doesn't include trim off set.
Note40.All dimensions in millimeters.
15/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
REVISION HISTORY
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
History
First revision
Fixed WRITE TRUTH TABLE
Fixed Note8,13 and 14
Add –13(133MHz)
Fixed THERMAL RESISTANCE
Preliminary
DC ELECTRICAL CHARACTERISTICS
Changed VIH limit from 0.65VDDQ to 2.0 at 3.3V VDDQ
Changed VIH limit from 0.65VDDQ to 1.7 at 2.5V VDDQ
Changed VIL limit from 0.35VDDQ to 0.8 at 3.3V VDDQ
Changed VIL limit from 0.35VDDQ to 0.7 at 2.5V VDDQ
Changed ICC1 limit from 340mA to 380mA at 167MHz(-16)
Changed ICC1 limit from 320mA to 350mA at 133MHz(-13)
Changed ICC2 limit from 90mA to 160mA at 167MHz(-16)
Changed ICC2 limit from 80mA to 130mA at 133MHz(-13)
Changed ICC5 limit from 45mA to 130mA at 167MHz(-16)
Changed ICC5 limit from 40mA to 120mA at 133MHz(-13)
AC ELECTRICAL CHARACTERISTICS
Changed tKHKL limit from 2.0ns to 2.7ns at 167MHz(-16)
Changed tKLKH limit from 2.0ns to 2.7ns at 167MHz(-16)
Changed tKHQX limit from 0.8ns to 1.5ns
Changed tKHQX1 limit from 0.8ns to 1.5ns
Changed tKHQZ limit from 0.8ns to 1.5ns
DC ELECTRICAL CHARACTERISTICS
Changed ILI limit from 10uA to 100uA
(Input Leakage Current of ZZ and LBO#)
Changed Icc3 and Icc4 limit from 20mA to 30mA
(Standby Current)
Date
June 4, 2001
July 16, 2001
March 28, 2002
Advanced Information
Advanced Information
Advanced Information
July 5, 2002
Preliminary
August 6, 2002
Preliminary
January 14, 2003
Preliminary
16/17
Preliminary
M5M5V5636GP REV.0.5
MITSUBISHI LSIs
M5M5V5636GP –16,13
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
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17/17
Preliminary
M5M5V5636GP REV.0.5