ams AS1339-BWLT 650ma rf step-down dc-dc for pa, with two ldo Datasheet

AS1339
D a ta s h e e t
6 5 0 m A R F St e p - D o w n D C - D C f o r PA, w i t h t w o L D O s
1 General Description
2 Key Features
The AS1339 is a high-frequency step-down converter
optimized for dynamically powering the power amplifier
(PA) in WCDMA or NCDMA handsets. The device uses
a 110mΩ typical bypass FET to power the PA directly
from the battery during high-power transmission. The IC
integrates two 10mA low-noise, low-dropout regulators
(LDOs) for PA biasing.
!
Fixed Switching Frequency: 2MHz
!
PA Step-Down Converter
!
Low Dropout Voltage
!
Low Output-Voltage Ripple
!
Dynamic Output Voltage Control (0.8V to 3.75V)
With a switching frequency of 2MHz, the device allows
optimization for smallest solution size or highest
efficiency. The AS1339 supports fast switching using
small ceramic 10μF input and 4.7µF output capacitors to
maintain low ripple voltage.
!
30µs Settling Time for 0.8V to 3.4V Output Voltage
Change
!
650mA Output Drive Capability
!
Two 10mA Low-Noise LDOs
The AS1339 uses an analog input driven by an external
DAC to control the output voltage linearly for continuous
PA power adjustment. The gain from REFIN to OUT is
2.5V/V. At high-duty cycle, the device automatically
switches to a bypass mode, connecting the input to the
output through a low-impedance MOSFET. The LDOs
are designed for low-noise operation, wherein each LDO
in the device is individually enabled through its own logic
control interface. The device is available in a 16-pin
WLP (2x2mm) package.
!
Low Shutdown Current
!
Supply Voltage Range: 2.7V to 5.5V
!
Thermal Shutdown
!
16-pin WLP (2x2mm) package
3 Applications
The AS1339 is ideal for WCDMA/NCDMA cellular
handsets, Wireless PDAs, and Smartphones.
Figure 1. Typical Operating Circuit
VIN
2.7V to 5.5V
10µF
IN1A
VPA
0.8V to 3.75V
PAA
PAB
IN1B
LX
2.2µH
4.7µF
Analog Control
REFIN
PA ON/OFF
PA_EN
LDO1 ON/OFF
EN1
LDO2 ON/OFF
EN2
NC
TEST
PGND
NC
AS1339
LDO1
0.1µF
VIN
2.7V to 5.5V
1µF
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2.85V
LDO2
IN2
AGND
Revision 1.04
2.85V
0.1µF
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AS1339
Datasheet - P i n o u t
4 Pinout
Figure 2. Pin Assignments (Top View)
NC
AGND
REFIN
PGND
A1
A2
A3
A4
LDO2
PA_EN
EN2
LX
B1
B2
B3
B4
IN2
TEST
IN1B
IN1A
C1
C2
C3
C4
LDO1
EN1
PAB
PAA
D1
D2
D3
D4
Pin Description
Table 1. Pin Description
Pin Name
Pin Number
NC
A1
Not Connected. Free, high impedance for normal operation. Used for
internal test purpose.
AGND
A2
Low-Noise Analog Ground
REFIN
A3
DAC-Controlled Input. Reference voltage for buck converter. The output of
the PA step-down converter is regulated to 2.5 x VREFIN. Bypass mode is
enabled when VIN ≤ 2.69V x VREFIN.
PGND
A4
Power Ground for PA Step-Down Converter
LDO2
B1
10mA LDO Regulator 2 Output. Connect LDO2 with a 0.1μF ceramic
capacitor as close as possible to LDO2 and AGND. LDO2 is internally pulled
down through a 100Ω resistor when this regulator is disabled.
PA_EN
B2
PA Step-Down Converter Enable Input. For normal operation, connect to
logic-high. For shutdown mode, connect to logic-low. The pin is internally
pulled down through a 110kΩ resistor.
EN2
B3
Enable Input for LDO2. For normal operation, connect to logic-high. For
shutdown mode, connect to logic-low. The pin is internally pulled down
through a 110kΩ resistor.
LX
B4
Inductor Connection. Connect an inductor from LX to the output of the PA
step-down converter.
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Description
Revision 1.04
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AS1339
Datasheet - P i n o u t
Table 1. Pin Description
Pin Name
Pin Number
Description
IN2
C1
Supply Voltage Input for LDO1 and LDO2. Connect IN2 to a battery or
supply voltage from 2.7V to 5.5V. Decouple IN2 with a 1μF ceramic
capacitor as close as possible to IN2 and AGND. Connect IN2 to the same
source as IN1A and IN1B.
TEST
C2
NC. Used for internal test purpose. The pin is internally pulled down with a
110kΩ resistor.
IN1B, IN1A
C3, C4
Supply Voltage Input for PA Step-Down Converter. Connect IN1A/B to a
battery or supply voltage from 2.7V to 5.5V. Decouple IN1A/B with a 10μF
ceramic capacitor as close as possible to IN1A/B, and PGND. IN1A and
IN1B are internally connected together. Connect IN1A/B to the same source
as IN2.
LDO1
D1
10mA LDO Regulator 1 Output. Decouple LDO1 with a 0.1μF ceramic
capacitor as close as possible to LDO1 and AGND. LDO1 is internally pulled
down through a 100Ω resistor when this regulator is disabled.
EN1
D2
Enable Input for LDO1. For normal operation, connect to logic-high. For
shutdown mode, connect to logic-low. The pin is internally pulled down
through a 110kΩ resistor.
PAB, PAA
D3, D4
PA Connection for Bypass Mode. Internally connected to IN1A/B using
the internal bypass MOSFET during bypass mode. Connect PAA/B with a
4.7μF ceramic capacitor as close as possible to PAA/B and PGND.
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Revision 1.04
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AS1339
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
IN1A, IN1B, IN2 to AGND
-0.3
+7
V
PAA, PAB, PA_EN, TEST, REFIN,
NC to AGND
-0.3
VIN1A/
VIN1B +
0.3
V
LDO1, LDO2, EN1, EN2 to AGND
-0.3
VIN2 +
0.3
V
IN2 to IN1B/IN1A
-0.3
+0.3
V
PGND to AGND
-0.3
+0.3
V
LX Current
0.7
ARMS
Bypass Current
1.6
ARMS
+150
ºC
Storage Temperature Range
-65
Comments
+260
ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020D “Moisture/Reflow
Sensitivity Classification for Non-Hermetic Solid
State Surface Mount Devices”.
1
kV
HBM MIL-Std. 883E 3015.7 methods
VIN
V
Recommended Load Current
650
mA
Continuous Power Dissipation
PD-MAX
0.75
W
+125
ºC
Package Body Temperature
ESD Rating
Human Body Model
Operating Ratings
REFIN Common-Mode Range
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
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0
-40
-40
+85
ºC
Revision 1.04
TA = +65ºC; derate 12.5mW/ºC above +65ºC
In applications where high power dissipation
and/or poor package thermal resistance is
present, the maximum ambient temperature
may have to be derated.
Maximum ambient temperature (TA-MAX) is
dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125ºC), the maximum
power dissipation
of the device in the application (PD-MAX), and the
junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by
the following
equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
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AS1339
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VIN1A = VIN1B = VIN2 = VPA_EN = VEN1 = VEN2 = 3.6V, TA = -40ºC to +85ºC. Typical values are at TA =+25ºC, (unless
otherwise specified), for external components refer to Table 5 on page 7.
Table 3. Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
5.5
V
Input Supply
VIN
ISHDN
IQ
Input Voltage Range
2.7
1
Shutdown Supply Current
VPA_EN = VEN1 = VEN2 = 0V
0.1
1
µA
DC-DC No-Load Supply
Current
VEN1 = VEN2 = 0V, ILOAD(DCDC) = 0mA,
switching, VIN = 4.5V, VOUT = 3.4V
4.5
6
mA
3.85
V
DCDC Output Voltage
Output Voltage Range
VOUT
Output Voltage
PWM Mode
0.8
VREFIN = 0.32V, VIN = 3.9V
0.75
0.8
0.85
V
VREFIN = 0.84V, VIN = 3.9V
2.05
2.1
2.15
V
VREFIN = 1.36V, VIN = 3.9V
3.319
3.4
3.481
V
Thermal Protection
Thermal Shutdown
TA rising, 10ºC typical hysteresis
+140
ºC
Logic Control
PA_EN, EN1, EN2, LogicInput High Voltage
2.7V ≤ VIN ≤ 5.5V
PA_EN, EN1, EN2, LogicInput Low Voltage
2.7V ≤ VIN ≤ 5.5V
VIL = 0V
Logic-Input Current
(PA_EN, EN1, EN2)
1.4
V
-1
VIH = VIN = 5.5V
50
0.5
V
+1
µA
75
µA
1.5
V
REFIN
REFIN Operating
Common-Mode Range
REFIN gain VOUT/VREFIN
0.32
2
REFIN Current
VREFIN = 0.32V
2.35
2.50
2.65
V/V
VREFIN = 0.84V, 1.36V
2.44
2.50
2.56
V/V
+1
µA
VREFIN = VIN = 5.5V
-1
LX
RDSONP Pin-Pin Resistance for PFET
RDSONN Pin-Pin Resistance for NFET
fOSC
ISW = 200mA; TA = +25°C
110
ISW = 200mA
200
230
ISW = -200mA; TA = +25°C
230
ISW = -200mA
415
485
mΩ
mΩ
PFET Leakage Current
VIN = 5.5V, VLX = 0V
0.1
3
µA
NFET Leakage Current
VIN = VLX = 5.5V
0.1
3
µA
PFET Peak Current Limit
VLX = 0V
1100
Internal Oscillator Frequency
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1.8
Revision 1.04
2
mA
2.2
MHz
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AS1339
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
2.56
2.69
2.78
V/V
110
200
BYPASS
VREFIN rising, 50mV hysteresis
Bypass Activation Factor
On-Resistance Bypass PFET
ISW = 200mA; TA = +25°C
ISW = 200mA
230
PFET Bypass Off-Leakage
Current
VIN = 5.5V,
VPAA = VPAB = 0V
Output Voltage
IOUT = 0mA, 10mA;
mΩ
0.1
3
µA
2.85
2.95
V
25
50
40
80
35
50
IOUT = 10mA
20
50
VEN1/2 = 0V
100
LDO1/2
one LDO enabled
Quiescent Current
both LDOs enabled
2.75
IOUT = 0mA
Output Current
10
VOUT = 0V
Current Limit
Dropout Voltage
ROFF
3
Shutdown Output Impedance
20
µA
mA
mV
Ω
1. Current into supply pins without leakage of DCDC switches.
2. Limited by the 50mV output voltage accuracy for VREFIN < 0.84V
3. The dropout voltage is the input to output difference at which the output is 100mV below its nominal value.
System Characteristics
VIN1A = VIN1B = VIN2 = VPA_EN = VEN1 = VEN2 = 3.9V, TA = -40ºC to +85ºC. Typical values are at TA =+25ºC, (unless
otherwise specified), for external components refer to Table 5 on page 7. The following parameters are verified by
characterisation and are not production tested.
Table 4. System Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
3
%
2.4
%
±10
50
mV
VOUT = 0.8 to 3.4V, RLOAD = 8Ω, no
bypass mode, no pulse-skip condition
10
25
Line_tr Line transient response
VIN = 3.4 to 3.9V, VOUT = 3.0V,
IOUT = 300mA, VIN increase 300mV in
10µs
30
50
Load_tr Load transient response
VIN = 3.4 to 4.2V, VOUT = 3.0V,
TRISE = TFALL = 10µs, IOUT = 100 to
300mA
50
70
REFIN
REFIN gain variation;
relative linearity
0.32V ≤ VREFIN ≤ 1.4V
1
REFIN gain variation;
absolute linearity
2
0.84V ≤ VREFIN ≤ 1.4V
-2.4
0.32V ≤ VREFIN ≤ 0.84V
-50
LX
Ripple voltage, PWM mode
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3
Revision 1.04
mVp-p
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AS1339
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. System Characteristics (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Start-Up Time
From PA_EN switch from 0V to 1.7V,
VOUT = 3.4V, ILOAD = 0mA, within 50mV
regulation error
100
150
Regulation Time; Rise Time
VOUT from 0.8V to 3.4V, RLOAD = 8Ω,
within 50mV regulation error
30
50
Regulation Time; Fall Time
VOUT from 3.4V to 0.8V, RLOAD = 8Ω,
within 50mV regulation error
30
50
Start-Up Time
IOUT=10mA, within 100mV of VOUT
30
50
Shut-Down Time
IOUT=0mA, within 100mV of GND
50
100
Unit
µs
LDO
Line Regulation
4
Load Regulation
5
Ripple Rejection
6
Output Noise
VIN = 4V to 3.5V; IOUT = 10mA;
10
IOUT stepped from 50µA to 10mA
25
IOUT = 4mA, VIN = 3.2V, f = 100kHz
45
IOUT = 4mA, VIN = 3.2V, f = 2MHz
45
10Hz to 100kHz, IOUT = 10mA
µs
mV
dB
50
100
µVRMS
1. The relative linearity is defined as the difference of the minimum to the maximum gain over the entire REFIN
range.
2. The absolute linearity is defined as the actual gain error (AE) of every applied VREFIN voltage between 0.32V
and 1.4V.
V OUT
AE = ⎛ --------------------------------- – 1⎞ × 100
⎝ 2, 5 × V REFIN ⎠
3. The ripple voltage should measured at COUT electrode on good layout PC board and under condition using suggested inductors and capacitors.
4. For dynamic change in VOUT (Line transient response) when VIN drops 500mV from 4V (see Figure 48 on page
15); Slew rate= 40mV/µs.
5. VRIPPLE = 200mVpp; TA = +25°C; CIN1, CIN2 removed; PA_EN = 0V;
6. VIN = 3.2V; TA = +25°C; PA_EN = 3.2V;
Table 5. External Components used for Characterisation
Name
Part Number
Value
Rating
Type
Size
CIN1
GRM21BR60J106KE01
10µF
6.3V
X5R
0805
CIN2
GRM155R61A105KE15
1µF
10V
X5R
0402
COUT
C0603C475K8PAC7867
4.7µF
10V
X5R
0603
CLDO1, CLDO2
C0402C104K4RAC
100nF
16V
X7R
0402
L
MLP2520S3R3S
3.3µH
1A
110mΩ
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Revision 1.04
Manufacturer
Murata
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KEMET
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TDK
2.2x2.0x1.4mm www.coilcraft.com
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AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
7 Typical Operation Characteristics
Figure 3. DC-DC Efficiency vs. VOUT; RLOAD = 5Ω
Figure 4. DC-DC Efficiency vs. VOUT; RLOAD = 7.5Ω
100
100
95
95
90
Bypass Mode
85
80
75
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
70
65
Efficiency (%)
Efficiency (%)
90
Bypass Mode
85
80
75
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
70
65
60
60
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
0.6
1
1.4
Output Voltage (V)
Figure 5. DC-DC Efficiency vs. VOUT; RLOAD = 10Ω
1.6
95
1.4
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
65
REFIN (V)
Efficiency (%)
80
70
3
3.4
3.8
1
0.8
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
0.6
0.4
60
0.2
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
0.6
Output Voltage (V)
Figure 7. DC-DC REFIN vs. VOUT; RLOAD = 7.5Ω
1.6
1.6
1.4
1.4
1.2
1.2
1
0.8
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
0.6
0.4
0.2
1
1.4
1.8
2.2
2.6
3
Output Voltage (V)
3.4
3.8
Figure 8. DC-DC REFIN vs. VOUT; RLOAD = 10Ω
REFIN (V)
REFIN (V)
2.6
1.2
Bypass Mode
85
75
2.2
Figure 6. DC-DC REFIN vs. VOUT; RLOAD = 5Ω
100
90
1.8
Output Voltage (V)
1
0.8
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
0.6
0.4
0.2
0.6
1
1.4
1.8
2.2
2.6
3
Output Voltage (V)
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3.4
3.8
0.6
Revision 1.04
1
1.4
1.8
2.2
2.6
3
Output Voltage (V)
3.4
3.8
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AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 10. DC-DC Efficiency vs. IOUT; VOUT = 1.2V
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
Figure 9. DC-DC Efficiency vs. IOUT; VOUT = 0.8V
70
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
60
50
10
100
60
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
50
40
1
70
40
1000
1
Output Current (mA)
100
100
90
90
80
80
70
60
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
50
1000
70
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
60
50
40
40
1
10
100
1
1000
Figure 13. DC-DC Load Regulation, VOUT vs. IOUT;
VOUT = 0.8V
0.81
1.21
Output Voltage (V)
1.22
0.8
0.79
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
0.77
100
1000
Figure 14. DC-DC Load Regulation, VOUT vs. IOUT;
VOUT = 1.2V
0.82
0.78
10
Output Current (mA)
Output Current (mA)
Output Voltage (V)
100
Figure 12. DC-DC Efficiency vs. IOUT; VOUT = 2.2V
Efficiency (%)
Efficiency (%)
Figure 11. DC-DC Efficiency vs. IOUT; VOUT = 1.8V
10
Output Current (mA)
1.2
1.19
1.18
Vin = 2.7V
Vin = 3.3V
Vin = 3.9V
1.17
0.76
Vin = 3.0V
Vin = 3.6V
1.16
1
10
100
1000
Output Current (mA)
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1
10
100
1000
Output Current (mA)
Revision 1.04
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AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 16. DC-DC Load Regulation, VOUT vs. IOUT;
VOUT = 2.2V
1.83
2.23
1.82
2.22
Output Voltage (V)
Output Voltage (V)
Figure 15. DC-DC Load Regulation, VOUT vs. IOUT;
VOUT = 1.8V
1.81
1.80
1.79
Vin = 2.7V
Vin = 3.3V
Vin = 3.9V
1.78
Vin = 3.0V
Vin = 3.6V
2.21
2.20
2.19
1.77
10
100
1000
1
Output Current (mA)
100
100
95
95
Bypass
PWM
Mode
Mode
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
100
90
Bypass
PWM
Mode
Mode
1000
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
85
80
80
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Input Voltage (V)
Input Voltage (V)
Figure 19. DC-DC Efficiency vs VIN; VOUT = 2.0V
Figure 20. DC-DC Efficiency vs VIN; VOUT = 1.5V
100
100
90
90
Efficiency (%)
Efficiency (%)
10
Output Current (mA)
Figure 18. DC-DC Efficiency vs VIN; VOUT = 3.4V
Efficiency (%)
Efficiency (%)
Figure 17. DC-DC Efficiency vs VIN; VOUT = 3.8V
85
Vin = 3.0V
Vin = 3.6V
2.17
1
90
Vin = 2.7V
Vin = 3.3V
Vin = 3.9V
2.18
80
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
70
80
70
60
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
60
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Input Voltage (V)
Input Voltage (V)
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AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 21. DC-DC Efficiency vs Input Voltage;
VOUT = 1.0V
Figure 22. DC-DC Line Regulation, VOUT vs. VIN;
VOUT = 3.8V
100
4.5
4
Output Voltage (V)
Efficiency (%)
90
80
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
70
Mode
3
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
2.7 3.05
Input Voltage (V)
4
2.02
Output Voltage (V)
2.03
3.5
PWM
Mode
Mode
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
2.5
2.00
1.99
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
1.97
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Input Voltage (V)
Input Voltage (V)
Figure 25. DC-DC Line Regulation, VOUT vs. VIN;
VOUT = 1.5V
Figure 26. DC-DC Line Regulation, VOUT vs. VIN;
VOUT = 1.0V
1.03
1.52
1.02
Output Voltage (V)
1.53
1.51
1.50
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
1.48
5.15 5.5
2.01
1.98
2
1.49
4.1 4.45 4.8
Figure 24. DC-DC Line Regulation, VOUT vs. VIN;
VOUT = 2.0V
4.5
Bypass
3.4 3.75
Input Voltage (V)
Figure 23. DC-DC Line Regulation, VOUT vs. VIN;
VOUT = 3.4V
Output Voltage (V)
PWM
Mode
2
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
3
Bypass
2.5
60
Output Voltage (V)
3.5
1.01
1
0.99
0.98
1.47
Iout = 300mA
Iout = 400mA
Iout = 500mA
Iout = 600mA
0.97
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Input Voltage (V)
Input Voltage (V)
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Revision 1.04
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AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 27. DC-DC Output Voltage Error vs. Reference
Voltage
Figure 28. DC-DC Bypass Dropout Voltage vs. Output
Current
100
6
Dropout Voltage (mV)
Output Voltage Error (mV)
8
4
2
0
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
Vin = 3.9V
-2
-4
0.25
0.5
0.75
1
1.25
80
60
40
Vin = 2.7V
Vin = 3.0V
Vin = 3.3V
Vin = 3.6V
20
0
0
1.5
Figure 29. DC-DC No-Load Supply Current vs. VIN
100 200 300 400 500 600 700 800 900
Output Current (mA)
Reference Voltage (V)
Figure 30. Shutdown Supply Current vs. VIN
120
6
Mode
Mode
3
2
100
80
60
40
1
20
0
0
1
2
3
4
5
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
6
Input Voltage (V)
Input Voltage (V)
Figure 32. DC-DC Switching; VIN=3.6V, VPA=1.2V,
IOUT=500mA
VLX
ILX
VPA
2V/Div
200mA/Div
ILX
VLX
VPA
20mV/Div
Figure 31. DC-DC Switching; VIN=3.6V, VPA=1.2V,
IOUT=50mA
1µs/Div
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20mV/Div
PWM
2V/Div
4
Bypass
500mA/Div
5
Shutdown Current (nA)
Quiescent Current (mA)
Vout = 3.4V
1µs/Div
Revision 1.04
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AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 33. DC-DC Soft-Start; RLOAD = 7.5Ω
2V/Div
500mA/Div
200µs/Div
2V/Div
REFIN
1A/Div
VPA
ILX
2V/Div
1A/Div
1V/Div
Figure 38. DC-DC Rectangular Wave Output in Bypass
Mode; VIN = 3.6V, RLOAD = 7.5Ω
2V/Div
Figure 37. DC-DC Rectangular Wave Output in PWM
Mode; VIN = 4.5V, RLOAD = 7.5Ω
REFIN
1V/Div
REFIN
ILX
500mA/Div
VPA
1V/Div
REFIN
VPA
ILX
200µs/Div
VPA
1V/Div
Figure 36. DC-DC Sine Wave Output in Bypass Mode;
VIN = 3.6V, RLOAD = 7.5Ω
1V/Div
Figure 35. DC-DC Sine Wave Output in PWM Mode;
VIN = 4.5V, RLOAD = 7.5Ω
ILX
200mA/Div
20µs/Div
20µs/Div
10µs/Div
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1V/Div
PA_EN
VPA
ILX
ILX
200mA/Div
VPA
1V/Div
PA_EN
2V/Div
Figure 34. DC-DC Shutdown
10µs/Div
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AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
VPA
500mA/Div
500mA/Div
ILX
200mA/Div
IOUT
500mV/Div
VPA
VIN
ILX
100mV/Div
Figure 40. DC-DC Load Transient; IOUT = 0mA to
500mA, VIN = 3.6V, VOUT = 2.5V
50mV/Div
Figure 39. DC-DC Line Transient; VIN = 4.0V to 3.5V,
VOUT = 1.2V, RLOAD = 10Ω
50µs/Div
50µs/Div
Figure 41. LDO Quiescent Current vs. VIN
Figure 42. LDO Line Regulation, VOUT vs. VIN
2.9
80
2.88
2.86
60
Output Voltage (V)
Quiescent Current (µA)
70
50
40
30
20
2.82
2.8
2.78
2.76
Iout = 0mA
Iout = 1mA
Iout = 10mA
Iout = 20mA
2.74
both LDO's
one LDO
10
2.72
2.7
0
1
2
3
4
5
Input Voltage (V)
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
6
Figure 43. LDO PSRR vs. Freq.; VIN = 3.2V, VOUT =
2.85V, VRIPPLE = 200mVPP, COUT =100nF
Input Voltage (V)
Figure 44. LDO Output Noise vs. Freq.; VIN = 3.2V,
VOUT = 2.85V, COUT =100nF
10
0
4mA
no Load
-10
10mA
no Load
Noise (µV / Hz)
-20
PSRR (dB)
2.84
-30
-40
-50
1
0.1
-60
-70
0.01
-80
10
100
1000
10000
100000
Frequency (Hz)
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10
100
1000
10000
100000
Frequency (Hz)
Revision 1.04
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AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
20µs/Div
20mV/Div
VLDO
VIN
50µs/Div
1V/Div
20mV/Div
Figure 48. LDO Line Transient; VIN = 4.0V to 3.5V,
IOUT = 10mA
2V/Div
VIN
VLDO
Figure 47. LDO Line Transient; VIN = 5.5V to 3.5V,
IOUT = 10mA
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20mV/Div
VLDO
IOUT
50µs/Div
5mA/Div
2V/Div
Figure 46. LDO Load Transient; IOUT = 0mA to 10mA,
VIN = 3.6V
2V/Div
EN2
VLDO
Figure 45. LDO Turn ON / OFF Response; VIN = 3.6V,
no load
50µs/Div
Revision 1.04
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AS1339
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1339 is designed to dynamically power the PA in WCDMA and NCDMA handsets. The device is empowered
with a high-frequency, high-efficiency step-down converter, and two LDOs. The step-down converters are capable of
delivering 650mA. The PWM control scheme provides fast transient response, while 2MHz switching frequency allows
the trade-off between efficiency and small external components. A 110mΩ bypass FET connects the PA directly to the
battery during high-power transmission.
Figure 49. Block Diagram
Li+ Battery
IN1A
Bypass FET
10µF
+
PFET
IN1B
LX
2MHz BUCK
REFIN
NFET
4.7µF
PGND
2.85V
LDO1
BASEBAND
PROCESSOR
GPIO
GPIO
GPIO
2.5x REFIN
PAB
PAA
DAC
2.2µH
PA_EN
EN1
EN2
TEST
Not
Connected
LDO1
Control
Logic
1µF
REF
2.85V
LDO2
LDO2
IN2
0.1µF
ROFF
AS1339
0.1µF
ROFF
NC
AGND
Operating the AS1339
The AS1339’s control block turns on the internal PFET (P-channel MOSFET) switch during the first part of each
switching cycle, thus allowing current to flow from the input through the inductor to the output filter capacitor and load.
The inductor limits the current to a ramp with a slope of (VIN - VOUT) / L, by storing energy in a magnetic field.
During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and
then turns the NFET (N-channel MOSFET) synchronous rectifier on. As a result, the inductor’s magnetic field
collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter
capacitor and load.
While the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope
of VOUT / L. The output filter capacitor stores charge when the inductor current is high, and releases it when low,
smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on-time to
control the average current sent to the load.
The output voltage is equal to the average voltage at the LX pin.
While in operation, the output voltage is regulated by switching at a constant frequency and then modulating the
energy per cycle to control the power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse
width to control the peak inductor current. This is done by comparing the signal from the current-sense amplifier with a
slope compensated error signal from the voltage-feedback error amplifier. At the beginning of each cycle, the clock
turns on the PFET switch, causing the inductor current to ramp up. When the current sense signal ramps past the error
amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending
the first part of the cycle.
If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to
ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and
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AS1339
Datasheet - D e t a i l e d D e s c r i p t i o n
adjusts for the increase in the load. Before appearing at the PWM comparator, a slope compensation ramp from the
oscillator is subtracted from the error signal for stability of the current feedback loop.
Internal Synchronous Rectifier
To reduce the rectifier forward voltage drop and the associated power loss, the AS1339 uses an internal NFET as a
synchronous rectifier. The big advantage of a synchronous rectification is the higher efficiency in a condition where the
output voltage is low compared to the voltage drop across an ordinary rectifier diode. During the inductor current down
slope in the second part of each cycle the synchronous rectifier is turned on. Before the next cycle the synchronous
rectifier is turned off.
There is no need for an external diode because the NFET is conducting through its intrinsic body diode during the
transient intervals before it turns on.
Bypass Mode
This mode connects IN1A and IN1B directly to PAA and PAB with the internal 110mΩ (typ) bypass FET, while the stepdown converter is forced into 100% duty-cycle operation during high-power transmission. Due to the low on-resistance
in this mode, the result is low dropout, high efficiency and a high output current capability.
The AS1339 enters bypass mode automatically when VIN ≤ 2.69 x VREFIN and thus prevents excessive output ripple as
the step-down converter approaches dropout. Due to an internal limitation of VREFIN ≤ 1.5V the maximum output voltage is limited to 2.78 x 1.5V = 4.17V in Bypass Mode.
Shutdown Mode
To put the PA step-down converter in shutdown mode, connect PA_EN to GND or disconnect PA_EN (NC =>logic-low).
During shutdown mode, the control circuitry, internal switching MOSFET, and synchronous rectifier are turned off and
LX becomes high impedance. For normal operation, connect PA_EN to IN1A/B or logic-high.
To place LDO1 or LDO2 in shutdown mode, connect EN1 or EN2 to GND or disconnect EN1 or EN2 (NC => logic-low).
The outputs of the LDOs are pulled to ground through an internal 100Ω resistor during shutdown. When the PA stepdown and LDOs are all in shutdown, the AS1339 enters a very low power state, where the input current drops to 0.8μA
(typ).
Note: All enable Pins (PA_EN, EN1 and EN2) have an internal 110kΩ pull-down resistance.
Soft-Start
The internal soft-start circuitry of the PA step-down converter limits inrush current at startup, reducing transients on the
input source. Soft-start is favorable for supplies with high output impedance such as Li+ and alkaline cells. The DC-DC
can start-up with full output load of 7.5Ω.
Analog REFIN Control
The PA step-down converter uses REFIN to set the output voltage, which enables the converter to operate in applications requiring dynamic voltage control. The output voltage is limited to an upper level of 3.85V, when operating in
PWM mode. In Bypass mode the output voltage is limited to VIN.
Notes:
1. VOUT = 2.5 x VREFIN
2. If REFIN is left floating the output voltage of the step-down converter can assume any value between 0.6V and
VIN.
Thermal Overload Protection
To prevent the AS1339 from short-term misuse and overload conditions the chip includes a thermal overload
protection. To block the normal operation mode the device is turning off the PFET and the NFET in PWM and bypass
mode as soon as the junction temperature exceeds 140°C. To resume the normal operation the temperature has to
drop below 130°C.
Note: Continuing operation in thermal overload conditions may damage the device and is considered bad practice.
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
9 Application Information
The AS1339 is designed to supply power amplifiers for RF applications. The output power of the PA can directly be
controlled via the output voltage of the AS1339. Figure 50 shows a typical application.
Figure 50. Typical Application Diagram
Li+ Battery
IN1A
CIN1
+
2.2µH
LX
IN1B
PAB
COUT
PAA
REFIN
DAC
PGND
LDO1
BASEBAND
PROCESSOR
PA_EN
GPIO
CLDO1
AS1339
BIAS
EN1
EN2
TEST
Not
Connected
GPIO
GPIO
RFIN
IN
LDO2
RFOUT
PA1
CLDO2
NC
IN2
BIAS
AGND
CIN2
RFIN
IN
RFOUT
PA2
Capacitor Selection for Step-Down Converter
Input Capacitor
To reduce the current peaks drawn from the battery or power source and to reduce the switching noise in the device an
input capacitor is highly recommended. At the switching frequency the impedance of the capacitor should be very low.
It’s recommended to use a X5R or X7R dielectric multilayer ceramic capacitor due to their small size, low ESR and
small temperature coefficients. For most applications a 4.7µF capacitor is sufficient. To decrease the interfering noise
and to lower the input ripple the capacitor value can be set higher (e.g. 10µF).
Output Capacitor
To ensure a stable loop regulation and a small output voltage ripple a low impedance capacitor should be used. It’s
recommended to use a X5R or X7R dielectric multilayer ceramic capacitor due to their small size, low ESR and small
temperature coefficients. For most applications a 4.7µF capacitor is sufficient. To achieve a better load-transient performance and to decrease the output ripple the capacitor value can be set higher (e.g. 10µF).
Table 6. Recommended Capacitors for the Step-Down Converter
Name
CIN1, COUT
Part Number
C
Voltage
Type
Size
GRM21BR60J106KE01
10µF
6.3V
X5R
0805
GRM21BR61C475KA88
4.7µF
16V
X5R
0805
C0603C475K8PAC7867
4.7µF
10V
X5R
0603
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Murata
www.murata.com
KEMET
www.kemet.com
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Capacitor Selection for LDO’s
Input Capacitor
The capacitor for the LDO Input should have at least a value of the sum of the output capacitors of LDO1 and LDO2.
With a larger input capacitance and lower ESR a better noise rejection and line transient response can be achieved.
Output Capacitor
For the LDO outputs the capacitor value depends on the needed load current. For a stable operation with rated maximum load currents a minimum output capacitor of 1µF is recommended. At light loads of 10mA or less a 0.1µF capacitor is sufficient. With larger output capacitance a reduced output noise, improved load-transient response, better
stability and power-supply rejection can be achieved.
Table 7. Recommended Capacitors for the LDO’s
Name
CIN2, CLDO1,
CLDO2
Part Number
C
Voltage
Type
Size
C0402C104K4RAC
100nF
16V
X7R
0402
GRM155R61A105KE15
1µF
10V
X5R
0402
Manufacturer
KEMET
www.kemet.com
Murata
www.murata.com
Inductor Selection
For most applications the value of the external inductor should be in the range of 1.5µH to 4.7µH as the inductor value
has a direct effect on the ripple current. The selected inductor must be rated for its DC resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN to VOUT.
In Equation (EQ 3) the maximum inductor current in PWM mode under static load conditions is calculated. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation (EQ
4). This is recommended because the inductor current will rise above the calculated value during heavy load transients.
The inductor current ripple ΔIL (see EQ 3) is defined by the slope of the current (dI / dt) (see EQ 1) multiplied by the
PFET on-time tON (see EQ 2).
Figure 51. Ripple Current Diagram
IL
ILmax
ΔIL
IOUTmax
dI
dt
t
tON
1/f
V IN – V OUT
dI
----- = ---------------------------dt
L
1
t ON = DutyCycle × --f
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V OUT
DutyCycle = ------------V IN
Revision 1.04
(EQ 1)
(EQ 2)
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
V OUT × ( V IN – V OUT )
ΔI L = -----------------------------------------------------V IN × f × L
(EQ 3)
ΔI L
I LMAX = I OUTMAX + -------2
(EQ 4)
f .... Switching Frequency (2.0MHz typical)
L .... Inductor Value
ILMAX .... Maximum Inductor current
ΔIL .... Peak to Peak inductor ripple current
IOUTMAX .... Applied load current
Accepting larger values of ripple current allows the use of low inductance values, but results in higher output voltage
ripple, greater core losses, and lower output current capability. The total losses of the coil have a strong impact on the
efficiency of the dc/dc conversion and consist of both the losses in the dc resistance and the following frequencydependent components:
1.
2.
3.
4.
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
Note: For highest efficiency, a low DC-resistance inductor is recommended.
Table 8. Recommended Inductors
Part Number
L
DCR
MLP2520S1R5S
1.5µH
80mΩ
Current Rating Dimensions (L/W/T)
1.5A
2.5x2.0x1.2mm
MLP2520S2R2S
2.2µH
110mΩ
1.2A
2.5x2.0x1.2mm
MLP2520S3R3S
3.3µH
110mΩ
1.0A
2.5x2.0x1.2mm
EPL2014-222MLC
2.2µH
120mΩ
0.98A
2.2x2.0x1.4mm
EPL2014-332MLC
3.3µH
152mΩ
0.8A
2.2x2.0x1.4mm
EPL2014-472MLC
4.7µH
231mΩ
0.65A
2.2x2.0x1.4mm
XPL2010-222ML
2.2µH
156mΩ
1.2A
2.0x1.9x1.0mm
XPL2010-332ML
3.3µH
207mΩ
0.925A
2.0x1.9x1.0mm
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TDK
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Coilcraft
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 53. Efficiency Comparison of different
Inductors; VIN = 3.9V, VOUT = 1.5V
100
100
90
90
80
80
70
70
Efficiency (%) .
Efficiency (%) .
Figure 52. Efficiency Comparison of different
Inductors; VIN = 3.9V, VOUT = 1.0V
60
50
40
30
MLP2520S1R5S
20
MLP2520S3R3S
10
EPL2014-332
MLP2520S2R2S
EPL2014-222
EPL2014-472
0
60
50
40
30
MLP2520S1R5S
20
MLP2520S3R3S
10
EPL2014-332
MLP2520S2R2S
EPL2014-222
EPL2014-472
0
10
100
1000
10
Output Current (mA)
100
1000
Output Current (mA)
Example
The following system should be designed:
- A supply with a Lithium-Ion Battery = 4.5V
- VOUT = 3.0V
- IOUTMAX = 500mA
For the first step VREF is calculated as shown in Equation (EQ 5).
V OUT
V REF = ------------- = 1, 2V
2, 5
V IN ≤ 2, 69 × V REF
(EQ 5)
(EQ 6)
Due to Equation (EQ 6): VIN = 3.23V
If VIN is falling below 3.23V the device is going into Bypass mode (see Bypass Mode on page 17).
Hence a 2.2µH coil is used, ΔIL can be calculated with Equation (EQ 3): ΔIL= 227mA
With this result IMAX can be calculated with Equation (EQ 4): IMAX = 614mA.
The saturation current of the coil should be chosen slightly higher than IMAX because heavy load transients could
increase the peak current. For a short period of time (~50µs) the peak inductor current can rise up to a value of approximately 1.1A (p-channel MOSFET peak current limit). In this case a coil with a rated saturation current of ~800mA can
be chosen.
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Layout Considerations
High peak currents of up to 1.1A and a high switching frequency makes the PCB layout important. Following rules
should be considered:
-
The power traces (IN1A, IN1B, IN2, LX, PAA, PAB, PGND) should be kept as short, direct and wide as practical.
All capacitors should be placed as close as possible near the device.
Try to keep the serial resistance (ESR) of CLDO1 and CLDO2 as low as possible.
The negative terminations of the capacitors COUT and CIN should be kept as close to each other as possible. A
starpoint to PGND is recommended.
As shown in Figure 54 the current path between the pins IN1A/IN1B (C3/C4) and pin PGND (A4) via CIN1 is kept as
short as possible. Also the current path between the pins PAB/PAA (D3/D4) and pin PGND (A4) via COUT is very close.
The negative terminals of CIN1 and COUT are connected to pin PGND (A4) as a starpoint.
In order to keep noise emissions suppressed the connection between pin LX (B4) and the pins PAB/PAA (D3/D4) via
the coil is kept very short. A shielded coil is recommended.
To keep the influence of the DC-DC on the LDOs in terms of supply ripple and noise quite low the IN1, IN2 and AGND,
PGND path are separated in the layout. These power paths should be connected via a starpoint directly at the supply.
Figure 54. Layout for Space Limited Applications
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AS1339
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
The devices are available in a 16-pin WLP (2x2mm) package.
Figure 55. 16-pin WLP (2x2mm) Package
2015±20
257.5±20
257.5±20
2015±20
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AS1339
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as the standard products shown in Table 9.
Table 9. Ordering Information
Part Number
AS1339-BWLT
Marking
Description
Delivery Form
Package
AS1339
650mA RF Step-Down DC-DC for PA,
with two LDOs
Tape and Reel
16-pin WLP (2x2mm)
All devices are RoHS compliant and free of halogene substances.
www.austriamicrosystems.com
Revision 1.04
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AS1339
Datasheet
Copyrights
Copyright © 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore,
prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten - Graz, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact-us
www.austriamicrosystems.com
Revision 1.04
25 - 25