STMicroelectronics M58LW032D110ZA6F 32 mbit 4mb x8, 2mb x16, uniform block 3v supply flash memory Datasheet

M58LW032D
32 Mbit (4Mb x8, 2Mb x16, Uniform Block)
3V Supply Flash Memory
FEATURES SUMMARY
■ WIDE x8 or x16 DATA BUS for HIGH
BANDWIDTH
■
Figure 1. Packages
SUPPLY VOLTAGE
– VDD = VDDQ = 2.7 to 3.6V for Program, Erase
and Read operations
■
ACCESS TIME
– Random Read 90ns,110ns
– Page Mode Read 90ns/25ns, 110ns/25ns
■
PROGRAMMING TIME
TSOP56 (N)
14 x 20 mm
– 16 Word Write Buffer
– 12µs Word effective programming time
■
32 UNIFORM 64 KWord/128KByte MEMORY
BLOCKS
■
ENHANCED SECURITY
– Block Protection/ Unprotection
– VPEN signal for Program Erase Enable
– 128 bit Protection Register with 64 bit Unique
Code in OTP area
■
PROGRAM and ERASE SUSPEND
■
128 bit PROTECTION REGISTER
■
COMMON FLASH INTERFACE
■
100, 000 PROGRAM/ERASE CYCLES per
BLOCK
■
ELECTRONIC SIGNATURE
TBGA
TBGA64 (ZA)
10 x 13 mm
– Manufacturer Code: 0020h
– Device Code M58LW032D: 0016h
September 2003
1/51
M58LW032D
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
7
8
9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Input (A0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A1-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enables (E0, E1, E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Status/(Ready/Busy) (STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program/Erase Enable (VPEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Device Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 12
. . . . 12
. . . . 12
. . . . 12
. . . . 12
. . . . 12
. . . 12
READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Word/Byte Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/51
M58LW032D
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Protect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Configure STS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Word-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Byte-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 20
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Program/Erase Controller Status (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Erase Suspend Status (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Erase Status (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Program Status (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VPEN Status (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program Suspend Status (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Protection Status (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reserved (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9. Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15. Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10. Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16. Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11. Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13. Reset, Power-Down and Power-Up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19. Reset, Power-Down and Power-Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
25
26
27
27
28
28
29
29
30
30
31
31
3/51
M58LW032D
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . .
Table 20. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
Figure 15. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline . . . . . . . . . . . . . . .
Table 21. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data . . . . . . .
32
32
33
33
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 25. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 26. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 27. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 28. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 29. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
37
37
38
39
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 16. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . .
Figure 17. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . .
Figure 18. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . .
Figure 20. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21. Block Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . .
Figure 23. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . .
Figure 24. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . .
Figure 25. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . .
40
41
42
43
44
45
46
47
48
49
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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M58LW032D
SUMMARY DESCRIPTION
The M58LW032D is a 32 Mbit (4Mb x 8 or 2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7V to 3.6V)
core supply.
The memory is divided into 32 blocks of 1Mbit that
can be erased independently so it is possible to
preserve valid data while old data is erased. Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are required to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The Write Buffer allows the microprocessor to program from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the microprocessor to perform other work. A Word Program
command is available to program a single word.
Erase can be suspended in order to perform either
Read or Program in any other block and then resumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cycles.
The M58LW032D has several security features to
increase data protection.
■ Block Protection, where each block can be
individually protected against program or erase
operations. All blocks are protected during
power-up. The protection of the blocks is nonvolatile; after power-up the protection status of
each block is restored to the state when power
was last removed.
■ Program Erase Enable input VPEN, program or
erase operations are not possible when the
Program Erase Enable input VPEN is low.
■ 128 bit Protection Register, divided into two 64
bit segments: the first contains a unique device
number written by ST, the second is user
programmable. The user programmable
segment can be protected.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the enabled memory and to set
the device in power-down mode.
The device features an Auto Low Power mode. If
the bus becomes inactive during read operations,
the device automatically enters Auto Low Power
mode. In this mode the power consumption is reduced to the Auto Low Power supply current.
The STS signal is an open drain output that can be
used to identify the Program/Erase Controller status. It can be configured in two modes: Ready/
Busy mode where a static signal indicates the status of the P/E.C, and Status mode where a pulsing
signal indicates the end of a Program or Block
Erase operation. In Status mode it can be used as
a system interrupt signal, useful for saving CPU
time.
The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10x13mm, 1mm pitch) packages.
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M58LW032D
Figure 2. Logic Diagram
VDD
Table 1. Signal Names
VDDQ
22
A0-A21
VPEN
16
BYTE
W
DQ0-DQ15
M58LW032D
E0
STS
E1
A0
Address input (used in X8 mode only)
A1-A21
Address inputs
BYTE
Byte/Word Organization Select
DQ0-DQ15
Data Inputs/Outputs
E0
Chip Enable
E1
Chip Enable
E2
Chip Enable
G
Output Enable
RP
Reset/Power-Down
STS
Status/(Ready/Busy)
VPEN
Program/Erase Enable
W
Write Enable
VDD
Supply Voltage
VDDQ
Input/Output Supply Voltage
VSS
Ground
VSSQ
Input/Output Ground
NC
Not Connected Internally
DU
Do Not Use
E2
G
RP
VSS VSSQ
AI06234b
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M58LW032D
Figure 3. TSOP56 Connections
NC
E1
A21
A20
A19
A18
A17
A16
VDD
A15
A14
A13
A12
E0
VPEN
RP
A11
A10
A9
A8
VSS
A7
A6
A5
A4
A3
A2
A1
1
56
14
43
M58LW032D
15
42
28
29
NC
W
G
STS
DQ15
DQ7
DQ14
DQ6
VSS
DQ13
DQ5
DQ12
DQ4
VDDQ
VSSQ
DQ11
DQ3
DQ10
DQ2
VDD
DQ9
DQ1
DQ8
DQ0
A0
BYTE
NC
E2
AI06235
7/51
M58LW032D
Figure 4. TBGA64 Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPEN
A13
VDD
A18
NC
B
A2
VSS
A9
E0
A14
DU
A19
E1
C
A3
A7
A10
A12
A15
DU
A20
A21
D
A4
A5
A11
RP
DU
DU
A16
A17
E
DQ8
DQ1
DQ9
DQ3
DQ4
DU
DQ15
STS
F
BYTE
DQ0
DQ10
DQ11
DQ12
DU
DU
G
G
NC
A0
DQ2
VDDQ
DQ5
DQ6
DQ14
W
H
E2
DU
VDD
VSSQ
DQ13
VSS
DQ7
NC
AI06236b
8/51
M58LW032D
Figure 5. Block Addresses
Byte (x8) Bus Width
3FFFFFh
3E0000h
3DFFFFh
Word (x16) Bus Width
1FFFFFh
1 Mbit or
128 KBytes
1F0000h
1EFFFFh
1 Mbit or
128 KBytes
3C0000h
1 Mbit or
64 KWords
1 Mbit or
64 KWords
1E0000h
Total of 32
1 Mbit Blocks
03FFFFh
020000h
01FFFFh
000000h
1 Mbit or
128 KBytes
1 Mbit or
128 KBytes
01FFFFh
010000h
00FFFFh
1 Mbit or
64 KWords
1 Mbit or
64 KWords
000000h
AI06238b
Note: Also see Appendix A, Table 23 for a full listing of the Block Addresses
9/51
M58LW032D
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Input (A0). The A0 address input is
used to select the higher or lower Byte in X8 mode.
It is not used in X16 mode (where A1 is the Lowest
Significant bit).
Address Inputs (A1-A21). The Address Inputs
are used to select the cells to access in the memory array during Bus Read operations either to
read or to program data to. During Bus Write operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
The device must be enabled (refer to Table 2, Device Enable) when selecting the addresses. The
address inputs are latched on the rising edge of
Write Enable or on the first edge of Chip Enables
E0, E1 or E2 that disable the device, whichever
occurs first.
Data Inputs/Outputs (DQ0-DQ15). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. During Bus Write operations they represent the commands sent to the Command Interface of the
Program/Erase Controller. When used to input
data or Write commands they are latched on the
rising edge of Write Enable or the first edge of
Chip Enables E0, E1 or E2 that disable the device,
whichever occurs first.
When the device is enabled and Output Enable is
low, VIL (refer to Table 2, Device Enable), the data
bus outputs data from the memory array, the Electronic Signature, the Block Protection status, the
CFI Information or the contents of the Status Register. The data bus is high impedance when the
device is deselected, Output Enable is high, VIH, or
the Reset/Power-Down signal is low, VIL. When
the Program/Erase Controller is active the Ready/
Busy status is given on DQ7.
Chip Enables (E0, E1, E2). The Chip Enable inputs E0, E1 and E2 activate the memory control
logic, input buffers, decoders and sense amplifiers. The device is selected at the first edge of Chip
Enables E0, E1 or E2 that enable the device and
deselected at the first edge of Chip Enables E0,
E1 or E2 that disable the device. Refer to Table 2,
Device Enable for more details.
When the Chip Enable inputs deselect the memory, power consumption is reduced to the Standby
level, IDD1.
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at VIH
the outputs are high impedance.
10/51
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write Enable.
Reset/PowerReset/Power-Down (RP). The
Down pin can be used to apply a Hardware Reset
to the memory.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, VIL, for at least tPLPH. When
Reset/Power-Down is Low, VIL, the Status Register information is cleared and the power consumption is reduced to power-down level. The device is
deselected and outputs are high impedance. If Reset/Power-Down goes low, VIL,during a Block
Erase, a Write to Buffer and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the STS pin
stays low, VIL, for a maximum timing of tPLPH + tPHBH, until the completion of the Reset/Power-Down
pulse.
After Reset/Power-Down goes High, VIH, the
memory will be ready for Bus Read and Bus Write
operations after tPHQV. Note that STS does not fall
during a reset, see Ready/Busy Output section.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an
Erase or Program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous
Random Read.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 bus widths of the
memory. When Byte/Word Organization Select is
Low, VIL, the memory is in x8 mode, when it is
High, VIH, the memory is in x16 mode.
Status/(Ready/Busy) (STS). The STS signal is
an open drain output that can be used to identify
the Program/Erase Controller status. It can be
configured in two modes:
■ Ready/Busy - the pin is Low, VOL, during
Program and Erase operations and high
impedance when the memory is ready for any
Read, Program or Erase operation.
■ Status - the pin gives a pulsing signal to indicate
the end of a Program or Block Erase operation.
After power-up or reset the STS pin is configured
in Ready/Busy mode. The pin can be configured
for Status mode using the Configure STS command.
When the Program/Erase Controller is idle, or suspended, STS can float High through a pull-up re-
M58LW032D
sistor. The use of an open-drain output allows the
STS pins from several memories to be connected
to a single pull-up resistor (a Low will indicate that
one, or more, of the memories is busy).
STS is not Low during a reset unless the reset was
applied when the Program/Erase controller was
active.
Program/Erase Enable (VPEN). The Program/
Erase Enable input, VPEN, is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, otherwise the operations is not guaranteed to succeed
and data may become corrupt.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
It is recommended to power-up and power-down
VDD and VDDQ together to avoid any condition that
would result in data corruption.
VSS Ground. Ground, VSS, is the reference for
the core power supply. It must be connected to the
system ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS.
Note: Each device in a system should have
VDD and VDDQ decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, inherently low inductance capacitors should be
as close as possible to the package). See Figure 8, AC Measurement Load Circuit.
Table 2. Device Enable
E2
E1
E0
Device
VIL
VIL
VIL
Enabled
VIL
VIL
VIH
Disabled
VIL
VIH
VIL
Disabled
VIL
VIH
VIH
Disabled
VIH
VIL
VIL
Enabled
VIH
VIL
VIH
Enabled
VIH
VIH
VIL
Enabled
VIH
VIH
VIH
Disabled
Note: For single device operations, E2 and E1 can be connected to VSS.
11/51
M58LW032D
BUS OPERATIONS
There are five standard bus operations that control
the memory. Each of these is described in this
section, see Tables 3, Bus Operations, for a summary.
On Power-up or after a Hardware Reset the memory defaults to Read Array mode (Page Read).
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register, the Common
Flash Interface and the Block Protection Status.
A valid bus operation involves setting the desired
address on the Address inputs, enabling the device (refer to Table 2, Device Enable), applying a
Low signal, VIL, to Output Enable and keeping
Write Enable High, VIH. The data read depends on
the previous command written to the memory (see
Command Interface section).
See Figure 9, Bus Read AC Waveforms, and Table 15, Bus Read AC Characteristics, for details of
when the output becomes valid.
Bus Write. Bus Write operations write Commands to the memory or latch addresses and input
data to be programmed.
A valid Bus Write operation begins by setting the
desired address on the Address Inputs and enabling the device (refer to Chip Enable section).
The Address Inputs are latched by the Command
Interface on the rising edge of Write Enable or the
first edge of E0, E1 or E2 that disables the device
(refer to Table 2, Device Enable).
The Data Input/Outputs are latched by the Command Interface on the rising edge of Write Enable
or the first edge of E0, E1 or E2 that disables the
device whichever occurs first. Output Enable must
remain High, VIH, during the Bus Write operation.
See Figures 11, and 12, Write AC Waveforms, and
Tables 17 and 18, Write and Chip Enable Controlled Write AC Characteristics, for details of the
timing requirements.
Output Disable. The Data Inputs/Outputs are
high impedance when the Output Enable is at VIH.
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, IDD2, and the outputs are high impedance,
independent of Chip Enable, Output Enable or
Write Enable.
Standby. Standby disables most of the internal
circuitry, allowing a substantial reduction of the
current consumption. The memory is in standby
when Chip Enable is at VIH. The power consumption is reduced to the standby level IDD1 and the
outputs are set to high impedance, independently
of the Output Enable or Write Enable inputs.
If Chip Enable switches to VIH during a program or
erase operation, the device enters Standby mode
when finished.
Table 3. Bus Operations
Bus Operation
E0, E1
or E2
G
W
RP
A1-A21 (x16)
A0-A21 (x8)
DQ0-DQ15 (x16)
DQ0-DQ7 (x8)(1)
Bus Read
VIL
VIL
VIH
VIH
Address
Data Output
Bus Write
VIL
VIH
VIL
VIH
Address
Data Input
Output Disable
VIL
VIH
VIH
VIH
X
High Z
Power-Down
X
X
X
VIL
X
High Z
Standby
VIH
X
X
VIH
X
High Z
Note: 1. DQ8-DQ15 are High Z in x8 mode.
2. X = Don’t Care VIL or VIH .
12/51
M58LW032D
READ MODES
Read operations in the M58LW032D are asynchronous. The device outputs the data corresponding to the address latched, that is the
memory array, Status Register, Common Flash Interface, Electronic Signature or Block Protection
Status depending on the command issued.
During read operations, if the bus is inactive for a
time equivalent to tAVQV, the device automatically
enters Auto Low Power mode. In this mode the internal supply current is reduced to the Auto Low
Power supply current, IDD5. The Data Inputs/Outputs will still output data if a Bus Read operation is
in progress.
Read operations can be performed in two different
ways, Random Read (where each Bus Read operation accesses a different Page) and Page Read.
In Page Read mode a Page of data is internally
read and stored in a Page Buffer. Each memory
page is a 4 Words or 8 Bytes and has the same
A3-A21. In x8 mode only A0, A1 and A2 may
change, in x16 mode only A1 and A2 may change.
The first read operation within the Page has the
normal access time (tAVQV), subsequent reads
within the same Page have much shorter access
times (tAVQV1). If the Page changes then the normal, longer timings apply again.
See Figure 10, Page Read AC Waveforms and
Table 16, Page Read AC Characteristics for details on when the outputs become valid.
13/51
M58LW032D
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. The Commands are summarized in Table
4, Commands. Refer to Table 4 in conjunction with
the text descriptions below.
After power-up or a Reset operation the memory
enters Read mode.
Read Memory Array Command. The Read Memory Array command is used to return the memory
to Read mode. One Bus Write cycle is required to
issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read
mode until another command is issued. From
Read mode Bus Read operations will access the
memory array. After power-up or a reset the memory defaults to Read Array mode (Page Read).
While the Program/Erase Controller is executing a
Program, Erase, Block Protect, Blocks Unprotect
or Protection Register Program operation the
memory will not accept the Read Memory Array
command until the operation completes.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Protection Register.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once the command is issued subsequent Bus Read operations
read the Manufacturer Code, the Device Code, the
Block Protection Status or the Protection Register
until another command is issued. Refer to Table 6,
Read Electronic Signature, Tables 7 and 8, Word
and Byte-wide Read Protection Register and Figure 6, Protection Register Memory Map for information on the addresses.
Read Query Command. The Read Query Command is used to read data from the Common Flash
Interface (CFI) Memory Area. One Bus Write cycle
is required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations read from the Common Flash Interface Memory Area. See Appendix B, Tables 24,
25, 26, 27, 28 and 29 for details on the information
contained in the Common Flash Interface (CFI)
memory area.
Read Status Register Command. The Read Status Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read operations read the Status Register until another command is issued.
14/51
The Status Register information is present on the
output data bus (DQ1-DQ7) when the device is enabled and Output Enable is Low, VIL.
See the section on the Status Register and Table
10 for details on the definitions of the Status Register bits
Clear Status Register Command. The Clear Status Register command can be used to reset bits
SR1, SR3, SR4 and SR5 in the Status Register to
‘0’. One Bus Write is required to issue the Clear
Status Register command.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Erase, Block Protect, Block
Unprotect or Protection Register Program command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by
issuing the Clear Status Register command before
attempting a new Program, Erase or Resume
command.
Block Erase Command. The Block Erase command can be used to erase a block. It sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.
Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address and starts the Program/Erase Controller. Once the command is issued subsequent
Bus Read operations read the Status Register.
See the section on the Status Register for details
on the definitions of the Status Register bits.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 9.
See Appendix C, Figure 18, Block Erase Flowchart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.
Word/Byte Program Command. The
Word/
Byte Program command is used to program a single Word or Byte in the memory array. Two Bus
Write operations are required to issue the command; the first write cycle sets up the Word Program command, the second write cycle latches the
address and data to be programmed, and starts
the Program/Erase Controller.
If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the
memory array. The block must be unprotected using the Blocks Unprotect command or by using the
M58LW032D
Blocks Temporary Unprotect feature of the Reset/
Power-Down pin, RP.
Write to Buffer and Program Command. The
Write to Buffer and Program command is used to
program the memory array.
Up to 16 Words/32 Bytes can be loaded into the
Write Buffer and programmed into the memory.
Each Write Buffer has the same A5-A21 addresses. In Byte-wide mode only A0-A4 may change in
Word-wide mode only A1-A4 may change, in .
Four successive steps are required to issue the
command.
1. One Bus Write operation is required to set up
the Write to Buffer and Program Command. Issue the set up command with the selected
memory Block Address where the program operation should occur (any address in the block
where the values will be programmed can be
used). Any Bus Read operations will start to output the Status Register after the 1st cycle.
2. Use one Bus Write operation to write the same
block address along with the value N on the
Data Inputs/Output, where N+1 is the number of
Words/Bytes to be programmed.
3. Use N+1 Bus Write operations to load the address and data for each Word into the Write
Buffer. See the constraints on the address combinations listed below. The addresses must
have the same A5-A21.
4. Finally, use one Bus Write operation to issue the
final cycle to confirm the command and start the
Program operation.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the operation without affecting the data in the memory array. The Status Register should be cleared before
re-issuing the command.
If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the
memory array. The block must be unprotected using the Blocks Unprotect command.
See Appendix C, Figure 16, Write to Buffer and
Program Flowchart and Pseudo Code, for a suggested flowchart on using the Write to Buffer and
Program command.
Program/Erase Suspend Command. The
Program/Erase Suspend command is used to pause a
Word/Byte Program, Write to Buffer and Program
or Erase operation. The command will only be accepted during a Program or an Erase operation. It
can be issued at any time during an Erase operation but will only be accepted during a Word Program or Write to Buffer and Program command if
the Program/Erase Controller is running.
One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (SR7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will continue to output the Status Register until another
command is issued.
During the polling period between issuing the Program/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase
Controller Status bit (SR7) indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit (SR2) or the Erase
Suspend Status bit (SR6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the
Program/Erase Suspend command and the Program/Erase Controller pausing see Table 9.
During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended
operation was Erase then the Write to Buffer and
Program, and the Program Suspend commands
will also be accepted. When a program operation
is completed inside a Block Erase Suspend the
Read Memory Array command must be issued to
reset the device in Read mode, then the Erase Resume command can be issued to complete the
whole sequence. Only the blocks not being erased
may be read or programmed correctly.
See Appendix C, Figure 17, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
19, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The
Program/Erase Resume command can be used to restart the Program/Erase Controller after a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations
read the Status Register.
Block Protect Command. The Block Protect
command is used to protect a block and prevent
Program or Erase operations from changing the
data in it. Two Bus Write cycles are required to issue the Block Protect command; the second Bus
Write cycle latches the block address and starts
the Program/Erase Controller. Once the command
is issued subsequent Bus Read operations read
15/51
M58LW032D
the Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
During the Block Protect operation the memory will
only accept the Read Status Register command.
All other commands will be ignored. Typical Block
Protection times are given in Table 9.
The Block Protection bits are non-volatile, once
set they remain set through reset and powerdown/power-up. They are cleared by a Blocks Unprotect command.
See Appendix C, Figure 20, Block Protect Flowchart and Pseudo Code, for a suggested flowchart
on using the Block Protect command.
Blocks Unprotect Command. The Blocks Unprotect command is used to unprotect all of the
blocks. Two Bus Write cycles are required to issue
the Blocks Unprotect command; the second Bus
Write cycle starts the Program/Erase Controller.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits.
During the Block Unprotect operation the memory
will only accept the Read Status Register command. All other commands will be ignored. Typical
Block Protection times are given in Table 9.
See Appendix C, Figure 21, Block Unprotect Flowchart and Pseudo Code, for a suggested flowchart
on using the Block Unprotect command.
Protection Register Program Command. The
Protection Register Program command is used to
Program the 64 bit user segment of the Protection
Register. Two write cycles are required to issue
the Protection Register Program command.
■ The first bus cycle sets up the Protection
Register Program command.
■ The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
16/51
The user-programmable segment can be locked
by programming bit 1 of the Protection Register
Lock location to ‘0’ (see Table 7 and x for Wordwide and Byte-wide protection addressing). Bit 0
of the Protection Register Lock location locks the
factory programmed segment and is programmed
to ‘0’ in the factory. The locking of the Protection
Register is not reversible, once the lock bits are
programmed no further changes can be made to
the values stored in the Protection Register, see
Figure 6, Protection Register Memory Map. Attempting to program a previously protected Protection Register will result in a Status Register
error.
The Protection Register Program cannot be suspended. See Appendix C, Figure 22, Protection
Register Program Flowchart and Pseudo Code,
for the flowchart for using the Protection Register
Program command.
Configure STS Command.
The Configure STS command is used to configure
the Status/(Ready/Busy) pin. After power-up or reset the STS pin is configured in Ready/Busy
mode. The pin can be configured in Status mode
using the Configure STS command (refer to Status/(Ready/Busy) section for more details.
Two write cycles are required to issue the Configure STS command.
■ The first bus cycle sets up the Configure STS
command.
■ The second specifies one of the four possible
configurations (refer to Table 5, Configuration
Codes):
– Ready/Busy mode
– Pulse on Erase complete mode
– Pulse on Program complete mode
– Pulse on Erase or Program complete mode
The device will not accept the Configure STS command while the Program/Erase controller is busy
or during Program/Erase Suspend. When STS pin
is pulsing it remains Low for a typical time of
250ns. Any invalid Configuration Code will set an
error in the Status Register.
M58LW032D
Table 4. Commands
Cycles
Bus Operations
Command
1st Cycle
2nd Cycle
Op. Addr. Data
Subsequent
Op.
Addr.
Data
Read Memory Array
≥2
Write
X
FFh
Read
RA
RD
Read Electronic Signature
≥2
Write
X
90h
Read
IDA(2)
IDD(2)
Read Status Register
2
Write
X
70h
Read
X
SRD
Read Query
≥2
Write
X
98h
Read
QA(3)
QD(3)
Clear Status Register
1
Write
X
50h
Block Erase
2
Write
X
20h
Write
BA
D0
Word/Byte Program
2
Write
X
40h
10h
Write
PA
PD
BA
E8h
Write
BA
N
Write to Buffer and
Program
4 + N Write
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Block Protect
2
Write
X
60h
Write
BA
01h
Blocks Unprotect
2
Write
X
60h
Write
X
D0h
Protection Register
Program
2
Write
X
C0h
Write
PRA
PRD
Configure STS command
2
Write
X
B8h
Write
X
CC
Op.
Write
Final
Addr. Data Op. Addr. Data
PA
PD Write
X
D0h
Note: 1. X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program
Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, PRA Protection register address,
PRD Protection Register Data, CC Configuration Code.
2. For Identifier addresses and data refer to Table 6, Read Electronic Signature.
3. For Query Address and Data refer to Appendix B, CFI.
Table 5. Configuration Codes
Configuration
Code
DQ1
DQ2
Mode
00h
0
0
Ready/Busy
01h
0
1
Pulse on Erase
complete
02h
1
0
Pulse on
Program
complete
03h
1
1
Pulse on Erase
or Program
complete
STS Pin
VOL during P/E
operations
Hi-Z when the
memory is ready
Description
The STS pin is Low during Program and
Erase operations and high impedance when
the memory is ready for any Read, Program
or Erase operation.
Supplies a system interrupt pulse at the end
of a Block Erase operation.
Pulse Low then
High when
operation
completed(2)
Supplies a system interrupt pulse at the end
of a Program operation.
Supplies a system interrupt pulse at the end
of a Block Erase or Program operation.
Note: 1. DQ2-DQ7 are reserved
2. When STS pin is pulsing it remains Low for a typical time of 250ns.
17/51
M58LW032D
Table 6. Read Electronic Signature
Code
Address (A21-A1)(3)
Bus Width
Data (DQ15-DQ0)
x8
20h
Manufacturer Code
000000h
x16
0020h
x8
16h
Device Code
000001h
x16
0016h
x8
00h (Block Unprotected)
01h (Block Protected)
SBA(1)+02h
Block Protection Status
0000h (Block Unprotected)
0001h (Block Protected)
x16
Protection Register
000080h(2)
x8, x16
PRD(1)
Note: 1. SBA is the Start Base Address of each block, PRD is Protection Register Data.
2. Base Address, refer to Figure 6 and Tables 7 and 8 for more information.
3. A0 is not used in Read Electronic Signature in either x8 or x16 mode. The data is always presented on the lower byte in x16 mode.
Figure 6. Protection Register Memory Map
WORD
ADDRESS
88h
User Programmable
85h
84h
Unique device number
81h
80h
Protection Register Lock
1
0
AI05501
Table 7. Word-Wide Read Protection Register
Word
Use
A8
A7
A6
A5
A4
A3
A2
A1
Lock
Factory, User
1
0
0
0
0
0
0
0
0
Factory (Unique ID)
1
0
0
0
0
0
0
1
1
Factory (Unique ID)
1
0
0
0
0
0
1
0
2
Factory (Unique ID)
1
0
0
0
0
0
1
1
3
Factory (Unique ID)
1
0
0
0
0
1
0
0
4
User
1
0
0
0
0
1
0
1
5
User
1
0
0
0
0
1
1
0
6
User
1
0
0
0
0
1
1
1
7
User
1
0
0
0
1
0
0
0
18/51
M58LW032D
Table 8. Byte-Wide Read Protection Register
Word
Use
A8
A7
A6
A5
A4
A3
A2
A1
Lock
Factory, User
1
0
0
0
0
0
0
0
Lock
Factory, User
1
0
0
0
0
0
0
0
0
Factory (Unique ID)
1
0
0
0
0
0
0
1
1
Factory (Unique ID)
1
0
0
0
0
0
0
1
2
Factory (Unique ID)
1
0
0
0
0
0
1
0
3
Factory (Unique ID)
1
0
0
0
0
0
1
0
4
Factory (Unique ID)
1
0
0
0
0
0
1
1
5
Factory (Unique ID)
1
0
0
0
0
0
1
1
6
Factory (Unique ID)
1
0
0
0
0
1
0
0
7
Factory (Unique ID)
1
0
0
0
0
1
0
0
8
User
1
0
0
0
0
1
0
1
9
User
1
0
0
0
0
1
0
1
A
User
1
0
0
0
0
1
1
0
B
User
1
0
0
0
0
1
1
0
C
User
1
0
0
0
0
1
1
1
D
User
1
0
0
0
0
1
1
1
E
User
1
0
0
0
1
0
0
0
F
User
1
0
0
0
1
0
0
0
19/51
M58LW032D
Table 9. Program, Erase Times and Program Erase Endurance Cycles
M58LW032D
Parameters
Unit
Typ(1,2)
Max(2)
Block (1Mb) Erase
1.2
4.8(4)
s
Chip Program (Write to Buffer)
24
72(4)
s
Chip Erase Time
37
110 (4)
s
192 (3)
576 (4)
µs
Word/Byte Program Time
(Word/Byte Program command)
16
48 (4)
µs
Program Suspend Latency Time
1
20 (5)
µs
Erase Suspend Latency Time
1
25 (5)
µs
18
30 (5)
µs
0.75
1.2 (5)
s
Min
Program Write Buffer
Block Protect Time
Blocks Unprotect Time
Program/Erase Cycles (per block)
Data Retention
Note: 1.
2.
3.
4.
5.
20/51
100,000
cycles
20
years
Typical values measured at room temperature and nominal voltages.
Sampled, but not 100% tested.
Effective byte programming time 6µs, effective word programming time 12µs.
Maximum value measured at worst case conditions for both temperature and VDD after 100,000 program/erase cycles.
Maximum value measured at worst case conditions for both temperature and VDD.
M58LW032D
STATUS REGISTER
The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Register command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Resume commands. The Status Register can be
read from any address.
The contents of the Status Register can be updated during an Erase or Program operation by toggling the Output Enable pin or by dis-activating
and then reactivating the device (refer to Table 2,
Device Enable).
Status Register bits SR5, SR4, SR3 and SR1 are
associated with various error conditions and can
only be reset with the Clear Status Register command. The Status Register bits are summarized in
Table 10, Status Register Bits. Refer to Table 10
in conjunction with the following text descriptions.
Program/Erase Controller Status (SR7). The Program/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low, VOL, the Program/Erase Controller is active
and all other Status Register bits are High Impedance; when the bit is High, VOH, the Program/
Erase Controller is inactive.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller pauses the bit is High.
During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Controller Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Controller completes the operation and the bit is High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status and
Block Protection Status bits should be tested for
errors.
Erase Suspend Status (SR6). The Erase Suspend Status bit indicates that an Erase operation
has been suspended and is waiting to be resumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller
inactive); after a Program/Erase Suspend command is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is Low, VOL,
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is High, VOH, a
Program/Erase Suspend command has been issued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.
Erase Status (SR5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly or that all
blocks have been unprotected successfully. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
When the Erase Status bit is Low, VOL, the memory has successfully verified that the block has
erased correctly or all blocks have been unprotected successfully. When the Erase Status bit is
High, VOH, the erase operation has failed. Depending on the cause of the failure other Status
Register bits may also be set to High, VOH.
■ If only the Erase Status bit (SR5) is set High,
VOH, then the Program/Erase Controller has
applied the maximum number of pulses to the
block and still failed to verify that the block has
erased correctly or that all the blocks have been
unprotected successfully.
■ If the failure is due to an erase or blocks
unprotect with VPEN low, VOL, then VPEN Status
bit (SR3) is also set High, VOH.
■ If the failure is due to an erase on a protected
block then Block Protection Status bit (SR1) is
also set High, VOH.
■ If the failure is due to a program or erase
incorrect command sequence then Program
Status bit (SR4) is also set High, VOH.
Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a
hardware reset. If set High it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (SR4). The Program Status bit
is used to identify a Program or Block Protect failure. The Program Status bit should be read once
the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
When the Program Status bit is Low, VOL, the
memory has successfully verified that the Write
Buffer has programmed correctly or the block is
protected. When the Program Status bit is High,
VOH, the program or block protect operation has
failed. Depending on the cause of the failure other
Status Register bits may also be set to High, VOH.
■ If only the Program Status bit (SR4) is set High,
VOH, then the Program/Erase Controller has
applied the maximum number of pulses to the
21/51
M58LW032D
byte and still failed to verify that the Write Buffer
has programmed correctly or that the Block is
protected.
■ If the failure is due to a program or block protect
with VPEN low, VOL, then VPEN Status bit (SR3)
is also set High, VOH.
■ If the failure is due to a program on a protected
block then Block Protection Status bit (SR1) is
also set High, VOH.
■ If the failure is due to a program or erase
incorrect command sequence then Erase
Status bit (SR5) is also set High, VOH.
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
VPEN Status (SR3). The VPEN Status bit can be
used to identify if a Program, Erase, Block Protection or Block Unprotection operation has been attempted when VPEN is Low, VIL.
When the VPEN Status bit is Low, VOL, no Program, Erase, Block Protection or Block Unprotection operations have been attempted with VPEN
Low, VIL, since the last Clear Status Register command, or hardware reset. When the VPEN Status
bit is High, VOH, a Program, Erase, Block Protection or Block Unprotection operation has been attempted with VPEN Low, VIL.
Once set High, the VPEN Status bit can only be reset by a Clear Status Register command or a hardware reset. If set High it should be reset before a
new Program, Erase, Block Protection or Block
Unprotection command is issued, otherwise the
new command will appear to fail.
Program Suspend Status (SR2). The Program
Suspend Status bit indicates that a Program oper-
22/51
ation has been suspended and is waiting to be resumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend
command is issued the memory may still complete
the operation rather than entering the Suspend
mode.
When the Program Suspend Status bit is Low,
VOL, the Program/Erase Controller is active or has
completed its operation; when the bit is High, VOH,
a Program/Erase Suspend command has been issued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.
Block Protection Status (SR1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the
contents of a protected block.
When the Block Protection Status bit is Low, VOL,
no Program or Erase operations have been attempted to protected blocks since the last Clear
Status Register command or hardware reset;
when the Block Protection Status bit is High, VOH,
a Program (Program Status bit SR4 set High) or
Erase (Erase Status bit SR5 set High) operation
has been attempted on a protected block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
Reserved (SR0). Bit SR0 of the Status Register
is reserved. Its value should be masked.
M58LW032D
Table 10. Status Register Bits
OPERATION
SR7
SR6
SR5
SR4
SR3
SR2
SR1
Result
(Hex)
Program/Erase Controller active
0
Hi-Z
N/A
Write Buffer not ready
0
Hi-Z
N/A
Write Buffer ready
1
0
0
0
0
0
0
80h
Write Buffer ready in Erase Suspend
1
1
0
0
0
0
0
C0h
Program suspended
1
0
0
0
0
1
0
84h
Program suspended in Erase Suspend
1
1
0
0
0
1
0
C4h
Program/Block Protect completed
successfully
1
0
0
0
0
0
0
80h
Program completed successfully in Erase
Suspend
1
1
0
0
0
0
0
C0h
Program/Block protect failure due to incorrect
command sequence
1
0
1
1
0
0
0
B0h
Program failure due to incorrect command
sequence in Erase Suspend
1
1
1
1
0
0
0
F0h
Program/Block Protect failure due to VPEN
error
1
0
0
1
1
0
0
98h
Program failure due to VPEN error in Erase
Suspend
1
1
0
1
1
0
0
D8h
Program failure due to Block Protection
1
0
0
1
0
0
1
92h
Program failure due to Block Protection in
Erase Suspend
1
1
0
1
0
0
1
D2h
Program/Block Protect failure due to cell
failure
1
0
0
1
0
0
0
90h
Program failure due to cell failure in Erase
Suspend
1
1
0
1
0
0
0
D0h
Erase Suspended
1
1
0
0
0
0
0
C0h
Erase/Blocks Unprotect completed
successfully
1
0
0
0
0
0
0
80h
Erase/Blocks Unprotect failure due to
incorrect command sequence
1
0
1
1
0
0
0
B0h
Erase/Blocks Unprotect failure due to VPEN
error
1
0
1
0
1
0
0
A8h
Erase failure due to Block Protection
1
0
1
0
0
0
1
A2h
Erase/Blocks Unprotect failure due to failed
cells in Block
1
0
1
0
0
0
0
A0h
Configure STS error due to invalid
configuration code
1
0
1
1
0
0
0
B0h
23/51
M58LW032D
MAXIMUM RATING
Stressing the device above the ratings listed in Table 11, Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 11. Absolute Maximum Ratings
Value
Symbol
Parameter
Max
TBIAS
Temperature Under Bias
–40
125
°C
TSTG
Storage Temperature
–55
150
°C
Input or Output Voltage
–0.6
VDDQ +0.6
V
Supply Voltage
–0.6
5.0
V
100(1)
mA
VIO
VDD, VDDQ
IOSC
Output Short-circuit Current
Note: 1. Maximum one output short-circuited at a time and for no longer than 1 second.
24/51
Unit
Min
M58LW032D
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 12,
Operating and AC Measurement Conditions. Designers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
M58LW032D
Parameter
Units
Min
Max
Supply Voltage (VDD)
2.7
3.6
V
Input/Output Supply Voltage (VDDQ)
2.7
3.6
V
Grade 1
0
70
°C
Grade 6
–40
85
°C
Ambient Temperature (TA)
Load Capacitance (CL)
30
pF
Input Pulses Voltages
0 to VDDQ
V
Input and Output Timing Ref. Voltages
0.5 VDDQ
V
Figure 7. AC Measurement Input Output
Waveform
Figure 8. AC Measurement Load Circuit
1.3V
1N914
VDDQ
VDD
3.3kΩ
VDDQ
0.5 VDDQ
DEVICE
UNDER
TEST
0V
DQS
CL
AI00610
0.1µF
0.1µF
CL includes JIG capacitance
AI03459
Table 13. Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Typ
Max
Unit
VIN = 0V
6
8
pF
VOUT = 0V
8
12
pF
Note: 1. TA = 25°C, f = 1 MHz
2. Sampled only, not 100% tested.
25/51
M58LW032D
Table 14. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VDDQ
±1
µA
0V ≤ VOUT ≤ VDDQ
±5
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
IDD
Supply Current (Random Read)
E = VIL, f=5MHz
20
mA
IDDO
Supply Current (Page Read)
E = VIL, f=33MHz
29
mA
IDD1
Supply Current (Standby)
E = VIH, RP = VIH
40
µA
IDD5
Supply Current (Auto Low-Power)
E = VIL, RP = VIH
40
µA
IDD2
Supply Current (Reset/Power-Down)
RP = VIL
40
µA
IDD3
Supply Current (Program or Erase,
Block Protect, Block Unprotect)
Program or Erase operation in
progress
30
mA
IDD4
Supply Current
(Erase/Program Suspend)
E = VIH
40
µA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2
VDDQ + 0.5
V
VOL
Output Low Voltage
IOL = 100µA
0.2
V
VOH
Output High Voltage
IOH = –100µA
VLKO
VDD Supply Voltage (Erase and
Program lockout)
VPENH
26/51
VPEN Supply Voltage (block erase,
program and block protect)
VDDQ –0.2
V
2
V
2.7
3.6
V
M58LW032D
Figure 9. Bus Read AC Waveforms
tAVAV
A0-A21
VALID
tELQV
tELQX
tAXQX
E2, E1, E0 (1)
tGLQV
tEHQZ
tGLQX
tEHQX
G
tELBL
BYTE
(2)
tBLQV
tGHQZ
tGHQX
tBLQZ
tAVQV
DQ0-DQ15
OUTPUT
AI06239b
Note: 1. VIH = Device Disabled (first edge of E0, E1 or E2), VIL = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
details.
2. BYTE can be Low or High.
Table 15. Bus Read AC Characteristics.
M58LW032D
Symbol
Parameter
Test Condition
Unit
90
110
tAVAV
Address Valid to Address Valid
E = VIL, G = VIL
Min
90
110
ns
tAVQV
Address Valid to Output Valid
E = VIL, G = VIL
Max
90
110
ns
tAXQX
Address Transition to Output Transition
E = VIL, G = VIL
Min
0
0
ns
tBLQV
Byte Low (or High) to Output Valid
E = VIL, G = VIL
Max
1
1
µs
tBLQZ
Byte Low (or High) to Output Hi-Z
E = VIL, G = VIL
Max
1
1
µs
tEHQX
Chip Enable High to Output Transition
G = VIL
Min
0
0
ns
tEHQZ
Chip Enable High to Output Hi-Z
G = VIL
Max
25
25
ns
tELBL
Chip Enable Low to Byte Low (or High)
G = VIL
Max
10
10
ns
tELQX
Chip Enable Low to Output Transition
G = VIL
Min
0
0
ns
tELQV
Chip Enable Low to Output Valid
G = VIL
Max
90
110
ns
tGHQX
Output Enable High to Output Transition
E = VIL
Min
0
0
ns
tGHQZ
Output Enable High to Output Hi-Z
E = VIL
Max
15
15
ns
tGLQX
Output Enable Low to Output Transition
E = VIL
Min
0
0
ns
tGLQV
Output Enable Low to Output Valid
E = VIL
Max
25
25
ns
27/51
M58LW032D
Figure 10. Page Read AC Waveforms
A1-A2
VALID
A3-A21
VALID
VALID
tAVQV
tELQV
tELQX
tAXQX
E2, E1, E0(1)
tAVQV1
tGLQV
tGLQX
tAXQX1
tEHQZ
tEHQX
G
tGHQZ
tGHQX
DQ0-DQ15
OUTPUT
OUTPUT
AI06240
Note: 1. VIH = Device Disabled (first edge of E0, E1 or E2), VIL = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
details.
Table 16. Page Read AC Characteristics
M58LW032D
Symbol
Parameter
Test Condition
Unit
90 - 110
tAXQX1
Address Transition to Output Transition
E = VIL, G = VIL
Min
6
ns
tAVQV1
Address Valid to Output Valid
E = VIL, G = VIL
Max
25
ns
Note: For other timings see Table 15, Bus Read AC Characteristics.
28/51
M58LW032D
Figure 11. Write AC Waveform, Write Enable Controlled
A0-A21
VALID
tAVWH
tWHAX
E2, E1, E0(1)
tWHEH
tELWL
G
tGHWL
tWLWH
tWHGL
tWHWL
W
tDVWH
DQ0-DQ15
INPUT
tWHDX
STS
(Ready/Busy mode)
tVPHWH
tWHBL
VPEN
AI06241
Note: 1. VIH = Device Disabled (first edge of E0, E1 or E2), VIL = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
details.
Table 17. Write AC Characteristics, Write Enable Controlled
M58LW032D
Symbol
Parameter
Test Condition
Unit
90 - 110
tAVWH
Address Valid to Write Enable High
E = VIL
Min
50
ns
tDVWH
Data Input Valid to Write Enable High
E = VIL
Min
50
ns
tELWL
Chip Enable Low to Write Enable Low
Min
0
ns
Program/Erase Enable High to Write Enable High
Min
0
ns
Min
0
ns
Max
500
ns
Min
0
ns
tVPHWH
E = VIL
tWHAX
Write Enable High to Address Transition
tWHBL
Write Enable High to Status/(Ready/Busy) low
tWHDX
Write Enable High to Input Transition
tWHEH
Write Enable High to Chip Enable High
Min
0
ns
tGHWL
Output Enable High to Write Enable Low
Min
20
ns
tWHGL
Write Enable High to Output Enable Low
Min
35
ns
tWHWL
Write Enable High to Write Enable Low
Min
30
ns
tWLWH
Write Enable Low to Write Enable High
Min
70
ns
E = VIL
E = VIL
29/51
M58LW032D
Figure 12. Write AC Waveforms, Chip Enable Controlled
A0-A21
VALID
tAVEH
tEHAX
W
tWLEL
tEHWH
G
tGHEL
tELEH
tEHEL
tEHGL
E2, E1, E0(1)
tDVEH
DQ0-DQ15
INPUT
tEHDX
STS
(Ready/Busy mode)
tVPHEH
tEHBL
VPEN
AI06242
Note: 1. VIH = Device Disabled (first edge of E0, E1 or E2), VIL = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
details.
Table 18. Write AC Characteristics, Chip Enable Controlled.
M58LW032D
Symbol
Parameter
Test Condition
Unit
90 - 110
tAVEH
Address Valid to Chip Enable High
W = VIL
Min
50
ns
tDVEH
Data Input Valid to Chip Enable High
W = VIL
Min
50
ns
tWLEL
Write Enable Low to Chip Enable Low
Min
0
ns
tVPHEH
Program/Erase Enable High to Chip Enable High
Min
0
ns
tEHAX
Chip Enable High to Address Transition
Min
0
ns
tEHBL
Chip Enable High to Status/(Ready/Busy) low
Max
500
ns
tEHDX
Chip Enable High to Input Transition
Min
0
ns
tEHWH
Chip Enable High to Write Enable High
Min
0
ns
tGHEL
Output Enable High to Chip Enable Low
Min
20
ns
tEHGL
Chip Enable High to Output Enable Low
Min
35
ns
tEHEL
Chip Enable High to Chip Enable Low
Min
30
ns
tELEH
Chip Enable Low to Chip Enable High
Min
70
ns
30/51
W = VIL
W = VIL
W = VIL
M58LW032D
Figure 13. Reset, Power-Down and Power-Up AC Waveform
W
tPHWL
E2, E1, E0(1), G
DQ0-DQ15
tPHQV
STS
(Ready/Busy mode)
tPLBH
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
and Reset
Reset during
Program or Erase
AI06217b
Note: 1. VIH = Device Disabled (first edge of E0, E1 or E2), VIL = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
details.
Table 19. Reset, Power-Down and Power-Up AC Characteristics
M58LW032D
Symbol
Parameter
Unit
90
110
tPHQV
Reset/Power-Down High to Data Valid
Max
130
150
ns
tPHWL
Reset/Power-Down High to Write Enable Low
Max
1
1
µs
tPLPH
Reset/Power-Down Low to Reset/Power-Down High
Min
100
100
ns
tPLBH
Reset/Power-Down Low to Status/(Ready/Busy) High
Max
30
30
µs
Supply Voltages High to Reset/Power-Down High
Min
0
0
µs
tVDHPH
31/51
M58LW032D
PACKAGE MECHANICAL
Figure 14. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline
A2
N
1
e
E
B
N/2
D1
A
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
Table 20. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
mm
inches
Symbol
Typ
Min
A
Typ
Min
1.20
Max
0.0472
A1
0.05
0.15
0.0020
0.0059
A2
0.95
1.05
0.0374
0.0413
B
0.17
0.27
0.0067
0.0106
C
0.10
0.21
0.0039
0.0083
D
19.80
20.20
0.7795
0.7953
D1
18.30
18.50
0.7205
0.7283
E
13.90
14.10
0.5472
0.5551
–
–
–
–
L
0.50
0.70
0.0197
0.0276
α
0°
5°
0°
5°
N
56
e
CP
32/51
Max
0.50
0.0197
56
0.10
0.0039
M58LW032D
Figure 15. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline
D
D1
FD
FE
E
SD
SE
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
Note: Drawing is not to scale.
Table 21. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
A1
Max
Typ
Min
1.200
0.300
0.200
A2
0.350
0.0472
0.0118
0.0079
0.850
b
0.400
0.500
Max
0.0138
0.0335
0.0157
0.0197
D
10.000
9.900
10.100
0.3937
0.3898
0.3976
D1
7.000
–
–
0.2756
–
–
ddd
0.100
0.0039
e
1.000
–
–
0.0394
–
–
E
13.000
12.900
13.100
0.5118
0.5079
0.5157
E1
7.000
–
–
0.2756
–
–
FD
1.500
–
–
0.0591
–
–
FE
3.000
–
–
0.1181
–
–
SD
0.500
–
–
0.0197
–
–
SE
0.500
–
–
0.0197
–
–
33/51
M58LW032D
PART NUMBERING
Table 22. Ordering Information Scheme
Example:
M58LW032D
110 N
1
T
Device Type
M58
Architecture
L = Page Mode
Operating Voltage
W = VDD = VDDQ = 2.7V to 3.6V
Device Function
032D = 32 Mbit (x8, x16), Uniform Block
Speed
110 = 110ns
90 = 90ns
Package
N = TSOP56: 14 x 20 mm
ZA = TBGA64: 10 x 13 mm, 1mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Note: Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
34/51
M58LW032D
APPENDIX A. BLOCK ADDRESS TABLE
Table 23. Block Addresses
Block
Number
Address Range
(x8 Bus Width)
Address Range
(x16 Bus Width)
32
3E0000h-3FFFFFh
1F0000h-1FFFFFh
31
3C0000h-3DFFFFh
1E0000h-1EFFFFh
30
3A0000h-3BFFFFh
1D0000h-1DFFFFh
29
380000h-39FFFFh
1C0000h-1CFFFFh
28
360000h-37FFFFh
1B0000h-1BFFFFh
27
340000h-35FFFFh
1A0000h-1AFFFFh
26
320000h-33FFFFh
190000h-19FFFFh
25
300000h-31FFFFh
180000h-18FFFFh
24
2E0000h-2FFFFFh
170000h-17FFFFh
23
2C0000h-2DFFFFh
160000h-16FFFFh
22
2A0000h-2BFFFFh
150000h-15FFFFh
21
280000h-29FFFFh
140000h-14FFFFh
20
260000h-27FFFFh
130000h-13FFFFh
19
240000h-25FFFFh
120000h-12FFFFh
18
220000h-23FFFFh
110000h-11FFFFh
17
200000h-21FFFFh
100000h-10FFFFh
16
1E0000h-1FFFFFh
0F0000h-0FFFFFh
15
1C0000h-1DFFFFh
0E0000h-0EFFFFh
14
1A0000h-1BFFFFh
0D0000h-0DFFFFh
13
180000h-19FFFFh
0C0000h-0CFFFFh
12
160000h-17FFFFh
0B0000h-0BFFFFh
11
140000h-15FFFFh
0A0000h-0AFFFFh
10
120000h-13FFFFh
090000h-09FFFFh
9
100000h-11FFFFh
080000h-08FFFFh
8
0E0000h-0FFFFFh
070000h-07FFFFh
7
0C0000h-0DFFFFh
060000h-06FFFFh
6
0A0000h-0BFFFFh
050000h-05FFFFh
5
080000h-09FFFFh
040000h-04FFFFh
4
060000h-07FFFFh
030000h-03FFFFh
3
040000h-05FFFFh
020000h-02FFFFh
2
020000h-03FFFFh
010000h-01FFFFh
1
000000h-01FFFFh
000000h-00FFFFh
35/51
M58LW032D
APPENDIX B. COMMON FLASH INTERFACE - CFI
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command (RCFI) is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 24, 25,
26, 27, 28 and 29 show the addresses used to retrieve the data.
Table 24. Query Structure Overview
Address
Sub-section Name
Description
x16
x8(4)
0000h
00h
Manufacturer Code
0001h
02h
Device Code
0010h
20h
CFI Query Identification String
Command set ID and algorithm data offset
001Bh
36h
System Interface Information
Device timing and voltage information
0027h
4Eh
Device Geometry Definition
Flash memory layout
P(h)(1)
Primary Algorithm-specific Extended
Query Table
Additional information specific to the Primary
Algorithm (optional)
A(h)(2)
Alternate Algorithm-specific Extended
Query Table
Additional information specific to the Alternate
Algorithm (optional)
Block Status Register
Block-related Information
(SBA+02)h
Note: 1.
2.
3.
4.
Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.
Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
SBA is the Start Base Address for each block.
In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
Table 25. CFI - Query Address and Data Output
Address
Data
Description
x16
x8(3)
0010h
20h
51h
"Q"
0011h
22h
52h
"R"
0012h
24h
59h
"Y"
0013h
26h
01h
0014h
28h
00h
0015h
2Ah
31h
0016h
2Ch
00h
0017h
2Eh
00h
0018h
30h
00h
0019h
32h
00h
001Ah(2)
34h
00h
Query ASCII String
51h; "Q"
52h; "R"
59h; "Y"
Primary Vendor:
Command Set and Control Interface ID Code
Primary algorithm extended Query Address Table: P(h)
Alternate Vendor:
Command Set and Control Interface ID Code
Alternate Algorithm Extended Query address Table
Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to '0'.
2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
3. In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
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M58LW032D
Table 26. CFI - Device Voltage and Timing Specification
Address
Data
Description
x16
x8(4)
001Bh
36h
27h (1)
VDD Min, 2.7V
001Ch
38h
36h (1)
VDD max, 3.6V
001Dh
3Ah
00h (2)
VPP min – Not Available
001Eh
3Ch
00h (2)
VPP max – Not Available
001Fh
3Eh
04h
2n µs typical time-out for Word, DWord prog – Not Available
0020h
40h
08h
2n µs, typical time-out for max buffer write
0021h
42h
0Ah
2n ms, typical time-out for Erase Block
0022h
44h
00h (3)
0023h
46h
04h
2n x typical for Word Dword time-out max – Not Available
0024h
48h
04h
2n x typical for buffer write time-out max
0025h
4Ah
04h
2n x typical for individual block erase time-out maximum
0026h
4Ch
00h (3)
2n x typical for chip erase max time-out – Not Available
Note: 1.
2.
3.
4.
2n ms, typical time-out for chip erase – Not Available
Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.
Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.
Not supported.
In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
Table 27. Device Geometry Definition
Address
Data
Description
x16
x8(1)
0027h
4Eh
16h
n where 2n is number of bytes memory Size
0028h
50h
02h
Device Interface
0029h
52h
00h
Organization Sync./Async.
002Ah
54h
05h
002Bh
56h
00h
002Ch
58h
01h
002Dh
5Ah
1Fh
002Eh
5Ch
00h
002Fh
5Eh
00h
0030h
60h
02h
Maximum number of bytes in Write Buffer, 2n
Bit7-0 = number of Erase Block Regions in device
Number (n-1) of Erase Blocks of identical size; n=64
Erase Block Region Information
x 256 bytes per Erase block (128K bytes)
Note: 1. In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
37/51
M58LW032D
Table 28. Block Status Register
Address
Data
Selected Block Information
0
Block Unprotected
1
Block Protected
0
Last erase operation ended successfully (3)
1
Last erase operation not ended successfully (3)
0
Reserved for future features
bit0
(BA+2)h(1,2)
bit1
bit7-2
Note: 1. BA specifies the block address location, A21-A17.
2. In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
3. Not Supported.
38/51
M58LW032D
Table 29. Extended Query information
Address
Data (Hex)
Description
offset
x16
x8(2)
(P)h
0031h
62h
50h
"P"
(P+1)h
0032h
64h
52h
"R"
(P+2)h
0033h
66h
49h
"Y"
(P+3)h
0034h
68h
31h
Major version number
(P+4)h
0035h
6Ah
31h
Minor version number
(P+5)h
0036h
6Ch
CEh
(P+6)h
0037h
6Eh
00h
(P+7)h
0038h
70h
00h
(P+8)h
0039h
72h
00h
Optional Feature: (1=yes, 0=no)
bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Protect/Unprotect Supported (1=yes)
bit4, Queue Erase Supported (0=no)
bit5, Instant Individual Block locking (0=no)
bit6, Protection bits supported (1=yes)
bit7, Page Read supported (1=yes)
bit8, Synchronous Read supported (0 =no)
bits 9 to 31 reserved for future use
(P+9)h
003Ah
74h
01h
(P+A)h
003Bh
76h
01h
(P+B)h
003Ch
78h
00h
(P+C)h
003Dh
7Ah
33h
VDD OPTIMUM Program/Erase voltage conditions
(P+D)h
003Eh
7Ch
00h
VPP OPTIMUM Program/Erase voltage conditions
(P+E)h
003Fh
7Eh
01h
OTP protection: No. of Protection Register fields
(P+F)h
0040h
80h
80h
Protection Register’s start address, least significant bits
(P+10)h
0041h
82h
00h
Protection Register’s start address, most significant bits
(P+11)h
0042h
84h
03h
n where 2n is number of factory reprogrammed bytes
(P+12)h
0043h
86h
03h
n where 2n is number of user programmable bytes
(P+13)h
0044h
88h
03h
Page Read: 2n Bytes (n = bits 0-7)
(P+14)h
0045h
8Ah
00h
Synchronous mode configuration fields
(P+15)h
0046h
8Ch
Query ASCII string - Extended Table
Function allowed after Suspend:
Program allowed after Erase Suspend (1=yes)
Bits 7-1 reserved for future use
Block Status Register
bit0, Block Protect Bit status active (1=yes)
bit1, Block Lock-Down Bit status active (not supported)
bits 2 to 15 Reserved for future use
Reserved for future use
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
2. In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
39/51
M58LW032D
APPENDIX C. FLOW CHARTS
Figure 16. Write to Buffer and Program Flowchart and Pseudo Code
Start
Write to Buffer E8h
Command, Block Address
Read Status
Register
NO
SR7 = 1
NO
Write to Buffer
Timeout
YES
YES
Note 1: N+1 is number of Words
to be programmed
Write N(1),
Block Address
Try Again Later
Write Buffer Data,
Start Address
X=0
X=N
YES
NO
Note 2: Next Program Address must
have same A5-A21.
Write Next Buffer Data,
Next Program Address(2)
X=X+1
Program Buffer to Flash
Confirm D0h
Read Status
Register
SR7 = 1
NO
YES
Note 3: A full Status Register Check must be
done to check the program operation's
success.
Full Status
Register Check(3)
End
40/51
AI05511
M58LW032D
Figure 17. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
– read status register
Read Status
Register
SR7 = 1
NO
while SR7 = 1
YES
SR2 = 1
NO
Program Complete
If SR2 = 0, Program completed
YES
Read Memory Array command:
– write FFh
– one or more data reads
from other blocks
Write FFh
Read data from
another block
Write D0h
Write FFh
Program Continues
Read Data
Program Erase Resume Command:
– write D0h
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).
AI00612b
41/51
M58LW032D
Figure 18. Erase Flowchart and Pseudo Code
Start
Erase command:
– write 20h
– write D0h to Block Address
(A12-A17)
(memory enters read Status
Register after the Erase command)
Write 20h
Write D0h to
Block Address
NO
Read Status
Register
Suspend
SR7 = 1
YES
NO
Suspend
Loop
do:
– read status register
– if Program/Erase Suspend command
given execute suspend erase loop
while SR7 = 1
YES
SR3 = 0
NO
VPEN Invalid
Error (1)
NO
Command
Sequence Error
NO
Erase
Error (1)
NO
Erase to Protected
Block Error
If SR3 = 1, VPEN invalid error:
– error handler
YES
SR4, SR5 = 0
If SR4, SR5 = 1, Command Sequence error:
– error handler
YES
SR5 = 0
If SR5 = 1, Erase error:
– error handler
YES
SR1 = 0
If SR1 = 1, Erase to Protected Block Error:
– error handler
YES
End
AI00613C
Note: 1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase operations.
42/51
M58LW032D
Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
– read status register
Read Status
Register
SR7 = 1
NO
while SR7 = 1
YES
SR6 = 1
NO
Erase Complete
If SR6 = 0, Erase completed
YES
Read Memory Array command:
– write FFh
– one or more data reads
from other blocks
Write FFh
Read data from
another block
or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command:
– write D0h to resume the Erase
operation
– if the Program operation completed
then this is not necessary. The device
returns to Read mode as normal
(as if the Program/Erase suspend
was not issued).
AI00615b
43/51
M58LW032D
Figure 20. Block Protect Flowchart and Pseudo Code
Start
Write 60h
Block Address
Block Protect Command
– write 60h, Block Adress
– write 01h, Block Adress
Write 01h
Block Address
do:
– read status register
Read Status Register
SR7 = 1
NO
while SR7 = 1
YES
SR3 = 1
YES
VPEN Invalid Error
If SR3 = 1, VPEN Invalid Error
YES
Invalid Command
Sequence Error
If SR4 = 1, SR5 = 1 Invalid Command Sequence
Error
YES
Block Protect
Error
NO
SR4, SR5 = 1,1
NO
SR4 = 1
If SR4 = 1, Block Protect Error
NO
Write FFh
Read Memory Array Command:
– write FFh
Block Protect
Sucessful
AI06157b
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M58LW032D
Figure 21. Block Unprotect Flowchart and Pseudo Code
Start
Write 60h
Blocks Unprotect Command
– write 60h, Block Adress
– write D0h, Block Adress
Write D0h
do:
– read status register
Read Status Register
SR7 = 1
NO
while SR7 = 1
YES
SR3 = 1
YES
VPEN Invalid Error
If SR3 = 1, VPEN Invalid Error
YES
Invalid Command
Sequence Error
If SR4 = 1, SR5 = 1 Invalid Command
Sequence Error
YES
Blocks Unprotect
Error
NO
SR4, SR5 = 1,1
NO
SR5 = 1
If SR5 = 1, Blocks Unprotect Error
NO
Write FFh
Read Memory Array Command:
– write FFh
Blocks Unprotect
Sucessful
AI06158b
45/51
M58LW032D
Figure 22. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
Protection Register Program Command
– write C0h
– write Protection Register Address,
Protection Register Data
Write
PR Address, PR Data
do:
– read status register
Read Status Register
SR7 = 1
NO
while SR7 = 1
YES
YES
SR3, SR4 = 1,1
VPEN Invalid Error
If SR3 = 1, SR4 = 1 VPEN Invalid Error
NO
YES
Protection Register
Program Error
If SR1 = 0, SR4 = 1 Protection Register
Program Error
YES
Protection Register
Program Error
If SR1 = 1, SR4 = 1 Program Error due to
Protection Register Protection
SR1, SR4 = 0,1
NO
SR1, SR4 = 1,1
NO
Write FFh
Read Memory Array Command:
– write FFh
PR Program
Sucessful
AI06159b
Note: PR = Protection Register
46/51
M58LW032D
Figure 23. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE
90h
NO
YES
READ
SIGNATURE
98h
NO
YES
CFI
QUERY
70h
NO
YES
READ
STATUS
READ
ARRAY
NO
50h
YES
CLEAR
STATUS
E8h
NO
YES
PROGRAM
BUFFER
LOAD
20h(1)
NO
YES
ERASE
SET-UP
NO
PROGRAM
COMMAND
ERROR
FFh
D0h
YES
NO
YES
D0h
NO
YES
C
A
ERASE
COMMAND
ERROR
B
Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
AI03618
47/51
M58LW032D
Figure 24. Command Interface and Program Erase Controller Flowchart (b)
A
B
ERASE
READ
STATUS
YES
(READ STATUS)
Program/Erase Controller
READY Status bit in the Status
Register
?
NO
READ
ARRAY
B0h
YES
NO
YES
FFh
READ
STATUS
NO
ERASE
SUSPEND
NO
YES
ERASE
SUSPENDED
READY
?
NO
READ
STATUS
YES
WAIT FOR
COMMAND
WRITE
READ
STATUS
YES
70h
NO
READ
SIGNATURE
YES
90h
NO
CFI
QUERY
YES
98h
NO
PROGRAM
BUFFER
LOAD
YES
E8h
NO
PROGRAM
COMMAND
ERROR
NO
D0h
YES
c
D0h
YES
READ
STATUS
(ERASE RESUME)
NO
READ
ARRAY
AI03619
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M58LW032D
Figure 25. Command Interface and Program Erase Controller Flowchart (c).
B
C
PROGRAM
READ
STATUS
YES
READY
?
(READ STATUS)
Program/Erase Controller
Status bit in the Status
Register
NO
READ
ARRAY
B0h
NO
YES
YES
NO
READ
STATUS
FFh
PROGRAM
SUSPEND
NO
YES
PROGRAM
SUSPENDED
READY
?
NO
YES
WAIT FOR
COMMAND
WRITE
READ
STATUS
YES
READ
STATUS
70h
NO
READ
SIGNATURE
YES
90h
NO
CFI
QUERY
YES
98h
NO
READ
ARRAY
NO
D0h
YES
READ
STATUS
(PROGRAM RESUME)
AI00618
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M58LW032D
REVISION HISTORY
Table 30. Document Revision History
Date
04-Jun-2002
Version
Revision Details
-01
First Issue
1.1
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot.
(revision version 01 becomes 1.0).
Figure 5 modified. tWHDX and tWHAX modified in Table 17.
2.0
Device Code changed, Word Effective Programming Time modified, VDDQ range
modified (esp. in Tables 12 and 22, and VDDQ removed from note 1 below Table 9).
Block Erase and Program Write Buffer Time parameters modified in Table 9.
90ns Speed Class added (Table 15, 16, 17, 18, 19 and 22 modified accordingly).
Figure 2, Logic Diagram modified. VDD, VDDQ, VSS and VSSQ pin descriptions
modified. Document status changed from Product Preview to Preliminary Data.
2.1
A0 Address Line described separately from others (A1-A21) in Table 1 and in
“SIGNAL DESCRIPTIONS” paragraph. Address Lines modified in Table 3, Bus
Operations. Byte signal added to Figure 9, Bus Read AC Waveforms, timings tELBL,
tBLQV and tBLQZ added to Table 15, Bus Read AC Characteristics, timings tAVLH and
tELLH removed from Table 18, Write AC Characteristics, Chip Enable Controlled. Chip
Enable Controlled. “Write 70h” removed from flowchart Figures 17 and 19. Table 3,
Bus operations, clarified. REVISION HISTORY moved to after the appendices.
16-Dec-2002
2.2
Table 9, Program, Erase Times and Program Erase Endurance Cycles table modified.
Table 6, Read Electronic Signature table clarified. Certain DU connections changed to
NC in Table 4, TBGA64 Connections (Top view through package). x8 Address
modified in Table 24, Query Structure Overview. Note regarding A0 value in x8 mode
added to all CFI Tables. Block Protect setup command address modified in Table 4,
Commands. Data and Descriptions clarified in CFI Table 29, Extended Query
information. IOSC parameter added to Absolute Maximum Ratings table. IDD and VLKO
clarified and IDDO and VPENH parameters added to DC Characteristics table. tPHWL
parameter added to Reset, Power-Down and Power-Up AC Waveforms figure and
Characteristics table.
30-May-2003
2.3
Summary Description clarified, Bus Operations clarified, READ MODES section
added, Status Register bit nomenclature modified, VPEN Invalid Error clarified in
Flowcharts. Lead-free packing options added to Ordering Information Scheme.
12-Sep-2003
2.4
tEHAX and tEHDX minimum values modified in Table 18, Write AC Characteristics, Chip
Enable Controlled.
Full datasheet.
16-Jun-2002
06-Aug-2002
14-Oct-2002
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M58LW032D
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