AD ADV7180 10-bit, 4 oversampling sdtv video decoder Datasheet

10-Bit, 4× Oversampling
SDTV Video Decoder
ADV7180
Data Sheet
APPLICATIONS
19B
Qualified for automotive applications
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling
for Y/C mode, and 2× oversampling for YPrPb (per channel)
3 video input channels with on-chip antialiasing filter
CVBS (composite), Y/C (S-Video), and YPrPb (component)
video input support
5-line adaptive comb filters and CTI/DNR video
enhancement
Mini-TBC functionality provided by adaptive digital line
length tracking (ADLLT), signal processing, and enhanced
FIFO management
Integrated AGC with adaptive peak white mode
Macrovision copy protection detection
NTSC/PAL/SECAM autodetection
8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, and FIELD1
1.0 V analog input signal range
Full-featured VBI data slicer with teletext support (WST)
Power-down mode and ultralow sleep mode current
2-wire serial MPU interface (I2C compatible)
Single 1.8 V supply possible
1.8 V analog, 1.8 V PLL, 1.8 V digital, 1.8 V to 3.3 V I/O supply
−10°C to +70°C commercial temperature grade
−40°C to +85°C industrial/automotive qualified temperature
grade
−40°C to +125°C temperature grade for automotive qualified
4 package types
64-lead, 10 mm × 10 mm, RoHS compliant LQFP
48-Lead, 7 mm × 7 mm, RoHS compliant LQFP
40-lead, 6 mm × 6 mm, RoHS compliant LFCSP
32-lead, 5 mm × 5 mm, RoHS compliant LFCSP
Digital camcorders and PDAs
Low cost SDTV PIP decoders for digital TVs
Multichannel DVRs for video security
AV receivers and video transcoding
PCI-/USB-based video capture and TV tuner cards
Personal media players and recorders
Smartphone/multimedia handsets
In-car/automotive infotainment units
Rearview camera/vehicle safety systems
GENERAL DESCRIPTION
18B
The ADV7180 automatically detects and converts standard
analog baseband television signals compatible with worldwide
NTSC, PAL, and SECAM standards into 4:2:2 component video
data compatible with the 8-bit ITU-R BT.656 interface standard.
The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devices, Inc., digital video encoders, such as the ADV7391.
External HS, VS, and FIELD signals provide timing references
for LCD controllers and other video ASICs, if required. Accurate
10-bit analog-to-digital conversion provides professional quality
FUNCTIONAL BLOCK DIAGRAM
20B
AIN2
AIN3
AIN41
AIN51
AIN61
MUX BLOCK
AIN1
AA
FILTER
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
VBI SLICER
AA
FILTER
COLOR
DEMOD
I2C/CONTROL
REFERENCE
LLC
8-BIT/16-BIT2
PIXEL DATA
FIFO
ANALOG
VIDEO
INPUTS
PLL
OUTPUT BLOCK
XTAL
P15 TO P0
VS
HS
FIELD3
GPO5
SFL
INTRQ
ADV7180
SCLK SDATA ALSB RESET PWRDWN4
1ONLY AVAILABLE ON 64-LEAD PACKAGE AND 48-LEAD PACKAGES.
216-BIT ONLY AVAILABLE ON 64-LEAD PACKAGE.
348-LEAD, 40-LEAD, AND 32-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD.
4NOT AVAILABLE ON 32-LEAD PACKAGE.
5ONLY AVAILABLE ON 48-LEAD AND 64-LEAD PACKAGES.
Figure 1.
video performance for consumer applications with true 8-bit
data resolution. Three analog video input channels accept standard
composite, S-Video, or component video signals, supporting a
wide range of consumer video sources. AGC and clamp-restore
circuitry allow an input video signal peak-to-peak range to 1.0 V.
Alternatively, these can be bypassed for manual settings.
The line-locked clock output allows the output data rate, timing
signals, and output clock signals to be synchronous, asynchronous,
or line locked even with ±5% line length variation. Output
control signals allow glueless interface connections in many
applications. The ADV7180 is programmed via a 2-wire, serial
bidirectional port (I2C-compatible) and is fabricated in a 1.8 V
CMOS process. Its monolithic CMOS construction ensures greater
functionality with lower power dissipation. LFCSP package options
make the decoder ideal for space-constrained portable applications.
The 64-lead LQFP package is pin compatible with the ADV7181C.
1
Rev. J
CLOCK PROCESSING BLOCK
XTAL1
05700-001
FEATURES
17B
The 48-Lead LQFP, 40-lead LFCSP, and 32-lead LFCSP use one pin to output
VS or FIELD.
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ADV7180
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Video Processor .............................................................................. 26
General Description ......................................................................... 1
SD Luma Path ............................................................................. 26
Applications ....................................................................................... 1
SD Chroma Path ......................................................................... 26
Functional Block Diagram .............................................................. 1
Sync Processing .......................................................................... 27
Revision History ............................................................................... 3
VBI Data Recovery..................................................................... 27
Introduction ...................................................................................... 5
General Setup .............................................................................. 27
Analog Front End ......................................................................... 5
Color Controls ............................................................................ 29
Standard Definition Processor ................................................... 5
Clamp Operation........................................................................ 31
Functional Block Diagrams ............................................................. 6
Luma Filter .................................................................................. 32
Specifications..................................................................................... 8
Chroma Filter.............................................................................. 35
Electrical Characteristics ............................................................. 8
Gain Operation ........................................................................... 36
Video Specifications ..................................................................... 9
Chroma Transient Improvement (CTI) .................................. 40
Timing Specifications ................................................................ 10
Digital Noise Reduction (DNR) and Luma Peaking Filter ... 41
Analog Specifications ................................................................. 11
Comb Filters ................................................................................ 42
Thermal Specifications .............................................................. 11
IF Filter Compensation ............................................................. 44
Absolute Maximum Ratings.......................................................... 12
AV Code Insertion and Controls ............................................. 45
ESD Caution ................................................................................ 12
Synchronization Output Signals............................................... 47
Pin Configurations and Function Descriptions ......................... 13
Sync Processing .......................................................................... 54
32-Lead LFCSP ........................................................................... 13
VBI Data Decode ....................................................................... 54
40-Lead LFCSP ........................................................................... 14
I2C Readback Registers .............................................................. 63
64-Lead LQFP ............................................................................. 15
Pixel Port Configuration ............................................................... 76
48-Lead LQFP ............................................................................. 17
GPO Control ................................................................................... 77
Power Supply Sequencing .............................................................. 18
MPU Port Description ................................................................... 78
Power-Up Sequence ................................................................... 18
Register Access............................................................................ 79
Power-Down Sequence .............................................................. 18
Register Programming............................................................... 79
Universal Power Supply ............................................................. 18
I2C Sequencer .............................................................................. 79
Analog Front End ........................................................................... 19
I2C Register Maps ........................................................................... 80
Input Configuration ................................................................... 20
PCB Layout Recommendations.................................................. 107
Analog Input Muxing ................................................................ 21
Analog Interface Inputs ........................................................... 107
Antialiasing Filters ..................................................................... 22
Power Supply Decoupling ....................................................... 107
Global Control Registers ............................................................... 23
PLL ............................................................................................. 107
Power-Saving Modes .................................................................. 23
VREFN and VREFP ................................................................. 107
Reset Control .............................................................................. 23
Digital Outputs (Both Data and Clocks) .............................. 107
Global Pin Control ..................................................................... 23
Digital Inputs ............................................................................ 107
Global Status Register .................................................................... 25
Typical Circuit Connection ......................................................... 108
Identification ............................................................................... 25
Outline Dimensions ..................................................................... 112
Status 1 ......................................................................................... 25
Ordering Guide ........................................................................ 114
Autodetection Result.................................................................. 25
Automotive Products ............................................................... 114
Status 2 ......................................................................................... 25
Status 3 ......................................................................................... 25
Rev. J | Page 2 of 114
Data Sheet
ADV7180
REVISION HISTORY
1/15—Rev. I to Rev. J
Changes to Table 3 ............................................................................ 8
Changes to Table 16, Table 17, and Table 18................................24
Changes to Table 107 ......................................................................99
Updated Outline Dimensions ......................................................112
Changes to Ordering Guide .........................................................114
2/14—Rev. H to Rev. I
Changes to Figure 3 Caption and Figure 4 Caption ..................... 6
Changes to Figure 7.........................................................................10
1/14—Rev. G to Rev. H
Changes to Figure 1........................................................................... 1
Changes to Figure 3 and Figure 4.................................................... 6
Changes to Analog Supply Current Parameter, Table 3 ............... 8
Changes to Data and Control Outputs Parameter, Table 5........10
Added Power Supply Sequencing Section ...................................18
Deleted Power-On RESET Section ...............................................21
Changes to Drive Strength Selection Data Section.....................24
Changes to Luma Gain Section .....................................................37
Changes to Comb Filters Section ..................................................42
Changes to Table 105 ......................................................................80
Deleted Register Select (SR7 to SR0) Section ..............................81
Changes to Table 107 ......................................................................84
Changes to Table 108 and Table Summary Statement .............100
Deleted I2C Programming Examples Section ............................106
Updated Outline Dimensions (Lead-to-Pad Dimension) .......112
3/12—Rev. F to Rev. G
Changed ADV7179 to ADV7391 Throughout ............................. 1
Changes to Figure 12 ......................................................................18
Changes to Table 14 ........................................................................19
Changes to Power-On RESET Section and MAN_MUX_EN,
Manual Input Muxing Enable, Address 0xC4[7] Section ..........20
Changed NTSM to NTSC Throughout ........................................24
Deleted ADV7190, ADV7191, and ADV7192 Throughout ......27
Change to DEF_C[7:0], Default Value C, Address 0x0D[7:0]
Section ..............................................................................................29
Changes to Luma Filter Section ....................................................31
Changes to Table 39 and LAGT[1:0], Luma Automatic Gain
Timing, Address 0x2F[7:6] Section ..............................................36
Changed Calculation of the Luma Calibration Factor Section
Heading to Calculation of the Chroma Calibration Factor
Section ..............................................................................................38
Changes to Range, Range Selection, Address 0x04[0] Section.......45
Changes to PHS, Polarity HS, Address 0x37[7] Section ............46
Changes to 0x0D, 0x1D, 0x2C, 0x37, and 0x41, Table 107 ........85
Changes to Power Supply Decoupling Section .........................110
Deleted Figure 55; Renumbered Sequentially ...........................110
Changes to Figure 55 ....................................................................111
Changes to Figure 56 ....................................................................112
Changes to Figure 57 ....................................................................113
Changes to Figure 58 ....................................................................114
Changes to Ordering Guide .........................................................117
7/10—Rev. E to Rev. F
Added 48-Lead LQFP ...................................................Throughout
Changes to Features Section ............................................................ 1
Changes to Table 2 ............................................................................ 4
Added Figure 5; Renumbered Sequentially ................................... 6
Added Input Current (SDA, SCLK) Parameter and Input
Current (PWRDWN) Parameter, Table 3 ...................................... 7
Added Figure 11 and Table 12; Renumbered Sequentially ........ 16
Changes to MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7] Section ................................................................ 19
Added GDE_SEL_OLD_ADF Bit Description, Table 107 ........ 92
Moved 32-Lead LFCSP Section...................................................108
Added Figure 58 ............................................................................112
Updated Outline Dimensions......................................................115
Changes to Ordering Guide .........................................................116
2/10—Rev. D to Rev. E
Added 32-Lead LFCSP .................................................Throughout
Changes to Features .......................................................................... 1
Changes to Figure 1 .......................................................................... 1
Changes to Introduction .................................................................. 4
Added Figure 4, Renumbered Sequentially ................................... 8
Added Figure 9 and Table 11 ......................................................... 14
Changes to Figure 11 ...................................................................... 15
Changes to Table 12 and Table 13 ................................................. 16
Changes to Power-On Reset Section, Analog Input Muxing
Section, and Table 14 ...................................................................... 17
Changes to PDBP Section and TOD Section .............................. 19
Changes to Identification Section ................................................. 21
Changes to VS and FIELD Configuration Section and SQPE
Section .............................................................................................. 44
Changes to Table 99 and Table 100 ............................................... 72
Changes to GPO Control Section ................................................. 73
Changes to Table 104 ...................................................................... 76
Changes to Table 106 ...................................................................... 80
Added Figure 56 ............................................................................108
Added Figure 59 ............................................................................110
Changes to Ordering Guide .........................................................110
6/09—Rev. C to Rev. D
Change to General Description....................................................... 1
Deleted Comparison with the ADV7181B Section ...................... 5
Deleted Figure 2; Renumbered Sequentially ................................. 5
Changes to Power Requirements Parameter, Table 2 ................... 6
Changes to Table 29 ........................................................................ 25
Changes to Figure 33 ...................................................................... 44
Changes to Subaddress 0x0A Notes, Table 104 ........................... 81
Changes to Ordering Guide .........................................................110
Rev. J | Page 3 of 114
ADV7180
Data Sheet
4/09—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Absolute Maximum Ratings, Table 7....................... 11
Changes to Figure 7 and Table 8, EPAD Addition ..................... 12
Added Power-On RESET Section ................................................ 17
Changes to MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7] Section and Table 12 ........................................ 17
Changes to Identification Section ................................................ 21
Added Table 16; Renumbered Sequentially ................................ 21
Changes to Table 21 ........................................................................ 23
Changes to CIL[2:0], Count Into Lock, Address 0x51[2:0]
Section and COL[2:0], Count Out of Lock, Address 0x51[5:3]
Section .............................................................................................. 25
Changes to Table 32 and Table 33 ................................................ 30
Changes to Table 34 ........................................................................ 32
Changes to Table 42 ........................................................................ 35
Changes to Table 52 ........................................................................ 38
Changes to Table 53 and Table 56 ................................................ 39
Changes to Table 61 and Figure 32............................................... 43
Added SQPE, Square Pixel Mode, Address 0x01[2] Section .... 44
Changes to NEWAVMODE, New AV Mode, Address 0x31[4]
Section .............................................................................................. 44
Changes to Figure 34 ...................................................................... 45
Changes to NFTOG[4:0], NTSC Field Toggle,
Address 0xE7[4:0] Section............................................................. 47
Changes to PFTOG, PAL Field Toggle, Address 0xEA[4:0]
Section .............................................................................................. 49
Changes to VDP Manuel Configuration Section ....................... 50
Changes to Table 66 ........................................................................ 51
Changes to Table 71 ........................................................................ 54
Changes to Table 72 ........................................................................ 55
Changes to VPS Section and PDC/UTC Section ....................... 63
Changes to Gemstar_2x Format, Half-Byte Output Mode
Section .............................................................................................. 66
Changes to NTSC CCAP Data Section and PAL CCAP Data
Section .............................................................................................. 69
Changes to Figure 48 ...................................................................... 74
Changes to I2C Sequencer Section ............................................... 75
Changes to Table 102...................................................................... 76
Changes to Table 104...................................................................... 80
Changes to Table 105...................................................................... 97
Changes to Figure 53 .................................................................... 108
Changes to Figure 54 .................................................................... 109
Added Exposed Paddle Notation to Outline Dimensions ...... 110
Changes to Ordering Guide ........................................................ 111
2/07—Rev. A to Rev. B
Changes to SFL_INV, Subcarrier Frequency Lock Inversion
Section.............................................................................................. 24
Changes to Table 103, Register 0x41 ............................................ 90
Updated Outline Dimensions ..................................................... 111
11/06—Rev. 0 to Rev. A
Changes to Table 10 and Table 11 ................................................ 16
Changes to Table 30 ....................................................................... 28
Changes to Gain Operation Section ............................................ 33
Changes to Table 43 ....................................................................... 35
Changes to Table 97 ....................................................................... 72
Changes to Table 99 ....................................................................... 73
Changes to Table 103 ..................................................................... 80
Changes to Figure 54.................................................................... 110
1/06—Revision 0: Initial Version
Rev. J | Page 4 of 114
Data Sheet
ADV7180
INTRODUCTION
The ADV7180 is a versatile one-chip multiformat video decoder
that automatically detects and converts PAL, NTSC, and SECAM
standards in the form of composite, S-Video, and component
video into a digital ITU-R BT.656 format.
The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devices digital video encoders, such as the ADV7391.
External HS, VS, and FIELD signals provide timing references
for LCD controllers and other video ASICs that do not support the
ITU-R BT.656 interface standard. The different package options
available for the ADV7180 are shown in Table 2.
ANALOG FRONT END
The ADV7180 analog front end comprises a single high speed,
10-bit analog-to-digital converter (ADC) that digitizes the
analog video signal before applying it to the standard definition
processor. The analog front end employs differential channels to
the ADC to ensure high performance in mixed-signal applications.
The front end also includes a 3-channel input mux that enables
multiple composite video signals to be applied to the ADV7180.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see Figure 29). Fine clamping of the video signal
is performed downstream by digital fine clamping within the
ADV7180.
Table 1 shows the three ADC clocking rates that are determined by
the video input format to be processed—that is, INSEL[3:0].
These clock rates ensure 4× oversampling per channel for CVBS
mode and 2× oversampling per channel for Y/C and YPrPb modes.
Table 1. ADC Clock Rates
Input Format
CVBS
Y/C (S-Video)2
YPrPb
1
2
ADC Clock Rate (MHz)1
57.27
86
86
STANDARD DEFINITION PROCESSOR
The ADV7180 is capable of decoding a large selection of baseband
video signals in composite, S-Video, and component formats.
The video standards supported by the video processor include
PAL B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J,
NTSC 4.43, and SECAM B/D/G/K/L. The ADV7180 can automatically detect the video standard and process it accordingly.
The ADV7180 has a five-line, superadaptive, 2D comb filter
that gives superior chrominance and luminance separation
when decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the video
standard and signal quality without requiring user intervention.
Video user controls such as brightness, contrast, saturation, and
hue are also available with the ADV7180.
The ADV7180 implements a patented ADLLT™ algorithm to
track varying video line lengths from sources such as a VCR.
ADLLT enables the ADV7180 to track and decode poor quality
video sources such as VCRs and noisy sources from tuner outputs,
VCD players, and camcorders. The ADV7180 contains a chroma
transient improvement (CTI) processor that sharpens the edge
rate of chroma transitions, resulting in sharper vertical transitions.
The video processor can process a variety of VBI data services,
such as closed captioning (CCAP), wide screen signaling (WSS),
copy generation management system (CGMS), EDTV, Gemstar®
1×/2×, and extended data service (XDS). Teletext data slicing
for world standard teletext (WST), along with program delivery
control (PDC) and video programming service (VPS), are
provided. Data is transmitted via the 8-bit video output port as
ancillary data packets (ANC). The ADV7180 is fully Macrovision®
certified; detection circuitry enables Type I, Type II, and Type III
protection levels to be identified and reported to the user. The
decoder is also fully robust to all Macrovision signal inputs.
Oversampling
Rate per Channel
4×
2×
2×
Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins.
See INSEL[3:0] in Table 107 for the mandatory write for Y/C (S-Video) mode.
Table 2. ADV7180 Selection Guide
Part Number1
ADV7180KCP32Z
ADV7180WBCP32Z (Automotive)
ADV7180BCPZ
ADV7180WBCPZ (Automotive)
ADV7180BSTZ
ADV7180WBSTZ (Automotive)
ADV7180WBST48Z (Automotive)
1
Package Type
32-lead LFCSP
32-lead LFCSP
40-lead LFCSP
40-lead LFCSP
64-lead LQFP
64-lead LQFP
48-lead LQFP
Analog Inputs
3
3
3
3
6
6
6
W = Automotive qualification completed.
Rev. J | Page 5 of 114
Digital Outputs
8-bit
8-bit
8-bit
8-bit
8-bit/16-bit
8-bit/16-bit
8-bit
Temperature Grade
−10°C to +70°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +85°C
−40°C to +125°C
−40°C to +85°C
ADV7180
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
1B
CLOCK PROCESSING BLOCK
ANALOG
VIDEO
INPUTS
AIN2
AIN3
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
VBI SLICER
AA
FILTER
COLOR
DEMOD
LLC
8-BIT
PIXEL DATA
FIFO
AA
FILTER
PLL
P7 TO P0
HS
VS/FIELD
SFL
INTRQ
I2C/CONTROL
REFERENCE
05700-055
AIN1
MUX BLOCK
XTAL
OUTPUT BLOCK
XTAL1
SCLK SDATA ALSB RESET
Figure 2. 32-Lead LFCSP Functional Diagram
CLOCK PROCESSING BLOCK
AIN3
AIN4
AIN5
AIN6
AA
FILTER
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
VBI SLICER
AA
FILTER
COLOR
DEMOD
LLC
16-BIT
PIXEL DATA
HS
VS
FIELD
GPO0 TO GPO3
SFL
INTRQ
I2C/CONTROL
REFERENCE
P15 TO P0
05700-003
ANALOG
VIDEO
INPUTS
AIN2
MUX BLOCK
AIN1
PLL
FIFO
XTAL
OUTPUT BLOCK
XTAL1
SCLK SDATA ALSB RESET PWRDWN
Figure 3. 64-Lead LQFP Functional Block Diagram
CLOCK PROCESSING BLOCK
ANALOG
VIDEO
INPUTS
AIN2
AIN3
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
VBI SLICER
AA
FILTER
COLOR
DEMOD
I2C/CONTROL
REFERENCE
LLC
8-BIT
PIXEL DATA
FIFO
AA
FILTER
PLL
P7 TO P0
HS
VS/FIELD
SFL
INTRQ
SCLK SDATA ALSB RESET PWRDWN
Figure 4. 40-Lead LFCSP Functional Block Diagram
Rev. J | Page 6 of 114
05700-004
AIN1
MUX BLOCK
XTAL
OUTPUT BLOCK
XTAL1
Data Sheet
ADV7180
CLOCK PROCESSING BLOCK
AIN3
AIN4
AIN5
AIN6
AA
FILTER
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
AA
FILTER
VBI SLICER
COLOR
DEMOD
I2C/CONTROL
REFERENCE
LLC
8-BIT
PIXEL DATA
P7 TO P0
VS/FIELD
HS
GPO0 TO GPO3
SFL
INTRQ
SCLK SDATA ALSB RESET PWRDWN
Figure 5. 48-Lead LQFP Functional Block Diagram
Rev. J | Page 7 of 114
05700-060
ANALOG
VIDEO
INPUTS
AIN2
MUX BLOCK
AIN1
PLL
FIFO
XTAL
OUTPUT BLOCK
XTAL1
ADV7180
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range,
unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage (DVDDIO = 3.3 V)
Input High Voltage (DVDDIO = 1.8 V)
Input Low Voltage (DVDDIO = 3.3 V)
Input Low Voltage (DVDDIO = 1.8 V)
Crystal Inputs
Input Current
Input Current (SDA, SCLK)1
Input Current (PWRDWN)2
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage (DVDDIO = 3.3 V)
Output High Voltage (DVDDIO = 1.8 V)
Output Low Voltage (DVDDIO = 3.3 V)
Output Low Voltage (DVDDIO = 1.8 V)
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS3, 4, 5
Digital Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Supply Current
Digital I/O Supply Current6
PLL Supply Current
Analog Supply Current
Power-Down Current
Total Power Dissipation in Power-Down Mode9
Power-Up Time
Symbol
Test Conditions/Comments
N
INL
DNL
BSL in CVBS mode
CVBS mode
VIH
VIH
VIL
VIL
VIH
VIL
IIN
IIN
IIN
CIN
Min
Typ
Max
Unit
10
Bits
LSB
LSB
2
−0.6/+0.6
2
1.2
0.4
+10
+15
+48
10
V
V
V
V
V
V
µA
µA
µA
pF
0.4
0.2
10
20
V
V
V
V
µA
pF
0.8
0.4
1.2
−10
−10
−10
VOH
VOH
VOL
VOL
ILEAK
COUT
ISOURCE = 0.4 mA
ISOURCE = 0.4 mA
ISINK = 3.2 mA
ISINK = 1.6 mA
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
IAVDD
2.4
1.4
1.65
1.62
1.65
1.71
CVBS input7
CVBS input8
Y/C input
YPrPb input
IDVDD
IDVDDIO
IPVDD
IAVDD
tPWRUP
1.8
3.3
1.8
1.8
77
3
12
33
43
59
77
6
0.1
1
1
15
20
ADV7180KCP32Z, ADV7180WBCP32Z, and ADV7180WBST48Z only.
Applies to ADV7180WBST48Z, ADV7180WBST48Z-RL, ADV7180KST48Z, ADV7180KST48Z-RL, ADV7180BST48Z, ADV7180BST48Z-RL only.
3
Guaranteed by characterization.
4
Typical current consumption values are recorded with nominal voltage supply levels and a SMPTEBAR pattern.
5
Maximum current consumption values are recorded with maximum rated voltage supply levels and a multiburst pattern.
6
Typical (Typ) number is measured with DVDDIO = 3.3 V and maximum (Max) number is measured with DVDDIO = 3.6 V.
7
CVBS input when CVBS_IBIAS[3:0] (User Map, Register 0x52, Bits[3:0]) equal 0b’1011.
8
CVBS input when CVBS_IBIAS[3:0] (User Map, Register 0x52, Bits [3:0]) equal 0b’1101. Recommended setting.
9
ADV7180 clocked.
1
2
Rev. J | Page 8 of 114
2
3.6
2.0
1.89
85
5
15
43
53
75
94
10
1
5
5
44
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µW
ms
Data Sheet
ADV7180
VIDEO SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 4.
Parameter
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
Analog Front-End Crosstalk
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
fSC Subcarrier Lock Range
Color Lock-In Time
Sync Depth Range
Color Burst Range
Vertical Lock Time
Autodetection Switch Speed
Chroma Luma Gain Delay
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
Symbol
Test Conditions/Comments
Min
Typ
DP
DG
LNL
CVBS input, modulate five-step [NTSC]
CVBS input, modulate five-step [NTSC]
CVBS input, five-step [NTSC]
0.6
0.5
2.0
Degrees
%
%
Luma ramp
Luma flat field
57.1
58
60
dB
dB
dB
−5
40
Max
+5
70
2
100
2.9
5.6
−3.0
%
Hz
kHz
Lines
%
%
Fields
Lines
ns
ns
ns
1
1
%
%
±1.3
60
20
5
CVBS
Y/C
YPrPb
CVBS, 1 V input
CVBS, 1 V input
Rev. J | Page 9 of 114
Unit
200
200
ADV7180
Data Sheet
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 5.
Parameter
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Times
SCLK and SDA Fall Times
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Data Output Transitional Time
t12
Test Conditions
Min
Typ
Max
Unit
±50
MHz
ppm
28.6363
400
0.6
1.3
0.6
0.6
100
300
300
0.6
5
t9:t10
ms
45:55
t11
55:45
Negative clock edge to start of valid data
(tSETUP = t10 − t11)
End of valid data to negative clock edge
(tHOLD = t9 − t12)
Timing Diagrams
t3
t5
t3
SDATA
t1
t6
t4
t7
05700-005
SCLK
t2
t8
Figure 6. I C Timing
2
t9
t10
OUTPUT LLC
t11
05700-006
t12
OUTPUTS P0 TO P7, HS,
VS/FIELD/SFL
Figure 7. Pixel Port and Control Output Timing
Rev. J | Page 10 of 114
kHz
µs
µs
µs
µs
ns
ns
ns
µs
% duty cycle
3.6
ns
2.4
ns
Data Sheet
ADV7180
ANALOG SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 6.
Parameter
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large-Clamp Source Current
Large-Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
Test Conditions
Min
Clamps switched off
Typ
Max
0.1
10
0.4
0.4
10
10
Unit
µF
MΩ
mA
mA
µA
µA
THERMAL SPECIFICATIONS
Table 7.
Parameter
THERMAL CHARACTERISTICS
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Symbol
Test Conditions
θJA
4-layer PCB with solid ground plane, 32-lead LFCSP
32.5
°C/W
θJC
θJA
4-layer PCB with solid ground plane, 32-lead LFCSP
4-layer PCB with solid ground plane, 40-lead LFCSP
2.3
30
°C/W
°C/W
θJC
θJA
4-layer PCB with solid ground plane, 40-lead LFCSP
4-layer PCB with solid ground plane, 64-lead LQFP
3
47
°C/W
°C/W
θJC
θJA
4-layer PCB with solid ground plane, 64-lead LQFP
4-layer PCB with solid ground plane, 48-lead LQFP
11.1
50
°C/W
°C/W
θJC
4-layer PCB with solid ground plane, 48-lead LQFP
20
°C/W
Rev. J | Page 11 of 114
Min
Typ
Max
Unit
ADV7180
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
AVDD to AGND
DVDD to DGND
PVDD to AGND
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO to PVDD
DVDDIO to DVDD
AVDD to PVDD
AVDD to DVDD
Digital Inputs Voltage
Digital Outputs Voltage
Analog Inputs to AGND
Maximum Junction Temperature
(TJ max)
Storage Temperature Range
Infrared Reflow Soldering (20 sec)
Rating
2.2 V
2.2 V
2.2 V
4V
−0.3 V to +4 V
−0.3 V to +0.9 V
–0.3 V to +4 V
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +0.9 V
DGND − 0.3 V to DVDDIO + 0.3 V
DGND − 0.3 V to DVDDIO + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
140°C
This device is a high performance integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
−65°C to +150°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. J | Page 12 of 114
Data Sheet
ADV7180
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
4B
32-LEAD LFCSP
32
31
30
29
28
27
26
25
INTRQ
VS/FIELD
DVDD
DGND
SCLK
SDATA
ALSB
RESET
31B
1
2
3
4
5
6
7
8
PIN1
INDICATOR
ADV7180
LFCSP
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
AIN3
AIN2
AVDD
VREFN
VREFP
AIN1
PVDD
ELPF
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
05700-057
P3
P2
LLC
XTAL1
XTAL
DVDD
P1
P0
9
10
11
12
13
14
15
16
HS
DGND
DVDDIO
SFL
P7
P6
P5
P4
Figure 8. 32-Lead LFCSP Pin Configuration
Table 9. 32-Lead LFCSP Pin Function Descriptions
Pin No.
1
2, 29
3
4
Mnemonic
HS
DGND
DVDDIO
SFL
Type
O
G
P
O
5 to 10, 15, 16
11
P7 to P2, P1, P0
LLC
O
O
12
XTAL1
O
13
XTAL
I
14, 30
17
18
19, 23, 24
20
21
22
25
DVDD
ELPF
PVDD
AIN1 to AIN3
VREFP
VREFN
AVDD
RESET
P
I
P
I
O
O
P
I
26
ALSB
I
27
28
31
32
SDATA
SCLK
VS/FIELD
INTRQ
I/O
I
O
O
E
A
E
A
EPAD (EP)
Description
Horizontal Synchronization Output Signal.
Ground for Digital Supply.
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
Video Pixel Output Port.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or
down according to video line length.
This pin should be connected to the 28.6363 MHz crystal or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
Digital Supply Voltage (1.8 V).
The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 60.
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Internal Voltage Reference Output. See Figure 60 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 60 for recommended output circuitry.
Analog Supply Voltage (1.8 V).
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7180 circuitry.
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
(see Table 108).
The exposed pad must be connected to GND.
Rev. J | Page 13 of 114
ADV7180
Data Sheet
40-LEAD LFCSP
40
39
38
37
36
35
34
33
32
31
DGND
HS
INTRQ
VS/FIELD
DVDD
DGND
SCLK
SDATA
ALSB
RESET
32B
PIN 1
INDICATOR
ADV7180
LFCSP
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
AIN3
AIN2
AGND
AVDD
VREFN
VREFP
AGND
AIN1
TEST_0
AGND
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
05700-007
LLC
XTAL1
XTAL
DVDD
DGND
P1
P0
PWRDWN
ELPF
PVDD
11
12
13
14
15
16
17
18
19
20
DVDDIO 1
SFL 2
DGND 3
DVDDIO 4
P7 5
P6 6
P5 7
P4 8
P3 9
P2 10
Figure 9. 40-Lead LFCSP Pin Configuration
Table 10. 40-Lead LFCSP Pin Function Descriptions
Pin No.
1, 4
2
Mnemonic
DVDDIO
SFL
Type
P
O
3, 15, 35, 40
5 to 10, 16, 17
11
DGND
P7 to P2, P1, P0
LLC
G
O
O
12
XTAL1
O
13
XTAL
I
14, 36
18
19
20
21, 24, 28
22
23, 29, 30
25
26
27
31
DVDD
PWRDWN
ELPF
PVDD
AGND
TEST_0
AIN1 to AIN3
VREFP
VREFN
AVDD
RESET
P
I
I
P
G
I
I
O
O
P
I
32
ALSB
I
33
34
37
38
SDATA
SCLK
VS/FIELD
INTRQ
I/O
I
O
O
39
HS
EPAD (EP)
O
E
A
E
A
E
A
Description
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
Ground for Digital Supply.
Video Pixel Output Port.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or
down according to video line length.
This pin should be connected to the 28.6363 MHz crystal or not connected if an external 1.8 V,
28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal
must be a fundamental crystal.
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
Digital Supply Voltage (1.8 V).
A logic low on this pin places the ADV7180 into power-down mode.
The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 57.
PLL Supply Voltage (1.8 V).
Ground for Analog Supply.
This pin must be tied to DGND.
Analog Video Input Channels.
Internal Voltage Reference Output. See Figure 57 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 57 for recommended output circuitry.
Analog Supply Voltage (1.8 V).
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7180 circuitry.
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
(see Table 108).
Horizontal Synchronization Output Signal.
The exposed pad must be connected to GND.
Rev. J | Page 14 of 114
64 63 62 61 60 59 58
NC
AIN6
RESET
GPO3
SCLK
DGND
GPO2
DVDD
P14
P15
P13
P12
FIELD
VS
64-LEAD LQFP
SDATA
ADV7180
ALSB
Data Sheet
57 56 55 54 53 52 51 50 49
48
AIN5
47
AIN4
3
46
AIN3
DVDDIO
4
45
NC
P11
5
44
NC
P10
6
43
AGND
P9
7
P8
8
SFL
9
INTRQ
1
HS
2
DGND
PIN 1
ADV7180
LQFP
TOP VIEW
(Not to Scale)
42
NC
41
NC
40
AVDD
DGND 10
39
VREFN
DVDDIO 11
38
VREFP
GPO1 12
37
AGND
GPO0 13
36
AIN2
P7 14
35
AIN1
P6 15
34
TEST_0
P5 16
33
NC
05700-008
NC = NO CONNECT
AGND
ELPF
PVDD
NC
PWRDWN
P0
NC
P1
DVDD
DGND
XTAL
XTAL1
LLC
P2
P4
P3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 10. 64-Lead LQFP Pin Configuration
Table 11. 64-Lead LQFP Pin Function Description
Pin No.
1
Mnemonic
INTRQ
Type
O
2
3, 10, 24, 57
4, 11
5 to 8, 14 to 19,
25, 26, 59 to 62
O
G
P
O
9
HS
DGND
DVDDIO
P11 to P8,
P7 to P2, P1,
P0, P15 to P12
SFL
O
12, 13, 55, 56
20
GPO0 to GPO3
LLC
O
O
21
XTAL1
O
22
XTAL
I
23, 58
27, 28, 33, 41, 42,
44, 45, 50
29
30
31
32, 37, 43
34
35, 36, 46 to 49
38
DVDD
NC
P
PWRDWN
ELPF
PVDD
AGND
TEST_0
AIN1 to AIN6
VREFP
I
I
P
G
I
I
O
Description
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 108).
Horizontal Synchronization Output Signal.
Digital Ground.
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital video
encoder.
General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices.
This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz but varies up or down according to video line length.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode,
the crystal must be a fundamental crystal.
This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external
1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental
crystal.
Digital Supply Voltage (1.8 V).
No Connect. These pins are not connected internally.
A logic low on this pin places the ADV7180 in power-down mode.
The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 58.
PLL Supply Voltage (1.8 V).
Analog Ground.
This pin must be tied to DGND.
Analog Video Input Channels.
Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.
Rev. J | Page 15 of 114
ADV7180
Data Sheet
Pin No.
39
40
51
Mnemonic
VREFN
AVDD
RESET
Type
O
P
I
52
ALSB
I
53
54
63
64
SDATA
SCLK
FIELD
VS
I/O
I
O
O
Description
Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.
Analog Supply Voltage (1.8 V).
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Field Synchronization Output Signal.
Vertical Synchronization Output Signal.
Rev. J | Page 16 of 114
Data Sheet
ADV7180
RESET
ALSB
SDATA
SCLK
GPO3
GPO2
DGND
DVDD
VS/FIELD
INTRQ
HS
NC
48-LEAD LQFP
DGND 1
36
AIN6
35
AIN5
SFL 3
34
AIN4
DVDDIO 4
33
AIN3
GPO1 5
ADV7180
32
AGND
GPO0 6
LQFP
TOP VIEW
(Not to Scale)
31
AVDD
30
VFEFN
29
VREFP
P5 9
28
AGND
P4 10
27
AIN2
P3 11
26
AIN1
P2 12
25
PVDD
PIN 1
2
P7 7
P6 8
ELPF
AGND
P0
PWRDWN
P1
DGND
DVDD
XTAL1
NC
LLC
13 14 15 16 17 18 19 20 21 22 23 24
DGND
NC = NO CONNECT
XTAL
DVDDIO
05700-062
48 47 46 45 44 43 42 41 40 39 38 37
Figure 11. 48-Lead LQFP Pin Configuration
Table 12. 48-Lead LQFP Pin Function Descriptions
Pin No.
1, 13, 19, 43
2, 4
3
Mnemonic
DGND
DVDDIO
SFL
Type
G
P
O
5, 6, 41, 42
7 to 12, 20, 22
14
GPO0 to GPO3
P7 to P2, P1, P0
LLC
O
O
O
15, 48
16
NC
XTAL1
O
17
XTAL
I
18, 44
21
23, 28, 32
DVDD
PWRDWN
AGND
P
I
G
24
25
26, 27, 33 to 36
29
30
31
37
ELPF
PVDD
AIN1 to AIN6
VREFP
VREFN
AVDD
RESET
I
P
I
O
O
P
I
38
ALSB
I
39
40
45
46
SDATA
SCLK
VS/FIELD
INTRQ
I/O
I
O
O
47
HS
O
E
E
E
Description
Digital Ground.
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices.
Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.
This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz but varies up or down according to video line length.
No Connect Pins. These pins are not connected internally.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 1.8 V,
28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal
must be a fundamental crystal.
This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
Digital Supply Voltage (1.8 V).
A logic low on this pin places the ADV7180 in power-down mode.
Analog Ground.
The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 59.
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Internal Voltage Reference Output. See Figure 59 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 59 for recommended output circuitry.
Analog Supply Voltage (1.8 V).
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
(see Table 108).
Horizontal Synchronization Output Signal.
Rev. J | Page 17 of 114
ADV7180
Data Sheet
POWER SUPPLY SEQUENCING
POWER-UP SEQUENCE
POWER-DOWN SEQUENCE
The power-up sequence for the ADV7180 is to power up all power
supplies simultaneously. If this is not possible, the 3.3 V supply
(DVDDIO) must be established first. When the 3.3 V supply is stable,
power up the 1.8 V supplies (DVDD, PVDD, and AVDD) as quickly as
possible. Until the 1.8 V supplies are fully established, all digital
pins are in an undefined state.
The ADV7180 supplies can be deasserted simultaneously as
long as DVDDIO does not go below a lower rated supply.
UNIVERSAL POWER SUPPLY
The ADV7180 can operate with a DVDDIO supply at a nominal
value of 1.8 V. Therefore, it is possible to power up all the supplies
for the ADV7180 (DVDD, AVDD, PVDD, and DVDDIO) to 1.8 V.
During power-up, all supplies must adhere to the specifications
listed in the Absolute Maximum Ratings section.
When DVDDIO is at a nominal value of 1.8 V, power up the
ADV7180 in the following manner:
Take care to ensure that a lower rated supply does not go above
a higher rated supply. For example, the 3.3 V DVDDIO supply must
never drop below a 1.8 V supply such as the DVDD, PVDD, or AVDD.
1.
To power up the ADV7180, follow these steps.
3.3V SUPPLIES
3.3V
If it is not possible to power up the DVDDIO and 1.8 V supplies simultaneously,
the DVDDIO supply must be powered up first. When the DVDDIO is stable, power
up the 1.8 V supplies as quickly as possible.
2
During power-up, take care to ensure that the DVDDIO supply never drops
below any of the 1.8 V supplies.
1
PWRDWN PIN
RESET PIN
1.8V
1.8V
SUPPLIES
RESET PIN
POWER-UP
PWRDWN PIN
POWER-UP
SUPPLIES
POWER-UP
TIME
5ms
WAIT
5ms
RESET
OPERATION
Figure 12. Power-Up Sequence of the 40-Lead LFCSP, 48-Lead LQFP, and 64-Lead LQFP
3.3V SUPPLIES
3.3V
RESET PIN
1.8V
1.8V
SUPPLIES
RESET PIN
POWER-UP
SUPPLIES
POWER-UP
5ms
RESET
OPERATION
5ms
WAIT
Figure 13. Power-Up Sequence of the 32-Lead LFCSP
Rev. J | Page 18 of 114
TIME
05700-100
4.
5.
3.
05700-101
3.
VOLTAGE
2.
2.
Assert the PWRDWN pin and the RESET pin (that is, pull
the pins low.)
Power up the 3.3 V supply (DVDDIO) and 1.8 V supplies
(DVDD, PVDD, and AVDD) simultaneously.1, 2
When all supplies are fully asserted, pull the PWRDWN
pin high. Note that this step can be ignored on the 32-lead
LFCSP, as the PWRDWN pin is not available.
Wait 5 ms, then pull the RESET pin high.
When all power supplies, the PWRDWN pin, and the RESET
pin are powered up and stable, wait an additional 5 ms
before initiating I2C communication with the ADV7180.
VOLTAGE
1.
Follow the power-up sequence described in the Power-Up
Sequence section, but power up the DVDDIO supply to 1.8 V
instead of 3.3 V. In addition, power up the PWRDWN pin
and the RESET pin to 1.8 V instead of 3.3 V.
Set the drive strengths of the digital outputs of the ADV7180
to their maximum setting. See the Global Pin Control section.
Connect any pull-up resistors connected to pins on the
ADV7180, such as the SCLK pin and the SDATA pin, to
1.8 V, rather than 3.3 V.
Data Sheet
ADV7180
ANALOG FRONT END
6B
AIN2
AIN1
AIN4
AIN3
AIN6
AIN5
MAN_MUX_EN
AIN2
AIN1
AIN4
AIN3
AIN6
AIN5
AIN4
AIN3
AIN6
AIN5
MUX_0[2:0]
MUX_1[2:0]
ADC
MUX_2[2:0]
05700-009
AIN2
AIN6
AIN5
Figure 14. 64-Lead and 48-Lead LQFP Internal Pin Connections
AIN1
AIN2
AIN3
MAN_MUX_EN
AIN1
AIN2
AIN3
AIN2
AIN3
MUX_0[2:0]
MUX_1[2:0]
ADC
MUX_2[2:0]
05700-010
AIN3
Figure 15. 40-Lead and 32-Lead LFCSP Internal Pin Connections
Rev. J | Page 19 of 114
ADV7180
Data Sheet
INPUT CONFIGURATION
Table 13. 64-Lead and 48-Lead LQFP INSEL[3:0]
The following are the two key steps for configuring the
ADV7180 to correctly decode the input video:
INSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
Video Format
Composite
Composite
Composite
Composite
Composite
Composite
Y/C (S-Video)
0111
Y/C (S-Video)
1000
Y/C (S-Video)
1001
YPrPb
1010
YPrPb
1011 to 1111
Reserved
38B
1.
2.
Use INSEL[3:0] to configure the routing and format decoding
(CVBS, Y/C, or YPrPb). For the 64-lead and 48-lead LQFP,
see Table 13. For the 40-lead and 32-lead LFCSP, see Table 14.
If the input requirements are not met using the INSEL[3:0]
options, the analog input muxing section must be configured
manually to correctly route the video from the analog
input pins to the ADC. The standard definition processor
block, which decodes the digital data, must be configured
to process the CVBS, Y/C, or YPrPb format. This is performed
by INSEL[3:0] selection.
CONNECT ANALOG VIDEO
SIGNALS TO ADV7180.
SET INSEL[3:0] TO CONFIGURE
VIDEO FORMAT. USE PREDEFINED
FORMAT/ROUTING.
NO
REFER TO
TABLE 13
LFCSP-40
LFCSP-32
REFER TO
TABLE 14
CONFIGURE ADC INPUTS USING
MANUAL MUXING CONTROL BITS:
MUX_0[2:0], MUX_1[2:0], MUX_2[2:0].
SEE TABLE 15.
Table 14. 40-Lead and 32-Lead LFCSP INSEL[3:0]
05700-011
LQFP-64
LQFP-48
YES
Figure 16. Signal Routing Options
INSEL[3:0], Input Selection, Address 0x00[3:0]
80B
The INSEL bits allow the user to select the input format. They
also configure the standard definition processor core to process
composite (CVBS), S-Video (Y/C), or component (YPrPb) format.
INSEL[3:0] has predefined analog input routing schemes that
do not require manual mux programming (see Table 13 and
Table 14). This allows the user to route the various video signal
types to the decoder and select them using INSEL[3:0] only.
The added benefit is that if, for example, the CVBS input is
selected, the remaining channels are powered down.
Analog Input
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
CVBS input on AIN5
CVBS input on AIN6
Y input on AIN1
C input on AIN4
Y input on AIN2
C input on AIN5
Y input on AIN3
C input on AIN6
Y input on AIN1
Pb input on AIN4
Pr input on AIN5
Y input on AIN2
Pr input on AIN6
Pb input on AIN3
Reserved
INSEL[3:0]
0000
0001 to 0010
0011
0100
0101
0110
Video Format
Composite
Reserved
Composite
Composite
Reserved
Y/C (S-Video)
0111 to 1000
1001
Reserved
YPrPb
1010 to 1111
Reserved
Rev. J | Page 20 of 114
Analog Input
CVBS input on AIN1
Reserved
CVBS input on AIN2
CVBS input on AIN3
Reserved
Y input on AIN1
C input on AIN2
Reserved
Y input on AIN1
Pr input on AIN3
Pb input on AIN2
Reserved
Data Sheet
ADV7180
ANALOG INPUT MUXING
The ADV7180 has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder. Figure 14 and Figure 15 outline the overall structure of
the input muxing provided in the ADV7180.
A maximum of six CVBS inputs can be connected to and
decoded by the 64-lead and 48-lead devices, and a maximum of
three CVBS inputs can be connected to and decoded by the 40-lead
and 32-lead LFCSP devices. As shown in the Pin Configurations
and Function Descriptions section, these analog input pins lie
in close proximity to one another, which requires careful design
of the printed circuit board (PCB) layout. For example, route
ground shielding between all signals through tracks that are
physically close together. It is strongly recommended to connect
any unused analog input pins to AGND to act as a shield.
MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7]
To configure the ADV7180 analog muxing section, the user
must select the analog input (AIN1 to AIN6 for the 64-lead LQFP
and 48-lead devices or AIN1 to AIN3 for the 40-lead and 32-lead
LFCSP devices) that is to be processed by the ADC. MAN_MUX_
EN must be set to 1 to enable the following muxing blocks:
•
•
•
MUX0[2:0], ADC Mux Configuration, Address 0xC3[2:0]
MUX1[2:0], ADC Mux Configuration, Address 0xC3[6:4]
MUX2[2:0], ADC Mux Configuration, Address 0xC4[2:0]
The three mux sections are controlled by the signal buses MUX0/
MUX1/MUX2[2:0]. Table 15 explains the control words used.
The input signal that contains the timing information (HS and VS)
must be processed by MUX0. For example, in a Y/C input
configuration, MUX0 should be connected to the Y channel
and MUX1 to the C channel. When one or more muxes are not
used to process video, such as the CVBS input, the idle mux and
associated channel clamps and buffers should be powered down
(see the description of Register 0x3A in Table 107).
Table 15. Manual Mux Settings for the ADC (MAN_MUX_EN Must be Set to 1)
MUX0[2:0]
000
001
010
011
100
101
110
111
ADC Connected To
LQFP-64 or
LFCSP-40 or
LQFP-48
LFCSP-32
No connect
No connect
AIN1
AIN1
AIN2
No connect
AIN3
No connect
AIN4
AIN2
AIN5
AIN3
AIN6
No connect
No connect
No connect
MUX1[2:0]
000
001
010
011
100
101
110
111
ADC Connected To
LQFP-64 or
LFCSP-40 or
LQFP-48
LFCSP-32
No connect
No connect
No connect
No connect
No connect
No connect
AIN3
No connect
AIN4
AIN2
AIN5
AIN3
AIN6
No connect
No connect
No connect
Note the following:
•
•
•
CVBS can only be processed by MUX0.
Y/C can only be processed by MUX0 and MUX1.
YPrPb can only be processed by MUX0, MUX1, and MUX2.
Rev. J | Page 21 of 114
MUX2[2:0]
000
001
010
011
100
101
110
111
ADC Connected To
LQFP-64 or
LFCSP-40 or
LQFP-48
LFCSP-32
No connect
No connect
No connect
No connect
AIN2
No connect
No connect
No connect
No connect
No connect
AIN5
AIN3
AIN6
No connect
No connect
No connect
ADV7180
Data Sheet
ANTIALIASING FILTERS
AA_FILT_EN, Address 0xF3[1]
The ADV7180 has optional on-chip antialiasing (AA) filters on
each of the three channels that are multiplexed to the ADC (see
Figure 17). The filters are designed for standard definition video
up to 10 MHz bandwidth. Figure 18 and Figure 19 show the
filter magnitude and phase characteristics.
When AA_FILT_EN[1] is 0, AA Filter 2 is bypassed.
The antialiasing filters are enabled by default and the selection
of INSEL[3:0] determines which filters are powered up at any
given time. For example, if CVBS mode is selected, the filter
circuits for the remaining input channels are powered down to
conserve power. However, the antialiasing filters can be disabled
or bypassed using the AA_FILT_MAN_OVR control.
When AA_FILT_EN[2] is 1, AA Filter 3 is enabled.
40B
1ONLY
MAGNITUDE (dB)
–8
AA
FILTER 2
SHA
–12
–16
–20
–24
–28
A/D
–32
AA
FILTER 3
AVAILABLE IN 64-LEAD AND 48-LEAD PACKAGES.
–36
1k
05700-013
AIN61
–4
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 18. Antialiasing Filter Magnitude Response
0
Figure 17. Antialias Filter Configuration
–10
AA_FILT_MAN_OVR, Antialiasing Filter Override,
Address 0xF3[3]
–20
This feature allows the user to override the antialiasing filters
on/off settings, which are automatically selected by INSEL[3:0].
–50
82B
–30
AA_FILT_EN, Antialiasing Filter Enable, Address 0xF3[2:0]
83B
These bits allow the user to enable or disable the antialiasing
filters on each of the three input channels multiplexed to the
ADC. When disabled, the analog signal bypasses the AA filter
and is routed directly to the ADC.
PHASE (Degrees)
–40
AA_FILT_EN, Address 0xF3[0]
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
1k
84B
When AA_FILT_EN[0] is 0, AA Filter 1 is bypassed.
05700-014
AIN51
0
05700-012
AIN41
When AA_FILT_EN[2] is 0, AA Filter 3 is bypassed.
AA
FILTER 1
MUX BLOCK
AIN3
AA_FILT_EN, Address 0xF3[2]
85B
10-BIT, 86MHz
ADC
AIN1
AIN2
When AA_FILT_EN[1] is 1, AA Filter 2 is enabled.
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Antialiasing Filter Phase Response
When AA_FILT_EN[0] is 1, AA Filter 1 is enabled.
Rev. J | Page 22 of 114
100M
Data Sheet
ADV7180
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVING MODES
Power-Down
PDBP, Address 0x0F[2]
The digital supply of the ADV7180 can be shut down by using
the PWRDWN pin or via I2C1 (see the PWRDWN, Address
0x0F[5] section). PDBP controls whether the I2C control or the
pin has the higher priority. The default is to give the pin
(PWRDWN) priority2. This allows the user to have the
ADV7180 powered down by default at power-up without the
need for an I2C write.
When PDBP is 0 (default), the digital supply power is controlled
by the PWRDWN pin2 (the PWRDWN bit, Address 0x0F[5], is
disregarded).
When PDBP is 1, the PWRDWN bit has priority (the pin is
disregarded).
When PDBP is set to 1, setting the PWRDWN bit switches the
ADV7180 to a chip-wide power-down mode. The power-down
stops the clock from entering the digital section of the chip,
thereby freezing its operation. No I2C bits are lost during powerdown. The PWRDWN bit also affects the analog blocks and
switches them into low current modes. The I2C interface is
unaffected and remains operational in power-down mode.
The ADV7180 leaves the power-down state if the PWRDWN bit is
set to 0 (via I2C) or if the ADV7180 is reset using the RESET pin.
PDBP must be set to 1 for the PWRDWN bit to power down
the ADV7180.
When PWRDWN is 0 (default), the chip is operational. When
PWRDWN is 1, the ADV7180 is in a chip-wide power-down
mode.
RESET CONTROL
Reset, Chip Reset, Address 0x0F[7]
Setting this bit, which is equivalent to controlling the RESET pin
on the ADV7180, issues a full chip reset. All I2C registers are reset
to their default/power-up values. Note that some register bits do
not have a reset value specified. They keep their last written value.
Those bits are marked as having a reset value of x in the register
tables (see Table 107 and Table 108). After the reset sequence,
the part immediately starts to acquire the incoming video signal.
For 32-lead, I2C is the only power-down option.
2
For 64-lead, 48-lead, and 40-lead only.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I2C writes are
performed.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented (see
the MPU Port Description section).
When the reset bit is 0 (default), operation is normal.
When the reset bit is 1, the reset sequence starts.
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03[6]
This bit allows the user to three-state the output drivers of the
ADV7180.
PWRDWN, Address 0x0F[5]
1
After setting the reset bit (or initiating a reset via the RESET pin),
the part returns to the default for its primary mode of operation.
All I2C bits are loaded with their default values, making this bit
self-clearing.
Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the 48-lead,
40-lead, and 32-lead devices), HS, VS, FIELD (VS/FIELD pin for
the 48-lead, 40-lead, and 32-lead LFCSP), and SFL pins are
three-stated.
The timing pins (HS, VS, FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, see
the Three-State LLC Driver and the Timing Signals Output
Enable sections.
Individual drive strength controls are provided via the
DR_STR_x bits.
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are three-stated.
Three-State LLC Driver
TRI_LLC, Address 0x1D[7]
This bit allows the output drivers for the LLC pin of the
ADV7180 to be three-stated. For more information on threestate control, refer to the Three-State Output Drivers and the
Timing Signals Output Enable sections.
Individual drive strength controls are provided via the
DR_STR_x bits.
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are three-stated.
Rev. J | Page 23 of 114
ADV7180
Data Sheet
Timing Signals Output Enable
TIM_OE, Address 0x04[3]
Table 17. DR_STR_C Function
89B
DR_STR_C[1:0]
00
01 (default)
10
11
137B
The TIM_OE bit is regarded as an addition to the TOD bit. Setting
it high forces the output drivers for HS, VS, and FIELD into the
active state (that is, driving state) even if the TOD bit is set. If
TIM_OE is set to low, the HS, VS, and FIELD pins are threestated depending on the TOD bit. This functionality is beneficial if
the decoder is only used as a timing generator. This may be the
case if only the timing signals are extracted from an incoming
signal or if the part is in free-run mode, where a separate chip
can output a company logo, for example.
1
Description
Low drive strength (1×)1
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
Not recommended for the optimal performance of the ADV7180.
Drive Strength Selection (Sync)
DR_STR_S[1:0], Address 0xF4[1:0]
92B
140B
For more information on three-state control, see the Three-State
Output Drivers section and the Three-State LLC Driver section.
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and FIELD are
driven. For more information, see the Drive Strength Selection
(Data) section.
Individual drive strength controls are provided via the
DR_STR_x bits.
Table 18. DR_STR_S Function
DR_STR_S[1:0]
00
01 (default)
10
11
When TIM_OE is 0 (default), HS, VS, and FIELD are threestated according to the TOD bit.
When TIM_OE is 1, HS, VS, and FIELD are forced active all
the time.
1
Drive Strength Selection (Data)
DR_STR[1:0], Address 0xF4[5:4]
Description
Low drive strength (1×)1
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
Not recommended for the optimal performance of the ADV7180.
90B
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN, Address 0x04[1]
93B
138B
For EMC and crosstalk reasons, it may be desirable to strengthen or
weaken the drive strength of the output drivers. The DR_STR[1:0]
bits affect the P[15:0] for the 64-lead device or P[7:0] for the
48-lead, 40-lead, and 32-lead devices output drivers.
14B
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as genlock) from the ADV7180 core
to an encoder in a decoder/encoder back-to-back arrangement.
Note that DR_STR[1:0] also affects the drive strength of the
INTRQ interrupt pin on all ADV7180 models.
When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.
For more information on three-state control, see the Drive
Strength Selection (Clock) and the Drive Strength Selection
(Sync) sections.
When EN_SFL_PIN is 1, the subcarrier frequency lock
information is presented on the SFL pin.
Polarity LLC Pin
PCLK, Address 0x37[0]
94B
Table 16. DR_STR Function
DR_STR[1:0]
00
01 (default)
10
11
1
142B
Description
Low drive strength (1×)1
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
The polarity of the clock that leaves the ADV7180 via the LLC
pin can be inverted using the PCLK bit.
Changing the polarity of the LLC clock output may be necessary to
meet the setup-and-hold time expectations of follow-on chips.
When PCLK is 0, the LLC output polarity is inverted.
Not recommended for the optimal performance of the ADV7180.
When PCLK is 1 (default), the LLC output polarity is normal
(see the Timing Specifications section).
Drive Strength Selection (Clock)
DR_STR_C[1:0], Address 0xF4[3:2]
91B
139B
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
see the Drive Strength Selection (Sync) and the Drive Strength
Selection (Data) sections.
Rev. J | Page 24 of 114
Data Sheet
ADV7180
GLOBAL STATUS REGISTER
Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV7180. The other three registers
(Address 0x10, Address 0x12, and Address 0x13) contain
status bits from the ADV7180.
Table 21. Status 1 Function
Status 1[7:0]
0
1
Bit Name
IN_LOCK
LOST_LOCK
IDENTIFICATION
2
3
FSC_LOCK
FOLLOW_PW
4
5
6
7
AD_RESULT[0]
AD_RESULT[1]
AD_RESULT[2]
COL_KILL
IDENT[7:0], Address 0x11[7:0]
This is the register identification of the ADV7180 revision.
Table 19 describes the various versions of the ADV7180.
Table 19. IDENT CODE
IDENT[7:0]
0x1B1
0x1C1
0x1E
1
Description
Initial release silicon
Improved ESD and PDC fix
48-lead and 32-lead devices only
Description
In lock (now)
Lost lock (since last read of
this register)
fSC locked (now)
AGC follows peak white
algorithm
Result of autodetection
Result of autodetection
Result of autodetection
Color kill active
STATUS 2
Status 2[7:0], Address 0x12[7:0]
Table 22. Status 2 Function
64-lead and 40-lead models only.
Status 2[7:0]
0
Bit Name
MVCS DET
This read-only register provides information about the internal
status of the ADV7180.
1
MVCS T3
See the CIL[2:0], Count Into Lock, Address 0x51[2:0] section
and the COL[2:0], Count Out of Lock, Address 0x51[5:3]
section for details on timing.
2
MV PS DET
3
MV AGC DET
Depending on the setting of the FSCLE bit, the Status Register 0
and Status Register 1 are based solely on horizontal timing information or on the horizontal timing and lock status of the color
subcarrier. See the FSCLE, fSC Lock Enable, Address 0x51[7]
section.
4
5
6
7
LL NSTD
FSC NSTD
Reserved
Reserved
AUTODETECTION RESULT
STATUS 3
AD_RESULT[2:0], Address 0x10[6:4]
Status 3[7:0], Address 0x13[7:0]
The AD_RESULT[2:0] bits report back on the findings from the
ADV7180 autodetection block. See the General Setup section for
more information on enabling the autodetection block and the
Autodetection of SD Modes section for more information on
how to configure it.
Table 23. Status 3 Function
STATUS 1
Status 1[7:0], Address 0x10[7:0]
Table 20. AD_RESULT Function
AD_RESULT[2:0]
000
001
010
011
100
101
110
111
Description
NTSC M/J
NTSC 4.43
PAL M
PAL 60
PAL B/G/H/I/D
SECAM
PAL Combination N
SECAM 525
Status 3[7:0]
0
Bit Name
INST_HLOCK
1
2
GEMD
SD_OP_50Hz
3
4
Reserved
FREE_RUN_ACT
5
STD FLD LEN
6
Interlaced
7
PAL_SW_LOCK
Rev. J | Page 25 of 114
Description
Detected Macrovision color
striping
Macrovision color striping
protection; conforms to Type 3
if high, Type 2 if low
Detected Macrovision pseudosync pulses
Detected Macrovision AGC
pulses
Line length is nonstandard
fSC frequency is nonstandard
Description
Horizontal lock indicator
(instantaneous)
Gemstar detect
Flags whether 50 Hz or 60 Hz is
present at output
Reserved for future use
ADV7180 outputs a blue
screen (see the DEF_VAL_EN,
Default Value Enable,
Address 0x0C[0] section)
Field length is correct for
currently selected video
standard
Interlaced video detected
(field sequence found)
Reliable sequence of
swinging bursts detected
ADV7180
Data Sheet
VIDEO PROCESSOR
9B
STANDARD DEFINITION PROCESSOR
MACROVISION
DETECTION
DIGITIZED CVBS
DIGITIZED Y (YC)
DIGITIZED CVBS
DIGITIZED C (YC)
VBI DATA
RECOVERY
LUMA
DIGITAL
FINE
CLAMP
CHROMA
DIGITAL
FINE
CLAMP
CHROMA
DEMOD
STANDARD
AUTODETECTION
SLLC
CONTROL
LUMA
FILTER
LUMA
GAIN
CONTROL
LUMA
RESAMPLE
SYNC
EXTRACT
LINE
LENGTH
PREDICTOR
RESAMPLE
CONTROL
CHROMA
FILTER
CHROMA
GAIN
CONTROL
CHROMA
RESAMPLE
LUMA
2D COMB
AV
CODE
INSERTION
CHROMA
2D COMB
VIDEO DATA
OUTPUT
MEASUREMENT
BLOCK (≥ I2C)
VIDEO DATA
PROCESSING
BLOCK
05700-015
fSC
RECOVERY
Figure 20. Block Diagram of the Video Processor
Figure 20 shows a block diagram of the ADV7180 video processor.
The ADV7180 can handle standard definition video in CVBS,
Y/C, and YPrPb formats. It can be divided into a luminance and
chrominance path. If the input video is of a composite type
(CVBS), both processing paths are fed with the CVBS input.
SD LUMA PATH
SD CHROMA PATH
50B
The input signal is processed by the following blocks:


49B
The input signal is processed by the following blocks:






Luma digital fine clamp. This block uses a high precision
algorithm to clamp the video signal.
Luma filter. This block contains a luma decimation filter
(YAA) with a fixed response and some shaping filters
(YSH) that have selectable responses.
Luma gain control. The automatic gain control (AGC) can
operate on a variety of different modes, including gain based
on the depth of the horizontal sync pulse, peak white mode,
and fixed manual gain.
Luma resample. To correct for line length errors as well as
dynamic line length changes, the data is digitally resampled.
Luma 2D comb. The 2D comb filter provides Y/C separation.
AV code insertion. At this point, the decoded luma (Y) signal
is merged with the retrieved chroma values. AV codes can
be inserted (as per ITU-R BT.656).





Rev. J | Page 26 of 114
Chroma digital fine clamp. This block uses a high precision
algorithm to clamp the video signal.
Chroma demodulation. This block employs a color
subcarrier (fSC) recovery unit to regenerate the color
subcarrier for any modulated chroma scheme. The
demodulation block then performs an AM demodulation
for PAL and NTSC, and an FM demodulation for SECAM.
Chroma filter. This block contains a chroma decimation
filter (CAA) with a fixed response and some shaping filters
(CSH) that have selectable responses.
Chroma gain control. AGC can operate on several different
modes, including gain based on the color subcarrier
amplitude, gain based on the depth of the horizontal sync
pulse on the luma channel, or fixed manual gain.
Chroma resample. The chroma data is digitally resampled
to keep it perfectly aligned with the luma data. The
resampling is done to correct for static and dynamic line
length errors of the incoming video signal.
Chroma 2D comb. The 2D, five line, superadaptive comb
filter provides high quality Y/C separation in case the input
signal is CVBS.
AV code insertion. At this point, the demodulated chroma
(Cr and Cb) signal is merged with the retrieved luma values.
AV codes can be inserted (as per ITU-R BT.656).
Data Sheet
ADV7180
SYNC PROCESSING
GENERAL SETUP
The ADV7180 extracts syncs embedded in the analog input
video signal. There is currently no support for external HS/VS
inputs. The sync extraction is optimized to support imperfect
video sources, such as VCRs with head switches. The actual
algorithm used employs a coarse detection based on a threshold
crossing, followed by a more detailed detection using an adaptive
interpolation algorithm. The raw sync information is sent to a
line length measurement and prediction block. The output of
this is then used to drive the digital resampling section to
ensure that the ADV7180 outputs 720 active pixels per line.
Video Standard Selection
The sync processing on the ADV7180 also includes the following
specialized postprocessing blocks that filter and condition the
raw sync information retrieved from the digitized analog video:
•
•
VSYNC processor. This block provides extra filtering of the
detected VSYNCs to improve vertical lock.
HSYNC processor. The HSYNC processor is designed to
filter incoming HSYNCs that have been corrupted by
noise, providing much improved performance for video
signals with a stable time base but poor SNR.
VBI DATA RECOVERY
The ADV7180 can retrieve the following information from the
input video:
•
•
•
•
•
•
•
•
Wide screen signaling (WSS)
Copy generation management system (CGMS)
Closed captioning (CCAP)
Macrovision protection presence
EDTV data
Gemstar-compatible data slicing
Teletext
VITC/VPS
Autodetection of SD Modes
To guide the autodetect system of the ADV7180, individual
enable bits are provided for each of the supported video standards.
Setting the relevant bit to 0 inhibits the standard from being
detected automatically. Instead, the system chooses the closest of
the remaining enabled standards. The results of the autodetection
block can be read back via the status registers (see the Global
Status Register section for more information).
VID_SEL[3:0], Address 0x00[7:4]
Table 24. VID_SEL Function
VID_SEL[3:0]
0000 (default)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
The ADV7180 is also capable of automatically detecting the
incoming video standard with respect to
•
•
•
The VID_SEL[3:0] bits (Address 0x00[7:4]) allow the user to
force the digital core into a specific video standard. Under normal
circumstances, this is not necessary. The VID_SEL[3:0] bits
default to an autodetection mode that supports PAL, NTSC,
SECAM, and variants thereof.
Color subcarrier frequency
Field rate
Line rate
The ADV7180 can configure itself to support PAL B/D/I/G/H,
PAL M, PAL N, PAL Combination N, NTSC M, NTSC J,
SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60.
Description
Autodetect (PAL B/G/H/I/D), NTSC J
(no pedestal), SECAM
Autodetect (PAL B/G/H/I/D), NTSC M
(pedestal), SECAM
Autodetect (PAL N) (pedestal), NTSC J
(no pedestal), SECAM
Autodetect (PAL N) (pedestal), NTSC M
(pedestal), SECAM
NTSC J
NTSC M
PAL 60
NTSC 4.43
PAL B/G/H/I/D
PAL N = PAL B/G/H/I/D (with pedestal)
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N (with pedestal)
SECAM
SECAM (with pedestal)
AD_SEC525_EN, Enable Autodetection of SECAM 525
Line Video, Address 0x07[7]
Setting AD_SEC525_EN to 0 (default) disables the autodetection
of a 525-line system with a SECAM style, FM-modulated color
component.
Setting AD_SEC525_EN to 1 enables the detection of a SECAM
style, FM-modulated color component.
Rev. J | Page 27 of 114
ADV7180
Data Sheet
AD_SECAM_EN, Enable Autodetection of SECAM,
Address 0x07[6]
AD_PAL_EN, Enable Autodetection of PAL B/D/I/G/H,
Address 0x07[0]
Setting AD_SECAM_EN to 0 (default) disables the autodetection
of SECAM.
Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.
Setting AD_SECAM_EN to 1 enables the detection of SECAM.
Setting AD_PAL_EN to 1 enables the detection of standard PAL.
AD_N443_EN, Enable Autodetection of NTSC 4.43,
Address 0x07[5]
SFL_INV, Subcarrier Frequency Lock Inversion
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection of
NTSC style systems with a 4.43 MHz color subcarrier.
This bit controls the behavior of the PAL switch bit in the SFL
(genlock telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems.
First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.
AD_P60_EN, Enable Autodetection of PAL 60,
Address 0x07[4]
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Setting AD_P60_EN to 1 (default) enables the detection of PAL
systems with a 60 Hz field rate.
AD_PALN_EN, Enable Autodetection of PAL N,
Address 0x07[3]
Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.
Setting AD_PALN_EN to 1 enables the detection of the PAL N
standard.
AD_PALM_EN, Enable Autodetection of PAL M,
Address 0x07[2]
Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(genlock telegram) bit directly, whereas the newer ones invert
the bit prior to using it. The reason for this is that the inversion
compensated for the one line delay of an SFL (genlock telegram)
transmission.
As a result, for the ADV717x and ADV73xx encoders, the PAL
switch bit in the SFL (genlock telegram) must be 0 for NTSC to
work. For the ADV7194 video encoder, the PAL switch bit in the
SFL must be 1 to work in NTSC. If the state of the PAL switch bit
is wrong, a 180° phase shift occurs.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
SFL_INV, Subcarrier Frequency Lock Inversion,
Address 0x41[6]
Setting AD_PALM_EN to 1 enables the detection of PAL M.
Setting SFL_INV to 0 (default) makes the part SFL compatible
with the ADV717x and ADV73xx video encoders.
AD_NTSC_EN, Enable Autodetection of NTSC,
Address 0x07[1]
Setting SFL_INV to 1 makes the part SFL compatible with the
ADV7194 video encoder.
Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.
Lock Related Controls
Lock information is presented to the user through Bits[1:0] of
the Status 1 register (see the Status 1[7:0], Address 0x10[7:0]
section). Figure 21 outlines the signal flow and the controls
available to influence the way the lock status information is
generated.
Setting AD_NTSC_EN to 1 enables the detection of standard
NTSC.
SELECT THE RAW LOCK SIGNAL
SRLS
1
0
0
1
fSC LOCK
COUNTER INTO LOCK
COUNTER OUT OF LOCK
STATUS 1[0]
MEMORY
STATUS 1[1]
05700-016
TIME_WIN
FREE_RUN
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TAKE fSC LOCK INTO ACCOUNT
FSCLE
Figure 21. Lock Related Signal Path
Rev. J | Page 28 of 114
Data Sheet
ADV7180
SRLS, Select Raw Lock Signal, Address 0x51[6]
COL[2:0], Count Out of Lock, Address 0x51[5:3]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
See Figure 21.
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into the unlocked state and reports this via Status 1[1:0]. It counts
the value in lines of video.
•
•
The TIME_WIN signal is based on a line-to-line evaluation
of the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.
The FREE_RUN signal evaluates the properties of the
incoming video over several fields, taking vertical
synchronization information into account.
Setting SRLS to 0 (default) selects the FREE_RUN signal.
Setting SRLS to 1 selects the TIME_WIN signal.
FSCLE, fSC Lock Enable, Address 0x51[7]
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in the
Status 1 register. This bit must be set to 0 when operating the
ADV7180 in YPrPb component mode to generate a reliable
HLOCK status bit.
When FSCLE is set to 0 (default), only the overall lock status is
dependent on horizontal sync lock.
When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and fSC lock.
CIL[2:0], Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which
the lock condition must be true before the system switches into
the locked state and reports this via Status 1[1:0]. The bit counts
the value in lines of video.
Table 25. CIL Function
CIL[2:0]
000
001
010
011
100 (default)
101
110
111
Number of Video Lines
1
2
5
10
100
500
1000
100,000
Table 26. COL Function
COL[2:0]
000
001
010
011
100 (default)
101
110
111
Number of Video Lines
1
2
5
10
100
500
1000
100,000
COLOR CONTROLS
These registers allow the user to control picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent of picture clamping,
although both controls affect the dc level of the signal.
CON[7:0], Contrast Adjust, Address 0x08[7:0]
This register allows the user to control contrast adjustment of
the picture.
Table 27. CON Function
CON[7:0]
0x80 (default)
0x00
0xFF
Description
Gain on luma channel = 1
Gain on luma channel = 0
Gain on luma channel = 2
SD_SAT_Cb[7:0], SD Saturation Cb Channel,
Address 0xE3[7:0]
This register allows the user to control the gain of the Cb channel
only, which in turn adjusts the saturation of the picture.
Table 28. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
0x80 (default)
0x00
0xFF
Description
Gain on Cb channel = 0 dB
Gain on Cb channel = −42 dB
Gain on Cb channel = +6 dB
SD_SAT_Cr[7:0], SD Saturation Cr Channel,
Address 0xE4[7:0]
This register allows the user to control the gain of the Cr channel
only, which in turn adjusts the saturation of the picture.
Table 29. SD_SAT_Cr Function
SD_SAT_Cr[7:0]
0x80 (default)
0x00
0xFF
Rev. J | Page 29 of 114
Description
Gain on Cr channel = 0 dB
Gain on Cr channel = −42 dB
Gain on Cr channel = +6 dB
ADV7180
Data Sheet
SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1[7:0]
DEF_Y[5:0], Default Value Y, Address 0x0C[7:2]
This register allows the user to select an offset for the Cb channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.
When the ADV7180 loses lock on the incoming video signal or
when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:
Table 30. SD_OFF_Cb Function
•
SD_OFF_Cr[7:0], SD Offset Cr Channel, Address 0xE2[7:0]
If the DEF_VAL_AUTO_EN bit is set to high and the
ADV7180 has lost lock to the input video signal. This is
the intended mode of operation (automatic mode).
The DEF_VAL_EN bit is set, regardless of the lock status of
the video decoder. This is a forced mode that may be useful
during configuration.
This register allows the user to select an offset for the Cr channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.
The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.
Table 31. SD_OFF_Cr Function
For DEF_Y[5:0], 0x0D (blue) is the default value for Y.
SD_OFF_Cr[7:0]
0x80 (default)
0x00
0xFF
Register 0x0C has a default value of 0x36.
SD_OFF_Cb[7:0]
0x80 (default)
0x00
0xFF
Description
0 mV offset applied to the Cb channel
−312 mV offset applied to the Cb channel
+312 mV offset applied to the Cb channel
Description
0 mV offset applied to the Cr channel
−312 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
BRI[7:0], Brightness Adjust, Address 0x0A[7:0]
This register controls the brightness of the video signal. It allows
the user to adjust the brightness of the picture.
Table 32. BRI Function
BRI[7:0]
0x00 (default)
0x7F
0x80
•
•
The DEF_VAL_AUTO_EN bit is set to high and the
ADV7180 cannot lock to the input video (automatic mode).
DEF_VAL_EN bit is set to high (forced output).
DEF_VAL_EN, Default Value Enable, Address 0x0C[0]
HUE[7:0] has a range of ±90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
The hue adjustment value is fed into the AM color demodulation
block. Therefore, it applies only to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM
and does not work on component video inputs (YPrPb).
Description (Adjust Hue of the Picture)
Phase of the chroma signal = 0°
Phase of the chroma signal = −90°
Phase of the chroma signal = +90°
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the four MSBs of Cr and Cb values to be output if
For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
Table 33. HUE Function
DEF_C[7:0], Default Value C, Address 0x0D[7:0]
The data that is finally output from the ADV7180 for the
chroma side is Cr[3:0] = {DEF_C[7:4], 0, 0, 0, 0}, and
Cb[3:0] = {DEF_C[3:0], 0, 0, 0, 0}.
Description
Offset of the luma channel = 0 IRE
Offset of the luma channel = +30 IRE
Offset of the luma channel = −30 IRE
HUE[7:0], Hue Adjust, Address 0x0B[7:0]
HUE[7:0]
0x00 (default)
0x7F
0x80
•
This bit forces the use of the default values for Y, Cr, and Cb. See
the descriptions in the DEF_Y[5:0], Default Value Y, Address
0x0C[7:2] and DEF_C[7:0], Default Value C, Address 0x0D[7:0]
sections for additional information. In this mode, the decoder
also outputs a stable 27 MHz clock, HS, and VS.
Setting DEF_VAL_EN to 0 (default) outputs a colored screen
determined by user-programmable Y, Cr, and Cb values when
the decoder free-runs. Free-run mode is turned on and off by
the DEF_VAL_AUTO_EN bit.
Setting DEF_VAL_EN to 1 forces a colored screen output
determined by user-programmable Y, Cr, and Cb values.
This overrides picture data even if the decoder is locked.
Rev. J | Page 30 of 114
Data Sheet
ADV7180
Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If
the decoder is unlocked, it outputs noise.
After digitization, the digital fine clamp block corrects for any
remaining variations in dc level. Because the dc level of an input
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations may occur. Furthermore, dynamic changes in the dc level almost certainly lead to
visually objectionable artifacts and must, therefore, be prohibited.
Setting DEF_VAL_EN to 1 (default) enables free-run mode, and
a colored screen set by user-programmable Y, Cr, and Cb values
is displayed when the decoder loses lock.
The clamping scheme has to complete two tasks. It must acquire
a newly connected video signal with a completely unknown dc
level, and it must maintain the dc level during normal operation.
CLAMP OPERATION
To acquire an unknown video signal quickly, the large current
clamps must be activated. It is assumed that the amplitude of
the video signal at this point is of a nominal value. Control of
the coarse and fine current clamp parameters is performed
automatically by the decoder.
DEF_VAL_AUTO_EN, Default Value Automatic Enable,
Address 0x0C[1]
167B
This bit enables the automatic use of the default values for Y, Cr,
and Cb when the ADV7180 cannot lock to the video signal.
5B
The input video is ac-coupled into the ADV7180. Therefore, its dc
value needs to be restored. This process is referred to as clamping
the video. This section explains the general process of clamping
on the ADV7180 and shows the different ways in which a user
can configure its behavior.
Standard definition video signals may have excessive noise on
them. In particular, CVBS signals transmitted by terrestrial
broadcast and demodulated using a tuner usually show very
large levels of noise (>100 mV). A voltage clamp is unsuitable
for this type of video signal. Instead, the ADV7180 employs a
set of four current sources that can cause coarse (>0.5 mA) and
fine (<0.1 mA) currents to flow into and away from the high
impedance node that carries the video signal (see Figure 22).
The ADV7180 uses a combination of current sources and a
digital processing block for clamping, as shown in Figure 22.
The analog processing channel shown is replicated three times
inside the IC. While only one single channel is needed for a
CVBS signal, two independent channels are needed for Y/C
(SVHS) type signals, and three independent channels are
needed to allow component signals (YPrPb) to be processed.
The following sections describe the I2C signals that can be used
to influence the behavior of the clamping block.
The clamping can be divided into two sections:


Clamping before the ADC (analog domain): current
sources.
Clamping after the ADC (digital domain): digital
processing block.
CCLEN, Current Clamp Enable, Address 0x14[4]
168B
The ADC can digitize an input signal only if it resides within
the ADC 1.0 V input voltage range. An input signal with a dc
level that is too large or too small is clipped at the top or bottom
of the ADC range.
The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This may be
useful if the incoming analog video signal is clamped externally.
When CCLEN is 0, the current sources are switched off.
When CCLEN is 1 (default), the current sources are enabled.
The primary task of the analog clamping circuits is to ensure that
the video signal stays within the valid ADC input window so that
the analog-to-digital conversion can take place. It is not necessary
to clamp the input signal with a very high accuracy in the analog
domain as long as the video signal fits within the ADC range.
ANALOG
VIDEO
INPUT
COARSE CURRENT SOURCES
ADC
DATA
PREPROCESSOR
(DPP)
CLAMP CONTROL
Figure 22. Clamping Overview
Rev. J | Page 31 of 114
VIDEO PROCESSOR
WITH DIGITAL
FINE CLAMP
05700-017
FINE CURRENT SOURCES
ADV7180
Data Sheet
DCT[1:0], Digital Clamp Timing, Address 0x15[6:5]
•
The clamp timing register determines the time constant of the
digital fine clamp circuitry. It is important to note that the digital
fine clamp reacts quickly because it immediately corrects any
residual dc level error for the active line. The time constant from
the digital fine clamp must be much quicker than the one from
the analog blocks.
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
Table 34. DCT Function
DCT[1:0]
00 (default)
01
10
11
Description
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
Determined by ADV7180, depending on the
input video parameters
•
DCFE, Digital Clamp Freeze Enable, Address 0x15[4]
This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who want to do their own
clamping. To do this, disable the current sources for analog
clamping via the appropriate register bits, wait until the digital
clamp loop settles, and then freeze it via the DCFE bit.
When DCFE is 0 (default), the digital clamp is operational.
When DCFE is 1, the digital clamp loop is frozen.
LUMA FILTER
Data from the digital fine clamp block is processed by the three
sets of filters that follow. Note that the data format at this point
is CVBS for CVBS input or luma only for Y/C and YPrPb input
formats.
•
Luma antialias filter (YAA). The ADV7180 receives video
at a rate of 28.6363 MHz. (In the case of 4× oversampled
video, the ADC samples at 57.27 MHz, and the first decimation is performed inside the DPP filters. Therefore, the
data rate into the ADV7180 is always 28.6363 MHz.) The
ITU-R BT.601 recommends a sampling frequency of
13.5 MHz. The luma antialias filter decimates the oversampled
video using a high quality linear phase, low-pass filter that
preserves the luma signal while at the same time attenuating
out-of-band components. The luma antialias filter (YAA)
has a fixed response.
Luma shaping filters (YSH). The shaping filter block is a
programmable low-pass filter with a wide variety of responses.
It can be used to selectively reduce the luma video signal
bandwidth (needed prior to scaling, for example). For
some video sources that contain high frequency noise,
reducing the bandwidth of the luma signal improves visual
picture quality. A follow-on video compression stage may
work more efficiently if the video is low-pass filtered.
The ADV7180 has two responses for the shaping filter: one
that is used for good quality composite, component, and
SVHS type sources, and a second for nonstandard CVBS
signals.
The YSH filter responses also include a set of notches for
PAL and NTSC. However, using the comb filters for Y/C
separation is recommended.
Digital resampling filter. This block allows dynamic
resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resampler
is a set of low-pass filters. The actual response is chosen by
the system with no requirement for user intervention.
Figure 24 through Figure 27 show the overall response of all filters
together. Unless otherwise noted, the filters are set into a typical
wideband mode.
Y Shaping Filter
For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. Y/C separation must aim for best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
Y/C separation can be achieved by using the internal comb
filters of the ADV7180. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of the
video line rate) and the color subcarrier (fSC). For good quality
CVBS signals, this relationship is known; the comb filter algorithms
can be used to separate luma and chroma with high accuracy.
In the case of nonstandard video signals, the frequency relationship
may be disturbed, and the comb filters may not be able to remove
all crosstalk artifacts in the best fashion without the assistance
of the shaping filter block.
Rev. J | Page 32 of 114
Data Sheet
ADV7180
YSFM[4:0], Y Shaping Filter Mode, Address 0x17[4:0]
An automatic mode is provided that allows the ADV7180 to
evaluate the quality of the incoming video signal and select the
filter responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.
The Y shaping filter mode bits allow the user to select from a
wide range of low-pass and notch filters. When switched in
automatic mode, the filter selection is based on other register
selections, such as detected video standard, as well as properties
extracted from the incoming video itself, such as quality and
time base stability. The automatic selection always selects the
widest possible bandwidth for the video input encountered.
The luma shaping filter has three control registers.
•
•
•
YSFM[4:0] allows the user to manually select a shaping
filter mode (applied to all video signals) or to enable an
automatic selection (depending on video quality and video
standard).
WYSFMOVR allows the user to manually override the
WYSFM decision.
WYSFM[4:0] allows the user to select a different shaping
filter mode for good quality composite (CVBS), component
(YPrPb), and SVHS (Y/C) input signals.
The Y-shaping filter mode operates as follows:
•
•
If the YSFM settings specify a filter (that is, YSFM is set to
values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.
In automatic selection mode, the notch filters are only used
for bad quality video signals. For all other video signals,
wideband filters are used.
In automatic mode, the system preserves the maximum possible
bandwidth for good CVBS sources (because they can be successfully combed) as well as for luma components of YPrPb and
Y/C sources (because they need not be combed). For poor quality
signals, the system selects from a set of proprietary shaping filter
responses that complements comb filter operation to reduce
visual artifacts.
WYSFMOVR, Wideband Y Shaping Filter Override,
Address 0x18[7]
The decisions of the control logic are shown in Figure 23.
When WYSFMOVR is 0, the shaping filter for good quality
video signals is selected automatically.
Setting the WYSFMOVR bit enables the use of the WYSFM[4:0]
settings for good quality video signals. For more information on
luma shaping filters, see the Y Shaping Filter section and the
flowchart shown in Figure 23.
Setting WYSFMOVR to 1 (default) enables manual override via
WYSFM[4:0].
SET YSFM
YES
YSFM IN AUTO MODE?
00000 OR 00001
NO
VIDEO
QUALITY
BAD
GOOD
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB
USE YSFM SELECTED
FILTER REGARDLESS OF
VIDEO QUALITY
0
SELECT WIDEBAND
FILTER AS PER
WYSFM[4:0]
SELECT AUTOMATIC
WIDEBAND FILTER
Figure 23. YSFM and WYSFM Control Flowchart
Rev. J | Page 33 of 114
05700-018
WYSFMOVR
1
ADV7180
Data Sheet
Table 35. YSFM Function
Table 36. WYSFM Function
YSFM[4:0]
00000
WYSFM[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011 (default)
10100 to 11111
Description
Do not use
Do not use
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Do not use
The filter plots in Figure 24 show the SVHS 1 (narrowest) to
SVHS 18 (widest) shaping filter settings. Figure 26 shows the
PAL notch filter responses. The NTSC-compatible notches are
shown in Figure 27.
WYSFM[4:0], Wideband Y Shaping Filter Mode,
Address 0x18[4:0]
COMBINED Y ANTIALIAS, SVHS LOW-PASS FILTERS,
Y RESAMPLE
0
–10
–20
–30
–40
–50
The WYSFM[4:0] bits allow the user to manually select a shaping
filter for good quality video signals, for example, CVBS with
stable time base, luma component of YPrPb, and luma component
of Y/C. The WYSFM bits are active only if the WYSFMOVR bit
is set to 1. See the general discussion of the shaping filter settings in
the Y Shaping Filter section.
Rev. J | Page 34 of 114
–60
05700-019
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
AMPLITUDE (dB)
00001 (default)
Description
Automatic selection including a wide notch
response (PAL/NTSC/SECAM)
Automatic selection including a narrow notch
response (PAL/NTSC/SECAM)
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
–70
0
2
4
6
8
10
FREQUENCY (MHz)
Figure 24. Y SVHS Combined Responses
12
Data Sheet
ADV7180
CHROMA FILTER

Data from the digital fine clamp block is processed by the three
sets of filters that follow. Note that the data format at this point is
CVBS for CVBS inputs, chroma only for Y/C, or U/V interleaved
for YPrPb input formats.

Chroma antialias filter (CAA). The ADV7180 oversamples
the CVBS by a factor of 4 and the chroma/YPrPb by a factor
of 2. A decimating filter (CAA) is used to preserve the active
video band and to remove any out-of-band components.
The CAA filter has a fixed response.
Figure 28 shows the overall response of all filters together.
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
Y RESAMPLE
0
0
–10
AMPLITUDE (dB)
AMPLITUDE (dB)
–20
–40
–60
–80
–20
–30
–40
–50
–100
0
2
4
6
8
10
05700-022
–60
05700-020
–120
–70
0
12
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27. Combined Y Antialias Filter, NTSC Notch Filters
Figure 25. Combined Y Antialias, CCIR Mode Shaping Filter
COMBINED C ANTIALIAS, C SHAPING FILTER,
C RESAMPLER
COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,
Y RESAMPLE
0
0
–10
ATTENUATION (dB)
–10
–20
–30
–40
–20
–30
–40
–50
–70
0
2
4
6
8
10
05700-023
–50
–60
05700-021
AMPLITUDE (dB)

Chroma shaping filters (CSH). The shaping filter block
(CSH) can be programmed to perform a variety of low-pass
responses. It can be used to selectively reduce the bandwidth
of the chroma signal for scaling or compression.
Digital resampling filter. This block allows dynamic
resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resampler
is a set of low-pass filters. The actual response is chosen by
the system without user intervention.
–60
0
12
1
2
3
4
5
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 28. Chroma Shaping Filter Responses
Figure 26. Combined Y Antialias, PAL Notch Filters
Rev. J | Page 35 of 114
6
ADV7180
Data Sheet
ADC, 0 V to 1 V. Place this circuit before all analog inputs to
the ADV7180.
CSFM[2:0], C Shaping Filter Mode, Address 0x17[7:5]
174B
The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see Setting 000
and Setting 001 in Table 37).
ANALOG VIDEO
INPUT
100nF
05700-024
AIN_OF_ADV7180
36Ω
39Ω
Figure 29. Input Voltage Divider Network
Table 37. CSFM Function
The minimum supported amplitude of the input video is
determined by the ability of the ADV7180 to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
Description
Autoselection 1.5 MHz bandwidth
Autoselection 2.17 MHz bandwidth
SH1
SH2
SH3
SH4
SH5
Wideband mode
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
The possible AGC modes are shown in Table 38.
Table 38. AGC Modes
Input
Video Type
Any
CVBS
Figure 28 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (shown in red).
GAIN OPERATION
58B
The gain control within the ADV7180 is done on a purely
digital basis. The input ADC supports a 10-bit range mapped
into a 1.0 V analog voltage range. Gain correction takes place
after the digitization in the form of a digital multiplier.
Luma Gain
Manual gain luma
Dependent on
horizontal sync depth
Peak white
Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADC include
the fact that the gain is now completely independent of supply,
temperature, and process variations.
Y/C
As shown in Figure 30, the ADV7180 can decode a video signal
as long as it fits into the ADC window. The components for this
are the amplitude of the input signal and the dc level it resides on.
The dc level is set by the clamping circuitry (see the Clamp
Operation section).
YPrPb
Dependent on
horizontal sync depth
Peak white
Dependent on
horizontal sync depth
If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the
Luma Gain and Chroma Gain sections.
Figure 29 shows a typical voltage divider network that is required
to keep the input video signal within the allowed range of the
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1V RANGE FOR ADV7180)
MAXIMUM
VOLTAGE
VIDEO PROCESSOR
(GAIN SELECTION ONLY)
ADC
DATA PREPROCESSOR
(DPP)
GAIN
CONTROL
MINIMUM
VOLTAGE
Chroma Gain
Manual gain chroma
Dependent on color-burst
amplitude taken from
luma path
Dependent on color-burst
amplitude taken from
luma path
Dependent on color-burst
amplitude taken from
luma path
Dependent on color-burst
amplitude
Taken from luma path
It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating and the AGC determined gain
at the time of the freeze to stay active until the loop is either
unfrozen or the gain mode of operation is changed.
CLAMP
LEVEL
Figure 30. Gain Control Overview
Rev. J | Page 36 of 114
05700-025
CSFM[2:0]
000 (default)
001
010
011
100
101
110
111
Data Sheet
ADV7180
Luma Gain
LAGC[2:0], Luma Automatic Gain Control,
Address 0x2C[6:4]
LG[11:0], Luma Gain, Address 0x2F[3:0],
Address 0x30[7:0]
The luma automatic gain control mode bits select the operating
mode for the gain control in the luma path.
Table 39. LAGC Function
LAGC[2:0]
000
001
010 (default)
011
100
101
110
111
Description
Manual fixed gain (use LMG[11:0])
AGC (blank level to sync tip), peak white algorithm off
AGC (blank level to sync tip), peak white algorithm on
Reserved
Reserved
Reserved
Reserved
Freeze gain
LAGT[1:0], Luma Automatic Gain Timing,
Address 0x2F[7:6]
The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. This register only has an effect if the LAGC[2:0] register is
set to 001 or 010 (automatic gain control modes).
If peak white AGC is enabled and active (see the Status 1[7:0],
Address 0x10[7:0] section), the actual gain update speed is
dictated by the peak white AGC loop and, as a result, the LAGT
settings have no effect. As soon as the part leaves peak white
AGC, LAGT becomes relevant again.
Table 40. LAGT Function
LAGT[1:0]
00
01
10
11 (default)
Description
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
LMG[11:0], Luma Manual Gain, Address 0x2F[3:0],
Address 0x30[7:0]
Luma gain[11:0] is a dual-function register. If all of these registers
are written to, a desired manual luma gain can be programmed.
This gain becomes active if the LAGC[2:0] mode is switched to
manual fixed gain. Equation 1 shows how to calculate a desired
gain.
If read back, this register returns the current gain value.
Depending on the setting in the LAGC[2:0] bits, the value is
one of the following:
•
•
Luma manual gain value (LAGC[2:0] set to luma manual
gain mode)
Luma automatic gain value (LAGC[2:0] set to any of the
automatic modes)
Table 41. LG/LMG Function
LG[11:0]/LMG[11:0]
LMG[11:0] = x
LG[11:0] = x
Luma Gain =
Read/Write
Write
Read
Description
Manual gain for luma path
Actual used gain
LMG [11 : 0]
LumaCalibrationFactor
(1)
where LMG[11:0] is a decimal value between 1024 and 4095.
Calculation of the Luma Calibration Factor
1.
2.
3.
4.
Using a video source, set content to a grey field and apply
as a standard CVBS signal to the CVBS input of the board.
Using an oscilloscope, measure the signal at CVBS input to
ensure that its sync depth, color burst, and luma are at the
standard levels.
Connect the output parallel pixel bus of the ADV7180 to a
backend system that has unity gain and monitor output
voltage.
Measure the luma level correctly from the black level. Turn
off the Luma AGC and manually change the value of the
luma gain control register, LMG[11:0], until the output
luma level matches the input measured in Step 2.
This value, in decimal, is the luma calibration factor.
Rev. J | Page 37 of 114
ADV7180
Data Sheet
BETACAM, Enable Betacam Levels, Address 0x01[5]
PW_UPD, Peak White Update, Address 0x2B[0]
If YPrPb data is routed through the ADV7180, the automatic
gain control modes can target different video input levels, as
outlined in Table 44. The BETACAM bit is valid only if the
input mode is YPrPb (component). The BETACAM bit sets the
target value for AGC operation.
The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0]
must be set to the appropriate mode to enable the peak white or
average video mode in the first place. For more information, see the
LAGC[2:0], Luma Automatic Gain Control, Address 0x2C[6:4]
section.
A review of the following sections is useful:
•
•
The MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7] section for how component video
(YPrPb) can be routed through the ADV7180.
The Video Standard Selection section to select the various
standards, for example, with and without pedestal.
The AGC algorithms adjust the levels based on the setting of
the BETACAM bit (see Table 42).
Setting PW_UPD to 0 updates the gain once per video line.
Setting PW_UPD to 1 (default) updates the gain once per field.
Chroma Gain
CAGC[1:0], Chroma Automatic Gain Control,
Address 0x2C[1:0]
The two bits of color automatic gain control mode select the
basic mode of operation for automatic gain control in the
chroma path.
Table 42. BETACAM Function
BETACAM
0 (default)
1
Description
Assuming YPrPb is selected as input format:
Selecting PAL with pedestal selects MII.
Selecting PAL without pedestal selects SMPTE.
Selecting NTSC with pedestal selects MII.
Selecting NTSC without pedestal selects SMPTE.
Assuming YPrPb is selected as input format:
Selecting PAL with pedestal selects BETACAM.
Selecting PAL without pedestal selects BETACAM variant.
Selecting NTSC with pedestal selects BETACAM.
Selecting NTSC without pedestal selects BETACAM variant.
Table 43. CAGC Function
CAGC[1:0]
00
01
10 (default)
11
Description
Manual fixed gain (use CMG[11:0])
Luma gain used for chroma
Automatic gain (based on color burst)
Freeze chroma gain
Table 44. BETACAM Levels
Name
Y
Pb and Pr
Sync Depth
BETACAM (mV)
0 to +714 (including 7.5% pedestal)
−467 to +467
+286
BETACAM Variant (mV)
0 to +714
−505 to +505
+286
Rev. J | Page 38 of 114
SMPTE (mV)
0 to +700
−350 to +350
+300
MII (mV)
0 to +700 (including 7.5% pedestal)
−324 to +324
+300
Data Sheet
ADV7180
CAGT[1:0], Chroma Automatic Gain Timing,
Address 0x2D[7:6]
4.
The chroma automatic gain timing register allows the user to
influence the tracking speed of the chroma automatic gain
control. This register has an effect only if the CAGC[1:0]
register is set to 10 (automatic gain).
This value, in decimal, is the chroma calibration factor.
CKE, Color Kill Enable, Address 0x2B[6]
Table 45. CAGT Function
CAGT[1:0]
00
01
10
11 (default)
The color kill enable bit allows the optional color kill function
to be switched on or off.
Description
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Reserved
Adaptive
For QAM-based video standards (PAL and NTSC) as well as
FM-based systems (SECAM), the threshold for the color kill
decision is selectable via the CKILLTHR[2:0] bits.
CG[11:0], Chroma Gain, Address 0x2D[3:0],
Address 0x2E[7:0]; CMG[11:0], Chroma Manual Gain,
Address 0x2D[3:0], Address 0x2E[7:0]
Chroma gain[11:0] is a dual-function register. If written to, a
desired manual chroma gain can be programmed. This gain
becomes active if the CAGC[1:0] function is switched to manual
fixed gain. See Equation 2 for calculating a desired gain.
If read back, this register returns the current gain value.
Depending on the setting in the CAGC[1:0] bits, this is either:
•
•
The chroma manual gain value (CAGC[1:0] set to chroma
manual gain mode).
The chroma automatic gain value (CAGC[1:0] set to any of
the automatic modes).
Table 46. CG/CMG Function
CG[11:0]/CMG[11:0]
CMG[11:0]
Read/Write
Write
CG[11:0]
Read
Chroma_Gain ≅
Description
Manual gain for chroma
path
Currently active gain
CMG[11 : 0]decimal
ChromaCalibrationFactor
(2)
where ChromaCalibrationFactor is a decimal value between 0
and 4095.
Calculation of the Chroma Calibration Factor
1.
2.
3.
Turn off the Chroma AGC and manually change the
Chroma Gain Control Register CMG[11:0] until the
chroma level matches that measured directly from the
source.
Apply a CVBS signal with the color bars/SMPTE bars test
pattern content directly to the measurement equipment.
Ensure correct termination of 75 Ω on the measurement
equipment. Measure chroma output levels.
Reconnect the source to the CVBS input of the ADV7180
system that has a backend gain of 1. Repeat the
measurement of chroma levels.
If color kill is enabled and the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
lines with a color burst greater than the threshold are required.
The color kill option works only for input signals with a modulated
chroma part. For component input (YPrPb), there is no color kill.
Setting CKE to 0 disables color kill.
Setting CKE to 1 (default) enables color kill.
CKILLTHR[2:0], Color Kill Threshold, Address 0x3D[6:4]
The CKILLTHR[2:0] bits allow the user to select a threshold for
the color kill function. The threshold applies only to QAM-based
(NTSC and PAL) or FM-modulated (SECAM) video standards.
To enable the color kill function, the CKE bit must be set. For
Setting 000, Setting 001, Setting 010, and Setting 011, chroma
demodulation inside the ADV7180 may not work satisfactorily
for poor input video signals.
Table 47. CKILLTHR Function
CKILLTHR[2:0]
000
001
010
011 (default)
100
101
110
111
Rev. J | Page 39 of 114
Description
SECAM
NTSC, PAL
No color kill
Kill at <0.5%
Kill at <5%
Kill at <1.5%
Kill at <7%
Kill at <2.5%
Kill at <8%
Kill at <4%
Kill at <9.5%
Kill at <8.5%
Kill at <15%
Kill at <16%
Kill at <32%
Kill at <32%
Reserved for Analog Devices internal use only;
do not select
ADV7180
Data Sheet
CHROMA TRANSIENT IMPROVEMENT (CTI)
59B
The signal bandwidth allocated for chroma is typically much
smaller than that for luminance. In the past, this was a valid way
to fit a color video signal into a given overall bandwidth because
the human eye is less sensitive to chrominance than to luminance.
CTI_AB_EN, Chroma Transient Improvement
Alpha Blend Enable, Address 0x4D[1]
189B
The uneven bandwidth, however, may lead to visual artifacts in
sharp color transitions. At the border of two bars of color, both
components (luma and chroma) change at the same time (see
Figure 31). Due to the higher bandwidth, the signal transition
of the luma component is usually much sharper than that of the
chroma component. The color edge is not sharp and can be
blurred, in the worst case, over several pixels.
The CTI_AB_EN bit enables an alpha blend function within
the CTI block. If set to 1, the alpha blender mixes the transient
improved chroma with the original signal. The sharpness of the
alpha blending can be configured via the CTI_AB[1:0] bits.
LUMA SIGNAL
For the alpha blender to be active, the CTI block must be
enabled via the CTI_EN bit.
Setting CTI_AB_EN to 0 disables the CTI alpha blender.
Setting CTI_AB_EN to 1 (default) enables the CTI alpha-blend
mixing function.
CTI_AB[1:0], Chroma Transient Improvement Alpha
Blend, Address 0x4D[3:2]
LUMA SIGNAL WITH A
TRANSITION, ACCOMPANIED
BY A CHROMA TRANSITION
190B
The CTI_AB[1:0] controls the behavior of alpha blend circuitry
that mixes the sharpened chroma signal with the original one. It
thereby controls the visual impact of CTI on the output data.
ORIGINAL, SLOW CHROMA
TRANSITION PRIOR TO CTI
SHARPENED CHROMA
TRANSITION AT THE
OUTPUT OF CTI
For CTI_AB[1:0] to become active, the CTI block must be
enabled via the CTI_EN bit, and the alpha blender must be
switched on via CTI_AB_EN.
05700-026
DEMODULATED
CHROMA SIGNAL
Figure 31. CTI Luma/Chroma Transition
Sharp blending maximizes the effect of CTI on the picture but
may also increase the visual impact of small amplitude, high
frequency chroma noise.
The chroma transient improvement block examines the input video
data. It detects transitions of chroma and can be programmed to
create steeper chroma edges in an attempt to artificially restore
lost color bandwidth. The CTI block, however, operates only
on edges above a certain threshold to ensure that noise is not
emphasized. Care has also been taken to ensure that edge
ringing and undesirable saturation or hue distortion are avoided.
Table 48. CTI_AB Function
CTI_AB[1:0]
00
01
10
11 (default)
Chroma transient improvements are needed primarily for
signals that have severe chroma bandwidth limitations. For
those types of signals, it is strongly recommended to enable
the CTI block via CTI_EN.
CTI_EN, Chroma Transient Improvement Enable,
Address 0x4D[0]
Description
Sharpest mixing between sharpened and
original chroma signal
Sharp mixing
Smooth mixing
Smoothest alpha blend function
CTI_C_TH[7:0], CTI Chroma Threshold, Address 0x4E[7:0]
19B
18B
Setting CTI_EN to 0 disables the CTI block.
Setting CTI_EN to 1 (default) enables the CTI block.
The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying
how big the amplitude step in a chroma transition must be to be
steepened by the CTI block. Programming a small value into this
register causes even smaller edges to be steepened by the CTI
block. Making CTI_C_TH[7:0] a large value causes the block to
improve large transitions only.
The default value for CTI_C_TH[7:0] is 0x08, indicating the
threshold for the chroma edges prior to CTI.
Rev. J | Page 40 of 114
Data Sheet
ADV7180
DIGITAL NOISE REDUCTION (DNR) AND LUMA
PEAKING FILTER
PEAKING_GAIN[7:0], Luma Peaking Gain,
Address 0xFB[7:0]
194B
60B
Digital noise reduction is based on the assumption that high
frequency signals with low amplitude are probably noise and
that, therefore, their removal improves picture quality. The
following are the two DNR blocks in the ADV7180: the DNR1
block before the luma peaking filter and the DNR2 block after
the luma peaking filter, as shown in Figure 32.
DNR1
LUMA PEAKING
FILTER
Table 51. PEAKING_GAIN[7:0] Function
LUMA
OUTPUT
DNR2
Setting
0x40 (Default)
05700-051
LUMA
SIGNAL
This filter can be manually enabled. The user can select to boost
or to attenuate the mid region of the Y spectrum around 3 MHz.
The peaking filter can visually improve the picture by showing
more definition on the picture details that contain frequency
components around 3 MHz. The default value on this register
passes through the luma data unaltered. A lower value attenuates
the signal, and a higher value gains the luma signal. A plot of
the responses of the filter is shown in Figure 33.
Figure 32. DNR and Peaking Block Diagram
Description
0 dB response
PEAKING GAIN USING BP FILTER
15
DNR_EN, Digital Noise Reduction Enable, Address 0x4D[5]
192B
10
Table 49. DNR_EN Function
FILTER RESPONSE (dB)
The DNR_EN bit enables the DNR block or bypasses it.
Description
Bypasses DNR (disable)
Enables digital noise reduction on the luma data
DNR_TH[7:0], DNR Noise Threshold, Address 0x50[7:0]
193B
The DNR1 block is positioned before the luma peaking block.
The DNR_TH[7:0] value is an unsigned, 8-bit number used to
determine the maximum edge that is interpreted as noise and,
therefore, blanked from the luma data. Programming a large
value into DNR_TH[7:0] causes the DNR block to interpret
even large transients as noise and remove them. As a result, the
effect on the video data is more visible. Programming a small
value causes only small transients to be seen as noise and to be
removed.
Table 50. DNR_TH[7:0] Function
Setting
0x08 (default)
Description
Threshold for maximum luma edges to be
interpreted as noise
0
–5
–10
–15
–20
05700-052
Setting
0
1 (default)
5
0
1
2
3
4
FREQUENCY (MHz)
5
6
7
Figure 33. Peaking Filter Responses
DNR_TH2[7:0], DNR Noise Threshold 2,
Address 0xFC[7:0]
195B
The DNR2 block is positioned after the luma peaking block
and, therefore, affects the gained luma signal. It operates in the
same way as the DNR1 block, but there is an independent
threshold control, DNR_TH2[7:0], for this block. This value is
an unsigned, 8-bit number used to determine the maximum
edge that is interpreted as noise and, therefore, blanked from
the luma data. Programming a large value into DNR_TH2[7:0]
causes the DNR block to interpret even large transients as noise
and remove them. As a result, the effect on the video data is more
visible. Programming a small value causes only small transients
to be seen as noise and to be removed.
Table 52. DNR_TH2[7:0] Function
Setting
0x04 (default)
Rev. J | Page 41 of 114
Description
Threshold for maximum luma edges to be
interpreted as noise
ADV7180
Data Sheet
COMB FILTERS
NTSC Comb Filter Settings
The comb filters of the ADV7180 have been greatly improved to
automatically handle video of all types, standards, and levels of
quality. The NTSC and PAL configuration registers allow the
user to customize the comb filter operation depending on which
video standard is detected (by autodetection) or selected (by
manual programming).
These settings are used for NTSC M/J CVBS inputs.
NSFSEL[1:0], Split Filter Selection NTSC, Address 0x19[3:2]
The NSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A narrow split filter selection
results in better performance on diagonal lines but more dot
crawl in the final output image. The opposite is true for selecting
a wide bandwidth split filter.
Table 53. NSFSEL Function
NSFSEL[1:0]
00 (default)
01
10
11
Description
Narrow
Medium
Medium
Wide
CTAPSN[1:0], Chroma Comb Taps, NTSC, Address 0x38[7:6]
Table 54. CTAPSN Function
CTAPSN[1:0]
00
01
10 (default)
11
Description
Do not use
NTSC chroma comb adapts three lines (three taps) to two lines (two taps)
NTSC chroma comb adapts five lines (five taps) to three lines (three taps)
NTSC chroma comb adapts five lines (five taps) to four lines (four taps)
CCMN[2:0], Chroma Comb Mode, NTSC, Address 0x38[5:3]
Table 55. CCMN Function
CCMN[2:0]
000 (default)
Description
Adaptive comb mode
Configuration
Adaptive three-line chroma comb for CTAPSN = 01
Adaptive four-line chroma comb for CTAPSN = 10
Adaptive five-line chroma comb for CTAPSN = 11
100
101
Disable chroma comb
Fixed chroma comb (top lines of line memory)
110
Fixed chroma comb (all lines of line memory)
111
Fixed chroma comb (bottom lines of line memory)
Rev. J | Page 42 of 114
Fixed two-line chroma comb for CTAPSN = 01
Fixed three-line chroma comb for CTAPSN = 10
Fixed four-line chroma comb for CTAPSN = 11
Fixed three-line chroma comb for CTAPSN = 01
Fixed four-line chroma comb for CTAPSN = 10
Fixed five-line chroma comb for CTAPSN = 11
Fixed two-line chroma comb for CTAPSN = 01
Fixed three-line chroma comb for CTAPSN = 10
Fixed four-line chroma comb for CTAPSN = 11
Data Sheet
ADV7180
YCMN[2:0], Luma Comb Mode NTSC, Address 0x38[2:0]
CCMP[2:0], Chroma Comb Mode PAL, Address 0x39[5:3]
Table 56. YCMN Function
Table 59. CCMP Function
YCMN[2:0]
000 (default)
Description
Adaptive comb mode
100
Disable luma comb
101
Fixed luma comb (top
lines of line memory)
Fixed luma comb (all
lines of line memory)
Fixed luma comb
(bottom lines of line
memory)
110
111
Configuration
Adaptive three-line
(three taps) luma comb
Use low-pass/notch
filter; see the Y Shaping
Filter section
Fixed two-line (two
taps) luma comb
Fixed three-line (three
taps) luma comb
Fixed two-line (two
taps) luma comb
CCMP[2:0]
000 (default)
Description
Adaptive comb mode
100
101
Disable chroma comb
Fixed chroma comb
(top lines of line
memory)
110
Fixed chroma comb (all
lines of line memory)
111
Fixed chroma comb
(bottom lines of line
memory)
PAL Comb Filter Settings
These settings are used for PAL B/G/H/I/D, PAL M, PAL
Combinational N, PAL 60, and NTSC 4.43 CVBS inputs.
PSFSEL[1:0], Split Filter Selection, PAL, Address 0x19[1:0]
The PSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A wide split filter selection
eliminates dot crawl but shows imperfections on diagonal lines.
The opposite is true for selecting a narrow bandwidth split filter.
Table 57. PSFSEL Function
PSFSEL[1:0]
00
01 (default)
10
11
Description
Narrow
Medium
Wide
Widest
Table 60. YCMP Function
YCMP[2:0]
000 (default)
Description
Adaptive comb mode
Table 58. CTAPSP Function
100
Disable luma comb
101
Fixed luma comb (top
lines of line memory)
Fixed luma comb (all
lines of line memory)
Fixed luma comb
(bottom lines of line
memory)
10
11 (default)
Fixed two-line chroma
comb for CTAPSN = 01
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
Fixed three-line chroma
comb for CTAPSN = 01
Fixed four-line chroma
comb for CTAPSN = 10
Fixed five-line chroma
comb for CTAPSN = 11
Fixed two-line chroma
comb for CTAPSN = 01
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
YCMP[2:0], Luma Comb Mode PAL, Address 0x39[2:0]
CTAPSP[1:0], Chroma Comb Taps PAL, Address 0x39[7:6]
CTAPSP[1:0]
00
01
Configuration
Adaptive three-line
chroma comb for
CTAPSN = 01
Adaptive four-line
chroma comb for
CTAPSN = 10
Adaptive five-line
chroma comb for
CTAPSN = 11
Description
Do not use.
PAL chroma comb adapts five lines (three taps)
to three lines (two taps); cancels cross luma only
PAL chroma comb adapts five lines (five taps) to
three lines (three taps); cancels cross luma and
hue error less well
PAL chroma comb adapts five lines (five taps) to
four lines (four taps); cancels cross luma and hue
error well
110
111
Rev. J | Page 43 of 114
Configuration
Adaptive five lines (three
taps) luma comb
Use low-pass/notch filter;
see the Y Shaping Filter
section
Fixed three lines (two
taps) luma comb
Fixed five lines (three
taps) luma comb
Fixed three lines (two
taps) luma comb
ADV7180
Data Sheet
IF FILTER COMPENSATION
6
IFFILTSEL[2:0], IF Filter Select, Address 0xF8[2:0]
4
62B
204B
Bypass mode
NTSC, consists of three filter characteristics
PAL, consists of three filter characteristics
–2
–4
–6
–8
05700-053



0
–10
See Table 107 for programming details.
–12
2.0
2.5
3.0
3.5
4.0
FREQUENCY (MHz)
4.5
5.0
Figure 34. NTSC IF Filter Compensation
6
IF COMP FILTERS PAL ZOOMED AROUND FSC
4
AMPLITUDE (dB)
2
0
–2
–4
–6
–8
3.0
05700-054
The options for this feature are as follows:
2
AMPLITUDE (dB)
The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input, as would be
observed on tuner outputs. Figure 34 and Figure 35 show IF
filter compensation for NTSC and PAL, respectively.
IF COMP FILTERS NTSC ZOOMED AROUND FSC
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
Figure 35. PAL IF Filter Compensation
Rev. J | Page 44 of 114
5.5
6.0
Data Sheet
ADV7180
AV CODE INSERTION AND CONTROLS
In this output interface mode, the following assignment takes
place: Cb = FF, Y = 00, Cr = 00, and Y = AV.
This section describes the I2C-based controls that affect the
following:
•
•
•
•
In a 16-bit output interface (64-lead LQFP only), where Y and
Cr/Cb are delivered via separate data buses, the AV code is
spread over the whole 16 bits. The SD_DUP_AV bit allows the
user to replicate the AV codes on both buses; therefore, the full
AV sequence can be found on the Y bus as well as on the Cr/Cb
bus (see Figure 36).
Insertion of AV codes into the data stream
Data blanking during the vertical blank interval (VBI)
The range of data values permitted in the output data stream
The relative delay of luma vs. chroma signals
Some of the decoded VBI data is inserted during the horizontal
blanking interval. See the Gemstar Data Recovery section for
more information.
When SD_DUP_AV is 0 (default), the AV codes are in single
fashion (to suit 8-bit interleaved data output).
When SD_DUP_AV is 1, the AV codes are duplicated (for
16-bit interfaces).
BT.656-4, ITU-R BT.656-4 Enable, Address 0x04[7]
Between Revision 3 and Revision 4 of the ITU-R BT.656 standards,
the ITU has changed the toggling position for the V bit within
the SAV EAV codes for NTSC. The ITU-R BT.656-4 standard
bit allows the user to select an output mode that is compliant
with either the previous or new standard. For further information,
visit the International Telecommunication Union website.
VBI_EN, Vertical Blanking Interval Data Enable,
Address 0x03[7]
The VBI enable bit allows data such as intercast and closed
caption data to be passed through the luma channel of the decoder
with a minimal amount of filtering. All data for Line 1 to Line 21 is
passed through and available at the output port. The ADV7180
does not blank the luma data and automatically switches all filters
along the luma data path into their widest bandwidth. For active
video, the filter settings for YSH and YPK are restored.
Note that the standard change only affects NTSC and has no
bearing on PAL.
When ITU-R BT.656-4 is 0 (default), the ITU-R BT.656-3
specification is used. The V bit goes low at EAV of Line 10
and Line 273.
See the BL_C_VBI, Blank Chroma During VBI, Address 0x04[2]
section for information on the chroma path.
When ITU-R BT.656-4 is 1, the ITU-R BT.656-4 specification is
used. The V bit goes low at EAV of Line 20 and Line 283.
When VBI_EN is 0 (default), all video lines are filtered/scaled.
When VBI_EN is 1, only the active video region is filtered/scaled.
SD_DUP_AV, Duplicate AV Codes, Address 0x03[0]
Depending on the output interface width, it may be necessary to
duplicate the AV codes from the luma path into the chroma path.
In an 8-bit wide output interface (Cb/Y/Cr/Y interleaved data),
the AV codes are defined as FF/00/00/AV, with AV being the
transmitted word that contains information about H/V/F.
SD_DUP_AV = 1
SD_DUP_AV = 0
8-BIT INTERFACE
FF
00
00
AV
Y
00
AV
Y
Cr/Cb DATA BUS
FF
00
00
AV
Cb
FF
00
Cb
Cb/Y/Cr/Y
INTERLEAVED
FF
00
00
AV
AV CODE SECTION
AV CODE SECTION
AV CODE SECTION
Figure 36. AV Code Duplication Control (64-Lead LQFP Only)
Rev. J | Page 45 of 114
Cb
05700-027
16-BIT INTERFACE
16-BIT INTERFACE
Y DATA BUS
ADV7180
Data Sheet
BL_C_VBI, Blank Chroma During VBI, Address 0x04[2]
Setting BL_C_VBI high blanks the Cr and Cb values of all VBI
lines. This is done so any data that may arrive during VBI is not
decoded as color and is output through Cr and Cb. As a result,
it is possible to send VBI lines into the decoder and then output
them through an encoder again, undistorted. Without this
blanking, any color that is incorrectly decoded is encoded by
the video encoder, thus distorting the VBI lines.
Setting BL_C_VBI to 0 decodes and outputs color during VBI.
Setting BL_C_VBI to 1 (default) blanks Cr and Cb values
during VBI.
Range, Range Selection, Address 0x04[0]
AV codes (as per ITU-R BT.656, formerly known as CCIR-656)
consist of a fixed header made up of 0xFF and 0x00 values.
These two values are reserved and, therefore, are not to be used
for active video. Additionally, the ITU specifies that the nominal
range for video should be restricted to values between 16 and
235 for luma and 16 and 240 for chroma.
The range bit allows the user to limit the range of values output
by the ADV7180 to the recommended value range. The ADV7180
does not scale the data to fit within the smaller range. Any value
outside of the range is ignored. In any case, it ensures that the
reserved values of 255d (0xFF) and 00d (0x00) are not presented
on the output pins unless they are part of an AV code header.
Table 61. RANGE Function
Range
0
1 (default)
Description
16 ≤ Y ≤ 235, 16 ≤ C/P ≤ 240
1 ≤ Y ≤ 254, 1 ≤ C/P ≤ 254
AUTO_PDC_EN, Automatic Programmed Delay Control,
Address 0x27[6]
Enabling AUTO_PDC_EN activates a function within the
ADV7180 that automatically programs the LTA[1:0] and CTA[2:0]
registers to have the chroma and luma data match delays for all
modes of operation. If AUTO_PDC__EN is set, the LTA[1:0]
and CTA[2:0] manual registers are not used. If the automatic
mode is disabled (by setting the AUTO_PDC_EN bit to 0), the
values programmed into the LTA[1:0] and CTA[2:0] registers
become active.
When AUTO_PDC_EN is 0, the ADV7180 uses the LTA[1:0] and
CTA[2:0] values for delaying luma and chroma samples. See the
LTA[1:0], Luma Timing Adjust, Address 0x27[1:0] section and
the CTA[2:0], Chroma Timing Adjust, Address 0x27[5:3]
section.
When AUTO_PDC_EN is 1 (default), the ADV7180 automatically
determines the LTA and CTA values to have luma and chroma
aligned at the output.
LTA[1:0], Luma Timing Adjust, Address 0x27[1:0]
The luma timing adjust register allows the user to specify a
timing difference between chroma and luma samples.
There is a functionality overlap with the CTA[2:0] register. For
manual programming, use the following defaults:
•
•
•
CVBS input LTA[1:0] = 00
Y/C input LTA[1:0] = 01
YPrPb input LTA[1:0] = 01
Table 62. LTA Function
LTA[1:0]
00 (default)
01
10
11
Description
No delay
Luma 1 clock (37 ns) late
Luma 2 clock (74 ns) early
Luma 1 clock (37 ns) early
CTA[2:0], Chroma Timing Adjust, Address 0x27[5:3]
The chroma timing adjust register allows the user to specify a
timing difference between chroma and luma samples. This can
be used to compensate for external filter group delay differences
in the luma vs. chroma path and to allow a different number of
pipeline delays while processing the video downstream. Review
this functionality together with the LTA[1:0] register.
The chroma can be delayed or advanced only in chroma pixel
steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, where delay
cannot be made by luma pixel steps.
For manual programming, use the following defaults:
•
•
•
CVBS input CTA[2:0] = 011
Y/C input CTA[2:0] = 101
YPrPb input CTA[2:0] = 110
Table 63. CTA Function
CTA[2:0]
000
001
010
011 (default)
100
101
110
111
Rev. J | Page 46 of 114
Description
Not a valid setting
Chroma + two pixels (early)
Chroma + one pixel (early)
No delay
Chroma − one pixel (late)
Chroma − two pixels (late)
Chroma − three pixels (late)
Not a valid setting
Data Sheet
ADV7180
HSE[10:0], HS End, Address 0x34[2:0], Address 0x36[7:0]
SYNCHRONIZATION OUTPUT SIGNALS
214B
64B
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 37). HSE is set to
00000000000b, which is 0 LLC clock cycles from count [0].
HS Configuration
109B
The following controls allow the user to configure the behavior
of the HS output pin only:



Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
The default value of HSE[10:0] is 00, indicating that the HS
pulse ends 0 pixels after the falling edge of HS.
The HS begin (HSB) and HS end (HSE) registers allow the user
to freely position the HS output (pin) within the video line. The
values in HSB[10:0] and HSE[10:0] are measured in pixel units
from the falling edge of HS. Using both values, the user can
program both the position and length of the HS output signal.
For example,

To shift the HS toward active video by 20 LLCs, add
20 LLCs to both HSB and HSE, that is,
HSB[10:0] = [00000010110], HSE[10:0] = [00000010100].
To shift the HS away from active video by 20 LLCs, add
1696 LLCs to both HSB and HSE (for NTSC), that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
Therefore, 1696 is derived from the NTSC total number of
pixels, 1716.
To move 20 LLCs away from active video, subtract 20 from
1716 and add the result in binary to both HSB[10:0] and
HSE[10:0].

HSB[10:0], HS Begin, Address 0x34[6:4], Address 0x35[7:0]
213B
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 37). HSB is set to
00000000010b, which is two LLC clock cycles from count [0].
The default value of HSB[10:0] is 0x02, indicating that the HS
pulse starts two pixels after the falling edge of HS.

PHS, Polarity HS, Address 0x37[7]
215B
The polarity of the HS pin can be inverted using the PHS bit.
When PHS is 0 (default), HS is active low.
When PHS is 1, HS is active high.
Table 64. HS Timing Parameters (See Figure 37)
Standard
NTSC
PAL
HS Begin Adjust
HSB[10:0] (Default)
00000000010b
00000000010b
Characteristic
HS to Active Video
LLC Clock Cycles, C
in Figure 37 (Default)
272
284
HS End Adjust
HSE[10:0] (Default)
00000000000b
00000000000b
Active Video Samples/
Line, D in Figure 37
720Y + 720C = 1440
720Y + 720C = 1440
Total LLC Clock
Cycles, E in Figure 37
1716
1728
LLC
HS
Cr
ACTIVE
VIDEO
Y
FF
00
00
XY
10
80
10
EAV
HSE[10:0]
D
E
80
4 LLC
80
10
FF
00
H BLANK
00
SAV
XY
Cb
Y
Cr
Y
Cb
Y
Cr
ACTIVE VIDEO
HSB[10:0]
C
D
E
Figure 37. HS Timing
Rev. J | Page 47 of 114
05700-028
PIXEL
BUS
ADV7180
Data Sheet
VS and FIELD Configuration
HVSTIM, Horizontal VS Timing, Address 0x31[3]
The following controls allow the user to configure the behavior
of the VS and FIELD output pins, as well as the generation of
embedded AV codes.
The HVSTIM bit allows the user to select where the VS signal is
asserted within a line of video. Some interface circuitry may require
VS to go low while HS is low.
The 64-lead LQFP has separate VS and FIELD pins. The 48-lead
LQFP, 40-lead LFCSP, and 32-lead LFCSP do not have separate
VS and FIELD pins but can output either VS or FIELD on Pin 45
(48-lead LQFP), Pin 37 (40-lead LFCSP), or Pin 31 (32-lead
LFCSP), which is the VS/FIELD pin.
When HVSTIM is 0 (default), the start of the line is relative to HSE.
SQPE, Square Pixel Mode, Address 0x01[2]
The SQPE bit allows the user to select the square pixel mode.
This mode is not suitable for poor time-based video sources.
This mode is recommended for professional applications only
and should not be used with VCR or tuner sources.
When HVSTIM is 1, the start of the line is relative to HSB.
VSBHO, VS Begin Horizontal Position Odd, Address 0x32[7]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high or low.
When VSBHO is 0 (default), the VS pin goes high in the middle
of a line of video (odd field).
Setting SQPE to 1 enables square pixel mode. The LLC for
NTSC is 24.5454 MHz and 29.5 MHz for PAL. The crystal
frequency does not change.
When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).
VS/FIELD, Address 0x58[0]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high or low.
VSBHE, VS Begin Horizontal Position Even, Address 0x32[6]
This feature is used for the 48-lead LQFP, 40-lead LFCSP, and
32-lead LFCSP only. The polarity of this bit determines what
signal appears on the VS/FIELD pin.
When this bit is set to 0 (default), the FIELD signal is output.
When this bit is set to 1, the VSYNC signal is output.
When VSBHE is 1, the VS pin changes state at the start of a line
(even field).
The 64-lead LQFP has dedicated FIELD and VSYNC pins.
ADV encoder-compatible signals via the NEWAVMODE
register follow:
VSEHO, VS End Horizontal Position Odd, Address 0x33[7]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high or low.
• PVS, PF
• HVSTIM
• VSBHO, VSBHE
• VSEHO, VSEHE
For NTSC control,
• NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0]
• NVENDDELO, NVENDDELE, NVENDSIGN, NVEND[4:0]
• NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG[4:0]
For PAL control,
•
•
•
When VSBHE is 0 (default), the VS pin goes high in the middle
of a line of video (even field).
PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0]
PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0]
PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0]
NEWAVMODE, New AV Mode, Address 0x31[4]
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit Analog Devices encoders. No adjustments are possible.
Setting NEWAVMODE to 1 (default) enables the manual position
of the VSYNC, FIELD, and AV codes using Register 0x32 to
Register 0x33 and Register 0xE5 to Register 0xEA. Default register
settings are CCIR656 compliant; see Figure 38 for NTSC and
Figure 43 for PAL. For recommended manual user settings, see
Table 65 and Figure 39 for NTSC and Table 66 and Figure 44 for
PAL.
When VSEHO is 0 (default), the VS pin goes low (inactive) in
the middle of a line of video (odd field).
When VSEHO is 1, the VS pin changes state at the start of a line
(odd field).
VSEHE, VS End Horizontal Position Even, Address 0x33[6]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high or low.
When VSEHE is 0 (default), the VS pin goes low (inactive) in
the middle of a line of video (even field).
When VSEHE is 1, the VS pin changes state at the start of a line
(even field).
PVS, Polarity VS, Address 0x37[5]
The polarity of the VS pin can be inverted using the PVS bit.
When PVS is 0 (default), VS is active high.
When PVS is 1, VS is active low.
Rev. J | Page 48 of 114
Data Sheet
ADV7180
PF, Polarity FIELD, Address 0x37[3]
Table 65. User Settings for NTSC (See Figure 39)
The polarity of the FIELD pin for the 64-lead LQFP part can be
inverted using the PF bit.
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE5
0xE6
0xE7
25B
The FIELD pin can be inverted using the PF bit.
When PF is 0 (default), FIELD is active high.
When PF is 1, FIELD is active low.
Register Name
VS/FIELD Control 1
VS/FIELD Control 2
VS/FIELD Control 3
HS Position Control 1
HS Position Control 2
HS Position Control 3
Polarity
NTSV V bit begin
NTSC V bit end
NTSC F bit toggle
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
19
20
21
22
OUTPUT
VIDEO
H
V
1BT.656-4
NVEND[4:0] = 0x04
NVBEG[4:0] = 0x05
REG 0x04, BIT 7 = 1
F
NFTOG[4:0] = 0x03
FIELD 2
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
283
284
285
OUTPUT
VIDEO
H
V
NVBEG[4:0] = 0x05
1BT.656-4
NVEND[4:0] = 0x04
REG 0x04, BIT 7 = 1
F
05700-029
NFTOG[4:0] = 0x03
1APPLIES IF NEWAVMODE = 0:
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
Figure 38. NTSC Default, ITU-R BT.656 (the Polarity of H, V, and F is Embedded in the Data)
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
21
22
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVBEG[4:0] = 0x01
FIELD
OUTPUT
NVEND[4:0] = 0x04
NFTOG[4:0] = 0x06
FIELD 2
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
284
285
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVEND[4:0] = 0x04
NFTOG[4:0] = 0x06
Figure 39. NTSC Typical VSYNC/FIELD Positions Using the Register Writes in Table 65
Rev. J | Page 49 of 114
05700-030
NVBEG[4:0] = 0x01
FIELD
OUTPUT
ADV7180
Data Sheet
1
NVBEGSIGN
ADVANCE BEGIN OF
VSYNC BY NVBEG[4:0]
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC signal on the VS pin are modified.
0
DELAY BEGIN OF
VSYNC BY NVBEG[4:0]
1
NVENDSIGN
ADVANCE END OF
VSYNC BY NVEND[4:0]
NOT VALID FOR USER
PROGRAMMING
0
DELAY END OF VSYNC
BY NVEND[4:0]
ODD FIELD?
YES
NO
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
NVBEGDELO
0
0
ADDITIONAL
DELAY BY
1 LINE
1
ADDITIONAL
DELAY BY
1 LINE
1
NVENDDELO
NVENDDELE
0
0
1
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
VSEHO
VSEHE
VSBHE
0
0
ADVANCE BY
0.5 LINE
1
ADVANCE BY
0.5 LINE
VSYNC BEGIN
1
0
0
ADVANCE BY
0.5 LINE
1
ADVANCE BY
0.5 LINE
Figure 40. NTSC VSYNC Begin
VSYNC END
NVBEGDELO, NTSC VSYNC Begin Delay on Odd Field,
Address 0xE5[7]
26B
05700-032
VSBHO
NO
1
05700-031
1
NVBEGDELE
YES
Figure 41. NTSC VSYNC End
NVENDDELO, NTSC VSYNC End Delay on Odd Field,
Address 0xE6[7]
When NVBEGDELO is 0 (default), there is no delay.
230B
Setting NVBEGDELO to 1 delays VSYNC going high on an odd
field by a line relative to NVBEG.
When NVENDDELO is 0 (default), there is no delay.
Setting NVENDDELO to 1 delays VSYNC from going low on
an odd field by a line relative to NVEND.
NVBEGDELE, NTSC VSYNC Begin Delay on Even Field,
Address 0xE5[6]
27B
NVENDDELE, NTSC VSYNC End Delay on Even Field,
Address 0xE6[6]
When NVBEGDELE is 0 (default), there is no delay.
231B
Setting NVBEGDELE to 1 delays VSYNC going high on an
even field by a line relative to NVBEG.
When NVENDDELE is set to 0 (default), there is no delay.
Setting NVENDDELE to 1 delays VSYNC from going low on an
even field by a line relative to NVEND.
NVBEGSIGN, NTSC VSYNC Begin Sign, Address 0xE5[5]
28B
Setting NVBEGSIGN to 0 delays the start of VSYNC. Set for
user manual programming.
NVENDSIGN, NTSC VSYNC End Sign, Address 0xE6[5]
23B
Setting NVBEGSIGN to 1 (default) advances the start of
VSYNC (not recommended for user programming).
Setting NVENDSIGN to 0 (default) delays the end of VSYNC.
Set for user manual programming.
NVBEG[4:0], NTSC VSYNC Begin, Address 0xE5[4:0]
Setting NVENDSIGN to 1 advances the end of VSYNC (not
recommended for user programming).
29B
The default value of NVBEG is 00101, indicating the NTSC
VSYNC begin position.
Rev. J | Page 50 of 114
Data Sheet
ADV7180
NVEND[4:0], NTSC VSYNC End, Address 0xE6[4:0]
NFTOG[4:0], NTSC Field Toggle, Address 0xE7[4:0]
23B
237B
The default value of NVEND is 00100, indicating the NTSC
VSYNC end position.
The default value of NFTOG is 00011, indicating the NTSC
field toggle position.
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC signal on the VS pin are modified.
For all NTSC/PAL field timing controls, both the F bit in the
AV code and the field signal on the FIELD pin are modified.
NFTOGDELO, NTSC FIELD Toggle Delay on Odd Field,
Address 0xE7[7]
234B
NFTOGSIGN
1
When NFTOGDELO is 0 (default), there is no delay.
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
Setting NFTOGDELO to 1 delays the field toggle/transition on
an odd field by a line relative to NFTOG.
0
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
NOT VALID FOR USER
PROGRAMMING
NFTOGDELE, NTSC Field Toggle Delay on Even Field,
Address 0xE7[6]
235B
ODD FIELD?
YES
NO
NFTOGDELO
NFTOGDELE
Setting NFTOGDELE to 1 (default) delays the field toggle/
transition on an even field by a line relative to NFTOG.
NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7[5]
236B
1
Setting NFTOGSIGN to 0 delays the field transition. Set for
user manual programming.
0
0
ADDITIONAL
DELAY BY
1 LINE
Setting NFTOGSIGN to 1 (default) advances the field transition
(not recommended for user programming).
1
ADDITIONAL
DELAY BY
1 LINE
05700-033
When NFTOGDELE is 0, there is no delay.
FIELD
TOGGLE
Figure 42. NTSC FIELD Toggle
FIELD 1
OUTPUT
VIDEO
622
623
624
625
1
2
3
4
5
6
7
8
9
10
22
23
24
H
V
PVBEG[4:0] = 0x05
PVEND[4:0] = 0x04
F
PFTOG[4:0] = 0x03
FIELD 2
310
311
312
313
314
315
316
317
318
319
320
321
322
335
336
337
OUTPUT
VIDEO
H
V
PVEND[4:0] = 0x04
05700-034
PVBEG[4:0] = 0x05
F
PFTOG[4:0] = 0x03
Figure 43. PAL Default, ITU-R BT.656 (the Polarity of H, V, and F Is Embedded in the Data)
Rev. J | Page 51 of 114
ADV7180
Data Sheet
FIELD 1
622
623
624
625
1
2
3
4
5
6
7
8
9
10
11
23
24
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x01
FIELD
OUTPUT
PVEND[4:0] = 0x04
PFTOG[4:0] = 0x06
FIELD 2
310
311
312
313
314
315
316
317
318
319
320
321
322
323
336
337
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVEND[4:0] = 0x04
05700-035
PVBEG[4:0] = 0x01
FIELD
OUTPUT
PFTOG[4:0] = 0x06
Figure 44. PAL Typical VS/FIELD Positions Using the Register Writes Shown in Table 66
PVBEG[4:0], PAL VSYNC Begin, Address 0xE8[4:0]
Table 66. User Settings for PAL (See Figure 44)
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE8
0xE9
0xEA
Register Name
VS/FIELD Control 1
VS/FIELD Control 2
VS/FIELD Control 3
HS Position Control 1
HS Position Control 2
HS Position Control 3
Polarity
PAL V bit begin
PAL V bit end
PAL F bit toggle
241B
The default value of PVBEG is 00101, indicating the PAL VSYNC
begin position. For all NTSC/PAL VSYNC timing controls, the
V bit in the AV code and the VSYNC signal on the VS pin are
modified.
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
1
PVBEGSIGN
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
0
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
PVBEGDELO, PAL VSYNC Begin Delay on Odd Field,
Address 0xE8[7]
YES
NO
PVBEGDELO
PVBEGDELE
238B
When PVBEGDELO is 0 (default), there is no delay.
1
Setting PVBEGDELO to 1 delays VSYNC going high on an odd
field by a line relative to PVBEG.
PVBEGDELE, PAL VSYNC Begin Delay on Even Field,
Address 0xE8[6]
0
0
1
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
VSBHO
VSBHE
239B
Setting PVBEGDELE to 1 (default) delays VSYNC going high
on an even field by a line relative to PVBEG.
PVBEGSIGN, PAL VSYNC Begin Sign, Address 0xE8[5]
240B
1
0
0
ADVANCE BY
0.5 LINE
1
ADVANCE BY
0.5 LINE
Setting PVBEGSIGN to 0 delays the beginning of VSYNC. Set
for user manual programming.
Setting PVBEGSIGN to 1 (default) advances the beginning of
VSYNC (not recommended for user programming).
Rev. J | Page 52 of 114
VSYNC BEGIN
Figure 45. PAL VSYNC Begin
05700-036
When PVBEGDELE is 0, there is no delay.
Data Sheet
ADV7180
PFTOGDELO, PAL Field Toggle Delay on Odd Field,
Address 0xEA[7]
246B
1
PVENDSIGN
ADVANCE END OF
VSYNC BY PVEND[4:0]
0
When PFTOGDELO is 0 (default), there is no delay.
DELAY END OF VSYNC
BY PVEND[4:0]
Setting PFTOGDELO to 1 delays the F toggle/transition on an
odd field by a line relative to PFTOG.
NOT VALID FOR USER
PROGRAMMING
PFTOGDELE, PAL Field Toggle Delay on Even Field,
Address 0xEA[6]
247B
ODD FIELD?
YES
NO
PVENDDELO
PVENDDELE
1
0
0
When PFTOGDELE is 0, there is no delay.
Setting PFTOGDELE to 1 (default) delays the F toggle/transition
on an even field by a line relative to PFTOG.
PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA[5]
248B
1
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
VSEHO
VSEHE
Setting PFTOGSIGN to 0 delays the field transition. Set for user
manual programming.
Setting PFTOGSIGN to 1 (default) advances the field transition
(not recommended for user programming).
PFTOG, PAL Field Toggle, Address 0xEA[4:0]
249B
1
0
0
ADVANCE BY
0.5 LINE
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
1
For all NTSC/PAL field timing controls, the F bit in the AV
code and the field signal on the FIELD pin are modified.
ADVANCE BY
0.5 LINE
VSYNC END
05700-037
1
ADVANCE TOGGLE OF
FIELD BY PFTOG[4:0]
Figure 46. PAL VSYNC End
PVENDDELO, PAL VSYNC End Delay on Odd Field,
Address 0xE9[7]
PFTOGSIGN
0
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
24B
NOT VALID FOR USER
PROGRAMMING
When PVENDDELO is 0 (default), there is no delay.
ODD FIELD?
Setting PVENDDELO to 1 delays VSYNC going low on an odd
field by a line relative to PVEND.
PVENDDELE, PAL VSYNC End Delay on Even Field,
Address 0xE9[6]
YES
NO
PFTOGDELO
PFTOGDELE
243B
1
0
0
1
When PVENDDELE is 0 (default), there is no delay.
Setting PVENDDELE to 1 delays VSYNC going low on an even
field by a line relative to PVEND.
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
PVENDSIGN, PAL VSYNC End Sign, Address 0xE9[5]
Setting PVENDSIGN to 0 (default) delays the end of VSYNC
(set for user manual programming).
FIELD
TOGGLE
Figure 47. PAL F Toggle
Setting PVENDSIGN to 1 advances the end of VSYNC (not
recommended for user programming).
PVEND[4:0], PAL VSYNC End, Address 0xE9[4:0]
245B
The default value of PVEND is 10100, indicating the PAL
VSYNC end position.
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC signal on the VS pin are modified.
Rev. J | Page 53 of 114
05700-038
24B
ADV7180
Data Sheet
SYNC PROCESSING
Table 68. NTSC
The ADV7180 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits: ENHSPLL and
ENVSPROC.
Feature
Teletext System B and D
Teletext System C/NABTS
Vertical Interval Time Codes (VITC)
Copy Generation Management
System (CGMS)
Gemstar
Closed Captioning (CCAP)
ENHSPLL, Enable HSYNC Processor, Address 0x01[6]
The HSYNC processor is designed to filter incoming HSYNCs that
have been corrupted by noise, providing improved performance
for video signals with stable time bases but poor SNR.
Setting ENHSPLL to 0 disables the HSYNC processor.
Setting ENHSPLL to 1 (default) enables the HSYNC processor.
ENVSPROC, Enable VSYNC Processor, Address 0x01[3]
This block provides extra filtering of the detected VSYNCs to
improve vertical lock.
Setting ENVSPROC to 0 disables the VSYNC processor.
Setting ENVSPROC to 1 (default) enables the VSYNC processor.
VBI DATA DECODE
The following are the two VBI data slicers on the ADV7180: the
VBI data processor (VDP) and the VBI System 2.
The VDP can slice both low bandwidth standards and high
bandwidth standards such as teletext. VBI System 2 can slice
low data rate VBI standards only.
The VDP is capable of slicing multiple VBI data standards on
SD video. It decodes the VBI data on the incoming CVBS and
Y/C or YUV data. The decoded results are available as ancillary
data in output 656 data stream. For low data rate VBI standards
like CC/WSS/CGMS, users can read the decoded data bytes
from the I2C registers.
The VBI data standards that can be decoded by the VDP are
listed in Table 67 and Table 68.
Table 67. PAL
Feature
Teletext System A, C, or D
Teletext System B/WST
Video Programming System (VPS)
Vertical Interval Time Codes (VITC)
Wide Screen Signaling (WSS)
Closed Captioning (CCAP)
Standard
ITU-R BT.653
ITU-R BT.653
ETSI EN 300 231 V 1.3.1
Not applicable
ITU-R BT.1119-1/
ETSI EN.300294
Not applicable
Standard
ITU-R BT.653
ITU-R BT.653/EIA-516
Not applicable
EIA-J CPR-1204/IEC 61880
Not applicable
EIA-608
The VBI data standard that the VDP decodes on a particular
line of incoming video has been set by default as described in
Table 69. This can be overridden manually and any VBI data can
be decoded on any line. The details of manual programming are
described in Table 70.
VDP Default Configuration
The VDP can decode different VBI data standards on a line-toline basis. The various standards supported by default on different
lines of VBI are explained in Table 69.
VDP Manual Configuration
MAN_LINE_PGM, Enable Manual Line Programming of
VBI Standards, Address 0x64[7], User Sub Map
The user can configure the VDP to decode different standards on
a line-to-line basis through manual line programming. For this,
the user must set the MAN_LINE_PGM bit. The user must write
into all the line programming registers, VBI_DATA_Px_Ny and
VBI_DATA_Px (see Register 0x64 to Register 0x77 in Table 108).
When MAN_LINE_PGM to 0 (default) is set, the VDP decodes
default standards on lines, as shown in Table 69.
When MAN_LINE_PGM to 1 is set, the VBI standards to be
decoded are manually programmed.
VBI_DATA_Px_Ny[3:0], VBI_DATA_Px[3:0], VBI
Standard to be Decoded on Line X for PAL, Line Y for
NTSC, Address 0x64 to Address 0x77, User Sub Map
These are related 4-bit clusters in Register 0x64 to Register 0x77
of the user sub map. These 4-bit, line programming registers,
VBI_DATA_Px_Ny and VBI_DATA_Px, identify the VBI data
standard that are decoded on Line X in PAL mode or on Line Y
in NTSC mode. The different types of VBI standards decoded
by VBI_DATA_Px_Ny and VBI_DATA_Px are shown in Table 70.
Note that the X or Y value depends on whether the ADV7180 is
in PAL or NTSC mode.
Rev. J | Page 54 of 114
Data Sheet
ADV7180
Table 69. Default Standards on Lines for PAL and NTSC
Line No.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PAL—625/50
Default VBI
Data Decoded
Line No.
WST
318
WST
319
WST
320
WST
321
WST
322
WST
323
WST
324
WST
325
WST
326
WST
327
VPS
328
N/A
329
N/A
332
VITC
333
WST
334
WST
335
Default VBI
Data Decoded
VPS
WST
WST
WST
WST
WST
WST
WST
WST
WST
WST
VPS
VITC
WST
WST
CCAP
22
CCAP
336
WST
23
WSS
337 + full
even field
WST
24 + full
odd field
WST
Line No.
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22 + full
odd field
NTSC—525/60
Default VBI
Data Decoded
Line No.
Gemstar_1×
286
Gemstar_1×
287
Gemstar_1×
288
NABTS
272
NABTS
273
NABTS
274
NABTS
275
VITC
276
NABTS
277
VITC
278
NABTS
279
NABTS
280
NABTS
281
CGMS
282
CCAP
283
NABTS
284
285 + full
even field
Default VBI
Data Decoded
Gemstar_1×
Gemstar_1×
Gemstar_1×
NABTS
NABTS
NABTS
NABTS
NABTS
VITC
NABTS
VITC
NABTS
NABTS
NABTS
CGMS
CCAP
NABTS
Table 70. VBI Data Standards for Manual Configuration
VBI_DATA_Px_Ny
0000
0001
0010
0011
0100
0101
0110
0111
1000 to 1111
625/50—PAL
Disable VDP
Teletext system identified by VDP_TTXT_TYPE
VPS-ETSI EN 300 231 V 1.3.1
VITC
WSS ITU-R BT.1119-1/ETSI.EN.300294
Reserved
Reserved
CCAP
Reserved
Rev. J | Page 55 of 114
525/60—NTSC
Disable VDP
Teletext system identified by VDP_TTXT_TYPE
Reserved
VITC
CGMS EIA-J CPR-1204/IEC 61880
Gemstar_1×
Gemstar_2×
CCAP EIA-608
Reserved
ADV7180
Data Sheet
Table 71.VBI Data Standards to be Decoded on Line Px (PAL) or Line Ny (NTSC)
Signal Name
VBI_DATA_P6_N23
VBI_DATA_P7_N24
VBI_DATA_P8_N25
VBI_DATA_P9
VBI_DATA_P10
VBI_DATA_P11
VBI_DATA_P12_N10
VBI_DATA_P13_N11
VBI_DATA_P14_N12
VBI_DATA_P15_N13
VBI_DATA_P16_N14
VBI_DATA_P17_N15
VBI_DATA_P18_N16
VBI_DATA_P19_N17
VBI_DATA_P20_N18
VBI_DATA_P21_N19
VBI_DATA_P22_N20
VBI_DATA_P23_N21
VBI_DATA_P24_N22
VBI_DATA_P318
VBI_DATA_P319_N286
VBI_DATA_P320_N287
VBI_DATA_P321_N288
VBI_DATA_P322
VBI_DATA_P323
VBI_DATA_P324_N272
VBI_DATA_P325_N273
VBI_DATA_P326_N274
VBI_DATA_P327_N275
VBI_DATA_P328_N276
VBI_DATA_P329_N277
VBI_DATA_P330_N278
VBI_DATA_P331_N279
VBI_DATA_P332_N280
VBI_DATA_P333_N281
VBI_DATA_P334_N282
VBI_DATA_P335_N283
VBI_DATA_P336_N284
VBI_DATA_P337_N285
Register Location
VDP_LINE_00F[7:4]
VDP_LINE_010[7:4]
VDP_LINE_011[7:4]
VDP_LINE_012[7:4]
VDP_LINE_013[7:4]
VDP_LINE_014[7:4]
VDP_LINE_015[7:4]
VDP_LINE_016[7:4]
VDP_LINE_017[7:4]
VDP_LINE_018[7:4]
VDP_LINE_019[7:4]
VDP_LINE_01A[7:4]
VDP_LINE_01B[7:4]
VDP_LINE_01C[7:4]
VDP_LINE_01D[7:4]
VDP_LINE_01E[7:4]
VDP_LINE_01F[7:4]
VDP_LINE_020[7:4]
VDP_LINE_021[7:4]
VDP_LINE_00E[3:0]
VDP_LINE_00F[3:0]
VDP_LINE_010[3:0]
VDP_LINE_011[3:0]
VDP_LINE_012[3:0]
VDP_LINE_013[3:0]
VDP_LINE_014[3:0]
VDP_LINE_015[3:0]
VDP_LINE_016[3:0]
VDP_LINE_017[3:0]
VDP_LINE_018[3:0]
VDP_LINE_019[3:0]
VDP_LINE_01A[3:0]
VDP_LINE_01B[3:0]
VDP_LINE_01C[3:0]
VDP_LINE_01D[3:0]
VDP_LINE_01E[3:0]
VDP_LINE_01F[3:0]
VDP_LINE_020[3:0]
VDP_LINE_021[3:0]
Dec Address
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
Note that full field detection (lines other than VBI lines) of any
standard can also be enabled by writing into the VBI_DATA_
P24_N22[3:0] and VBI_DATA_P337_N285[3:0] registers. So, if
VBI_DATA_P24_N22[3:0] is programmed with any teletext
standard, then teletext is decoded off for the entire odd field.
The corresponding register for the even field is VBI_DATA_
P337_N285[3:0].
Hex Address
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
For teletext system identification, VDP assumes that if teletext
is present in a video channel, all the teletext lines comply with a
single standard system. Therefore, the line programming using
the VBI_DATA_Px_Ny and VBI_DATA_Px registers identifies
whether the data in line is teletext; the actual standard is
identified by the VDP_TTXT_TYPE_MAN bit.
To program the VDP_TTXT_TYPE_MAN bit, the
VDP_TTXT_TYPE_MAN_ENABLE bit must be set to 1.
Rev. J | Page 56 of 114
Data Sheet
ADV7180
VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual
Selection of Teletext Type, Address 0x60[2], User Sub Map
Setting ADF_ENABLE to 1 enables the insertion of VBI
decoded data into the ancillary 656 stream.
Setting VDP_TTXT_TYPE_MAN_ENABLE to 0 (default), the
manual programming of the teletext type is disabled.
The user may select the data identification word (DID) and the
secondary data identification word (SDID) through programming
the ADF_DID[4:0] and ADF_SDID[5:0] bits, respectively.
Setting VDP_TTXT_TYPE_MAN_ENABLE to 1, the manual
programming of the teletext type is enabled.
VDP_TTXT_TYPE_MAN[1:0], Specify the Teletext Type,
Address 0x60[1:0], User Sub Map
These bits specify the teletext type to be decoded. These bits are
functional only if VDP_TTXT_TYPE_MAN_ENABLE is set to 1.
01
10
11
625/50 (PAL)
Teletext-ITU-BT.653625/50-A
Teletext-ITU-BT.653625/50-B (WST)
Teletext-ITU-BT.653625/50-C
Teletext-ITU-BT.653625/50-D
This bit selects the data ID word to be inserted into the ancillary
data stream with the data decoded by the VDP.
The default value of ADF_DID[4:0] is 10101.
ADF_SDID[5:0], User-Specified Secondary Data ID Word
in Ancillary Data, Address 0x63[5:0], User Sub Map
Table 72. VDP_TTXT_TYPE_MAN Function
VDP_TTXT_
TYPE_MAN[1:0]
00 (default)
ADF_DID[4:0], User-Specified Data ID Word in Ancillary
Data, Address 0x62[4:0], User Sub Map
525/60 (NTSC)
Reserved
These bits select the secondary data ID word to be inserted in
the ancillary data stream with the data decoded by the VDP.
Teletext-ITU-BT.653525/60-B
Teletext-ITU-BT.653525/60-C or EIA516
(NABTS)
Teletext-ITU-BT.653525/60-D
VDP Ancillary Data Output
Reading the data back via I2C may not be feasible for VBI data
standards with high data rates (for example, teletext). An alternative
is to place the sliced data in a packet in the line blanking of the
digital output CCIR656 stream. This is available for all standards
sliced by the VDP module.
When data is sliced on a given line, the corresponding ancillary
data packet is placed immediately after the next EAV code that
occurs at the output (that is, data sliced from multiple lines are
not buffered up and then emitted in a burst). Note that, due to
the vertical delay through the comb filters, the line number on
which the packet is placed differs from the line number on
which the data was sliced.
The user can enable or disable the insertion of VDP results that
have been decoded into the 656 ancillary streams by using the
ADF_ENABLE bit.
The default value of ADF_SDID[5:0] is 101010.
DUPLICATE_ADF, Enable Duplication/Spreading of
Ancillary Data over Y and C Buses, Address 0x63[7], User
Sub Map
This bit determines whether the ancillary data is duplicated over
both Y and C buses or if the data packets are spread between
the two channels.
When DUPLICATE_ADF to 0 (default) is set, the ancillary data
packet is spread across the Y and C data streams.
When DUPLICATE_ADF to 1 is set, the ancillary data packet is
duplicated on the Y and C data streams.
ADF_MODE[1:0], Determine the Ancillary Data Output
Mode, Address 0x62[6:5], User Sub Map
These bits determine whether the ancillary data output mode is
in byte mode or nibble mode.
Table 73. ADF_MODE
ADF_MODE[1:0]
00 (default)
01
10
11
ADF_ENABLE, Enable Ancillary Data Output Through
656 Stream, Address 0x62[7], User Sub Map
Setting ADF_ENABLE to 0 (default) disables the insertion of
VBI decoded data into the ancillary 656 stream.
Rev. J | Page 57 of 114
Description
Nibble mode
Byte mode, no code restrictions
Byte mode, but 0x00 and 0xFF prevented
(0x00 replaced by 0x01, 0xFF replaced by 0xFE)
Reserved
ADV7180
Data Sheet
•
The ancillary data packet sequence is explained in Table 74 and
Table 75. The nibble output mode is the default mode of output
from the ancillary stream when ancillary stream output is
enabled. This format is in compliance with ITU-R BT.1364.
•
The following abbreviations are used in Table 74 and Table 75:
•
•
EP—Even parity for Bit B8 to Bit B2. The EP of the parity
bit is set so that an even number of 1s are in Bit B8 to
Bit B2, including the parity bit, D8.
CS—Checksum word. The CS word is used to increase
confidence of the integrity of the ancillary data packet
from the DID, SDID, and DC through user data-words
(UDWs). It consists of 10 bits that include the following:
a 9-bit calculated value and B9 as the inverse of B8. The
checksum value B8 to B0 is equal to the nine LSBs of the
sum of the nine LSBs of the DID, SDID, and DC and all
UDWs in the packet. Prior to the start of the checksum
count cycle, all checksum and carry bits are preset to 0.
Any carry resulting from the checksum count cycle is
ignored.
•
EP—The MSB, B9, is the inverse of EP. This ensures that
restricted Code 0x00 and Code 0xFF do not occur.
LINE_NUMBER[9:0]—The line number of the line that
immediately precedes the ancillary data packet. The line
number is from the numbering system in ITU-R BT.470.
The line number runs from 1 to 625 in a 625-line system
and from 1 to 263 in a 525-line system. Note that, due to
the vertical delay through the comb filters, the line number
on which the packet is output differs from the line number
on which the VBI data was sliced.
Data count—The data count specifies the number of UDWs
in the ancillary stream for the standard. The total number
of user data-words is four times the data count. Padding
words can be introduced to make the total number of
UDWs divisible by 4.
Table 74. Ancillary Data in Nibble Output Format
Byte
0
1
2
3
B9
0
1
1
EP
B8
0
1
1
EP
B7
0
1
1
0
B6
0
1
1
4
EP
EP
5
EP
EP
6
EP
EP
7
EP
EP
0
8
EP
EP
EVEN_FIELD
9
EP
EP
0
0
10
EP
EP
0
0
11
EP
EP
0
0
12
EP
EP
0
13
EP
EP
0
14
EP
EP
0
B5
0
1
1
B4
B3
0
0
1
1
1
1
I2C_DID6_2[4:0]
B2
0
1
1
B1
0
1
1
0
B0
0
1
1
0
0
0
Description
Ancillary data preamble
0
0
DID (data identification
word)
SDID (secondary data
identification word)
Data count
0
0
ID0 (User Data-Word 1)
LINE_NUMBER[9:5]
0
0
ID1 (User Data-Word 2)
LINE_NUMBER[4:0]
0
0
ID2 (User Data-Word 3)
0
0
ID3 (User Data-Word 4)
VBI_WORD_1[7:4]
0
0
ID4 (User Data-Word 5)
VBI_WORD_1[3:0]
0
0
ID5 (User Data-Word 6)
0
VBI_WORD_2[7:4]
0
0
ID6 (User Data-Word 7)
0
VBI_WORD_2[3:0]
0
0
ID7 (User Data-Word 8)
0
VBI_WORD_3[7:4]
0
0
ID8 (User Data-Word 9)
I2C_SDID7_2[5:0]
0
DC[4:0]
Padding[1:0]
VBI_DATA_STD[3:0]
0
0
VDP_TTXT_TYPE[1:0]
Pad 0x200; these
padding words may be
present, depending on
ancillary data type; user
data-word
n−3
n−2
n−1
1
1
B8
0
0
0
0
0
0
0
0
0
0
Checksum (CS)
0
0
Rev. J | Page 58 of 114
0
0
0
0
0
0
0
0
CS (checksum word)
Data Sheet
ADV7180
Table 75. Ancillary Data in Byte Output Format1
Byte
0
1
2
3
B9
0
1
1
EP
B8
0
1
1
EP
4
EP
EP
5
EP
EP
6
EP
EP
7
EP
EP
0
8
EP
EP
EVEN_FIELD
9
10
11
12
13
14
EP
EP
0
n−3
n−2
n−1
1
1
B8
0
0
0
0
1
B7
0
1
1
0
B6
0
1
1
B5
0
1
1
B4
B3
0
0
1
1
1
1
I2C_DID6_2[4:0]
B2
0
1
1
I C_SDID7_2[5:0]
2
0
DC[4:0]
Padding[1:0]
VBI_DATA_STD[3:0]
B0
0
1
1
0
Description
Ancillary data preamble
0
0
SDID
0
0
Data count
DID
0
0
ID0 (User Data-Word 1)
LINE_NUMBER[9:5]
0
0
ID1 (User Data-Word 2)
LINE_NUMBER[4:0]
0
0
0
VBI_WORD_1[7:0]
VBI_WORD_2[7:0]
VBI_WORD_3[7:0]
VBI_WORD_4[7:0]
VBI_WORD_5[7:0]
0
0
B1
0
1
1
0
0
0
0
0
Checksum
0
0
ID2 (User Data-Word 3)
VDP_TTXT_TYPE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
ID3 (User Data-Word 4)
ID4 (User Data-Word 5)
ID5 (User Data-Word 6)
ID6 (User Data-Word 7)
ID7 (User Data-Word 8)
ID8 (User Data-Word 9)
Pad 0x200; these
padding words may be
present, depending on
ancillary data type; user
data-word
0
0
0
0
0
0
0
0
0
0
CS (checksum word)
This mode does not fully comply with ITU-R BT.1364.
Structure of VBI Words in the Ancillary Data Stream
Each VBI data standard has been split into a clock-run-in
(CRI), a framing code (FC), and a number of data bytes (n).
The data packet in the ancillary stream includes only the FC
and data bytes. Table 76 shows the format of VBI_WORD_x in
the ancillary data stream.
Table 76. Structure of VBI Data-Words in the Ancillary Stream
Ancillary Data Byte No.
VBI_WORD_1
VBI_WORD_2
VBI_WORD_3
VBI_WORD_4
…
VBI_WORD_N + 3
Byte Type
FC0
FC1
FC2
DB1
…
DBn
Description
Framing Code[23:16]
Framing Code[15:8]
Framing Code[7:0]
First data byte
…
Last (nth) data byte
Table 77 shows the framing code and its valid length for VBI
data standards supported by VDP.
Example
For teletext (B-WST), the framing code byte is 11100100 (0xE4),
with bits shown in the order of transmission. VBI_WORD_1 =
0x27, VBI_WORD_2 = 0x00, and VBI_WORD_3 = 0x00
translated into UDWs in the ancillary data stream for nibble
mode are as follows:
UDW5[5:2] = 0010
UDW6[5:2] = 0111
UDW7[5:2] = 0000 (undefined bits set to 0)
UDW8[5:2] = 0000 (undefined bits set to 0)
UDW9[5:2] = 0000 (undefined bits set to 0)
UDW10[5:2] = 0000 (undefined bits set to 0)
VDP Framing Code
The length of the actual framing code depends on the VBI data
standard. For uniformity, the length of the framing code reported
in the ancillary data stream is always 24 bits. For standards with
a smaller framing code length, the extra LSB bits are set to 0.
The valid length of the framing code can be decoded from the
VBI_DATA_STD bits available in ID0 (UDW 1). The framing
code is always reported in the inverse-transmission order.
For byte mode,
Rev. J | Page 59 of 114
UDW5[9:2] = 0010_0111
UDW6[9:2] = 0000_0000 (undefined bits set to 0)
UDW7[9:2] = 0000_0000 (undefined bits set to 0)
ADV7180
Data Sheet
Data Bytes
The data bytes in the ancillary data stream are as follows:
VBI_WORD_4 to VBI_WORD_N + 3 contain the data-words
that were decoded by the VDP in the transmission order. The
position of bits in bytes is in the inverse transmission order.
For example, closed captioning has two user data bytes, as
shown in Table 82.
VBI_WORD_4 = Byte 1[7:0]
VBI_WORD_5 = Byte 2[7:0]
The number of VBI_WORDS for each VBI data standard and
the total number of UDWs in the ancillary data stream is shown
in Table 78.
Table 77. Framing Code Sequence for Different VBI Standards
VBI Standard
TTXT_SYSTEM_A (PAL)
TTXT_SYSTEM_B (PAL)
TTXT_SYSTEM_B (NTSC)
TTXT_SYSTEM_C (PAL and NTSC)
TTXT_SYSTEM_D (PAL and NTSC)
VPS (PAL)
VITC (NTSC and PAL)
WSS (PAL)
GEMSTAR_1× (NTSC)
GEMSTAR_2× (NTSC)
CCAP (NTSC and PAL)
CGMS (NTSC)
Length in Bits
8
8
8
8
8
16
1
24
3
11
3
1
Error-Free Framing Code Bits
(in Order of Transmission)
11100111
11100100
11100100
11100111
11100101
10001010100011001
0
000111100011110000011111
001
1001_1011_101
001
0
Error-Free Framing Code Reported by
VDP (in Reverse Order of Transmission)
11100111
00100111
00100111
11100111
10100111
1001100101010001
0
111110000011110001111000
100
101_1101_1001
100
0
Table 78. Total User Data-Words for Different VBI Standards1
VBI Standard
TTXT_SYSTEM_A (PAL)
ADF Mode
00 (nibble mode)
01, 10 (byte mode)
TTXT_SYSTEM_B (PAL)
00 (nibble mode)
01, 10 (byte mode)
TTXT_SYSTEM_B (NTSC)
00 (nibble mode)
01, 10 (byte mode)
TTXT_SYSTEM_C (PAL and NTSC) 00 (nibble mode)
01, 10 (byte mode)
00 (nibble mode)
TTXT_SYSTEM_D (PAL and
NTSC)
01, 10 (byte mode)
VPS (PAL)
00 (nibble mode)
01, 10 (byte mode)
VITC (NTSC and PAL)
00 (nibble mode)
01, 10 (byte mode)
WSS (PAL)
00 (nibble mode)
01, 10 (byte mode)
GEMSTAR_1× (NTSC)
00 (nibble mode)
01, 10 (byte mode)
GEMSTAR_2× (NTSC)
00 (nibble mode)
01, 10 (byte mode)
CCAP (NTSC and PAL)
00 (nibble mode)
01, 10 (byte mode)
CGMS (NTSC)
00 (nibble mode)
01, 10 (byte mode)
1
Framing Code UDWs
6
3
6
3
6
3
6
3
6
VBI Data-Words
74
37
84
42
68
34
66
33
68
No. of Padding Words
0
0
2
3
2
3
0
2
2
Total UDWs
84
44
96
52
80
44
76
42
80
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
34
26
13
18
9
4
2
4
2
8
4
4
2
6
3+3
3
0
0
0
0
2
3
2
3
2
1
2
3
0
2
44
36
20
28
16
16
12
16
12
20
12
16
12
16
12
The first four UDWs are always the ID.
Rev. J | Page 60 of 114
Data Sheet
ADV7180
I2C Interface
Dedicated I C readback registers are available for CCAP, CGMS,
WSS, Gemstar, VPS, PDC/UTC, and VITC. Because teletext is a
high data rate standard, data extraction is supported only through
the ancillary data packet.
2
User Interface for I2C Readback Registers
The VDP decodes all enabled VBI data standards in real time.
Because the I2C access speed is much lower than the decoded
rate, when the registers are accessed, they may be updated with
data from the next line. To avoid this, VDP has a self-clearing
clear bit and an available (AVL) status bit accompanying all I2C
readback registers.
The user must clear the I2C readback register by writing a high to
the clear bit. This resets the state of the available bit to low and
indicates that the data in the associated readback registers is not
valid. After the VDP decodes the next line of the corresponding
VBI data, the decoded data is placed into the I2C readback
register and the available bit is set to high to indicate that valid
data is now available.
Though the VDP decodes this VBI data in subsequent lines if
present, the decoded data is not updated to the readback registers
until the clear bit is set high again. However, this data is
available through the 656 ancillary data packets.
The clear and available bits are in the VDP_STATUS_CLEAR
(Address 0x78, user sub map, write only) and VDP_STATUS
(Address 0x78, user sub map, read only) registers, respectively.
Example I C Readback Procedure
2
The following tasks must be performed to read one packet
(line) of PDC data from the decoder:
1.
2.
3.
4.
Write 10 to I2C_GS_VPS_PDC_UTC[1:0] (Address 0x9C,
user sub map) to specify that PDC data must be updated to
I2C registers.
Write high to the GS_PDC_VPS_UTC_CLEAR bit
(Address 0x78, user sub map) to enable I2C register
updating.
Poll the GS_PDC_VPS_UTC_AVL bit (Address 0x78, user
sub map) going high to check the availability of the PDC
packets.
Read the data bytes from the PDC I2C registers. Repeat
Step 1 to Step 3 to read another line or packet of data.
To read a packet of CCAP, CGMS, or WSS data, Step 1 to Step 3
are required only because they have dedicated registers.
Therefore, the available bit shows the availability of that standard
only when its content has changed.
Content-based updating also applies to lines with lost data.
Therefore, for standards like VPS, Gemstar, CGMS, and WSS, if no
data arrives in the next four lines programmed, the corresponding
available bit in the VDP_STATUS register is set high and the
content in the I2C registers for that standard is set to 0. The user
must write high to the corresponding clear bit so that when a
valid line is decoded after some time, the decoded results are
available in the I2C registers, with the available status bit set high.
If content-based updating is enabled, the available bit is set high
(assuming the clear bit was written) in the following cases:
•
•
•
GS_VPS_PDC_UTC_CB_CHANGE, Enable ContentBased Updating for Gemstar/VPS/PDC/UTC,
Address 0x9C[5], User Sub Map
Setting GS_VPS_PDC_UTC_CB_CHANGE to 0 disables
content-based updating.
Setting GS_VPS_PDC_UTC_CB_CHANGE to 1 (default)
enables content-based updating.
WSS_CGMS_CB_CHANGE, Enable Content-Based
Updating for WSS/CGMS, Address 0x9C[4],
User Sub Map
Setting WSS_CGMS_CB_CHANGE to 0 disables content-based
updating.
Setting WSS_CGMS_CB_CHANGE to 1 (default) enables
content-based updating.
VDP—Interrupt-Based Reading of VDP I2C Registers
Some VDP status bits are also linked to the interrupt request
controller so that the user does not have to poll the available status
bit. The user can configure the video decoder to trigger an
interrupt request on the INTRQ pin in response to the valid
data available in the I2C registers. This function is available for
the following data types:
•
VDP—Content-Based Data Update
For certain standards, such as WSS, CGMS, Gemstar, PDC, UTC,
and VPS, the information content in the signal transmitted remains
the same over numerous lines, and the user may want to be notified
only when there is a change in the information content or loss
of the information content. The user must enable content-based
updating for the required standard through the GS_VPS_PDC_
UTC_CB_CHANGE and WSS_CGMS_CB_CHANGE bits.
The data contents have changed.
Data was being decoded and four lines with no data have
been detected.
No data was being decoded and new data is now being
decoded.
•
Rev. J | Page 61 of 114
CGMS or WSS. The user can select either triggering an
interrupt request each time sliced data is available or
triggering an interrupt request only when the sliced data
has changed. Selection is made via the WSS_CGMS_CB_
CHANGE bit.
Gemstar, PDC, VPS, or UTC. The user can select to trigger
an interrupt request each time sliced data is available or to
trigger an interrupt request only when the sliced data has
changed. Selection is made via the GS_VPS_PDC_UTC_
CB_CHANGE bit.
ADV7180
Data Sheet
The sequence for the interrupt-based reading of the VDP I2C
data registers is as follows for the CCAP standard:
Setting VDP_VITC_MSK to 1 enables the interrupt on the
VDP_VITC_Q signal.
1.
Interrupt Status Register Details
2.
3.
4.
5.
6.
7.
The user unmasks the CCAP interrupt mask bit
(Register 0x50, Bit 0, user sub map = 1). CCAP data occurs
on the incoming video. VDP slices CCAP data and places it
into the VDP readback registers.
The VDP CCAP available bit CC_CAP goes high, and the
VDP module signals to the interrupt controller to stimulate
an interrupt request (for CCAP in this case).
The user reads the interrupt status bits (user sub map) and
sees that new CCAP data is available (Register 0x4E, Bit 0,
user sub map = 1).
The user writes 1 to the CCAP interrupt clear bit
(Register 0x4F, Bit 0, user sub map = 1) in the interrupt I2C
space (this is a self-clearing bit). This clears the interrupt
on the INTRQ pin but does not have an effect in the VDP I2C
area.
The user reads the CCAP data from the VDP I2C area.
The user writes to Bit CC_CLEAR in the
VDP_STATUS_CLEAR register, (Register 0x78, Bit 0,
user sub map = 1) to signify the CCAP data has been read
(therefore the VDP CCAP can be updated at the next
occurrence of CCAP).
The user goes back to Step 2.
The following read-only bits contain data detection information
from the VDP module since the status bit is last cleared or
unmasked.
VDP_CCAPD_Q, Address 0x4E[0], User Sub Map
When VDP_CCAPD_Q is 0 (default), CCAP data is not
detected.
When VDP_CCAPD_Q is 1, CCAP data is detected.
VDP_CGMS_WSS_CHNGD_Q, Address 0x4E[2],
User Sub Map
When VDP_CGMS_WSS_CHNGD_Q is 0 (default), CGMS or
WSS data is not detected.
When VDP_CGMS_WSS_CHNGD_Q is 1, CGM or WSS data
is detected.
VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E[4],
User Sub Map
When VDP_GS_VPS_PDC_UTC_CHNG_Q is 0 (default),
Gemstar, PDC, UTC, or VPS data is not detected.
Interrupt Mask Register Details
When VDP_GS_VPS_PDC_UTC_CHNG_Q is 1, Gemstar,
PDC, UTC, or VPS data is detected.
The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.
VDP_VITC_Q, Address 0x4E[6], User Sub Map,
Read Only
VDP_CCAPD_MSK, Address 0x50[0], User Sub Map
When VDP_VITC_Q is 0 (default), VITC data is not detected.
Setting VDP_CCAPD_MSK to 0 (default) disables the interrupt
on the VDP_CCAPD_Q signal.
When VDP_VITC_Q is 1, VITC data is detected.
Setting VDP_CCAPD_MSK to 1 enables the interrupt on the
VDP_CCAPD_Q signal.
It is not necessary to write 0 to these write-only bits because
they automatically reset after they are set to 1 (self-clearing).
VDP_CGMS_WSS_CHNGD_MSK, Address 0x50[2], User
Sub Map
VDP_CCAPD_CLR, Address 0x4F[0], User Sub Map
Setting VDP_CGMS_WSS_CHNGD_MSK to 0 (default) disables
the interrupt on the VDP_CGMS_WSS_ CHNGD_Q signal.
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F[2],
User Sub Map
Setting VDP_CGMS_WSS_CHNGD_MSK to 1 enables the
interrupt on the VDP_CGMS_WSS_CHNGD_Q signal.
Interrupt Status Clear Register Details
Setting VDP_CCAPD_CLR to 1 clears the VDP_CCAP_Q bit.
Setting VDP_CGMS_WSS_CHNGD_CLR to 1 clears the
VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_MSK,
Address 0x50[4], User Sub Map
VDP_GS_VPS_PDC_UTC_CHNG_CLR,
Address 0x4F[4], User Sub Map
Setting VDP_GS_VPS_PDC_UTC_CHNG_MSK to 0 (default)
disables the interrupt on the
VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
Setting VDP_GS_VPS_PDC_UTC_CHNG_CLR to 1 clears the
VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
Setting VDP_GS_VPS_PDC_UTC_CHNG_MSK to 1 enables
the interrupt on the VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
Setting VDP_VITC_CLR to 1 clears the VDP_VITC_Q bit.
VDP_VITC_CLR, Address 0x4F[6], User Sub Map
VDP_VITC_MSK, Address 0x50[6], User Sub Map
Setting VDP_VITC_MSK to 0 (default) disables the interrupt
on the VDP_VITC_Q signal.
Rev. J | Page 62 of 114
Data Sheet
ADV7180
WST_PKT_DECODE_DISABLE, Disable Hamming
Decoding of Bytes in WST, Address 0x60[3], User Sub Map
I2C READBACK REGISTERS
Teletext
Because teletext is a high data rate standard, the decoded bytes
are available only as ancillary data. However, a TTXT_AVL bit
is provided in I2C so that the user can check whether the VDP
detects teletext. Note that the TTXT_AVL bit is a plain status
bit and does not use the protocol identified in the I2C Interface
section.
TTXT_AVL, Teletext Detected Status, Address 0x78[7],
User Sub Map, Read Only
When TTXT_AVL is 0, teletext is not detected.
Setting WST_PKT_DECODE_DISABLE to 0 enables hamming
decoding of WST packets.
Setting WST_PKT_DECODE_DISABLE to 1 (default) disables
hamming decoding of WST packets.
For hamming-coded bytes, the dehammed nibbles are output
along with some error information from the hamming decoder
as follows:
•
Input hamming coded byte: {D3, P3, D2, P2, D1, P1, D0, P0}
(bits in decoded order)
Output dehammed byte: {E1, E0, 0, 0, D3', D2', D1', D0'}
(Di' – corrected bits, Ei error information).
•
When TTXT_AVL is 1, teletext is detected.
WST Packet Decoding
For WST only, the VDP decodes the magazine and row address
of teletext packets and further decodes 8 × 4 hamming coded
words of the packet. This feature can be disabled using the
WST_PKT_DECODE_DISABLE bit (Bit 3, Register 0x60, user
sub map). This feature is valid for WST only.
Table 79. Error Bits in the Dehammed Output Byte
E[1:0]
00
01
10
11
Error Information
No errors detected
Error in P4
Double error
Single error found and corrected
Output Data Bits
in Nibble
Okay
Okay
Bad
Okay
Table 80 describes the WST packets that are decoded.
Table 80. WST Packet Description
Packet
Header Packet (X/00)
Text Packets (X/01 to X/25)
8/30 (Format 1) Packet
Design Code = 0000 or 0001
UTC
8/30 (Format 2) Packet
Design Code = 0010 or 0011
PDC
X/26, X/27, X/28, X/29, X/30, X/311
1
Byte
1st
2nd
3rd
4th
5th to 10th
11th to 42nd
1st
2nd
3rd to 42nd
1st
2nd
3rd
4th to 10th
11th to 23rd
24th to 42nd
1st
2nd
3rd
4th to 10th
11th to 23rd
24th to 42nd
1st
2nd
3rd
4th to 42nd
Description
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Page number—Dehammed Byte 6
Page number—Dehammed Byte 7
Control bytes—Dehammed Byte 8 to Byte 13
Raw data bytes
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Raw data bytes
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
Dehammed initial teletext page, Byte 7 to Byte 12
UTC bytes—Dehammed Byte 13 to Byte 25
Raw status bytes
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
Dehammed initial teletext page, Byte 7 to Byte 12
PDC bytes—Dehammed Byte 13 to Byte 25
Raw status bytes
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
Raw data bytes
For X/26, X/28, and X/29, further decoding needs 24 × 18 hamming decoding. Not supported at present.
Rev. J | Page 63 of 114
ADV7180
Data Sheet
CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78[2],
User Sub Map, Read Only
CGMS and WSS
283B
123B
The CGMS and WSS data packets convey the same type of
information for different video standards. WSS is for PAL and
CGMS is for NTSC; therefore, the CGMS and WSS readback
registers are shared. WSS is biphase coded; the VDP performs a
biphase decoding to produce the 14 raw WSS bits in the CGMS/
WSS readback I2C registers and to set the CGMS_WSS_AVL bit.
When CGMS_WSS_AVL is 0, CGMS/WSS is not detected.
When CGMS_WSS_AVL is 1, CGMS/WSS is detected.
VDP_CGMS_WSS_DATA_0[3:0], Address 0x7D[3:0];
284B
VDP_CGMS_WSS_DATA_1[7:0], Address 0x7E[7:0];
285B
VDP_CGMS_WSS_DATA_2[7:0], Address 0x7F[7:0];
User Sub Map, Read Only
CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78[2],
User Sub Map, Write Only, Self-Clearing
286B
28B
These bits hold the decoded CGMS or WSS data.
Setting CGMS_WSS_CLEAR to 1 reinitializes the CGMS/WSS
readback registers.
Refer to Figure 48 and Figure 49 for the I2C-to-WSS and I2C-toCGMS bit mapping.
VDP_CGMS_WSS_
DATA_1[5:0]
VDP_CGMS_WSS_DATA_2
0
RUN-IN
SEQUENCE
1
2
3
4
5
6
7
0
1
2
3
4
5
START
CODE
ACTIVE
VIDEO
11.0µs
05700-039
38.4µs
42.5µs
Figure 48. WSS Waveform
+100 IRE
REF
+70 IRE
VDP_CGMS_WSS_DATA_2
0
1
2
3
4
5
6
VDP_CGMS_WSS_
DATA_0[3:0]
VDP_CGMS_WSS_DATA_1
7
0
1
2
3
4
5
6
7
0
1
2
3
0 IRE
11.2µs
CRC SEQUENCE
2.235µs ± 20ns
05700-040
49.1µs ± 0.5µs
–40 IRE
Figure 49. CGMS Waveform
Table 81. CGMS Readback Registers1
Signal Name
CGMS_WSS_DATA_0[3:0]
CGMS_WSS_DATA_1[7:0]
CGMS_WSS_DATA_2[7:0]
1
Register Location
VDP_CGMS_WSS_DATA_0[3:0]
VDP_CGMS_WSS_DATA_1[7:0]
VDP_CGMS_WSS_DATA_2[7:0]
These registers are readback registers; default value does not apply.
Rev. J | Page 64 of 114
125
126
127
Address (User Sub Map)
0x7D
0x7E
0x7F
Data Sheet
ADV7180
CCAP
Two bytes of decoded closed caption data are available in the
I2C registers. The field information of the decoded CCAP data
can be obtained from the CC_EVEN_FIELD bit (Register 0x78).
CC_CLEAR, Closed Caption Clear, Address 0x78[0],
User Sub Map, Write Only, Self-Clearing
CC_EVEN_FIELD, Address 0x78[1], User Sub Map,
Read Only
Identifies the field from which the CCAP data is decoded.
When CC_EVEN_FIELD is 0, closed captioning is detected
from an odd field.
When CC_EVEN_FIELD is 1, closed captioning is detected
from an even field.
Setting CC_CLEAR to 1 reinitializes the CCAP readback
registers.
VDP_CCAP_DATA_0, Address 0x79[7:0], User Sub Map,
Read Only
CC_AVL, Closed Caption Available, Address 0x78[0],
User Sub Map, Read Only
Decoded Byte 1 of CCAP data.
When CC_AVL is 0, closed captioning is not detected.
VDP_CCAP_DATA_1, Address 0x7A[7:0], User Sub Map,
Read Only
When CC_AVL is 1, closed captioning is detected.
Decoded Byte 2 of CCAP data.
10.5 ± 0.25µs
12.91µs
7 CYCLES
OF 0.5035MHz
(CLOCK RUN-IN)
50 IRE
40 IRE
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
P
A
R
I
T
Y
VDP_CCAP_D ATA_0
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = fSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003µs
27.382µs
P
A
R
I
T
Y
VDP_CCAP_D ATA_1
05700-041
S
T
A
R
T
33.764µs
Figure 50. CCAP Waveform and Decoded Data Correlation
Table 82. CCAP Readback Registers1
Signal Name
CCAP_BYTE_1[7:0]
CCAP_BYTE_2[7:0]
1
Register Location
VDP_CCAP_DATA_0[7:0]
VDP_CCAP_DATA_1[7:0]
These registers are readback registers; default value does not apply.
Rev. J | Page 65 of 114
121
122
Address (User Sub Map)
0x79
0x7A
ADV7180
Data Sheet
VITC
VITC_CLEAR, VITC Clear, Address 0x78[6],
User Sub Map, Write Only, Self-Clearing
VITC has a sequence of 10 syncs between each data byte. The
VDP strips these syncs from the data stream to output only the
data bytes. The VITC results are available in Register VDP_VITC_
DATA_0 to Register VDP_VITC_DATA_8 (Register 0x92 to
Register 0x9A, user sub map).
Setting VITC_CLEAR to 1 reinitializes the VITC readback
registers.
VITC_AVL, VITC Available, Address 0x78[6],
User Sub Map, Read Only
The VITC has a CRC byte at the end; the syncs in between each
data byte are also used in this CRC calculation. Because the syncs
in between each data byte are not output, the CRC is calculated
internally. The calculated CRC is available for the user in the
VDP_VITC_CALC_CRC register (Resister 0x9B, user sub
map). When the VDP completes decoding the VITC line, the
VITC_DATA_x and VITC_CRC registers are updated and the
VITC_AVL bit is set.
When VITC_AVL is 0, VITC data is not detected.
When VITC_AVL is 1, VITC data is detected.
VITC Readback Registers
TO
BIT 0, BIT 1
BIT 88, BIT 89
VITC WAVEFORM
05700-042
See Figure 51 for the I2C-to-VITC bit mapping.
Figure 51. VITC Waveform and Decoded Data Correlation
Table 83. VITC Readback Registers1
Signal Name
VITC_DATA_0[7:0]
VITC_DATA_1[7:0]
VITC_DATA_2[7:0]
VITC_DATA_3[7:0]
VITC_DATA_4[7:0]
VITC_DATA_5[7:0]
VITC_DATA_6[7:0]
VITC_DATA_7[7:0]
VITC_DATA_8[7:0]
VITC_CRC[7:0]
1
Register Location
VDP_VITC_DATA_0[7:0] (VITC Bits[9:2])
VDP_VITC_DATA_1[7:0] (VITC Bits[19:12])
VDP_VITC_DATA_2[7:0] (VITC Bits[29:22])
VDP_VITC_DATA_3[7:0] (VITC Bits[39:32])
VDP_VITC_DATA_4[7:0] (VITC Bits[49:42])
VDP_VITC_DATA_5[7:0] (VITC Bits[59:52])
VDP_VITC_DATA_6[7:0] (VITC Bits[69:62])
VDP_VITC_DATA_7[7:0] (VITC Bits[79:72])
VDP_VITC_DATA_8[7:0] (VITC Bits[89:82])
VDP_VITC_CALC_CRC[7:0]
These registers are readback registers; default value does not apply.
Rev. J | Page 66 of 114
Address (User Sub Map)
146
0x92
147
0x93
148
0x94
149
0x95
150
0x96
151
0x97
152
0x98
153
0x99
154
0x9A
155
0x9B
Data Sheet
ADV7180
VPS/PDC/UTC/GEMSTAR
The readback registers for VPS, PDC, and UTC are shared.
Gemstar is a high data rate standard and is available only through
the ancillary stream. However, for evaluation purposes, any one
line of Gemstar is available through the I2C registers sharing the
same register space as PDC, UTC, and VPS. Therefore, only VPS,
PDC, UTC, or Gemstar can be read through the I2C at one time.
To identify the data that should be made available in the I2C
registers, the user must program I2C_GS_VPS_PDC_UTC[1:0]
(Register Address 0x9C, user sub map).
I C_GS_VPS_PDC_UTC[1:0] (VDP), Address 0x9C[7:6],
User Sub Map
2
Specifies which standard result is available for I C readback.
2
VDP supports autodetection of the Gemstar standard, either
Gemstar 1× or Gemstar 2×, and decodes accordingly. For the
autodetection mode to work, the user must set the AUTO_
DETECT_GS_TYPE bit (Register 0x61, user sub map) and
program the decoder to decode Gemstar 2× on the required lines
through line programming. The type of Gemstar decoded can
be determined by observing the GS_DATA_TYPE bit
(Register 0x78, user sub map).
AUTO_DETECT_GS_TYPE, Address 0x61[4], User Sub Map
Setting AUTO_DETECT_GS_TYPE to 0 (default) disables the
autodetection of the Gemstar type.
Setting AUTO_DETECT_GS_TYPE to 1 enables the
autodetection of the Gemstar type.
GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear,
Address 0x78[4], User Sub Map, Write Only, Self-Clearing
GS_DATA_TYPE, Address 0x78[5], User Sub Map, Read Only
Setting GS_PDC_VPS_UTC_CLEAR to 1 reinitializes the
GS/PDC/VPS/UTC data readback registers.
When GS_DATA_TYPE is 0, Gemstar 1× mode is detected.
Read two data bytes from Register 0x84.
GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available,
Address 0x78[4], User Sub Map, Read Only
When GS_DATA_TYPE is 1, Gemstar 2× mode is detected.
Read four data bytes from Register 0x84.
When GS_PDC_VPS_UTC_AVL is 0, no GS, PDC, VPS, or
UTC data is detected.
The Gemstar data that is available in the I2C register can be
from any line of the input video on which Gemstar was decoded.
To read the Gemstar data on a particular video line, the user
should use the manual configuration described in Table 70 and
Table 71 and enable Gemstar decoding only on the required line.
When GS_PDC_VPS_UTC_AVL is 1, one GS, PDC, VPS, or
UTC data is detected.
VDP_GS_VPS_PDC_UTC, Readback Registers,
Address 0x84 to Address 0x90
Identifies the decoded Gemstar data type.
PDC/UTC
See Table 85 for information on the readback registers.
VPS
The VPS data bits are biphase decoded by the VDP. The decoded
data is available in both the ancillary stream and in the I2C
readback registers. VPS decoded data is available in the
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers (Address 0x84 to Address 0x90, user sub map). The
GS_PDC_VPS_UTC_AVL bit is set if the user programmed
I2C_GS_VPS_PDC_UTC to 01, as explained in Table 84.
Gemstar
The Gemstar-decoded data is made available in the ancillary
stream, and any one line of Gemstar is also available in the I2C
registers for evaluation purposes. To read Gemstar results
through the I2C registers, the user must program
I2C_GS_VPS_PDC_UTC to 00, as explained in Table 84.
PDC and UTC are data transmitted through Teletext Packet 8/30
Format 2 (Magazine 8, Row 30, Design Code 2 or Design Code 3)
and Packet 8/30 Format 1 (Magazine 8, Row 30, Design Code 0
or Design Code 1). Therefore, if PDC or UTC data is to be read
through I2C, the corresponding teletext standard (WST or PAL
System B) should be decoded by VDP. The whole teletext
decoded packet is output on the ancillary data stream. The user
can look for the magazine number, row number, and design
code and qualify the data as PDC, UTC, or neither of these.
If PDC/UTC packets are identified, Byte 0 to Byte 12 are updated
to the VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers, and the GS_PDC_VPS_UTC_AVL bit is set. The full
packet data is also available in the ancillary data format.
Note that the data available in the I2C register depends on the
status of the WST_PKT_DECODE_DISABLE bit (Bit 3,
Subaddress 0x60, user sub map).
Table 84. I2C_GS_VPS_PDC_UTC[1:0] Function
I2C_GS_VPS_PDC_UTC[1:0]
00 (default)
01
10
11
Description
Gemstar 1×/2×
VPS
PDC
UTC
Rev. J | Page 67 of 114
ADV7180
Data Sheet
Table 85. GS/VPS/PDC/UTC Readback Registers1
Signal Name
GS_VPS_PDC_UTC_BYTE_0[7:0]
GS_VPS_PDC_UTC_BYTE_1[7:0]
GS_VPS_PDC_UTC_BYTE_2[7:0]
GS_VPS_PDC_UTC_BYTE_3[7:0]
VPS_PDC_UTC_BYTE_4[7:0]
VPS_PDC_UTC_BYTE_5[7:0]
VPS_PDC_UTC_BYTE_6[7:0]
VPS_PDC_UTC_BYTE_7[7:0]
VPS_PDC_UTC_BYTE_8[7:0]
VPS_PDC_UTC_BYTE_9[7:0]
VPS_PDC_UTC_BYTE_10[7:0]
VPS_PDC_UTC_BYTE_11[7:0]
VPS_PDC_UTC_BYTE_12[7:0]
1
Register Location
VDP_GS_VPS_PDC_UTC_0[7:0]
VDP_GS_VPS_PDC_UTC_1[7:0]
VDP_GS_VPS_PDC_UTC_2[7:0]
VDP_GS_VPS_PDC_UTC_3[7:0]
VDP_VPS_PDC_UTC_4[7:0]
VDP_VPS_PDC_UTC_5[7:0]
VDP_VPS_PDC_UTC_6[7:0]
VDP_VPS_PDC_UTC_7[7:0]
VDP_VPS_PDC_UTC_8[7:0]
VDP_VPS_PDC_UTC_9[7:0]
VDP_VPS_PDC_UTC_10[7:0]
VDP_VPS_PDC_UTC_11[7:0]
VDP_VPS_PDC_UTC_12[7:0]
Dec Address (User Sub Map)
132
133
134
135
136
137
138
139
140
141
142
143
144
Hex Address (User Sub Map)
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
The default value does not apply to readback registers.
VBI System 2
GDE_SEL_OLD_ADF, Address 0x4C[3], User Sub Map
The user has an option of using a different VBI data slicer called
VBI System 2. This data slicer is used to decode Gemstar and
closed caption VBI signals only.
The ADV7180 has a new ancillary data output block that
can be used by the VDP data slicer and the VBI System 2
data slicer. The new ancillary data formatter is used by setting
GDE_SEL_OLD_ADF to 0 (default). See Table 74 and Table 75
for information about how the data is packaged in the ancillary
data stream when this bit is set low.
Using this system, the Gemstar data is available only in the
ancillary data stream. A special mode enables one line of data to
be read back through I2C.
Gemstar Data Recovery
The Gemstar-compatible data recovery block (GSCD) supports
1× and 2× data transmissions. In addition, it can serve as a closed
caption decoder. Gemstar-compatible data transmissions can
occur only in NTSC. Closed caption data can be decoded in
both PAL and NTSC.
The block can be configured via I2C as follows:
•
•
•
GDECEL[15:0] allows data recovery on selected video lines
on even fields to be enabled or disabled.
GDECOL[15:0] enables the data recovery on selected lines
for odd fields.
GDECAD[0] configures the way in which data is
embedded in the video data stream.
The recovered data is not available through I2C but is inserted into
the horizontal blanking period of an ITU-R BT.656-compatible
data stream. The data format is intended to comply with the
recommendation by the International Telecommunications
Union, ITU-R BT.1364. For more information, visit the
International Telecommunication Union website. See Figure 52.
To use the old ancillary data formatter (to be backward compatible
with the ADV7183B), set GDE_SEL_OLD_ADF to 1. The ancillary
data format in this section refers to the ADV7183B-compatible
ancillary data formatter.
Setting GDE_SEL_OLD_ADF to 0 (default) enables a new
ancillary data system for use with the VDP and VBI System 2.
Setting GDE_SEL_OLD_ADF to 1 enables the old ancillary
data system for use with the VBI System 2 only (ADV7183B
compatible).
The format of the data packet depends on the following criteria:
•
•
•
Transmission is 1× or 2×.
Data is output in 8-bit or 4-bit format (see the description
of the bit).
Data is closed caption (CCAP) or Gemstar compatible.
Data packets are output if the corresponding enable bit is set
(see the GDECEL[15:0], Gemstar Decoding Even Lines,
Address 0x48[7:0], Address 0x49[7:0] and the GDECOL[15:0],
Gemstar Decoding Odd Lines, Address 0x4A[7:0], Address
0x4B[7:0] sections), and the decoder detects the presence of
data. For video lines where no data is decoded, no data packet
is output, even if the corresponding line enable bit is set.
Rev. J | Page 68 of 114
Data Sheet
ADV7180

Each data packet starts immediately after the EAV code of the
preceding line. Figure 52 and Table 86 show the overall structure
of the data packet.


Entries within the packet are as follows:

Fixed preamble sequence of 0x00, 0xFF, and 0xFF.
DID. The value for the DID marking a Gemstar or CCAP
data packet is 0x140 (10-bit value).
SDID, which contains information about the video line
from which data was retrieved, whether the Gemstar
transmission was in 1× or 2× format, and whether it was
retrieved from an even or odd field.
DATA IDENTIFICATION
00
FF
FF
DID

Table 86 lists the values within a generic data packet that is
output by the ADV7180 in 8-bit format.
SECONDARY DATA IDENTIFICATION
SDID
DATA
COUNT
OPTIONAL PADDING
BYTES
USER DATA
PREAMBLE FOR ANCILLARY DATA
CHECK
SUM
05700-043


Data count byte, giving the number of user data-words that
follow.
User data section.
Optional padding to ensure that the length of the user
data-word section of a packet is a multiple of four bytes
(requirement as set in ITU-R BT.1364).
Checksum byte.
USER DATA (4 OR 8 WORDS)
Figure 52. Gemstar- and CCAP-Embedded Data Packet (Generic)
Table 86. Generic Data Output Packet
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
D[6]
0
1
1
1
2X
D[5]
0
1
1
0
D[4]
0
1
1
0
5
EP
EP
0
0
0
0
0
0
Data count (DC)
6
EP
EP
0
0
Word1[7:4]
0
0
7
EP
EP
0
0
Word1[3:0]
0
0
User data-words
User data-words
8
EP
EP
0
0
Word2[7:4]
0
0
User data-words
9
EP
EP
0
0
Word2[3:0]
0
0
User data-words
10
EP
EP
0
0
Word3[7:4]
0
0
User data-words
11
EP
EP
0
0
Word3[3:0]
0
0
User data-words
12
EP
EP
0
0
Word4[7:4]
0
0
User data-words
13
EP
EP
0
0
0
0
User data-words
14
CS[8]
CS[8]
CS[7]
CS[6]
Word4[3:0]
CS[4]
CS[3]
0
0
Checksum
E
CS[5]
D[3]
0
1
1
0
Line[3:0]
DC[1]
D[2]
0
1
1
0
DC[0]
CS[2]
D[1]
0
1
1
0
0
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Table 87. Data Byte Allocation
2×
1
1
0
0
Raw Information Bytes Retrieved from the Video Line
4
4
2
2
GDECAD
0
1
0
1
Rev. J | Page 69 of 114
User Data-Words
(Including Padding)
8
4
4
4
Padding Bytes
0
0
0
2
DC[1:0]
10
01
01
01
ADV7180
Data Sheet
Gemstar Bit Names
•
The following are the Gemstar bit names:
•
•
•
•
•
DID—The data identification value is 0x140 (10-bit value).
Care is taken so that in 8-bit systems, the two LSBs do not
carry vital information.
EP and EP—The EP bit is set to ensure even parity on the
D[8:0] data-word. Even parity means there is always an
even number of 1s within the D[8:0] bit arrangement. This
includes the EP bit. EP describes the logic inverse of EP
and is output on D[9]. The EP is output to ensure that the
reserved codes of 00 and FF do not occur.
EF—Even field identifier. EF = 1 indicates that the data was
recovered from a video line on an even field.
2×—This bit indicates whether the data sliced was in
Gemstar 1× or 2× format. A high indicates 2× format.
The 2× bit determines whether the raw information
retrieved from the video line was two bytes or four bytes.
The state of the GDECAD bit affects whether the bytes are
transmitted straight (that is, two bytes transmitted as two
bytes) or whether they are split into nibbles (that is, two
bytes transmitted as four half bytes). Padding bytes are
then added where necessary.
Line[3:0]—This entry provides a code that is unique for
each of the possible 16 source lines of video from which
Gemstar data may have been retrieved. Refer to Table 96
and Table 97.
•
DC[1:0]—Data count value. The number of UDWs in the
packet divided by 4. The number of UDWs in any packet
must be an integral number of 4. Padding may be required
at the end, as set in ITU-R BT.1364. See Table 87.
CS[8:2]—The checksum is provided to determine the
integrity of the ancillary data packet. It is calculated by
summing up D[8:2] of DID, SDID, the data count byte, and
all UDWs and ignoring any overflow during the summation.
Because all data bytes that are used to calculate the checksum
have their two LSBs set to 0, the CS[1:0] bits are also always 0.
CS[8]—describes the logic inversion of CS[8]. The value CS[8]
is included in the checksum entry of the data packet to ensure
that the reserved values of 0x00 and 0xFF do not occur. Table 88
to Table 91 outline the possible data packages.
Gemstar_2× Format, Half-Byte Output Mode
Half-byte output mode is selected by setting GDECAD to 0;
full-byte output mode is selected by setting GDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C[0] section.
Gemstar_1× Format
Half-byte output mode is selected by setting CDECAD to 0,
full-byte output mode is selected by setting CDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C[0] section.
Table 88. Gemstar_2× Data, Half-Byte Mode
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
D[6]
0
1
1
1
1
D[5]
0
1
1
0
D[4]
0
1
1
0
5
EP
EP
0
0
0
0
6
EP
EP
0
0
7
EP
EP
0
0
8
EP
EP
0
9
EP
EP
0
10
EP
EP
11
EP
12
EP
13
EP
EP
0
0
14
CS[8]
CS[8]
CS[7]
CS[6]
D[2]
0
1
1
0
D[1]
0
1
1
0
0
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
0
0
0
Data count
Gemstar Word1[7:4]
0
0
Gemstar Word1[3:0]
0
0
User data-words
User data-words
0
Gemstar Word2[7:4]
0
0
User data-words
0
Gemstar Word2[3:0]
0
0
User data-words
0
0
Gemstar Word3[7:4]
0
0
User data-words
EP
0
0
Gemstar Word3[3:0]
0
0
User data-words
EP
0
0
Gemstar Word4[7:4]
0
0
User data-words
Gemstar Word4[3:0]
CS[4]
CS[3]
CS[2]
0
0
User data-words
CS[1]
CS[0]
Checksum
CS[5]
D[3]
0
1
1
0
Line[3:0]
1
Rev. J | Page 70 of 114
Data Sheet
ADV7180
Table 89. Gemstar_2× Data, Full-Byte Mode
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
5
EP
EP
0
6
7
8
9
10
CS[8]
CS[8]
CS[7]
D[6]
0
1
1
1
1
D[5]
0
1
1
0
0
0
D[4]
D[3]
0
0
1
1
1
1
0
0
Line[3:0]
0
0
Gemstar Word1[7:0]
Gemstar Word2[7:0]
Gemstar Word3[7:0]
Gemstar Word4[7:0]
CS[6]
CS[5]
CS[4]
CS[3]
D[2]
0
1
1
0
D[1]
0
1
1
0
0
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
1
0
0
Data count
CS[2]
0
0
0
0
CS[1]
0
0
0
0
CS[0]
User data-words
User data-words
User data-words
User data-words
Checksum
Table 90. Gemstar_1× Data, Half-Byte Mode
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
D[6]
0
1
1
1
0
D[5]
0
1
1
0
5
EP
EP
0
0
0
6
EP
EP
0
0
Gemstar Word1[7:4]
7
EP
EP
0
0
8
EP
EP
0
0
9
EP
EP
0
0
10
CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
D[4]
0
1
1
0
D[2]
0
1
1
0
D[1]
0
1
1
0
0
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
1
0
0
Data count
0
0
Gemstar Word1[3:0]
0
0
User data-words
User data-words
Gemstar Word2[7:4]
0
0
User data-words
Gemstar Word2[3:0]
CS[4]
CS[3]
CS[2]
0
0
User data-words
CS[1]
CS[0]
Checksum
0
D[3]
0
1
1
0
Line[3:0]
0
Table 91. Gemstar_1× Data, Full-Byte Mode
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
5
EP
EP
0
6
7
8
9
10
1
1
CS[8]
0
0
CS[8]
0
0
CS[7]
D[6]
0
1
1
1
0
D[5]
0
1
1
0
D[4]
0
1
1
0
0
0
0
D[3]
0
1
1
0
Line[3:0]
0
Gemstar Word1[7:0]
Gemstar Word2[7:0]
0
0
0
0
0
0
CS[6]
CS[5]
CS[4]
0
0
CS[3]
Rev. J | Page 71 of 114
D[2]
0
1
1
0
D[1]
0
1
1
0
0
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
1
0
0
Data count
0
0
CS[2]
0
0
0
0
CS[1]
0
0
0
0
CS[0]
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
ADV7180
Data Sheet
Table 92. NTSC CCAP Data, Half-Byte Mode
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
D[6]
0
1
1
1
0
D[5]
0
1
1
0
1
D[4]
0
1
1
0
0
D[3]
0
1
1
0
1
D[2]
0
1
1
0
1
5
EP
EP
0
0
0
0
0
1
0
0
Data count
6
EP
EP
0
0
CCAP Word1[7:4]
0
0
7
EP
EP
0
0
CCAP Word1[3:0]
0
0
User data-words
User data-words
8
EP
EP
0
0
CCAP Word2[7:4]
0
0
User data-words
9
EP
EP
0
0
10
CS[8]
CS[8]
CS[7]
CS[6]
CCAP Word2[3:0]
CS[4]
CS[3]
CS[5]
D[1]
0
1
1
0
0
CS[2]
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
0
0
User data-words
CS[1]
CS[0]
Checksum
Table 93. NTSC CCAP Data, Full-Byte Mode
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
D[6]
0
1
1
1
0
D[5]
0
1
1
0
1
D[4]
0
1
1
0
0
D[3]
0
1
1
0
1
D[2]
0
1
1
0
1
5
EP
EP
0
0
0
0
0
1
0
0
Data count
0
0
CS[7]
CCAP Word1[7:0]
CCAP Word2[7:0]
0
0
0
0
CS[6]
CS[5]
0
0
CS[2]
0
0
0
0
CS[1]
0
0
0
0
CS[0]
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
6
7
8
9
10
1
1
CS[8]
0
0
CS[8]
0
0
CS[4]
0
0
CS[3]
Rev. J | Page 72 of 114
D[1]
0
1
1
0
0
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data Sheet
ADV7180
Table 94. PAL CCAP Data, Half-Byte Mode
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
D[6]
0
1
1
1
0
D[5]
0
1
1
0
1
D[4]
0
1
1
0
0
D[3]
0
1
1
0
1
D[2]
0
1
1
0
0
5
EP
EP
0
0
0
0
0
1
0
0
Data count
6
EP
EP
0
0
CCAP Word1[7:4]
0
0
7
EP
EP
0
0
CCAP Word1[3:0]
0
0
User data-words
User data-words
8
EP
EP
0
0
CCAP Word2[7:4]
0
0
User data-words
9
EP
EP
0
0
10
CS[8]
CS[8]
CS[7]
CS[6]
CCAP Word2[3:0]
CS[4]
CS[3]
CS[5]
D[1]
0
1
1
0
0
CS[2]
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
0
0
User data-words
CS[1]
CS[0]
Checksum
Table 95. PAL CCAP Data, Full-Byte Mode
Byte
0
1
2
3
4
D[9]
0
1
1
0
EP
D[8]
0
1
1
1
EP
D[7]
0
1
1
0
EF
D[6]
0
1
1
1
0
D[5]
0
1
1
0
1
D[4]
0
1
1
0
0
D[3]
0
1
1
0
1
D[2]
0
1
1
0
0
D[1]
0
1
1
0
0
D[0]
0
1
1
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
5
EP
EP
0
0
0
0
0
1
0
0
Data count
0
0
CS[7]
CCAP Word1[7:0]
CCAP Word2[7:0]
0
0
0
0
CS[6]
CS[5]
0
0
CS[2]
0
0
0
0
CS[1]
0
0
0
0
CS[0]
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
6
7
8
9
10
1
1
CS[8]
0
0
CS[8]
0
0
CS[4]
NTSC CCAP Data
Half-byte output mode is selected by setting GDECAD to 0, and
the full-byte mode is enabled by setting GDECAD to 1. See the
GDECAD, Gemstar Decode Ancillary Data Format, Address
0x4C[0] section. The data packet formats are shown in Table 92
and Table 93. Only closed caption data can be embedded in the
output data stream.
NTSC closed caption data is sliced on Line 21 of even and odd
fields. The corresponding enable bit must be set high. See the
GDECAD, Gemstar Decode Ancillary Data Format, Address
0x4C[0] section and the GDECOL[15:0], Gemstar Decoding
Odd Lines, Address 0x4A[7:0], Address 0x4B[7:0] section.
PAL CCAP Data
Half-byte output mode is selected by setting GDECAD to 0, and
full-byte output mode is selected by setting GDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C[0] section. Table 94 and Table 95 list the
bytes of the data packet.
Only closed caption data can be embedded in the output data
stream. PAL closed caption data is sliced from Line 22 and
Line 335. The corresponding enable bits must be set.
0
0
CS[3]
See the GDECEL[15:0], Gemstar Decoding Even Lines,
Address 0x48[7:0], Address 0x49[7:0] section and the
GDECOL[15:0], Gemstar Decoding Odd Lines,
Address 0x4A[7:0], Address 0x4B[7:0] section.
GDECEL[15:0], Gemstar Decoding Even Lines,
Address 0x48[7:0], Address 0x49[7:0]
The 16 bits of GDECEL[15:0] are interpreted as a collection of
16 individual line decode enable signals. Each bit refers to a line
of video in an even field. Setting the bit enables the decoder block
trying to find Gemstar or closed caption-compatible data on
that particular line. Setting the bit to 0 prevents the decoder
from trying to retrieve data. See Table 96 and Table 97.
To retrieve closed caption data services on NTSC (Line 284),
GDECEL[11] must be set.
To retrieve closed caption data services on PAL (Line 335),
GDECEL[14] must be set.
The default value of GDECEL[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the even field. Enable Gemstar
slicing only on lines where VBI data is expected.
Rev. J | Page 73 of 114
ADV7180
Data Sheet
Table 96. NTSC Line Enable Bits and Corresponding Line
Numbering
Line[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
Line Number
(ITU-R BT.470)
10
11
12
13
14
15
16
17
18
19
20
21
Enable Bit
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
22
23
24
25
273 (10)
274 (11)
275 (12)
276 (13)
277 (14)
278 (15)
279 (16)
280 (17)
281 (18)
282 (19)
283 (20)
284 (21)
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
12
13
14
15
285 (22)
286 (23)
287 (24)
288 (25)
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
Comment
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar or
closed caption
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar or
closed caption
Gemstar
Gemstar
Gemstar
Gemstar
GDECOL[15:0], Gemstar Decoding Odd Lines,
Address 0x4A[7:0], Address 0x4B[7:0]
The 16 bits of GDECOL[15:0] form a collection of 16 individual
line decode enable signals. See Table 96 and Table 97.
To retrieve closed caption data services on NTSC (Line 21),
GDECOL[11] must be set.
To retrieve closed caption data services on PAL (Line 22),
GDECOL[14] must be set.
The default value of GDECOL[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or CCAP
data from any line in the odd field. Enable Gemstar slicing only
on lines where VBI data is expected.
GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C[0]
The decoded data from Gemstar-compatible transmissions or
closed caption-compatible transmissions is inserted into the
horizontal blanking period of the respective line of video. A
potential problem can arise if the retrieved data bytes have a
value of 0x00 or 0xFF. In an ITU-R BT.656-compatible data
stream, these values are reserved and used only to form a fixed
preamble. The GDECAD bit allows the data to be inserted into
the horizontal blanking period in two ways:
•
•
Insert all data straight into the data stream, even the
reserved values of 0x00 and 0xFF, if they occur. This may
violate output data format specification ITU-R BT.1364.
Split all data into nibbles and insert the half-bytes over
double the number of cycles in a 4-bit format.
When GDECAD is 0 (default), the data is split into half-bytes
and inserted.
When GDECAD is 1, the data is output straight into the data
stream in 8-bit format.
Table 97. PAL Line Enable Bits and Line Numbering
Line[3:0]
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
Rev. J | Page 74 of 114
Line Number
(ITU-R BT.470)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
321 (8)
322 (9)
323 (10)
324 (11)
325 (12)
326 (13)
327 (14)
328 (15)
329 (16)
330 (17)
331 (18)
332 (19)
333 (20)
334 (21)
335 (22)
336 (23)
Enable Bit
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
Comment
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
Data Sheet
ADV7180
Letterbox Detection
There is a two-field delay in reporting any line count parameter.
Incoming video signals may conform to different aspect ratios
(16:9 wide screen or 4:3 standard). For certain transmissions in
the wide-screen format, a digital sequence (WSS) is transmitted
with the video signal. If a WSS sequence is provided, the aspect
ratio of the video can be derived from the digitally decoded bits
that WSS contains.
There is no letterbox detected bit. Read the LB_LCT[7:0] and
LB_LCB[7:0] register values to determine whether the letterboxtype video is present in the software.
In the absence of a WSS sequence, letterbox detection can be
used to find wide-screen signals. The detection algorithm examines
the active video content of lines at the start and end of a field. If
black lines are detected, this may indicate that the currently
shown picture is in wide-screen format.
The active video content (luminance magnitude) over a line of
video is summed together. At the end of a line, this accumulated
value is compared with a threshold, and a decision is made as to
whether or not a particular line is black. The threshold value
needed may depend on the type of input signal; some control is
provided via LB_TH[4:0].
Detection at the Start of a Field
The ADV7180 expects a section of at least six consecutive black
lines of video at the top of a field. After those lines are detected,
LB_LCT[7:0] reports the number of black lines that were actually
found. By default, the ADV7180 starts looking for those black
lines in sync with the beginning of active video, for example,
immediately after the last VBI video line. LB_SL[3:0] allows the
user to set the start of letterbox detection from the beginning of
a frame on a line-by-line basis. The detection window closes in
the middle of the field.
Detection at the End of a Field
The ADV7180 expects at least six continuous lines of black video
at the bottom of a field before reporting the number of lines
actually found via the LB_LCB[7:0] value. The activity window
for letterbox detection (end of field) starts in the middle of an
active field. Its end is programmable via LB_EL[3:0].
Detection at the Midrange
Some transmissions of wide-screen video include subtitles
within the lower black box. If the ADV7180 finds at least two
black lines followed by some more nonblack video, for example, the
subtitle followed by the remainder of the bottom black block, it
reports a midcount via LB_LCM[7:0]. If no subtitles are found,
LB_LCM[7:0] reports the same number as LB_LCB[7:0].
LB_LCT[7:0], Letterbox Line Count Top, Address 0x9B[7:0];
LB_LCM[7:0], Letterbox Line Count Mid, Address 0x9C[7:0];
LB_LCB[7:0], Letterbox Line Count Bottom, Address 0x9D[7:0]
Table 98. LB_LCx Access Information
Signal Name
LB_LCT[7:0]
LB_LCM[7:0]
LB_LCB[7:0]
Address
0x9B
0x9C
0x9D
LB_TH[4:0], Letterbox Threshold Control,
Address 0xDC[4:0]
Table 99. LB_TH Function
LB_TH[4:0]
01100 (default)
01101 to 10000
00000 to 01011
Description
Default threshold for detection of black lines
Increase threshold (need larger active video
content before identifying nonblack lines)
Decrease threshold (even small noise levels
can cause the detection of nonblack lines)
LB_SL[3:0], Letterbox Start Line, Address 0xDD[7:4]
The LB_SL[3:0] bits are set at 0100 by default. For an NTSC
signal, this window is from Line 23 to Line 286.
By changing the bits to 0101, the detection window starts on
Line 24 and ends on Line 287.
LB_EL[3:0], Letterbox End Line, Address 0xDD[3:0]
The LB_EL[3:0] bits are set at 1101 by default. This means that the
letterbox detection window ends with the last active video line.
For an NTSC signal, this window is from Line 262 to Line 525.
By changing the bits to 1100, the detection window starts on
Line 261 and ends on Line 254.
Rev. J | Page 75 of 114
ADV7180
Data Sheet
PIXEL PORT CONFIGURATION
The ADV7180 has a very flexible pixel port that can be configured
in a variety of formats to accommodate downstream ICs.
SWPC, Swap Pixel Cr/Cb, Address 0x27[7]
Table 100, Table 101, and Table 102 summarize the various
functions that the ADV7180 pins can have in different modes of
operation.
When SWPC is 0 (default), no swapping is allowed.
This bit allows Cr and Cb samples to be swapped.
When SWPC is 1, the Cr and Cb values can be swapped.
The ordering of components, for example, Cr vs. Cb for
Channel A, Channel B, and Channel C can be changed. See the
SWPC, Swap Pixel Cr/Cb, Address 0x27[7] section. Table 100
indicates the default positions for the Cr/Cb components.
LLC_PAD_SEL[2:0] LLC Output Selection,
Address 0x8F[6:4]
OF_SEL[3:0], Output Format Selection, Address 0x03[5:2]
The LLC signal is useful for LLC-compatible wide bus (16-bit)
output modes. See the OF_SEL[3:0], Output Format Selection,
Address 0x03[5:2] section for additional information. The LLC
signal and data on the data bus are synchronized. By default, the
rising edge of LLC/LLC is aligned with the Y data; the falling
edge occurs when the data bus holds C data. The polarity of the
clock, and therefore the Y/C assignments to the clock edges, can
be altered by using the polarity LLC pin.
The following I2C write allows the user to select between LLC
(nominally at 27 MHz) and LLC (nominally at 13.5 MHz).
The modes in which the ADV7180 pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 102 for details.
The default LLC frequency output on the LLC pin is approximately
27 MHz. For modes that operate with a nominal data rate of
13.5 MHz (0001, 0010), the clock frequency on the LLC pin stays
at the higher rate of 27 MHz. For information on outputting the
nominal 13.5 MHz clock on the LLC pin, see the
LLC_PAD_SEL[2:0] LLC Output Selection,
Address 0x8F[6:4] section.
When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC pin (default).
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC pin.
Table 100. 64-Lead LQFP P15 to P0 Output/Input Pin Mapping
Format and Mode
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
15
14
13
12
11
10
YCrCb[7:0]OUT
Y[7:0]OUT
Data Port Pins P[15:0]
9
8
7
6
5
4
3
2
1
0
CrCb[7:0]OUT
Table 101. 48-Lead, 40-Lead, and 32-Lead Devices P7 to P0 Output/Input Pin Mapping
Format and Mode
Video Out, 8-Bit, 4:2:2
7
6
5
Data Port Pins P[7:0]
4
3
YCrCb[7:0]OUT
2
1
Table 102. ADV7180 Standard Definition Pixel Port Modes
OF_SEL[3:0]
0000 to 0001
0010
0011 (default)
0100 to 1111
Format
Reserved
16-bit at LLC 4:2:2
8-bit at LLC 4:2:2 (default)
Reserved
64-Lead LQFP P[15:0]
P[15:8]
P[7:0]
Y[7:0]
YCrCb[7:0]
CrCb[7:0]
Three-state
Rev. J | Page 76 of 114
48-Lead LQFP, 40-Lead LFCSP, or 32-Lead LFCSP
P[7:0]
Reserved, do not use
Not valid
YCrCb[7:0]
Reserved, do not use
0
Data Sheet
ADV7180
GPO CONTROL
The 64-lead and 48-lead LQFP has four general-purpose
outputs (GPO). These outputs allow the user to control other
devices in a system via the I2C port of the device.
The 40-lead and 32-lead LFCSP do not have GPO pins.
GPO_ENABLE, General-Purpose Output Enable,
Address 0x59[4]
When GPO_ENABLE is set to 0, all GPO pins are three-stated.
When GPO_ENABLE is set to 1, all GPO pins are in a driven
state. The polarity output from each GPO is controlled by
GPO[3:0] for the 64-lead and 48-lead LQFP.
GPO[3:0], General-Purpose Outputs, Address 0x59[3:0]
Individual control of the four GPO ports is achieved using
GPO[3:0].
GPO_ENABLE must be set to 1 for the GPO pins to become active.
GPO[0]
When GPO[0] is set to 0, Logic 0 is output from the GPO0 pin.
When GPO[0] is set to 1, Logic 1 is output from the GPO0 pin.
Table 103. General-Purpose Output Truth Table
GPO_ENABLE
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPO[3:0]
XXXX1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
X indicates any value.
GPO[1]
When GPO[1] is set to 0, Logic 0 is output from the GPO1 pin.
When GPO[1] is set to 1, Logic 1 is output from the GPO1 pin.
GPO[2]
When GPO[2] is set to 0, Logic is output from the GPO2 pin.
When GPO[2] is set to 1, Logic 1 is output from the GPO2 pin.
GPO[3]
When GPO[3] is set to 0, Logic 0 is output from the GPO3 pin.
When GPO[3] is set to 1, Logic 1 is output from the GPO3 pin.
Rev. J | Page 77 of 114
GPO3
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
GPO2
Z
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
GPO1
Z
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
GPO0
Z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ADV7180
Data Sheet
MPU PORT DESCRIPTION
12B
The ADV7180 supports a 2-wire (I2C-compatible) serial interface.
Two inputs, serial data (SDATA) and serial clock (SCLK), carry
information between the ADV7180 and the system I2C master
controller. Each slave device is recognized by a unique address.
The ADV7180 I2C port allows the user to set up and configure
the decoder and to read back the captured VBI data. The ADV7180
has four possible slave addresses for both read and write operations,
depending on the logic level of the ALSB pin. The four unique
addresses are shown in Table 104. The ADV7180 ALSB pin
controls Bit 1 of the slave address. By altering the ALSB, it is
possible to control two ADV7180 devices in an application
without the conflict of using the same slave address. The LSB
(Bit 0) sets either a read or write operation. Logic 1 corresponds
to a read operation, and Logic 0 corresponds to a write operation.
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADV7180 acts as a standard slave device on the bus. The
data on the SDATA pin is eight bits long, supporting the 7-bit
address plus the R/W bit. The device has 249 subaddresses to
enable access to the internal registers. Therefore, it interprets
the first byte as the device address and the second byte as the
starting subaddress. The subaddresses auto-increment, allowing
data to be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one
basis without updating all the registers.
A
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCLK high period, the user
should only issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADV7180 does not
issue an acknowledge and returns to the idle condition.
Table 104. I2C Address for ADV7180
R/W
A
E
0
1
0
1
Slave Address
0x40
0x41
0x42
0x43
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establishing a
start condition, which is defined by a high-to-low transition on
SDATA while SCLK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/W bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse; this is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDATA and SCLK lines for the
start condition and the correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
In auto-increment mode, if the user exceeds the highest
subaddress, the following action is taken:

E
A
A

In read mode, the highest subaddress register contents
continue to be output until the master device issues a no
acknowledge. This indicates the end of a read. A no
acknowledge condition occurs when the SDATA line is
not pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register. A no acknowledge is issued by
the ADV7180, and the part returns to the idle condition.
E
A
A
SDATA
SCLK
S
1–7
8
9
1–7
8
9
1–7
START ADDR R/W ACK SUBADDRESS ACK
DATA
8
9
P
ACK
STOP
05700-044
Figure 53. Bus Data Transfer
WRITE
SEQUENCE
S SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
LSB = 0
READ
SEQUENCE
S SLAVE ADDR
S = START BIT
P = STOP BIT
A(S)
A(S)
DATA
A(S) P
LSB = 1
SUB ADDR
A(S) S
SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 54. Read and Write Sequence
Rev. J | Page 78 of 114
DATA
A(M) P
05700-045
ALSB
0
0
1
1
A
Data Sheet
ADV7180
REGISTER ACCESS
I2C SEQUENCER
The MPU can write to or read from all of the ADV7180 registers
except the subaddress register, which is write only. The subaddress
register determines which register the next read or write operation
accesses. All communications with the part through the bus start
with an access to the subaddress register. A read/write operation is
then performed from or to the target address, which increments
to the next address until a stop command on the bus is performed.
An I2C sequencer is used when a parameter exceeds eight bits
and is therefore distributed over two or more I2C registers, for
example, HSB[10:0].
REGISTER PROGRAMMING
The following sections describe the configuration for each
register. The communication register is an 8-bit, write-only
register. After the part is accessed over the bus and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to or from which register the operation
takes place. Table 105 lists the various operations under the
control of the subaddress register for the control port.
SUB_USR_EN, Address 0x0E[5]
When such a parameter is changed using two or more I2C write
operations, the parameter may hold an invalid value for the
time between the first I2C being completed and the last I2C
being completed. In other words, the top bits of the parameter
may hold the new value while the remaining bits of the parameter
still hold the previous value.
To avoid this problem, the I2C sequencer holds the updated bits
of the parameter in local memory, and all bits of the parameter
are updated together once the last register write operation has
completed.
The correct operation of the I2C sequencer relies on the following:
•
This bit splits the register map at Register 0x40.
USER MAP
USER SUB MAP
•
COMMON I2C SPACE
ADDRESS 0x00 ≥ 0x3F
ADDRESS 0x0E BIT 5 = 1b
I2C SPACE
ADDRESS 0x40 ≥ 0xFF
I2C SPACE
ADDRESS 0x40 ≥ 0x9C
NORMAL REGISTER SPACE
INTERRUPT AND VDP REGISTER SPACE
05700-050
ADDRESS 0x0E BIT 5 = 0b
Figure 55. Register Access—User Map and User Sub Map
Rev. J | Page 79 of 114
All I2C registers for the parameter in question must be
written to in order of ascending addresses. For example,
for HSB[10:0], write to Address 0x34 first, followed by
Address 0x35, and so on.
No other I2C can take place between the two (or more) I2C
writes for the sequence. For example, for HSB[10:0], write to
Address 0x34 first, immediately followed by Address 0x35,
and so on.
ADV7180
Data Sheet
I2C REGISTER MAPS
Table 105. Main Register Map Details (User Map)
Address
Reset
Dec Hex Register Name
RW 7
6
5
4
3
2
1
0
Value
0
00
RW VID_SEL[3]
VID_SEL[2]
VID_SEL[1]
VID_SEL[0]
INSEL[3]
INSEL[2]
INSEL[1]
INSEL[0]
00000000 00
1
01
Video selection
RW
ENHSPLL
BETACAM
ENVSPROC
SQPE
3
03
Output control
RW VBI_EN
TOD
OF_SEL[3]
OF_SEL[1]
OF_SEL[0]
4
04
Extended output control
RW BT.656-4
TIM_OE
BL_C_VBI
5
05
Reserved
6
06
Reserved
7
07
Autodetect enable
RW AD_SEC525_EN AD_SECAM_EN
AD_N443_EN
AD_P60_EN
AD_PALN_EN
8
08
Contrast
RW CON[7]
CON[6]
CON[5]
CON[4]
CON[3]
9
09
Reserved
10
0A
Brightness
RW BRI[7]
BRI[6]
BRI[5]
BRI[4]
11
0B
Hue
RW HUE[7]
HUE[6]
HUE[5]
HUE[4]
12
0C
Default Value Y
RW DEF_Y[5]
DEF_Y[4]
DEF_Y[3]
13
0D
Default Value C
RW DEF_C[7]
DEF_C[6]
DEF_C[5]
14
0E
ADI Control 1
RW
SUB_USR_EN
15
0F
Power management
RW Reset
PWRDWN
16
10
Status 1
R
COL_KILL
AD_RESULT[2]
AD_RESULT[1] AD_RESULT[0]
FOLLOW_PW
FSC_LOCK
LOST_LOCK
IN_LOCK
17
11
IDENT
R
IDENT[7]
IDENT[6]
IDENT[5]
IDENT[4]
IDENT[3]
IDENT[2]
IDENT[1]
IDENT[0]
18
12
Status 2
R
FSC NSTD
LL NSTD
MV AGC DET
MV PS DET
MVCS T3
MVCS DET
19
13
Status 3
R
STD FLD LEN
FREE_RUN_ACT Reserved
SD_OP_50Hz
GEMD
INST_HLOCK
20
14
Analog clamp control
RW
VCLEN
CCLEN
00010010 12
21
15
Digital Clamp Control 1
RW
DCT[1]
DCT[0]
DCFE
0000xxxx 00
22
16
Reserved
23
17
Shaping Filter Control 1
RW CSFM[2]
CSFM[1]
CSFM[0]
YSFM[4]
YSFM[3]
YSFM[2]
YSFM[1]
YSFM[0]
00000001 01
24
18
Shaping Filter Control 2
RW WYSFMOVR
WYSFM[4]
WYSFM[3]
WYSFM[2]
WYSFM[1]
WYSFM[0]
10010011 93
25
19
Comb filter control
RW
NSFSEL[1]
NSFSEL[0]
PSFSEL[1]
PSFSEL[0]
11110001 F1
29
1D
ADI Control 2
RW TRI_LLC
EN28XTAL
39
27
Pixel delay control
RW SWPC
AUTO_PDC_EN
LTA[1]
LTA[0]
01011000 58
43
2B
Misc gain control
RW
CKE
44
2C
AGC mode control
RW
LAGC[2]
45
2D
Chroma Gain Control 1
W
45
2D
Chroma Gain 1
R
46
2E
Chroma Gain Control 2
W
CMG[7]
CMG[6]
CMG[5]
46
2E
Chroma Gain 2
R
CG[7]
CG[6]
CG[5]
47
2F
Luma Gain Control 1
W
LAGT[1]
LAGT[0]
47
2F
Luma Gain 1
R
48
30
Luma Gain Control 2
W
LMG[7]
LMG[6]
LMG[5]
48
30
Luma Gain 2
R
LG[7]
LG[6]
LG[5]
49
31
VS/FIELD Control 1
RW
50
32
VS/FIELD Control 2
RW VSBHO
VSBHE
51
33
VS/FIELD Control 3
RW VSEHO
VSEHE
52
34
HS Position Control 1
RW
HSB[10]
HSB[9]
HSB[8]
53
35
HS Position Control 2
RW HSB[7]
HSB[6]
HSB[5]
HSB[4]
54
36
HS Position Control 3
RW HSE[7]
HSE[6]
HSE[5]
HSE[4]
55
37
Polarity
RW PHS
56
38
NTSC comb control
RW CTAPSN[1]
CTAPSN[0]
CCMN[2]
CCMN[1]
CCMN[0]
YCMN[2]
57
39
PAL comb control
RW CTAPSP[1]
CTAPSP[0]
CCMP[2]
CCMP[1]
CCMP[0]
58
3A
ADC control
RW
PWRDWN_MUX_0
61
3D
Manual window control
RW
CKILLTHR[2]
65
41
Resample control
RW
SFL_INV
72
48
Gemstar Control 1
RW GDECEL[15]
73
49
Gemstar Control 2
74
4A
Gemstar Control 3
75
4B
76
77
Input control
PAL_SW_LOCK Interlaced
CAGT[1]
OF_SEL[2]
(Hex)
11001000 C8
SD_DUP_AV
00001100 0C
EN_SFL_PIN
Range
01xx0101 45
AD_PALM_EN
AD_NTSC_EN
AD_PAL_EN
01111111 7F
CON[2]
CON[1]
CON[0]
10000000 80
BRI[3]
BRI[2]
BRI[1]
BRI[0]
00000000 00
HUE[3]
HUE[2]
HUE[1]
HUE[0]
00000000 00
DEF_Y[2]
DEF_Y[1]
DEF_Y[0]
DEF_VAL_
AUTO_EN
DEF_VAL_EN
00110110 36
DEF_C[4]
DEF_C[3]
DEF_C[2]
DEF_C[1]
DEF_C[0]
01111100 7C
00000000 00
PDBP
00000000 00
00011100 1C
01000xxx 40
CTA[2]
CTA[1]
LAGC[1]
LAGC[0]
CAGT[0]
CTA[0]
PW_UPD
11100001 E1
CAGC[1]
CAGC[0]
10101110 AE
11110100 F4
CMG[11]
CMG[10]
CMG[9]
CMG[8]
CG[11]
CG[10]
CG[9]
CG[8]
CMG[4]
CMG[3]
CMG[2]
CMG[1]
CMG[0]
CG[4]
CG[3]
CG[2]
CG[1]
CG[0]
LMG[11]
LMG[10]
LMG[9]
LMG[8]
LG[11]
LG[10]
LG[9]
LG[8]
LMG[4]
LMG[3]
LMG[2]
LMG[1]
LMG[0]
LG[4]
LG[3]
LG[2]
LG[1]
LG[0]
NEWAVMODE
HVSTIM
00000000 00
1111xxxx F0
xxxxxxxx 00
00010010 12
01000001 41
10000100 84
PVS
HSE[10]
HSE[9]
HSE[8]
00000000 00
HSB[3]
HSB[2]
HSB[1]
HSB[0]
00000010 02
HSE[3]
HSE[2]
HSE[1]
HSE[0]
00000000 00
PF
PCLK
00000001 01
YCMN[1]
YCMN[0]
10000000 80
YCMP[2]
YCMP[1]
YCMP[0]
11000000 C0
PWRDWN_MUX_1
PWRDWN_MUX_2 MUX PDN override 00010000 10
CKILLTHR[1]
CKILLTHR[0]
GDECEL[14]
GDECEL[13]
GDECEL[12]
GDECEL[11]
GDECEL[10]
GDECEL[9]
GDECEL[8]
00000000 00
RW GDECEL[7]
GDECEL[6]
GDECEL[5]
GDECEL[4]
GDECEL[3]
GDECEL[2]
GDECEL[1]
GDECEL[0]
00000000 00
RW GDECOL[15]
GDECOL[14]
GDECOL[13]
GDECOL[12]
GDECOL[11]
GDECOL[10]
GDECOL[9]
GDECOL[8]
00000000 00
Gemstar Control 4
RW GDECOL[7]
GDECOL[6]
GDECOL[5]
GDECOL[4]
GDECOL[3]
GDECOL[2]
GDECOL[1]
GDECOL[0]
00000000 00
4C
Gemstar Control 5
RW
GDECAD
xxxx0000 00
4D
CTI DNR Control 1
RW
CTI_AB[1]
CTI_AB[0]
CTI_AB_EN
CTI_EN
11101111 EF
78
4E
CTI DNR Control 2
RW CTI_C_TH[7]
CTI_C_TH[6]
CTI_C_TH[5]
CTI_C_TH[4]
CTI_C_TH[3]
CTI_C_TH[2]
CTI_C_TH[1]
CTI_C_TH[0]
00001000 08
80
50
CTI DNR Control 4
RW DNR_TH[7]
DNR_TH[6]
DNR_TH[5]
DNR_TH[4]
DNR_TH[3]
DNR_TH[2]
DNR_TH[1]
DNR_TH[0]
00001000 08
81
51
Lock count
RW FSCLE
SRLS
COL[2]
COL[1]
COL[0]
CIL[2]
CIL[1]
CIL[0]
00100100 24
82
52
CVBS_TRIM
RW
CVBS_IBIAS[3]
CVBS_IBIAS[2]
CVBS_IBIAS[1]
CVBS_IBIAS[0]
00001011 0B
88
58
VS/FIELD pin control1
RW
VS/FIELD
00000000 00
89
59
General-purpose outputs2 RW
GPO[0]
00000000 00
143 8F
Free-Run Line Length 1
W
153 99
CCAP 1
R
01110010 B2
00000001 01
GDE_SEL_OLD_ADF
DNR_EN
ADC sampling control
GPO_ENABLE
CCAP1[7]
LLC_PAD_SEL[2] LLC_PAD_
SEL[1]
LLC_PAD_
SEL[0]
CCAP1[6]
CCAP1[4]
CCAP1[5]
GPO[3]
GPO[2]
GPO[1]
00000000 00
CCAP1[3]
Rev. J | Page 80 of 114
CCAP1[2]
CCAP1[1]
CCAP1[0]
Data Sheet
ADV7180
Address
Reset
Dec Hex Register Name
RW 7
6
5
4
3
2
1
0
154 9A
CCAP 2
R
CCAP2[7]
CCAP2[6]
CCAP2[5]
CCAP2[4]
CCAP2[3]
CCAP2[2]
CCAP2[1]
CCAP2[0]
155 9B
Letterbox 1
R
LB_LCT[7]
LB_LCT[6]
LB_LCT[5]
LB_LCT[4]
LB_LCT[3]
LB_LCT[2]
LB_LCT[1]
LB_LCT[0]
156 9C
Letterbox 2
R
LB_LCM[7]
LB_LCM[6]
LB_LCM[5]
LB_LCM[4]
LB_LCM[3]
LB_LCM[2]
LB_LCM[1]
LB_LCM[0]
157 9D
Letterbox 3
R
LB_LCB[7]
LB_LCB[6]
LB_LCB[5]
LB_LCB[4]
LB_LCB[3]
LB_LCB[2]
LB_LCB[1]
LB_LCB[0]
178 B2
CRC enable
W
195 C3
ADC Switch 1
RW Reserved
196 C4
ADC Switch 2
RW MAN_MUX_EN
220 DC
Letterbox Control 1
RW
CRC_ENABLE
221 DD Letterbox Control 2
RW LB_SL[3]
222 DE
ST Noise Readback 1
R
223 DF
ST Noise Readback 2
R
224 E0
Reserved
225 E1
SD Offset Cb
226 E2
SD Offset Cr
227 E3
228 E4
LB_SL[2]
MUX1[1]
LB_SL[1]
MUX1[0]
(Hex)
00011100 1C
Reserved
MUX0[2]
MUX0[1]
MUX0[0]
xxxxxxxx 00
Reserved
MUX2[2]
MUX2[1]
MUX2[0]
0xxxxxxx 00
LB_TH[4]
LB_TH[3]
LB_TH[2]
LB_TH[1]
LB_TH[0]
10101100 AC
LB_SL[0]
LB_EL[3]
LB_EL[2]
LB_EL[1]
LB_EL[0]
01001100 4C
ST_NOISE_VLD
ST_NOISE[10]
ST_NOISE[9]
ST_NOISE[8]
ST_NOISE[3]
ST_NOISE[2]
ST_NOISE[1]
ST_NOISE[0]
ST_NOISE[6]
ST_NOISE[5]
RW SD_OFF_Cb[7]
SD_OFF_Cb[6]
SD_OFF_Cb[5] SD_OFF_Cb[4]
SD_OFF_Cb[3]
SD_OFF_Cb[2]
SD_OFF_Cb[1]
SD_OFF_Cb[0]
10000000 80
RW SD_OFF_Cr[7]
SD_OFF_Cr[6]
SD_OFF_Cr[5] SD_OFF_Cr[4]
SD_OFF_Cr[3]
SD_OFF_Cr[2]
SD_OFF_Cr[1]
SD_OFF_Cr[0]
10000000 80
SD Saturation Cb
RW SD_SAT_Cb[7]
SD_SAT_Cb[6]
SD_SAT_Cb[5] SD_SAT_Cb[4]
SD_SAT_Cb[3]
SD_SAT_Cb[2]
SD_SAT_Cb[1]
SD_SAT_Cb[0]
10000000 80
SD Saturation Cr
RW SD_SAT_Cr[7]
SD_SAT_Cr[6]
SD_SAT_Cr[5] SD_SAT_Cr[4]
SD_SAT_Cr[3]
SD_SAT_Cr[2]
SD_SAT_Cr[1]
SD_SAT_Cr[0]
10000000 80
229 E5
NTSC V bit begin
RW NVBEGDELO
NVBEGDELE
NVBEGSIGN
NVBEG[4]
NVBEG[3]
NVBEG[2]
NVBEG[1]
NVBEG[0]
00100101 25
230 E6
NTSC V bit end
RW NVENDDELO
NVENDDELE
NVENDSIGN
NVEND[4]
NVEND[3]
NVEND[2]
NVEND[1]
NVEND[0]
00000100 04
231 E7
NTSC F bit toggle
RW NFTOGDELO
NFTOGDELE
NFTOGSIGN
NFTOG[4]
NFTOG[3]
NFTOG[2]
NFTOG[1]
NFTOG[0]
01100011 63
232 E8
PAL V bit begin
RW PVBEGDELO
PVBEGDELE
PVBEGSIGN
PVBEG[4]
PVBEG[3]
PVBEG[2]
PVBEG[1]
PVBEG[0]
01100101 65
233 E9
PAL V bit end
RW PVENDDELO
PVENDDELE
PVENDSIGN
PVEND[4]
PVEND[3]
PVEND[2]
PVEND[1]
PVEND[0]
00010100 14
234 EA
PAL F bit toggle
RW PFTOGDELO
PFTOGDELE
PFTOGSIGN
PFTOG[4]
PFTOG[3]
PFTOG[2]
PFTOG[1]
PFTOG[0]
01100011 63
235 EB
Vblank Control 1
RW NVBIOLCM[1]
NVBIOLCM[0]
NVBIELCM[1]
NVBIELCM[0]
PVBIOLCM[1]
PVBIOLCM[0]
PVBIELCM[1]
PVBIELCM[0]
01010101 55
236 EC
Vblank Control 2
RW NVBIOCCM[1]
NVBIOCCM[0]
NVBIECCM[1]
NVBIECCM[0]
PVBIOCCM[1]
PVBIOCCM[0]
PVBIECCM[1]
PVBIECCM[0]
01010101 55
243 F3
AFE_CONTROL 1
RW
AA_FILT_
MAN_OVR
AA_FILT_EN[2]
AA_FILT_EN[1]
AA_FILT_EN[0]
00000000 00
244 F4
Drive strength
RW
DR_STR_C[1]
DR_STR_C[0]
DR_STR_S[1]
DR_STR_S[0]
xx010101 15
248 F8
IF comp control
RW
IFFILTSEL[2]
IFFILTSEL[1]
IFFILTSEL[0]
00000000 00
249 F9
VS mode control
RW
VS_COAST_
MODE[1]
VS_COAST_
MODE[0]
EXTEND_VS_
MIN_FREQ
EXTEND_VS_
MAX_FREQ
00000011 03
251 FB
Peaking control
RW PEAKING_
GAIN[7]
PEAKING_
GAIN[6]
PEAKING_
GAIN[5]
PEAKING_
GAIN[4]
PEAKING_
GAIN[3]
PEAKING_
GAIN[2]
PEAKING_
GAIN[1]
PEAKING_
GAIN[0]
01000000 40
252 FC
Coring threshold
RW DNR_TH2[7]
DNR_TH2[6]
DNR_TH2[5]
DNR_TH2[4]
DNR_TH2[3]
DNR_TH2[2]
DNR_TH2[1]
DNR_TH2[0]
00000100 04
1
2
ST_NOISE[7]
MUX1[2]
Value
DR_STR[1]
ST_NOISE[4]
DR_STR[0]
This feature applies to the 48-lead, 40-lead, and 32-lead LFCSP only because VS or FIELD is shared on a single pin.
This feature applies to the 64-lead and 48-lead LQFP only.
Rev. J | Page 81 of 114
ADV7180
Data Sheet
Table 106. Interrupt and VDP System Register Map Details (User Sub Map)1, 2
Address
Dec
Hex
Register Name
RW
7
6
5
4
64
40
Interrupt
Configuration 1
RW
INTRQ_DUR_
SEL[1]
INTRQ_DUR_
SEL[0]
MV_INTRQ_
SEL[1]
MV_INTRQ_
SEL[0]
66
42
Interrupt Status 1
R
MV_PS_CS_Q
SD_FR_CHNG_Q
SD_UNLOCK_Q
SD_LOCK_Q
67
43
Interrupt Clear 1
W
MV_PS_CS_CLR
SD_FR_CHNG_
CLR
SD_UNLOCK_
CLR
SD_LOCK_CLR
x0000000
00
68
44
Interrupt Mask 1
RW
MV_PS_CS_
MSKB
SD_FR_CHNG_
MSKB
SD_UNLOCK_
MSKB
SD_LOCK_MSKB x0000000
00
69
45
Raw Status 1
R
MPU_STIM_
INTRQ
EVEN_FIELD
70
46
Interrupt Status 2
R
MPU_STIM_
INTRQ_Q
SD_FIELD_
CHNGD_Q
GEMD_Q
CCAPD_Q
71
47
Interrupt Clear 2
W
MPU_STIM_
INTRQ_CLR
SD_FIELD_
CHNGD_CLR
GEMD_CLR
CCAPD_CLR
0xx00000
00
72
48
Interrupt Mask 2
RW
MPU_STIM_
INTRQ_MSKB
SD_FIELD_
CHNGD_MSKB
GEMD_MSKB
CCAPD_MSKB
0xx00000
00
73
49
Raw Status 2
R
SD_V_LOCK
SD_OP_50Hz
74
4A
Interrupt Status 3
R
PAL_SW_LK_
CHNG_Q
SCM_LOCK_
CHNG_Q
SD_AD_CHNG_Q SD_H_LOCK_
CHNG_Q
SD_V_LOCK_
CHNG_Q
SD_OP_CHNG_Q
75
4B
Interrupt Clear 3
W
PAL_SW_LK_
CHNG_CLR
SCM_LOCK_
CHNG_CLR
SD_AD_CHNG_
CLR
SD_H_LOCK_
CHNG_CLR
SD_V_LOCK_
CHNG_CLR
SD_OP_CHNG_
CLR
xx000000
00
76
4C
Interrupt Mask 3
RW
PAL_SW_LK_
CHNG_MSKB
SCM_LOCK_
CHNG_MSKB
SD_AD_CHNG_
MSKB
SD_H_LOCK_
CHNG_MSKB
SD_V_LOCK_
CHNG_MSKB
SD_OP_CHNG_
MSKB
xx000000
00
78
4E
Interrupt Status 4
R
VDP_VITC_Q
VDP_GS_VPS_
PDC_UTC_
CHNG_Q
VDP_CGMS_
WSS_CHNGD_Q
VDP_CCAPD_Q
79
4F
Interrupt Clear 4
W
VDP_VITC_CLR
VDP_GS_VPS_
PDC_UTC_
CHNG_CLR
VDP_CGMS_
WSS_CHNGD_
CLR
VDP_CCAPD_CLR 00x0x0x0
00
80
50
Interrupt Mask 4
RW
VDP_VITC_MSKB
VDP_GS_VPS_
PDC_UTC_
CHNG_MSKB
VDP_CGMS_
WSS_CHNGD_
MSKB
VDP_CCAPD_
MSKB
00x0x0x0
00
96
60
VDP_Config_1
RW
VDP_TTXT_
TYPE_MAN[0]
10001000
88
97
61
VDP_Config_2
RW
0001xx00
10
98
62
VDP_ADF_Config_1 RW
ADF_ENABLE
99
63
VDP_ADF_Config_2 RW
DUPLICATE_ADF
100
64
VDP_LINE_00E
RW
MAN_LINE_PGM
101
65
VDP_LINE_00F
RW
VBI_DATA_
P6_N23[3]
VBI_DATA_
P6_N23[2]
VBI_DATA_
P6_N23[1]
102
66
VDP_LINE_010
RW
VBI_DATA_
P7_N24[3]
VBI_DATA_
P7_N24[2]
103
67
VDP_LINE_011
RW
VBI_DATA_
P8_N25[3]
104
68
VDP_LINE_012
RW
105
69
VDP_LINE_013
106
6A
107
3
2
1
0
MPU_STIM_
INTRQ
INTRQ_OP_
SEL[1]
INTRQ_OP_SEL[0] 0001x000
10
CCAPD
SCM_LOCK
SD_H_LOCK
WST_PKT_
DECODE_
DISABLE
VDP_TTXT_
TYPE_MAN_
ENABLE
VDP_TTXT_
TYPE_MAN[1]
AUTO_DETECT_
GS_TYPE
ADF_MODE[1]
Reset Value (Hex)
ADF_MODE[0]
ADF_DID[4]
ADF_DID[3]
ADF_DID[2]
ADF_DID[1]
ADF_DID[0]
00010101
15
ADF_SDID[5]
ADF_SDID[4]
ADF_SDID[3]
ADF_SDID[2]
ADF_SDID[1]
ADF_SDID[0]
0x101010
2A
VBI_DATA_
P318[3]
VBI_DATA_
P318[2]
VBI_DATA_
P318[1]
VBI_DATA_
P318[0]
0xxx0000
00
VBI_DATA_
P6_N23[0]
VBI_DATA_
P319_N286[3]
VBI_DATA_
P319_N286[2]
VBI_DATA_
P319_N286[1]
VBI_DATA_
P319_N286[0]
00000000
00
VBI_DATA_
P7_N24[1]
VBI_DATA_
P7_N24[0]
VBI_DATA_
P320_N287[3]
VBI_DATA_
P320_N287[2]
VBI_DATA_
P320_N287[1]
VBI_DATA_
P320_N287[0]
00000000
00
VBI_DATA_
P8_N25[2]
VBI_DATA_
P8_N25[1]
VBI_DATA_
P8_N25[0]
VBI_DATA_
P321_N288[3]
VBI_DATA_
P321_N288[2]
VBI_DATA_
P321_N288[1]
VBI_DATA_
P321_N288[0]
00000000
00
VBI_DATA_
P9[3]
VBI_DATA_
P9[2]
VBI_DATA_
P9[1]
VBI_DATA_
P9[0]
VBI_DATA_
P322[3]
VBI_DATA_
P322[2]
VBI_DATA_
P322[1]
VBI_DATA_
P322[0]
00000000
00
RW
VBI_DATA_
P10[3]
VBI_DATA_
P10[2]
VBI_DATA_
P10[1]
VBI_DATA_
P10[0]
VBI_DATA_
P323[3]
VBI_DATA_
P323[2]
VBI_DATA_
P323[1]
VBI_DATA_
P323[0]
00000000
00
VDP_LINE_014
RW
VBI_DATA_
P11[3]
VBI_DATA_
P11[2]
VBI_DATA_
P11[1]
VBI_DATA_
P11[0]
VBI_DATA_
P324_N272[3]
VBI_DATA_
P324_N272[2]
VBI_DATA_
P324_N272[1]
VBI_DATA_
P324_N272[0]
00000000
00
6B
VDP_LINE_015
RW
VBI_DATA_
P12_N10[3]
VBI_DATA_
P12_N10[2]
VBI_DATA_
P12_N10[1]
VBI_DATA_
P12_N10[0]
VBI_DATA_
P325_N273[3]
VBI_DATA_
P325_N273[2]
VBI_DATA_
P325_N273[1]
VBI_DATA_
P325_N273[0]
00000000
00
108
6C
VDP_LINE_016
RW
VBI_DATA_
P13_N11[3]
VBI_DATA_
P13_N11[2]
VBI_DATA_
P13_N11[1]
VBI_DATA_
P13_N11[0]
VBI_DATA_
P326_N274[3]
VBI_DATA_
P326_N274[2]
VBI_DATA_
P326_N274[1]
VBI_DATA_
P326_N274[0]
00000000
00
109
6D
VDP_LINE_017
RW
VBI_DATA_
P14_N12[3]
VBI_DATA_
P14_N12[2]
VBI_DATA_
P14_N12[1]
VBI_DATA_
P14_N12[0]
VBI_DATA_
P327_N275[3]
VBI_DATA_
P327_N275[2]
VBI_DATA_
P327_N275[1]
VBI_DATA_
P327_N275[0]
00000000
00
110
6E
VDP_LINE_018
RW
VBI_DATA_
P15_N13[3]
VBI_DATA_
P15_N13[2]
VBI_DATA_
P15_N13[1]
VBI_DATA_
P15_N13[0]
VBI_DATA_
P328_N276[3]
VBI_DATA_
P328_N276[2]
VBI_DATA_
P328_N276[1]
VBI_DATA_
P328_N276[0]
00000000
00
111
6F
VDP_LINE_019
RW
VBI_DATA_
P16_N14[3]
VBI_DATA_
P16_N14[2]
VBI_DATA_
P16_N14[1]
VBI_DATA_
P16_N14[0]
VBI_DATA_
P329_N277[3]
VBI_DATA_
P329_N277[2]
VBI_DATA_
P329_N277[1]
VBI_DATA_
P329_N277[0]
00000000
00
112
70
VDP_LINE_01A
RW
VBI_DATA_
P17_N15[3]
VBI_DATA_
P17_N15[2]
VBI_DATA_
P17_N15[1]
VBI_DATA_
P17_N15[0]
VBI_DATA_
P330_N278[3]
VBI_DATA_
P330_N278[2]
VBI_DATA_
P330_N278[1]
VBI_DATA_
P330_N278[0]
00000000
00
113
71
VDP_LINE_01B
RW
VBI_DATA_
P18_N16[3]
VBI_DATA_
P18_N16[2]
VBI_DATA_
P18_N16[1]
VBI_DATA_
P18_N16[0]
VBI_DATA_
P331_N279[3]
VBI_DATA_
P331_N279[2]
VBI_DATA_
P331_N279[1]
VBI_DATA_
P331_N279[0]
00000000
00
114
72
VDP_LINE_01C
RW
VBI_DATA_
P19_N17[3]
VBI_DATA_
P19_N17[2]
VBI_DATA_
P19_N17[1]
VBI_DATA_
P19_N17[0]
VBI_DATA_
P332_N280[3]
VBI_DATA_
P332_N280[2]
VBI_DATA_
P332_N280[1]
VBI_DATA_
P332_N280[0]
00000000
00
115
73
VDP_LINE_01D
RW
VBI_DATA_
P20_N18[3]
VBI_DATA_
P20_N18[2]
VBI_DATA_
P20_N18[1]
VBI_DATA_
P20_N18[0]
VBI_DATA_
P333_N281[3]
VBI_DATA_
P333_N281[2]
VBI_DATA_
P333_N281[1]
VBI_DATA_
P333_N281[0]
00000000
00
116
74
VDP_LINE_01E
RW
VBI_DATA_
P21_N19[3]
VBI_DATA_
P21_N19[2]
VBI_DATA_
P21_N19[1]
VBI_DATA_
P21_N19[0]
VBI_DATA_
P334_N282[3]
VBI_DATA_
P334_N282[2]
VBI_DATA_
P334_N282[1]
VBI_DATA_
P334_N282[0]
00000000
00
117
75
VDP_LINE_01F
RW
VBI_DATA_
P22_N20[3]
VBI_DATA_
P22_N20[2]
VBI_DATA_
P22_N20[1]
VBI_DATA_
P22_N20[0]
VBI_DATA_
P335_N283[3]
VBI_DATA_
P335_N283[2]
VBI_DATA_
P335_N283[1]
VBI_DATA_
P335_N283[0]
00000000
00
Rev. J | Page 82 of 114
Data Sheet
ADV7180
Address
Dec
Hex
Register Name
RW
7
6
5
4
3
2
1
0
Reset Value (Hex)
118
76
VDP_LINE_020
RW
VBI_DATA_
P23_N21[3]
VBI_DATA_
P23_N21[2]
VBI_DATA_
P23_N21[1]
VBI_DATA_
P23_N21[0]
VBI_DATA_
P336_N284[3]
VBI_DATA_
P336_N284[2]
VBI_DATA_
P336_N284[1]
VBI_DATA_
P336_N284[0]
00000000
00
119
77
VDP_LINE_021
RW
VBI_DATA_
P24_N22[3]
VBI_DATA_
P24_N22[2]
VBI_DATA_
P24_N22[1]
VBI_DATA_
P24_N22[0]
VBI_DATA_
P337_N285[3]
VBI_DATA_
P337_N285[2]
VBI_DATA_
P337_N285[1]
VBI_DATA_
P337_N285[0]
00000000
00
120
78
VDP_STATUS
R
TTXT_AVL
VITC_AVL
GS_DATA_
TYPE
GS_PDC_VPS_
UTC_AVL
CGMS_WSS_AVL CC_EVEN_FIELD
CC_AVL
120
78
VDP_STATUS_
CLEAR
W
GS_PDC_VPS_
UTC_CLEAR
CGMS_WSS_
CLEAR
CC_CLEAR
00000000
00
121
79
VDP_CCAP_
DATA_0
R
CCAP_BYTE_1[7] CCAP_BYTE_1[6] CCAP_BYTE_1[5] CCAP_BYTE_1[4] CCAP_BYTE_1[3] CCAP_BYTE_1[2] CCAP_BYTE_1[1] CCAP_BYTE_1[0]
122
7A
VDP_CCAP_
DATA_1
R
CCAP_BYTE_2[7] CCAP_BYTE_2[6] CCAP_BYTE_2[5] CCAP_BYTE_2[4] CCAP_BYTE_2[3] CCAP_BYTE_2[2] CCAP_BYTE_2[1] CCAP_BYTE_2[0]
125
7D
VDP_CGMS_
WSS_DATA_0
R
126
7E
VDP_CGMS_
WSS_DATA_1
R
CGMS_CRC[1]
CGMS_CRC[0]
CGMS_WSS[13]
127
7F
VDP_CGMS_
WSS_DATA_2
R
CGMS_WSS[7]
CGMS_WSS[6]
132
84
VDP_GS_VPS_
PDC_UTC_0
R
GS_VPS_PDC_
UTC_BYTE_0[7]
133
85
VDP_GS_VPS_
PDC_UTC_1
R
134
86
VDP_GS_VPS_
PDC_UTC_2
135
87
136
00110000
30
VITC_CLEAR
CGMS_CRC[5]
CGMS_CRC[4]
CGMS_CRC[3]
CGMS_CRC[2]
CGMS_WSS[12]
CGMS_WSS[11]
CGMS_WSS[10]
CGMS_WSS[9]
CGMS_WSS[8]
CGMS_WSS[5]
CGMS_WSS[4]
CGMS_WSS[3]
CGMS_WSS[2]
CGMS_WSS[1]
CGMS_WSS[0]
GS_VPS_PDC_
UTC_BYTE_0[6]
GS_VPS_PDC_
UTC_BYTE_0[5]
GS_VPS_PDC_
UTC_BYTE_0[4]
GS_VPS_PDC_
UTC_BYTE_0[3]
GS_VPS_PDC_
UTC_BYTE_0[2]
GS_VPS_PDC_
UTC_BYTE_0[1]
GS_VPS_PDC_
UTC_BYTE_0[0]
GS_VPS_PDC_
UTC_BYTE_1[7]
GS_VPS_PDC_
UTC_BYTE_1[6]
GS_VPS_PDC_
UTC_BYTE_1[5]
GS_VPS_PDC_
UTC_BYTE_1[4]
GS_VPS_PDC_
UTC_BYTE_1[3]
GS_VPS_PDC_
UTC_BYTE_1[2]
GS_VPS_PDC_
UTC_BYTE_1[1]
GS_VPS_PDC_
UTC_BYTE_1[0]
R
GS_VPS_PDC_
UTC_BYTE_2[7]
GS_VPS_PDC_
UTC_BYTE_2[6]
GS_VPS_PDC_
UTC_BYTE_2[5]
GS_VPS_PDC_
UTC_BYTE_2[4]
GS_VPS_PDC_
UTC_BYTE_2[3]
GS_VPS_PDC_
UTC_BYTE_2[2]
GS_VPS_PDC_
UTC_BYTE_2[1]
GS_VPS_PDC_
UTC_BYTE_2[0]
VDP_GS_VPS_
PDC_UTC_3
R
GS_VPS_PDC_
UTC_BYTE_3[7]
GS_VPS_PDC_
UTC_BYTE_3[6]
GS_VPS_PDC_
UTC_BYTE_3[5]
GS_VPS_PDC_
UTC_BYTE_3[4]
GS_VPS_PDC_
UTC_BYTE_3[3]
GS_VPS_PDC_
UTC_BYTE_3[2]
GS_VPS_PDC_
UTC_BYTE_3[1]
GS_VPS_PDC_
UTC_BYTE_3[0]
88
VDP_VPS_
PDC_UTC_4
R
VPS_PDC_UTC_
BYTE_4[7]
VPS_PDC_UTC_
BYTE_4[6]
VPS_PDC_UTC_
BYTE_4[5]
VPS_PDC_UTC_
BYTE_4[4]
VPS_PDC_UTC_
BYTE_4[3]
VPS_PDC_UTC_
BYTE_4[2]
VPS_PDC_UTC_
BYTE_4[1]
VPS_PDC_UTC_
BYTE_4[0]
137
89
VDP_VPS_
PDC_UTC_5
R
VPS_PDC_UTC_
BYTE_5[7]
VPS_PDC_UTC_
BYTE_5[6]
VPS_PDC_UTC_
BYTE_5[5]
VPS_PDC_UTC_
BYTE_5[4]
VPS_PDC_UTC_
BYTE_5[3]
VPS_PDC_UTC_
BYTE_5[2]
VPS_PDC_UTC_
BYTE_5[1]
VPS_PDC_UTC_
BYTE_5[0]
138
8A
VDP_VPS_
PDC_UTC_6
R
VPS_PDC_UTC_
BYTE_6[7]
VPS_PDC_UTC_
BYTE_6[6]
VPS_PDC_UTC_
BYTE_6[5]
VPS_PDC_UTC_
BYTE_6[4]
VPS_PDC_UTC_
BYTE_6[3]
VPS_PDC_UTC_
BYTE_6[2]
VPS_PDC_UTC_
BYTE_6[1]
VPS_PDC_UTC_
BYTE_6[0]
139
8B
VDP_VPS_PDC_
UTC_7
R
VPS_PDC_UTC_
BYTE_7[7]
VPS_PDC_UTC_
BYTE_7[6]
VPS_PDC_UTC_
BYTE_7[5]
VPS_PDC_UTC_
BYTE_7[4]
VPS_PDC_UTC_
BYTE_7[3]
VPS_PDC_UTC_
BYTE_7[2]
VPS_PDC_UTC_
BYTE_7[1]
VPS_PDC_UTC_
BYTE_7[0]
140
8C
VDP_VPS_PDC_
UTC_8
R
VPS_PDC_UTC_
BYTE_8[7]
VPS_PDC_UTC_
BYTE_8[6]
VPS_PDC_UTC_
BYTE_8[5]
VPS_PDC_UTC_
BYTE_8[4]
VPS_PDC_UTC_
BYTE_8[3]
VPS_PDC_UTC_
BYTE_8[2]
VPS_PDC_UTC_
BYTE_8[1]
VPS_PDC_UTC_
BYTE_8[0]
141
8D
VDP_VPS_PDC_
UTC_9
R
VPS_PDC_UTC_
BYTE_9[7]
VPS_PDC_UTC_
BYTE_9[6]
VPS_PDC_UTC_
BYTE_9[5]
VPS_PDC_UTC_
BYTE_9[4]
VPS_PDC_UTC_
BYTE_9[3]
VPS_PDC_UTC_
BYTE_9[2]
VPS_PDC_UTC_
BYTE_9[1]
VPS_PDC_UTC_
BYTE_9[0]
142
8E
VDP_VPS_PDC_
UTC_10
R
VPS_PDC_UTC_
BYTE_10[7]
VPS_PDC_UTC_
BYTE_10[6]
VPS_PDC_UTC_
BYTE_10[5]
VPS_PDC_UTC_
BYTE_10[4]
VPS_PDC_UTC_
BYTE_10[3]
VPS_PDC_UTC_
BYTE_10[2]
VPS_PDC_UTC_
BYTE_10[1]
VPS_PDC_UTC_
BYTE_10[0]
143
8F
VDP_VPS_PDC_
UTC_11
R
VPS_PDC_UTC_
BYTE_11[7]
VPS_PDC_UTC_
BYTE_11[6]
VPS_PDC_UTC_
BYTE_11[5]
VPS_PDC_UTC_
BYTE_11[4]
VPS_PDC_UTC_
BYTE_11[3]
VPS_PDC_UTC_
BYTE_11[2]
VPS_PDC_UTC_
BYTE_11[1]
VPS_PDC_UTC_
BYTE_11[0]
144
90
VDP_VPS_PDC_
UTC_12
R
VPS_PDC_UTC_
BYTE_12[7]
VPS_PDC_UTC_
BYTE_12[6]
VPS_PDC_UTC_
BYTE_12[5]
VPS_PDC_UTC_
BYTE_12[4]
VPS_PDC_UTC_
BYTE_12[3]
VPS_PDC_UTC_
BYTE_12[2]
VPS_PDC_UTC_
BYTE_12[1]
VPS_PDC_UTC_
BYTE_12[0]
146
92
VDP_VITC_DATA_0 R
VITC_DATA_0[7] VITC_DATA_0[6] VITC_DATA_0[5] VITC_DATA_0[4] VITC_DATA_0[3] VITC_DATA_0[2] VITC_DATA_0[1] VITC_DATA_0[0]
147
93
VDP_VITC_DATA_1 R
VITC_DATA_1[7] VITC_DATA_1[6] VITC_DATA_1[5] VITC_DATA_1[4] VITC_DATA_1[3] VITC_DATA_1[2] VITC_DATA_1[1] VITC_DATA_1[0]
148
94
VDP_VITC_DATA_2 R
VITC_DATA_2[7] VITC_DATA_2[6] VITC_DATA_2[5] VITC_DATA_2[4] VITC_DATA_2[3] VITC_DATA_2[2] VITC_DATA_2[1] VITC_DATA_2[0]
149
95
VDP_VITC_DATA_3 R
VITC_DATA_3[7] VITC_DATA_3[6] VITC_DATA_3[5] VITC_DATA_3[4] VITC_DATA_3[3] VITC_DATA_3[2] VITC_DATA_3[1] VITC_DATA_3[0]
150
96
VDP_VITC_DATA_4 R
VITC_DATA_4[7] VITC_DATA_4[6] VITC_DATA_4[5] VITC_DATA_4[4] VITC_DATA_4[3] VITC_DATA_4[2] VITC_DATA_4[1] VITC_DATA_4[0]
151
97
VDP_VITC_DATA_5 R
VITC_DATA_5[7] VITC_DATA_5[6] VITC_DATA_5[5] VITC_DATA_5[4] VITC_DATA_5[3] VITC_DATA_5[2] VITC_DATA_5[1] VITC_DATA_5[0]
152
98
VDP_VITC_DATA_6 R
VITC_DATA_6[7] VITC_DATA_6[6] VITC_DATA_6[5] VITC_DATA_6[4] VITC_DATA_6[3] VITC_DATA_6[2] VITC_DATA_6[1] VITC_DATA_6[0]
153
99
VDP_VITC_DATA_7 R
VITC_DATA_7[7] VITC_DATA_7[6] VITC_DATA_7[5] VITC_DATA_7[4] VITC_DATA_7[3] VITC_DATA_7[2] VITC_DATA_7[1] VITC_DATA_7[0]
154
9A
VDP_VITC_DATA_8 R
VITC_DATA_8[7] VITC_DATA_8[6] VITC_DATA_8[5] VITC_DATA_8[4] VITC_DATA_8[3] VITC_DATA_8[2] VITC_DATA_8[1] VITC_DATA_8[0]
155
9B
VDP_VITC_CALC_
CRC
VITC_CRC[7]
VITC_CRC[6]
VITC_CRC[5]
VITC_CRC[4]
156
9C
VDP_OUTPUT_SEL RW
I C_GS_VPS_
PDC_UTC[1]
I C_GS_VPS_
PDC_UTC[0]
GS_VPS_
PDC_UTC_
CB_CHANGE
WSS_CGMS_
CB_CHANGE
1
2
R
2
2
VITC_CRC[3]
To access the registers listed in Table 106, SUB_USR_EN in Register Address 0x0E must be programmed to 1.
x in a reset value indicates do not care.
Rev. J | Page 83 of 114
VITC_CRC[2]
VITC_CRC[1]
VITC_CRC[0]
ADV7180
Data Sheet
Table 107. Main Register Map Descriptions (User Map)1, 2
Main Map
Subaddress
Register
0x00
Input control
Bit Description
INSEL[3:0]; the INSEL bits
allow the user to select
an input channel and
the input format; refer
to Table 13 and Table 14
for full routing details
VID_SEL[3:0]; the VID_SEL
bits allow the user to
select the input video
standard
0x01
Video selection
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0 0 0 0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
SQPE
0
0
1
ENVSPROC
0
1
Reserved
BETACAM
0
0
1
ENHSPLL
Reserved
0
1
1
Rev. J | Page 84 of 114
0
Comments
Composite (LQFP and LFCSP)
Composite (LQFP)/reserved (LFCSP)
Composite (LQFP)/reserved (LFCSP)
Composite (LQFP and LFCSP)
Composite (LQFP and LFCSP)
Composite (LQFP)/reserved (LFCSP)
S-Video (LQFP and LFCSP)
S-Video (LQFP)/reserved (LFCSP)
S-Video (LQFP)/reserved (LFCSP)
YPrPb (LQFP and LFCSP)
YPrPb (LQFP)/reserved (LFCSP)
Reserved (LQFP and LFCSP)
Reserved (LQFP and LFCSP)
Reserved (LQFP and LFCSP)
Reserved (LQFP and LFCSP)
Reserved (LQFP and LFCSP)
Autodetect PAL B/G/H/I/D,NTSC J
(no pedestal), SECAM
Autodetect PAL B/G/H/I/D, NTSC M
(pedestal), SECAM
Autodetect (PAL N) (pedestal), NTSC J
(no pedestal), SECAM
Autodetect (PAL N) (pedestal), NTSC M
(pedestal), SECAM
NTSC J
NTSC M
PAL 60
NTSC 4.43
PAL B/G/H/I/D
PAL N = PAL B/G/H/I/D (with pedestal)
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N (with pedestal)
SECAM
SECAM (with pedestal)
Set to default
Disable square pixel mode
Enable square pixel mode
Disable VSYNC processor
Enable VSYNC processor
Set to default
Standard video input
Betacam input enable
Disable HSYNC processor
Enable HSYNC processor
Set to default
Notes
Mandatory write
required for Y/C
(S-Video mode)
Reg 0x58 = 0x04;
see Reg 0x58 for
bit description
Data Sheet
Main Map
Subaddress
Register
0x03
Output control
ADV7180
Bit Description
SD_DUP_AV; duplicates
the AV codes from the
luma into the chroma path
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
1
Reserved
OF_SEL[3:0]; allows the
user to choose from a set
of output formats
0x04
Extended
output control
TOD; three-state output
drivers; this bit allows the
user to three-state the
output drivers; pixel
outputs, HS, VS, FIELD,
and SFL
VBI_EN; allows VBI data
(Line 1 to Line 21) to be
passed through with
only a minimum amount
of filtering performed
Range; allows the user
to select the range of
output values; can be
ITU-R BT.656 compliant or
can fill the whole accessible
number range
EN_SFL_PIN
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
8-bit at LLC 4:2:2 ITU-R BT.656
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Output pins enabled
1
Drivers three-stated
0
1
Notes
Options apply to
64-lead LQFP only
See also TIM_OE
and TRI_LLC
All lines filtered and scaled
Only active video region filtered
0
1
0
1
BL_C_VBI; blank chroma
during VBI; if set, it enables
data in the VBI region
to be passed through the
decoder undistorted
TIM_OE; timing signals
output enable
Reserved
Reserved
BT.656-4; allows the
user to select an output
mode compatible with
ITU-R BT.656-3/-4
Comments
AV codes to suit 8-bit interleaved data
output
AV codes duplicated (for 16-bit interfaces)
Set as default
Reserved
Reserved
16-bit at LLC 4:2:2
0
1
x
0
16 ≤ Y ≤ 235, 16 ≤ C/P ≤ 240
ITU-R BT.656
1
1 ≤ Y ≤ 254, 1 ≤ C/P ≤ 254
Extended range
SFL output is disabled
SFL information output on the SFL pin
SFL output
enables encoder
and decoder to be
connected directly
During VBI
Decode and output color
Blank Cr and Cb
HS, VS, FIELD three-stated
HS, VS, FIELD forced active
x
1
0
1
ITU-R BT.656-3 compatible
ITU-R BT.656-4 compatible
Rev. J | Page 85 of 114
Controlled by TOD
ADV7180
Main Map
Subaddress
Register
0x07
Autodetect
enable
Data Sheet
Bit Description
AD_PAL_EN; PAL B/D/I/G/H
autodetect enable
AD_NTSC_EN; NTSC
autodetect enable
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
1
0
1
1
Enable
Disable
0
AD_PALN_EN; PAL N
autodetect enable
1
Enable
Disable
0
AD_P60_EN; PAL 60
autodetect enable
1
Enable
Disable
0
AD_N443_EN; NTSC 4.43
autodetect enable
1
Enable
Disable
0
AD_SECAM_EN; SECAM
autodetect enable
1
AD_SEC525_EN; SECAM
525 autodetect enable
0x08
Contrast
0x0A
Brightness
0x0B
Hue
0x0C
Default Value Y
CON[7:0]; contrast adjust;
this is the user control for
contrast adjustment
BRI[7:0]; this register
controls the brightness
of the video signal
HUE[7:0]; this register
contains the value for
the color hue adjustment
DEF_VAL_EN;
default value enable
Enable
Disable
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
DEF_VAL_AUTO_EN;
default value automatic
enable
0x0D
Default Value C
0x0E
ADI Control 1
DEF_Y[5:0]; default value is
Y; this register holds the Y
default value
DEF_C[7:0]; default value
is C; the Cr and Cb default
values are defined in this
register
Reserved
SUB_USR_EN; enables
user to access the interrupt/
VDP register map
Reserved
Enable
Luma gain = 1
Free-run mode dependent on
DEF_VAL_AUTO_EN
Force free-run mode on and output
blue screen
Disable free-run mode
Enable automatic free-run mode
(blue screen)
0
0
1
1
0
1
0
1
1
1
1
1
0
0
Cr[3:0] = {DEF_C[7:4], 0, 0, 0, 0}
Cb[3:0] = {DEF_C[3:0], 0, 0, 0, 0}
0
0
0
0
0
Set as default
Access main register space
Access interrupt/VDP register space
0
1
0
Notes
Enable
Disable
0
AD_PALM_EN; PAL M
autodetect enable
Comments
Disable
Enable
Disable
0
Y[7:0] = {DEF_Y[5:0], 0, 0}
Set as default
Rev. J | Page 86 of 114
0x00 gain = 0,
0x80 gain = 1,
0xFF gain = 2
0x00 = 0 IRE,
0x7F = +30 IRE,
0x80 = −30 IRE
Hue range =
−90° to +90°
When lock is lost,
free-run mode
can be enabled to
output stable
timing, clock, and
a set color
Default Y value
output in free-run
mode
Default Cb/Cr
value output in
free-run mode;
default values give
blue screen output
See Figure 55
Data Sheet
Main Map
Subaddress
Register
0x0F
Power
management
ADV7180
Bit Description
Reserved
PDBP; power-down bit
priority selects between
PWRDWN bit or pin control
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
0
0
1
Reserved
PWRDWN; power-down
places the decoder into a
full power-down mode
Reserved
Reset; chip reset, loads
all I2C bits with default
values
0x10
Status 1
(read only)
0x11
IDENT
(read only)
0x12
Status 2
(read only)
0x13
Status 3
(read only)
0
MV PS DET
MV AGC DET
LL NSTD
FSC NSTD
Reserved
INST_HLOCK
GEMD
SD_OP_50Hz
0
0
Set to default
Normal operation
1
Start reset sequence
x
x
x
x
x
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
Analog
clamp control
0
x
MV color striping detected
MV color striping type
MV pseudosync detected
MV AGC pulses detected
Nonstandard line length
fSC frequency nonstandard
x
x
x
1 = in lock (now)
1 = lost lock (since last read)
1 = fSC lock (now)
1 = peak white AGC mode active
NTSC M/J
NTSC 4.43
PAL M
PAL 60
PAL B/G/H/I/D
SECAM
PAL Combination N
SECAM 525
1 = color kill is active
0
x
Notes
Not applicable for
32-lead LFCSP
See PDBP,
0x0F Bit 2
Executing reset
takes approximately 2 ms; this
bit is self-clearing
Provides info
about the internal
status of the
decoder
Detected
standard
Color kill
Power-up
value = 0x1C
1 = detected
0 = Type 2,
1 = Type 3
1 = detected
1 = detected
1 = detected
1 = detected
x
x
x
0
1
1 = horizontal lock achieved
1 = Gemstar data detected
SD 60 Hz detected
SD 50 Hz detected
Unfiltered
1 = free-run mode active
1 = field length standard
Blue screen output
Correct field
length found
Field sequence
found
Reliable swinging
burst sequence
SD field rate detect
x
x
x
x
1 = interlaced video detected
x
1 = swinging burst detected
Reserved
CCLEN; current clamp
enable allows the user
to switch off the current
sources in the analog
front
VCLEN; allows the user to
reset the clamp circuitry
Reserved
1
x
Interlaced
0x14
1
x
Reserved
FREE_RUN_ACT
STD FLD LEN
PAL_SW_LOCK
Bit has priority (pin disregarded)
Set to default
System functional
Powered down
0
0
1
IN_LOCK
LOST_LOCK
FSC_LOCK
FOLLOW_PW
AD_RESULT[2:0]; autodetection result reports
the standard of the
input video
COL_KILL
IDENT[7:0]; provides
identification on the
revision of the part
MVCS DET
MVCS T3
Comments
Set to default
Chip power-down controlled by pin
0
0
0
1
0
1
0
0
Rev. J | Page 87 of 114
1
0
Set to default
Current sources switched off
Current sources enabled
Normal Operation
Reset Clamp Circuitry
Set to default
ADV7180
Main Map
Subaddress
Register
0x15
Digital Clamp
Control 1
Data Sheet
Bit Description
Reserved
DCFE; digital clamp
freeze enable
DCT[1:0]; digital clamp
timing determines the
time constant of the
digital fine clamp circuitry
0x17
Shaping Filter
Control 1
Reserved
YSFM[4:0]; selects Y
shaping filter mode in
CVBS-only mode;
allows the user to select
a wide range of low-pass
and notch filters; if either
auto mode is selected,
the decoder selects
the optimum Y filter
depending on the CVBS
video source quality
(good vs. poor)
CSFM[2:0]; C shaping filter
mode allows selection
from a range of low-pass
chrominance filters;
if either auto mode is
selected, the decoder
selects the optimum C
filter depending on the
CVBS video source quality
(good vs. bad); nonauto
settings force a C filter for
all standards and quality
of CVBS video
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
x
x
x
x
0
1
0 0
0 1
1 0
1 1
0
0
0
0
0
0
0
0
0
0
0
1
Comments
Set to default
Digital clamp on
Digital clamp off
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
TC dependent on video
Set to default
Autowide notch for poor quality
sources or wideband filter with
comb for good quality input
Autonarrow notch for poor quality
sources or wideband filter with
comb for good quality input
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
Autoselection 1.5 MHz
Autoselection 2.17 MHz
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
SH1
SH2
SH3
SH4
SH5
Wideband mode
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. J | Page 88 of 114
Notes
Decoder selects
optimum Y
shaping filter
depending on
CVBS quality
If one of these
modes is selected,
the decoder does
not change filter
modes; depending
on video quality, a
fixed filter response
(the one selected)
is used for good
and bad quality
video
Automatically
selects a C filter
based on video
standard and
quality
Selects a C filter for
all video standards
and for good and
bad video
Data Sheet
Main Map
Subaddress
Register
0x18
Shaping Filter
Control 2
0x19
Comb filter
control
ADV7180
Bit Description
WYSFM[4:0]; wideband Y
shaping filter mode allows
the user to select which Y
shaping filter is used for
the Y component of Y/C,
YPrPb, B/W input signals;
it is also used when a
good quality input CVBS
signal is detected; for all
other inputs, the Y
shaping filter chosen is
controlled by YSFM[4:0]
Reserved
WYSFMOVR; enables
use of the automatic
WYSFM filter
PSFSEL[1:0]; controls
the signal bandwidth
that is fed to the comb
filters (PAL)
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
~ ~ ~ ~ ~
1
1
1
1
1
0 0
0
1
NSFSEL[1:0]; controls
the signal bandwidth
that is fed to the comb
filters (NTSC)
0x1D
ADI Control 2
Reserved
Reserved
EN28XTAL
1
TRI_LLC
0
1
1
1
0
1
0
0
0
1
1
0
1
0
1
0
x
0
1
Rev. J | Page 89 of 114
0
0
1
1
0
1
0
1
x
x
Comments
Reserved, do not use
Reserved, do not use
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved, do not use
Reserved, do not use
Reserved, do not use
Set to default
Autoselection of best filter
Manual select filter using WYSFM[4:0]
Narrow
Medium
Wide
Widest
Narrow
Medium
Medium
Wide
Set as default
Set to default
Reserved, do not use
Use 28 MHz crystal
LLC pin active
LLC pin three-stated
Notes
ADV7180
Main Map
Subaddress
Register
0x27
Pixel delay
control
Data Sheet
Bit Description
LTA[1:0]; luma timing
adjust allows the user to
specify a timing difference
between chroma and
luma samples
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
0
0
1
1
1
Reserved
CTA[2:0]; chroma
timing adjust allows
a specified timing
difference between
the luma and chroma
samples
AUTO_PDC_EN;
automatically programs
the LTA/CTA values so
that luma and chroma are
aligned at the output for
all modes of operation
SWPC; allows the Cr and
Cb samples to be swapped
0x2B
0x2C
0x2D
Misc gain
control
AGC mode
control
Chroma Gain
Control 1,
Chroma Gain1
(CG)
PW_UPD; peak white
update determines the
rate of gain
Reserved
CKE; color kill enable
allows the color kill
function to be switched
on and off
Reserved
CAGC[1:0]; chroma automatic gain control selects
the basic mode of
operation for the AGC in
the chroma path
Reserved
LAGC[2:0]; luma auto
matic gain control selects
the mode of operation for
the gain control in the
luma path
Reserved
CMG[11:8]/CG[11:8]; in
manual mode, the chroma
gain control can be used to
program a desired manual
chroma gain; in auto mode,
it can be used to read back
the current gain value
Reserved
CAGT[1:0]; chroma auto
matic gain timing allows
adjustment of the chroma
AGC tracking speed
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Luma two clocks (74 ns) early
Luma one clock (37 ns) early
Set to 0
Not a valid setting
Chroma + two pixels (early)
Chroma + one pixel (early)
No delay
Chroma − one pixel (late)
Chroma − two pixels (late)
Chroma − three pixels (late)
Not a valid setting
Use values in LTA[1:0] and CTA[2:0]
for delaying luma/chroma
0
1
0
1
0
1
0
1
0
1
Notes
CVBS mode
LTA[1:0] = 00b,
S-Video mode
LTA[1:0] = 01b,
YPrPb mode
LTA[1:0] = 01b
CVBS mode
CTA[2:0] = 011b,
S-Video mode
CTA[2:0] = 101b,
YPrPb mode
CTA[2:0] = 110b
LTA and CTA values determined
automatically
0
1
0
1
1
0
0
0
0
1
0
0
1
1
1
No swapping
Swap the Cr and Cb output samples
Update once per video line
Update once per field
Set to default
Color kill disabled
Color kill enabled
0
1
0
1
0
1
1
Set to default
Manual fixed gain
Use luma gain for chroma
Automatic gain
Freeze chroma gain
0
0
0
0
0
1
Set to 1
Manual fixed gain
Peak white algorithm off
0
1
0
Peak white algorithm on
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Freeze gain
Set to 1
1
0
1
0
0
1
1
Comments
No delay
Luma one clock (37 ns) late
1
1
0
1
0
1
Rev. J | Page 90 of 114
0
0
Peak white must
be enabled; see
LAGC[2:0]
For SECAM color
kill, the threshold
is set at 8%; see
CKILLTHR[2:0]
Use CMG[11:0]
Based on color burst
Use LMG[11:0]
Blank level to
sync tip
Blank level to
sync tip
CAGC[1:0] settings
decide in which
mode CMG[11:0]
operates
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Reserved
Adaptive
Has an effect only
if CAGC[1:0] is set
to autogain (10)
Data Sheet
Main Map
Subaddress
Register
0x2E
Chroma Gain
Control 2,
Chroma Gain2
(CG)
0x2F
Luma Gain
Control 1, Luma
Gain1 (LG)
0x30
Luma Gain
Control 2, Luma
Gain2 (LG)
0x31
VS/FIELD
Control 1
ADV7180
Bit Description
CMG[7:0]/CG[7:0]; chroma
manual gain lower eight
bits; see CMG[11:8]/
CG[11:8] for description
LMG[11:8]/LG[11:8]; in
manual mode, luma gain
control can be used to
program a desired manual
luma gain; in auto mode,
it can be used to read back
the actual gain value used
Reserved
LAGT[1:0]; luma auto
matic gain timing allows
adjustment of the luma
AGC tracking speed
LMG[7:0]/LG[7:0]; luma
manual gain lower eight
bits; see LMG[11:8]/
LG[11:8] for description
Reserved
HVSTIM; selects where
within a line of video the
VS signal is asserted
NEWAVMODE; sets the
EAV/SAV mode
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0 0 0 0
0
0
0
0
x
1
0
0
1
1
x
0
1
0
1
x
x
x
x
x
1
x
x
x
x
x
0
1
0
0
1
0
1
0x32
VS/FIELD
Control 2
Reserved
Reserved
VSBHE
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
VSBHO
0
1
0x33
VS/FIELD
Control 3
Reserved
VSEHE
0
1
VSEHO
0
1
0x34
HS Position
Control 1
0x35
HS Position
Control 2
0x36
HS Position
Control 3
HSE[10:8]; HS end allows
positioning of the HS
output within the
video line
Reserved
HSB[10:8]; HS begin
allows positioning of
the HS output within
the video line
Reserved
HSB[7:0]; see Address 0x34,
using HSB[10:0] and
HSE[10:0], users can
program the position
and length of the HS
output signal
HSE[7:0]; see Address
0x35 description
0
0
0
0
Comments
CMG[11:0] = see the CMG section
CMG[11:0] = see the CMG section
LAGC[1:0] settings decide in which
mode LMG[11:0] operates
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
LMG[11:0] - see the LMG section
LMG[11:0] =- see the LMG section
Set to default
Start of line relative to HSE
Start of line relative to HSB
EAV/SAV codes generated to suit
Analog Devices encoders
Manual VS/FIELD position controlled by
Register 0x32, Register 0x33, and
Register 0xE5 to Register 0xEA
Set to default
Set to default
VS goes high in the middle of the
line (even field)
VS changes state at the start of the
line (even field)
VS goes high in the middle of the
line (odd field)
VS changes state at the start of the
line (odd field)
Set to default
VS goes low in the middle of the
line (even field)
VS changes state at the start of the
line (even field)
VS goes low in the middle of the line
(odd field)
VS changes state at the start of the
line odd field
HS output ends HSE[10:0] pixels after
the falling edge of HSYNC
Set to 0
HS output starts HSB[10:0] pixels
after the falling edge of HSYNC
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Set to 0
Rev. J | Page 91 of 114
Notes
Min value = 0d,
Max value = 4095d
Only has an effect
if LAGC[1:0] is set
to autogain (001,
010, 011, or 100)
Min value = 1024d,
Max value = 4095d
HSE = HSYNC end
HSB = HSYNC begin
NEWAVMODE bit
must be set high
NEWAVMODE bit
must be set high
Using HSB and
HSE the user can
program the
position and length
of the output
HSYNC
ADV7180
Main Map
Subaddress
Register
0x37
Polarity
Data Sheet
Bit Description
PCLK; sets polarity of LLC
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
1
Reserved
PF; sets the FIELD polarity
Reserved
PVS; sets the VS polarity
Reserved
PHS; sets HS polarity
0x38
NTSC comb
control
PAL comb
control
0
0
0
1
1
0
0
1
0
0
1
1
0
Three-line adaptive for CTAPSN = 01,
Four-line adaptive for CTAPSN = 10,
Five-line adaptive for CTAPSN = 11
1
1
0
0
0
1
Disable chroma comb
Fixed two-line for CTAPSN = 01,
Fixed three-line for CTAPSN = 10,
Fixed four-line for CTAPSN = 11
1
1
0
Fixed three-line for CTAPSN = 01,
Fixed four-line for CTAPSN = 10,
Fixed five-line for CTAPSN = 11
All lines of memory
1
1
1
Fixed two-line for CTAPSN = 01,
Fixed three-line for CTAPSN = 10,
Fixed four-line for CTAPSN = 11
Bottom lines of
memory
0
1
0
1
CCMP[2:0]; chroma
comb mode, PAL
Top lines of memory
All lines of memory
Bottom lines of
memory
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
Notes
0
YCMP[2:0]; luma
comb mode, PAL
CTAPSP[1:0]; chroma
comb taps, PAL
0
1
1
1
1
0
CCMN[2:0]; chroma
comb mode, NTSC
0x39
0
0
1
YCMN[2:0]; luma comb
mode, NTSC
CTAPSN[1:0]; chroma
comb taps, NTSC
0
0
1
Comments
Invert polarity
Normal polarity as per the timing
diagrams
Set to 0
Active high
Active low
Set to 0
Active high
Active low
Set to 0
Active low
Active high
Adaptive three-line, three-tap luma
Use low-pass notch
Fixed luma comb (two-line)
Fixed luma comb (three-line)
Fixed luma comb (two-line)
0
0
0
1
1
0
0
0
1
1
1
0
1
1
1
0
0
0
1
1
0
0
1
0
1
Not used
Adapts three lines to two lines
Adapts five lines to three lines
Adapts five lines to four lines
Adaptive five-line, three-tap luma comb
Use low-pass notch
Fixed luma comb (three-line)
Fixed luma comb (five-line)
Fixed luma comb (three-line)
Three-line adaptive for CTAPSN = 01,
Four-line adaptive for CTAPSN = 10,
Five-line adaptive for CTAPSN = 11
Disable chroma comb
Fixed two-line for CTAPSN = 01
Fixed three-line for CTAPSN = 10
Fixed four-line for CTAPSN = 11
Fixed three-line for CTAPSN = 01
Fixed four-line for CTAPSN = 10
Fixed five-line for CTAPSN = 11
Fixed two-line for CTAPSN = 01
Fixed three-line for CTAPSN = 10
Fixed four-line for CTAPSN = 11
Not used
Adapts five lines to three lines (two taps)
Adapts five lines to three lines (three taps)
Adapts five lines to four lines (four taps)
0
1
0
1
Rev. J | Page 92 of 114
Top lines of memory
Top lines of memory
All lines of memory
Bottom lines of
memory
Top lines of memory
All lines of memory
Bottom lines
of memory
Data Sheet
Main Map
Subaddress
Register
0x3A
ADC control
ADV7180
Bit Description
MUX PDN override; mux
power-down override
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
Comments
1
PWRDWN_MUX_2;
enables power-down of
MUX2 and associated
channel clamp and buffer
0
MUX2 and associated channel in
normal operation
1
Power down MUX2 and associated
channel operation
MUX1 and associated channel in
normal operation
MUX PDN
Override = 1
Power down MUX1 and associated
channel operation
MUX0 and associated channel in
normal operation
MUX PDN
Override = 1
Power down MUX0 and associated
channel operation
Set as default
Set to default
NTSC, PAL color kill at <0.5%,
SECAM no color kill
NTSC, PAL color kill at <1.5%,
SECAM color kill at <5%
NTSC, PAL color kill at <2.5%,
SECAM color kill at <7%
NTSC, PAL color kill at <4%,
SECAM color kill at <8%
NTSC, PAL color kill at <8.5%,
SECAM color kill at <9.5%
NTSC, PAL color kill at <16%,
SECAM color kill at <15%
NTSC, PAL color kill at <32%,
SECAM color kill at <32%
Reserved
Set to default
Set to default
SFL-compatible with the ADV717x and
ADV73xx video encoders
SFL-compatible with the ADV7194
video encoder
Set to default
GDECEL[15:0]: 16 individual enable bits
that select the lines of video (even field
Line 10 to Line 25) that the decoder
checks for Gemstar-compatible data
MUX PDN
Override = 1
0
PWRDWN_MUX_1;
enables power-down of
MUX1 and associated
channel clamp and buffer
1
0
PWRDWN_MUX_0;
enables power-down of
MUX0 and associated
channel clamp and buffer
1
0x3D
0x41
0x48
0x49
Manual
window
control
Resample
control
Gemstar
Control 1
Gemstar
Control 2
Reserved
Reserved
CKILLTHR[2:0]
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
0
1
0
Reserved
Reserved
SFL_INV; controls the
behavior of the PAL
switch bit
1
Reserved
GDECEL[15:8]; see the
Comments column
GDECEL[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Rev. J | Page 93 of 114
Notes
No control over
power-down for
muxes and associated channel circuit
Allows power-down
of MUX0/MUX1/
MUX2 and
associated channel
circuit. When
INSEL[3:0] is used,
unused channels
are automatically
powered down.
CKE = 1 enables
the color kill
function and must
be enabled for
CKILLTHR[2:0] to
take effect
LSB = Line 10,
MSB = Line 25,
Default = do not
check for Gemstarcompatible data
on any lines [10 to
25] in even fields
ADV7180
Main Map
Subaddress
Register
0x4A
Gemstar
Control 3
0x4B
Gemstar
Control 4
0x4C
0x4D
Gemstar
Control 5
CTI DNR
Control 1
Data Sheet
Bit Description
GDECOL[15:8]; see the
Comments column
GDECOL[7:0]
GDECAD; controls the
manner decoded Gemstar
data is inserted into the
horizontal blanking period
GDE_SEL_OLD_ADF
Reserved
CTI_EN; CTI enable
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0 0 0 0
0
0
0
0
0
0
0
0
x
0x50
CTI DNR
Control 4
0x51
Lock count
Reserved
CTI_C_TH[7:0]; specifies
how big the amplitude
step must be to be steepened by the CTI block
DNR_TH[7:0]; specifies
the maximum edge that is
interpreted as noise and is
therefore blanked
CIL[2:0]; count into lock
determines the number of
lines the system must
remain in lock before
showing a locked status
0x52
CVBS_TRIM
x
x
0
1
Split data into half-byte
Output in straight 8-bit format
x
0
1
Enables a new ancillary data system
Undefined
Disable CTI
Enable CTI
Disable CTI alpha blender
Enable CTI alpha blender
x
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
CVBS_IBIAS[3:0], sets the
bias current for the analog
front end for CVBS inputs.
Reserved
0
0
1
COL[2:0]; count out of
lock determines the
number of lines the
system must remain outof-lock before showing a
lost-locked status
SRLS; select raw lock signal;
selects the determination
of the lock status
FSCLE; fSC lock enable
0
0
1
Reserved
DNR_EN; enable or bypass
the DNR block
CTI DNR
Control 2
0
0
x
CTI_AB_EN; enables the
mixing of the transient
improved chroma with
the original signal
CTI_AB[1:0]; controls the
behavior of the alphablend circuitry
0x4E
0
1
1
0
0
0
0
1
0
Rev. J | Page 94 of 114
1
0
Comments
GDECOL[15:0]: 16 individual enable bits
that select the lines of video (odd field
Line 10 to Line 25) that the decoder
checks for Gemstar-compatible data
1
1
Sharpest mixing
Sharp mixing
Smooth mixing
Smoothest mixing
Set to default
Bypass the DNR block
Enable the DNR block
Set to default
Set to 0x04 for AV input;
set to 0x0A for tuner input
One line of video
Two lines of video
Five lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100,000 lines of video
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100,000 lines of video
Over field with vertical info
Line-to-line evaluation
Lock status set only by horizontal lock
Lock status set by horizontal lock and
subcarrier lock
Default AFE bias current setting
Recommended AFE bias current for
CVBS inputs
Notes
LSB = Line 10,
MSB = Line 25,
Default = do not
check for Gemstarcompatible data on
any lines [10 to 25]
in odd fields
To avoid 00/FF code
Data Sheet
Main Map
Subaddress
Register
VS/FIELD
0x58
pin control
0x59
Generalpurpose
outputs
ADV7180
Bit Description
VS/FIELD; VSYNC or FIELD
output; 40-lead and
32-lead LFCSP only
Reserved
ADC sampling control
Reserved
GPO[3:0]; LQFP only
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
1
GPO_ENABLE
0
1
Reserved
Reserved
LLC_PAD_SEL[2:0]; enables
manual selection of the
clock for the LLC pin
0
CCAP1
(read only)
CCAP2
(read only)
Letterbox 1
(read only)
Reserved
CCAP1[7:0]; closed
caption data register
CCAP2[7:0]; closed
caption data register
LB_LCT[7:0]; letterbox
data register
0x9C
Letterbox 2
(read only)
0x9D
0xB2
0x8F
0x99
0x9A
0x9B
Comments
FIELD
VSYNC
Set to default
ADC sampling control
Y/C mode only
Set to default
Outputs 0 to GPO0
Outputs 1 to GPO0
Outputs 0 to GPO1
Outputs 1 to GPO1
Outputs 0 to GPO2
Outputs 1 to GPO2
Outputs 0 to GPO3
Outputs 1 to GPO3
GPO[3:0] three-stated
GPO[3:0] enabled
0
0
0
0
0
1
0
1
0
x
x
x
x
x
x
x
x
Set to default
LLC (nominal 27 MHz) selected out
on LLC pin
LLC (nominal 13.5 MHz) selected out
on LLC pin
Set to default
CCAP1[7] contains parity bit for Byte 0
x
x
x
x
x
x
x
x
CCAP2[7] contains parity bit for Byte 0
x
x
x
x
x
x
x
x
Reports the number of black lines
detected at the top of active video
LB_LCM[7:0]; letterbox
data register
x
x
x
x
x
x
x
x
Letterbox 3
(read only)
LB_LCB[7:0]; letterbox
data register
x
x
x
x
x
x
x
x
Reports the number of black lines
detected in the bottom half of active
video if subtitles are detected
Reports the number of black lines
detected at the bottom of active video
CRC enable
(write only)
Reserved
CRC_ENABLE; enable CRC
checksum decoded from
FMS packet to validate
CGMSD
Reserved
0
0
Free-Run Line
Length 1
0
0
0
1
0
0
0
1
1
Rev. J | Page 95 of 114
0
0
Set as default
Turn off CRC check
CGMSD goes high with valid checksum
Set as default
Notes
Pin 37 on 40-lead
LFCSP, Pin 31 on
32-lead LFCSP
Mandatory write
GPO_ENABLE
must be set to 1
for these bits to
take effect
For 16-bit 4:2:2 out,
OF_SEL[3:0] = 0010
This feature
examines the active
video at the start
and end of each
field; it enables
format detection
even if the video is
not accompanied
by a CGMS or WSS
sequence
ADV7180
Main Map
Subaddress
Register
0xC3
ADC Switch 1
Data Sheet
Bit Description
MUX0[2:0]; manual
muxing control for MUX0;
this setting controls which
input is routed to the ADC
for processing
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
0
0
0
1
1
1
1
Reserved
MUX1[2:0]; manual
muxing control for MUX1;
this setting controls which
input is routed to the ADC
for processing
0xC4
ADC Switch 2
0xDC
Letterbox
Control 1
0xDD
Letterbox
Control 2
0xDE
Reserved
MUX2[2:0]; manual
muxing control for MUX2;
this setting controls which
input is routed to the ADC
for processing
Reserved
MAN_MUX_EN; enable
manual setting of the
input signal muxing
LB_TH[4:0]; sets the
threshold value that
determines if a line is
black
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
x
x
x
x
x
x
SD_OFF_Cb[7:0]; adjusts
the hue by selecting the
offset for the Cb channel
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0xE3
SD Saturation Cb
SD_SAT_Cb[7:0]; adjusts
the saturation by affecting
gain on the Cb channel
0
0
1
x
SD_OFF_Cr[7:0]; adjusts
the hue by selecting the
offset for the Cr channel
LFCSP
No connect
No connect
No connect
No connect
AIN2
AIN3
No connect
No connect
MAN_MUX_EN = 1
LQFP
No connect
No connect
AIN2
No connect
No connect
AIN5
AIN6
No connect
LFCSP
No connect
No connect
No connect
No connect
No connect
AIN3
No connect
No connect
MAN_MUX_EN = 1
Disable
Enable
x
SD Offset Cr
LQFP
No connect
No connect
No connect
AIN3
AIN4
AIN5
AIN6
No connect
0
0
1
ST_NOISE[7:0]
0xE2
Notes
MAN_MUX_EN = 1
0
1
0xE1
LFCSP
No connect
AIN1
No connect
No connect
AIN2
AIN3
No connect
No connect
0
Reserved
LB_EL[3:0]; programs the
end line of the activity
window for LB detection
(end of field)
LB_SL[3:0]; programs the
start line of the activity
window for LB detection
(start of field)
ST_NOISE[10:8]
ST_NOISE_VLD
ST Noise
Readback 1
(read only)
ST Noise
Readback 2
(read only)
SD Offset Cb
0xDF
0
0
1
1
0
0
1
1
Comments
LQFP
No connect
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
No connect
1
1
0
0
Default threshold for the detection of
black lines
01101 to 10000—increase threshold,
00000 to 01011—decrease threshold
Set as default
LB detection ends with the last line of
active video on a field, 1100b: 262/525
Letterbox detection aligned with the
start of active video, 0100b: 23/286 NTSC
x
x
x
x
When = 1, ST_NOISE[10:0] is valid
Rev. J | Page 96 of 114
−312 mV offset applied to the Cb channel
0 mV offset applied to the Cb channel
+312 mV offset applied to the Cb channel
−312 mV offset applied to the Cr channel
0 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
Gain on Cb channel = −42 dB
Gain on Cb channel = 0 dB
Gain on Cb channel = +6 dB
This bit must be set
to 1 for manual
muxing
Data Sheet
Main Map
Subaddress
Register
0xE4
SD Saturation Cr
0xE5
0xE6
0xE7
0xE8
NTSC V bit
begin
NTSC V bit end
NTSC F bit
toggle
PAL V bit begin
ADV7180
Bit Description
SD_SAT_Cr[7:0]; adjusts
the saturation by affecting
gain on the Cr channel
NVBEG[4:0]; number of
lines after lCOUNT rollover
to set V high
NVBEGSIGN
NVBEGDELE; delay V bit
going high by one line
relative to NVBEG (even
field)
NVBEGDELO; delay V bit
going high by one line
relative to NVBEG (odd
field)
NVEND[4:0]; number of
lines after lCOUNT rollover
to set V low
NVENDSIGN
NVENDDELE; delay V bit
going low by one line
relative to NVEND (even
field)
NVENDDELO; delay V bit
going low by one line
relative to NVEND (odd
field)
NFTOG[4:0]; number of
lines after lCOUNT rollover to
toggle F signal
NFTOGSIGN
NFTOGDELE; delay
F transition by one line
relative to NFTOG (even
field)
NFTOGDELO; delay
F transition by one line
relative to NFTOG
(odd field)
PVBEG[4:0]; number of
lines after lCOUNT rollover
to set V high
PVBEGSIGN
PVBEGDELE; delay V bit
going high by one line
relative to PVBEG (even
field)
PVBEGDELO; delay V bit
going high by one line
relative to PVBEG (odd
field)
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0 0 0 0
0
0
0
0
1 0 0 0
0
0
0
0
1 1 1 1
1
1
1
1
0
0
1
0
1
0
1
Comments
Gain on Cr channel = −42 dB
Gain on Cb channel = 0 dB
Gain on Cb channel = +6 dB
NTSC default (ITU-R BT.656)
Set to low when manual programming
Not suitable for user programming
No delay
Additional delay by one line
0
1
0
1
No delay
Additional delay by one line
0
0
1
0
0
0
1
NTSC default (ITU-R BT.656)
Set to low when manual programming
Not suitable for user programming
No delay
Additional delay by one line
0
1
0
1
No delay
Additional delay by one line
0
0
0
1
1
0
1
NTSC default
Set to low when manual programming
Not suitable for user programming
No delay
Additional delay by one line
0
1
0
1
No delay
Additional delay by one line
0
0
1
0
1
0
1
0
1
0
1
PAL default (ITU-R BT.656)
Set to low when manual programming
Not suitable for user programming
No delay
Additional delay by one line
No delay
Additional delay by one line
Rev. J | Page 97 of 114
Notes
ADV7180
Main Map
Subaddress
Register
0xE9
PAL V bit end
0xEA
0xEB
PAL F bit toggle
Vblank Control 1
Data Sheet
Bit Description
PVEND[4:0]; number of
lines after lCOUNT rollover
to set V low.
PVENDSIGN
PVENDDELE; delay V bit
going low by one line
relative to PVEND (even
field)
PVENDDELO; delay V bit
going low by one line
relative to PVEND (odd
field)
PFTOG[4:0]; number of
lines after lCOUNT rollover
to toggle F signal
PFTOGSIGN
PFTOGDELE; delay
F transition by one line
relative to PFTOG
(even field)
PFTOGDELO; delay
F transition by one line
relative to PFTOG
(odd field)
PVBIELCM[1:0]; PAL VBI
even field line control
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
1
0
1
0
0
0
1
0
1
0
1
No delay
Additional delay by one line
0
Vblank Control 2
0
1
PAL default (ITU-R BT.656)
Set to low when manual programming
Not suitable for user programming
No delay
Additional delay by one line
0
1
No delay
Additional delay by one line
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PVBIECCM[1:0]; PAL VBI
even field color control
PVBIOCCM[1:0]; PAL VBI
odd field color control
NVBIECCM[1:0]; NTSC VBI
even field color control
NVBIOCCM[1:0]; NTSC VBI
odd field color control
1
0
1
NVBIELCM[1:0]; NTSC VBI
even field line control
0xEC
0
0
1
0
0
1
1
Notes
Set to low when manual programming
Not suitable for user programming
No delay
Additional delay by one line
PVBIOLCM[1:0]; PAL VBI
odd field line control
NVBIOLCM[1:0]; NTSC VBI
odd field line control
Comments
PAL default (ITU-R BT.656)
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
Rev. J | Page 98 of 114
VBI ends one line earlier (Line 335)
ITU-R BT.470 compliant (Line 336)
VBI ends one line later (Line 337)
VBI ends two lines later (Line 338)
VBI ends one line earlier (Line 22)
ITU-R BT.470 compliant (Line 23)
VBI ends one line later (Line 24)
VBI ends two lines later (Line 25)
VBI ends one line earlier (Line 282)
ITU-R BT.470 compliant (Line 283)
VBI ends one line later (Line 284)
VBI ends two lines later (Line 285)
VBI ends one line earlier (Line 20)
ITU-R BT.470 compliant (Line 21)
VBI ends one line later (Line 22)
VBI ends two lines later (Line 23)
Color output beginning Line 335
ITU-R BT.470 compliant color output
beginning Line 336
Color output beginning Line 337
Color output beginning Line 338
Color output beginning Line 22
ITU-R BT.470-compliant color output
beginning Line 23
Color output beginning Line 24
Color output beginning Line 25
Color output beginning Line 282
ITU-R BT.470-compliant color output
beginning Line 283
VBI ends one line later (Line 284)
Color output beginning Line 285
Color output beginning Line 20
ITU-R BT.470 compliant color output
beginning Line 21
Color output beginning Line 22
Color output beginning Line 23
Controls position of
first active (comb
filtered) line after VBI
on even field in PAL
Controls position of
first active (comb
filtered) line after VBI
on odd field in PAL
Controls position of
first active (comb
filtered) line after VBI
on even field in NTSC
Controls position of
first active (comb
filtered) line after VBI
on odd field in NTSC
Controls the position
of first line that
outputs color after
VBI on even field in
PAL
Controls the position
of first line that
outputs color after
VBI on odd field in
PAL
Controls the position
of first line that
outputs color after
VBI on even field in
NTSC
Controls the position
of first line that
outputs color after
VBI on odd field in
NTSC
Data Sheet
Main Map
Subaddress
Register
0xF3
AFE_CONTROL 1
ADV7180
Bit Description
AA_FILT_EN[2:0];
antialiasing filter enable
Bits
(Shading Indicates Default State)
7 6 5 4 3 2 1 0
0
Antialiasing Filter 1 enabled
Antialiasing Filter 2 disabled
Antialiasing Filter 2 enabled
Antialiasing Filter 3 disabled
Antialiasing Filter 3 enabled
Override disabled
Override enabled
0
0
1
1
0
1
0
1
Low drive strength (1×)
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
Low drive strength (1×)
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
Low drive strength (1×)
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
The low drive
strength (1×)
setting for
DR_STR_S,
DR_STR_C, and
DR_STR is not
recommended for
the optimal
performance of
the ADV7180
0
0
Bypass mode
2 MHz
−3 dB
−6 dB
−10 dB
Reserved
3 MHz
−2 dB
−5 dB
−7 dB
0 dB
NTSC filters
0
1
0xF4
Drive strength
Reserved
DR_STR_S[1:0]; selects
the drive strength for
the sync output signals
0
1
0
0
0
0
0
0
1
1
DR_STR_C[1:0]; selects
the drive strength for
the clock output signal
0xF8
0xF9
IF comp
control
VS mode
control
DR_STR[1:0]; selects the
drive strength for the data
output signals; can be
increased or decreased for
EMC or crosstalk reasons
Reserved
IFFILTSEL[2:0]; IF filter
selection for PAL and
NTSC
Reserved
EXTEND_VS_MAX_FREQ
0
0
1
1
x
0
1
0
1
0
1
0
1
x
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
0
EXTEND_VS_MIN_FREQ
0
1
VS_COAST_MODE[1:0]
Peaking control
0xFC
Coring
threshold
1
2
5 MHz
−2 dB
+3.5 dB
+5 dB
6 MHz
+2 dB
+3 dB
+5 dB
PAL filters
0
1
0xFB
Notes
AA_FILT_MAN_OVR
must be enabled
to change settings
defined by
INSEL[3:0]
1
0
1
AA_FILT_MAN_OVR;
antialiasing filter override
Comments
Antialiasing Filter 1 disabled
0
0
1
1
0
1
0
1
Reserved
PEAKING_GAIN[7:0]
0
0
0
1
0
0
0
0
0
0
0
0
DNR_TH2[7:0]
0
0
0
0
0
1
0
0
Shading indicates default values.
x indicates a bit that keeps the last written value.
Rev. J | Page 99 of 114
Limits maximum VSYNC frequency to
66.25 Hz (475 lines/frame)
Limits maximum VSYNC frequency to
70.09 Hz (449 lines/frame)
Limits minimum VSYNC frequency to
42.75 Hz (731 lines/frame)
Limits minimum VSYNC frequency to
39.51 Hz (791 lines/frame)
Autocoast mode
50 Hz coast mode
60 Hz coast mode
Reserved
Increases/decreases the gain for high
frequency portions of the video signal
Specifies the maximum edge that is
interpreted as noise and therefore
blanked
This value sets up
the output coast
frequency
ADV7180
Data Sheet
To read to and write from the registers in Table 108, the SUB_USR_EN bit (Address 0x0E[5]) must be set to Logic 1.
Table 108. Register Map Descriptions (User Sub Map)1, 2
Bit (Shading Indicates
Interrupt and VDP Map
Address Register
Bit Description
0x40
Interrupt Configuration 1
INTRQ_OP_SEL[1:0]; interrupt
drive level select
MPU_STIM_INTRQ; manual
interrupt set mode
Reserved
MV_INTRQ_SEL[1:0];
Macrovision interrupt select
INTRQ_DUR_SEL[1:0];
interrupt duration select
0x42
Interrupt Status 1
(read only)
Default State)
7 6 5 4 3 2 1
0
0
1
1
0
1
x
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
SD_LOCK_Q
0
1
SD_UNLOCK_Q
0
1
Reserved
SD_FR_CHNG_Q
Interrupt Clear 1
(write only)
Reserved
SD_LOCK_CLR
No change
Denotes a change in the free-run status
No change
Pseudo sync/color striping detected;
see Register 0x40 MV_INTRQ_SEL[1:0]
for selection
0
1
x
0
1
SD_UNLOCK_CLR
0
1
Reserved
SD_FR_CHNG_CLR
0 0 0
0
1
MV_PS_CS_CLR
0x44
Interrupt Mask 1
(read/write)
Reserved
SD_LOCK_MSK
0
1
x
0
1
SD_UNLOCK_MSK
0
1
Reserved
SD_FR_CHNG_MSK
0 0 0
0
1
MV_PS_CS_MSK
Reserved
Comments
Open drain
Drive low when active
Drive high when active
Reserved
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
Three XTAL periods
15 XTAL periods
63 XTAL periods
Active until cleared
No change
SD input has caused the decoder to go
from an unlocked state to a locked state
No change
SD input has caused the decoder to go
from a locked state to an unlocked state
x x x
0
1
MV_PS_CS_Q
0x43
0
0
1
0
1
0
1
x
Rev. J | Page 100 of 114
Do not clear
Clears SD_LOCK_Q bit
Do not clear
Clears SD_UNLOCK_Q bit
Not used
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
Clears MV_PS_CS_Q bit
Not used
Masks SD_LOCK_Q bit
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Not used
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
Notes
These bits can be cleared
or masked in Register 0x43
and Register 0x44, respectively
Data Sheet
ADV7180
Bit (Shading Indicates
Default State)
Interrupt and VDP Map
Address Register
0x45
Raw Status 2
(read only)
Bit Description
CCAPD
7 6 5 4 3 2 1 0
0
1
Reserved
EVEN_FIELD
Reserved
MPU_STIM_INTRQ
0x46
Interrupt Status 2
(read only)
x x x
0
1
Current SD field is odd numbered
Current SD field is even numbered
0
1
GEMD_Q
0
1
Reserved
SD_FIELD_CHNGD_Q
Interrupt Clear 2
(write only)
x
x
0
1
CCAPD_CLR
0
1
GEMD_CLR
0
1
Reserved
SD_FIELD_CHNGD_CLR
Reserved
MPU_STIM_INTRQ_CLR
0x48
Interrupt Mask 2
(read/write)
x x
0
1
0
1
GEMD_MSK
0
1
Reserved
SD_FIELD_CHNGD_MSK
0x49
Raw Status 3
(read only)
0 0
0
1
0 0
0
1
SD_OP_50Hz; SD 60 Hz/50 Hz
frame rate at output
0
1
SD_V_LOCK
0
1
SD_H_LOCK
0
1
Reserved
SCM_LOCK
Reserved
These bits can be cleared
or masked by Register 0x47
and Register 0x48, respectively; note that the
interrupt in Register 0x46
for the CCAP, Gemstar,
CGMS, and WSS data uses
the Mode 1 data slicer
SD signal has not changed field from
odd to even or vice versa
SD signal has changed Field from odd to
even or vice versa
Not used
Not used
Manual interrupt not set
Manual interrupt set
Do not clear—VBI System 2
Clears CCAPD_Q bit—VBI System 2
Do not clear
Clears GEMD_Q bit
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS,
and WSS data uses the
Mode 1 data slicer
0 0
0
1
CCAPD_MSK
Reserved
MPU_STIM_INTRQ_MSK
MPU_STIM_INTRQ = 0
MPU_STIM_INTRQ = 1
Closed captioning not detected in the
input video signal—VBI System 2
Closed captioning data detected in the
video input signal—VBI System 2
Gemstar data not detected in the input
video signal—VBI System 2
Gemstar data detected in the input
video signal—VBI System 2
x x
0
1
0x47
Notes
These bits are status
bits only; they cannot be
cleared or masked;
Register 0x46 is used for
this purpose
x x
0
1
CCAPD_Q
Reserved
Reserved
MPU_STIM_INTRQ_Q
Comments
No CCAPD data detected—
VBI System 2
CCAPD data detected—VBI System 2
x
0
1
x x x
Rev. J | Page 101 of 114
Do not clear
Clears SD_FIELD_CHNGD_Q bit
Not used
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Masks CCAPD_Q bit—VBI System 2
Unmasks CCAPD_Q bit—VBI System 2
Masks GEMD_Q bit—VBI System 2
Unmasks GEMD_Q bit—VBI System 2
Not used
Masks SD_FIELD_CHNGD_Q bit
Unmasks SD_FIELD_CHNGD_Q bit
Not used
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not established
SD vertical sync lock established
SD horizontal sync lock not established
SD horizontal sync lock established
Not used
SECAM lock not established
SECAM lock established
Not used
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS,
and WSS data uses the
Mode 1 data slicer
These bits are status
bits only; they cannot be
cleared or masked;
Register 0x4A is used for
this purpose
ADV7180
Data Sheet
Bit (Shading Indicates
Default State)
Interrupt and VDP Map
Address Register
0x4A
Interrupt Status 3
(read only)
Bit Description
SD_OP_CHNG_Q; SD 60 Hz/50 Hz
frame rate at output
7 6 5 4 3 2 1 0
0
1
SD_V_LOCK_CHNG_Q
SD_H_LOCK_CHNG_Q
SD_AD_CHNG_Q; SD autodetect
changed
0
No change in SD VSYNC lock status
1
SD VSYNC lock status has changed
0
No change in HSYNC lock status
1
SD HSYNC lock status has changed
0
1
SCM_LOCK_CHNG_Q; SECAM lock
0
1
PAL_SW_LK_CHNG_Q
0
1
0x4B
Interrupt Clear 3
(write only)
Reserved
SD_OP_CHNG_CLR
x x
0
1
SD_V_LOCK_CHNG_CLR
0
1
SD_H_LOCK_CHNG_CLR
0
1
SD_AD_CHNG_CLR
0
1
SCM_LOCK_CHNG_CLR
0
1
PAL_SW_LK_CHNG_CLR
0x4C
Interrupt Mask 3
(read/write)
0
1
Reserved
SD_OP_CHNG_MSK
x x
0
1
SD_V_LOCK_CHNG_MSK
0
1
SD_H_LOCK_CHNG_MSK
0
1
SD_AD_CHNG_MSK
0
1
SCM_LOCK_CHNG_MSK
0
1
PAL_SW_LK_CHNG_MSK
0x4E
Interrupt Status 4 (read only)
0
1
Reserved
VDP_CCAPD_Q
x x
0
1
Reserved
VDP_CGMS_WSS_CHNGD_Q; see
0x9C Bit 4 of user sub map to determine
whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content
Reserved
VDP_GS_VPS_PDC_UTC_CHNG_Q;
see 0x9C Bit 5 of User Sub Map to determine whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content
Reserved
VDP_VITC_Q
Reserved
Comments
No change in SD signal standard
detected at the output
A change in SD signal standard is
detected at the output
No change in AD_RESULT[2:0] bits in
Status 1 register
AD_RESULT[2:0] bits in Status 1 register
have changed
No change in SECAM lock status
SECAM lock status has changed
No change in PAL swinging burst
lock status
PAL swinging burst lock status has
changed
Not used
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
Clears SD_AD_CHNG_Q bit
Do not clear
Clears SCM_LOCK_CHNG_Q bit
Do not clear
Clears PAL_SW_LK_CHNG_Q bit
Not used
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q bit
Masks SD_H_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q bit
Not used
Closed captioning not detected
Closed captioning detected
x
0
1
CGMS/WSS data is not changed/
not available
CGMS/WSS data is changed/available
x
0
1
Gemstar/PDC/VPS/UTC data is not
changed/not available
Gemstar/PDC/VPS/UTC data is
changed/available
x
0
1
x
Rev. J | Page 102 of 114
VITC data is not available in the VDP
VITC data is available in the VDP
Notes
These bits can be cleared
and masked by
Register 0x4B and
Register 0x4C, respectively
These bits can be cleared
and masked by Register
0x4F and Register 0x50,
respectively; note that an
interrupt in Register 0x4E
for the CCAP, Gemstar,
CGMS, WSS, VPS, PDC,
UTC, and VITC data uses
the VDP data slicer
Data Sheet
ADV7180
Bit (Shading Indicates
Default State)
Interrupt and VDP Map
Address Register
0x4F
Interrupt Clear 4
(write only)
Bit Description
VDP_CCAPD_CLR
Reserved
VDP_CGMS_WSS_CHNGD_CLR
Reserved
VDP_GS_VPS_PDC_UTC_CHNG_CLR
Reserved
VDP_VITC_CLR
0x50
Interrupt Mask 4
Reserved
VDP_CCAPD_MSK
Reserved
VDP_CGMS_WSS_CHNGD_MSK
Reserved
VDP_GS_VPS_PDC_UTC_CHNG_MSK
7 6 5 4 3 2 1 0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
Reserved
VDP_VITC_MSK
0x60
VDP_Config_1
Reserved
VDP_TTXT_TYPE_MAN[1:0]
1 1
VDP_TTXT_TYPE_MAN_ENABLE
0
1
WST_PKT_DECODE_DISABLE
0
1
0x62
VDP_ADF_Config_1
Reserved
Reserved
AUTO_DETECT_GS_TYPE
1 0 0 0
Reserved
ADF_DID[4:0]
0 0 0
PAL: Teletext-ITU-BT.653-625/50-A,
NTSC: reserved
PAL: Teletext-ITU-BT.653-625/50-B (WST),
NTSC: Teletext-ITU-BT.653-525/60-B
PAL: Teletext-ITU-BT.653-625/50-C,
NTSC: Teletext-ITU-BT.653-525/60-C, or
EIA516 (NABTS)
PAL: Teletext-ITU-BT.653-625/50-D,
NTSC: Teletext-ITU-BT.653-525/60-D
User programming of teletext type
disabled
User programming of teletext type
enabled
Enable hamming decoding of WST
packets
Disable hamming decoding of WST
packets
1 0 1 0 1
User-specified DID sent in the ancillary
data stream with VDP decoded data
Nibble mode
Byte mode, no code restrictions
Byte mode with 0x00 and 0xFF
prevented
Reserved
Disable insertion of VBI decoded data
into ancillary 656 stream
Enable insertion of VBI decoded data
into ancillary 656 stream
User-specified SDID sent in the ancillary
data stream with VDP decoded data
0 0
0 1
1 0
0
ADF_SDID[5:0]
Reserved
DUPLICATE_ADF
Masks VDP_GS_VPS_PDC_UTC_CHNG_Q
Unmasks VDP_GS_VPS_PDC_UTC_
CHNG_Q
Disable autodetection of Gemstar type
Enable autodetection of Gemstar type
1
VDP_ADF_Config_2
Masks VDP_CGMS_WSS_CHNGD_Q
Unmasks VDP_CGMS_WSS_CHNGD_Q
0
1
1 1
0x63
Masks VDP_CCAPD_Q
Unmasks VDP_CCAPD_Q
x x 0 0
ADF_MODE[1:0]
ADF_ENABLE
Do not clear
Clears VDP_VITC_Q
0
0 0
1 0 1 0 1 0
x
0
1
Rev. J | Page 103 of 114
Notes
Note that an interrupt
in Register 0x4E for the
CCAP, Gemstar, CGMS,
WSS, VPS, PDC, UTC, and
VITC data uses the VDP
data slicer
Do not clear
Clears VDP_GS_VPS_PDC_UTC_CHNG_Q
Masks VDP_VITC_Q
Unmasks VDP_VITC_Q
1 0
VDP_Config_2
Do not clear
Clears VDP_CGMS_WSS_CHNGD_Q
0
0
1
0 1
0x61
Comments
Do not clear
Clears VDP_CCAPD_Q
Ancillary data packet is spread across
the Y and C data streams
Ancillary data packet is duplicated on
the Y and C data streams
Note that an interrupt
in Register 0x4E for the
CCAP, Gemstar, CGMS,
WSS, VPS, PDC, UTC, and
VITC data uses the VDP
data slicer
ADV7180
Data Sheet
Bit (Shading Indicates
Default State)
Interrupt and VDP Map
Address Register
0x64
VDP_LINE_00E
Bit Description
VBI_DATA_P318[3:0]
7 6 5 4 3 2 1 0
0 0 0 0
Reserved
MAN_LINE_PGM
0
VDP_LINE_00F
VBI_DATA_P319_N286[3:0]
VBI_DATA_P6_N23[3:0]
0x66
VDP_LINE_010
0x67
VDP_LINE_011
VDP_LINE_012
VDP_LINE_013
VDP_LINE_014
VDP_LINE_015
VDP_LINE_016
VDP_LINE_017
VDP_LINE_018
VDP_LINE_019
VDP_LINE_01A
VDP_LINE_01B
VDP_LINE_01C
VDP_LINE_01D
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
VBI_DATA_P332_N280[3:0]
VBI_DATA_P19_N17[3:0]
0x73
0 0 0 0
VBI_DATA_P331_N279[3:0]
VBI_DATA_P18_N16[3:0]
0x72
0 0 0 0
VBI_DATA_P330_N278[3:0]
VBI_DATA_P17_N15[3:0]
0x71
0 0 0 0
VBI_DATA_P329_N277[3:0]
VBI_DATA_P16_N14[3:0]
0x70
0 0 0 0
VBI_DATA_P328_N276[3:0]
VBI_DATA_P15_N13[3:0]
0x6F
0 0 0 0
VBI_DATA_P327_N275[3:0]
VBI_DATA_P14_N12[3:0]
0x6E
0 0 0 0
VBI_DATA_P326_N274[3:0]
VBI_DATA_P13_N11[3:0]
0x6D
0 0 0 0
VBI_DATA_P325_N273[3:0]
VBI_DATA_P12_N10[3:0]
0x6C
0 0 0 0
VBI_DATA_P324_N272[3:0]
VBI_DATA_P11[3:0]
0x6B
0 0 0 0
VBI_DATA_P323[3:0]
VBI_DATA_P10[3:0]
0x6A
0 0 0 0
VBI_DATA_P322[3:0]
VBI_DATA_P9[3:0]
0x69
0 0 0 0
VBI_DATA_P321_N288[3:0]
VBI_DATA_P8_N25[3:0]
0x68
0 0 0 0
VBI_DATA_P320_N287[3:0]
VBI_DATA_P7_N24[3:0]
0 0 0 0
0 0 0 0
VBI_DATA_P333_N281[3:0]
VBI_DATA_P20_N18[3:0]
Notes
0 0 0
1
0x65
Comments
Sets VBI standard to be decoded from
Line 318 (PAL), NTSC—N/A
0 0 0 0
0 0 0 0
Rev. J | Page 104 of 114
Decode default standards on the lines
indicated in Table 69
Manually program the VBI standard
If set to 1, all VBI_DATA_
to be decoded on each line; see Table 70 Px_Ny bits can be set as
desired
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 319 (PAL), Line 286 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 6 (PAL), Line 23 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 320 (PAL), Line 287 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 7 (PAL), Line 24 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 321 (PAL), Line 288 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 8 (PAL), Line 25 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 322 (PAL), NTSC—N/A
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 9 (PAL), NTSC—N/A
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 323 (PAL), NTSC—N/A
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 10 (PAL), NTSC—N/A
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 324 (PAL), Line 272 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 11 (PAL); NTSC—N/A
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 325 (PAL), Line 273 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 12 (PAL), Line 10 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 326 (PAL), Line 274 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 13 (PAL), Line 11 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 327 (PAL), Line 275 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 14 (PAL), Line 12 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 328 (PAL), Line 276 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 15 (PAL), Line 13 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 329 (PAL), Line 277 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 16 (PAL), Line 14 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 330 (PAL), Line 278 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 17 (PAL), Line 15 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 331 (PAL), Line 279 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 18 (PAL), Line 16 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 332 (PAL), Line 280 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 19 (PAL), Line 17 (NTSC)
Sets VBI standard to be decoded from
MAN_LINE_PGM must
Line 333 (PAL), Line 281 (NTSC)
be set to 1 for these bits
to be effective
Sets VBI standard to be decoded from
Line 20 (PAL), Line 18 (NTSC)
Data Sheet
ADV7180
Bit (Shading Indicates
Default State)
Interrupt and VDP Map
Address Register
0x74
VDP_LINE_01E
0x75
VDP_LINE_01F
Bit Description
VBI_DATA_P334_N282[3:0]
7 6 5 4 3 2 1 0
0 0 0 0
VBI_DATA_P21_N19[3:0]
0 0 0 0
VBI_DATA_P335_N283[3:0]
VBI_DATA_P22_N20[3:0]
0x76
VDP_LINE_020
VDP_LINE_021
VDP_STATUS
(read only)
0 0 0 0
0 0 0 0
VBI_DATA_P337_N285[3:0]
VBI_DATA_P24_N22[3:0]
0x78
0 0 0 0
VBI_DATA_P336_N284[3:0]
VBI_DATA_P23_N21[3:0]
0x77
0 0 0 0
0 0 0 0
0 0 0 0
CC_AVL
0
1
CC_EVEN_FIELD
0
1
CGMS_WSS_AVL
0
1
Reserved
GS_PDC_VPS_UTC_AVL
0
1
VITC_AVL
VDP_STATUS_CLEAR
(write only)
0
1
0
1
CC_CLEAR
0
1
Reserved
CGMS_WSS_CLEAR
0
Reserved
GS_PDC_VPS_UTC_CLEAR
0x7A
0x7D
VDP_CCAP_DATA_0
(read only)
VDP_CCAP_DATA_1
(read only)
VDP_CGMS_WSS_DATA_0
(read only)
0x7E
VDP_CGMS_WSS_DATA_1
(read only)
0x7F
VDP_CGMS_WSS_DATA_2
(read only)
VDP_GS_VPS_PDC_UTC_0
(read only)
VDP_GS_VPS_PDC_UTC_1
(read only)
0x84
0x85
GS_PDC_VPS_UTC_CLEAR
resets the
GS_PDC_VPS_UTC_AVL
bit
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
CC_CLEAR resets the
CC_AVL bit
CGMS_WSS_CLEAR resets
the CGMS_WSS_AVL bit
Gemstar_1× detected
Gemstar_2× detected
VITC not detected
VITC_CLEAR resets the
VITC_AVL bit
VITC detected
Teletext not detected
Teletext detected
Does not reinitialize the CCAP readback
This is a self-clearing bit
registers
Reinitializes the CCAP readback registers
Does not reinitialize the CGMS/WSS
readback registers
Reinitializes the CGMS/WSS readback
registers
This is a self-clearing bit
Does not reinitialize the GS/PDC/VPS/
UTC readback registers
Refreshes the GS/PDC/VPS/UTC
readback registers
This is a self-clearing bit
Does not reinitialize the VITC readback
registers
Reinitializes the VITC readback registers
This is a self-clearing bit
0
0
1
0x79
GS/PDC/VPS/UTC not detected
GS/PDC/VPS/UTC detected
MAN_LINE_PGM must be
set to 1 for these bits to
be effective
0
1
Reserved
VITC_CLEAR
Notes
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
0
0
1
GS_DATA_TYPE
TTXT_AVL
Comments
Sets VBI standard to be decoded from
Line 334 (PAL), Line 282 (NTSC)
Sets VBI standard to be decoded from
Line 21 (PAL), Line 19 (NTSC)
Sets VBI standard to be decoded from
Line 335 (PAL), Line 283 (NTSC)
Sets VBI standard to be decoded from
Line 22 (PAL), Line 20 (NTSC)
Sets VBI standard to be decoded from
Line 336 (PAL), Line 284 (NTSC)
Sets VBI standard to be decoded from
Line 23 (PAL), Line 21 (NTSC)
Sets VBI standard to be decoded from
Line 337 (PAL), Line 285 (NTSC)
Sets VBI standard to be decoded from
Line 24 (PAL), Line 22 (NTSC)
Closed captioning not detected
Closed captioning detected
Closed captioning decoded from
odd field
Closed captioning decoded from
even field
CGMS/WSS not detected
CGMS/WSS detected
0
0
Reserved
CCAP_BYTE_1[7:0]
1
0
x x x x x x x x
Decoded Byte 1 of CCAP
CCAP_BYTE_2[7:0]
x x x x x x x x
Decoded Byte 2 of CCAP
CGMS_CRC[5:2]
Reserved
CGMS_WSS[13:8]
CGMS_CRC[1:0]
CGMS_WSS[7:0]
x x x x
0 0 0 0
x x x x x x
x x
x x x x x x x x
Decoded CRC sequence for CGMS
GS_VPS_PDC_UTC_BYTE_0[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
GS_VPS_PDC_UTC_BYTE_1[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
Rev. J | Page 105 of 114
Decoded CGMS/WSS data
Decoded CRC sequence for CGMS
Decoded CGMS/WSS data
ADV7180
Data Sheet
Bit (Shading Indicates
Default State)
Interrupt and VDP Map
Address Register
0x86
VDP_GS_VPS_PDC_UTC_2
(read only)
0x87
VDP_GS_VPS_PDC_UTC_3
(read only)
0x88
VDP_VPS_PDC_UTC_4
(read only)
0x89
VDP_VPS_PDC_UTC_5
(read only)
0x8A
VDP_VPS_PDC_UTC_6
(read only)
0x8B
VDP_VPS_PDC_UTC_7
(read only)
0x8C
VDP_VPS_PDC_UTC_8
(read only)
0x8D
VDP_VPS_PDC_UTC_9
(read only)
0x8E
VDP_VPS_PDC_UTC_10
(read only)
0x8F
VDP_VPS_PDC_UTC_11
(read only)
0x90
VDP_VPS_PDC_UTC_12
(read only)
0x92
VDP_VITC_DATA_0
(read only)
0x93
VDP_VITC_DATA_1
(read only)
0x94
VDP_VITC_DATA_2
(read only)
0x95
VDP_VITC_DATA_3
(read only)
0x96
VDP_VITC_DATA_4
(read only)
0x97
VDP_VITC_DATA_5
(read only)
0x98
VDP_VITC_DATA_6
(read only)
0x99
VDP_VITC_DATA_7
(read only)
0x9A
VDP_VITC_DATA_8
(read only)
0x9B
VDP_VITC_CALC_CRC
(read only)
0x9C
VDP_OUTPUT_SEL
Bit Description
GS_VPS_PDC_UTC_BYTE_2[7:0]
7 6 5 4 3 2 1 0
x x x x x x x x
Comments
Decoded Gemstar/VPS/PDC/UTC data
GS_VPS_PDC_UTC_BYTE_3[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_4[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_5[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_6[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_7[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_8[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_9[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_10[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_11[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VPS_PDC_UTC_BYTE_12[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
VITC_DATA_0[7:0]
x x x x x x x x
Decoded VITC data
VITC_DATA_1[7:0]
x x x x x x x x
Decoded VITC data
VITC_DATA_2[7:0]
x x x x x x x x
Decoded VITC data
VITC_DATA_3[7:0]
x x x x x x x x
Decoded VITC data
VITC_DATA_4[7:0]
x x x x x x x x
Decoded VITC data
VITC_DATA_5[7:0]
x x x x x x x x
Decoded VITC data
VITC_DATA_6[7:0]
x x x x x x x x
Decoded VITC data
VITC_DATA_7[7:0]
x x x x x x x x
Decoded VITC data
VITC_DATA_8[7:0]
x x x x x x x x
Decoded VITC data
VITC_CRC[7:0]
x x x x x x x x
Decoded VITC CRC data
Reserved
WSS_CGMS_CB_CHANGE
0 0 0 0
0
1
GS_VPS_PDC_UTC_CB_CHANGE
0
1
I2C_GS_VPS_PDC_UTC[1:0]
1
2
Notes
0
0
1
1
0
1
0
1
Shading indicates default values.
x indicates a bit that keeps the last written value.
Rev. J | Page 106 of 114
Disable content-based updating of
CGMS and WSS data
Enable content-based updating of
CGMS and WSS data
Disable content-based updating of
Gemstar, VPS, PDC, and UTC data
Enable content-based updating of
Gemstar, VPS, PDC, and UTC data
Gemstar_1×/Gemstar_2×
VPS
PDC
UTC
The available bit shows
the availability of data
only when its content
has changed
Standard expected to
be decoded
Data Sheet
ADV7180
PCB LAYOUT RECOMMENDATIONS
14B
Using a single ground plane for the entire board is also recommended.
The ADV7180 is a high precision, high speed, mixed-signal
device. To achieve the maximum performance from the part, it
is important to have a well laid out PCB. The following is a
guide for designing a board using the ADV7180.
ANALOG INTERFACE INPUTS
Experience repeatedly shows that the noise performance is the
same or better with a single ground plane. Using multiple ground
planes can be detrimental because each separate ground plane is
smaller, and long ground loops can result.
71B
Take care when routing the inputs on the PCB. Keep track
lengths to a minimum, and use 75 Ω trace impedances when
possible. In addition, trace impedances other than 75 Ω
increase the chance of reflections.
PLL
73B
POWER SUPPLY DECOUPLING
Place the PLL loop filter components as close as possible to the
ELPF pin. It must also be placed on the same side of the PCB as
the ADV7180. Do not place any digital or other high frequency
traces near these components. Use the values suggested in this
data sheet with tolerances of 10% or less.
72B
It is recommended to decouple each power supply pin with
0.1 μF and 10 nF capacitors. The fundamental idea is to have a
decoupling capacitor within about 0.5 cm of each power pin. In
addition, avoid placing the capacitor on the opposite side of the
PCB from the ADV7180 because doing so interposes inductive
vias in the path. The decoupling capacitors must be located
between the power plane and the power pin. Current must flow
from the power plane to the capacitor and then to the power
pin. Do not apply the power connection between the capacitor
and the power pin. Placing a via underneath the 100 nF
capacitor pads, down to the power plane, is the best approach
(see Figure 56).
SUPPLY
Place the circuit associated with these pins as close as possible
and on the same side of the PCB as the ADV7180.
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
75B
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, requiring more
current and, in turn, causing more internal digital noise.
Shorter traces reduce the possibility of reflections.
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce the current spikes inside the ADV7180.
If series resistors are used, place them as close as possible to the
ADV7180 pins. However, try not to add vias or extra length to
the output trace to place the resistors closer.
VIA TO SUPPLY
10nF
100nF
VIA TO GND
05700-046
GROUND
VREFN AND VREFP
74B
If possible, limit the capacitance that each of the digital outputs
drives to less than 15 pF. This can easily be accomplished by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside the ADV7180, creating more digital
noise on its power supplies.
Figure 56. Recommended Power Supply Decoupling
It is particularly important to maintain low noise and good
stability of PVDD. Careful attention must be paid to regulation,
filtering, and decoupling. It is highly desirable to provide separate
regulated supplies for each of the analog circuitry groups (AVDD,
DVDD, DVDDIO, and PVDD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can in turn produce changes in the regulated
analog supply voltage. This can be mitigated by regulating the
analog supply, or at least PVDD, from a different, cleaner power
source, for example, from a 12 V supply.
The 40-lead and 32-lead LFCSP have an exposed metal paddle
on the bottom of the package. This paddle must be soldered to
PCB ground for proper heat dissipation and for noise and
mechanical strength benefits.
DIGITAL INPUTS
76B
The digital inputs on the ADV7180 are designed to work with
1.8 V to 3.3 V signals and are not tolerant of 5 V signals. Extra
components are needed if 5 V logic signals are required to be
applied to the decoder.
Rev. J | Page 107 of 114
ADV7180
Data Sheet
TYPICAL CIRCUIT CONNECTION
15B
Examples of how to connect the 40-lead LFCSP, 64-lead LQFP, 48-lead LQFP, and 32-lead LFCSP video decoders are shown in Figure 57,
Figure 58, Figure 59, and Figure 60. For a detailed schematic of the ADV7180 evaluation boards, contact a local Analog Devices field
applications engineer or an Analog Devices distributor.
ANALOG_INPUT_1
DVDD_1.8V
0.1µF
DVDDIO
AVDD _1.8V
AIN1
36Ω
0.1µF
39Ω
ANALOG_INPUT_2
0.1µF
10nF
0.1µF
10nF
0.1µF
10nF
10nF
0.1µF
AIN2
36Ω
PVDD_1.8V
DVDDIO_3.3V
39Ω
DVDD _1.8V
0.1µF
AVDD _1.8V
ANALOG_INPUT_3
AIN2
30
AIN3
31
RESET
AIN2
20
14
36
27
P0
P1
P2
P3
P4
P5
P6
P7
AIN3
RESET
ADV7180BCPZ
KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE
26
OF THE PCB AS THE ADV7180.
10nF
P[0:7]
PVDD
AIN1
AVDD
29
DVDD
AIN1
DVDD
23
DVDDIO
39Ω
DVDDIO
1
AIN3
36Ω
4
0.1µF
LFCSP–40
17
16
10
9
8
7
6
5
P0
P1
P2
P3
P4
P5
P6
P7
YCrCb
8-BIT
656 DATA
VREFN
0.1µF
25
VREFP
LLC
INTRQ
LOCATE CLOSE TO, AND ON THE
SAME SIDE AS, THE ADV7180.
13
47pF
28.63636MHz
SFL
XTAL
VS/FIELD
1MΩ
HS
12
47pF
11
38
2
37
39
LLC
INTRQ
SFL
VS/FIELD
HS
XTAL1
DVDDIO
4kΩ
32
ALSB
PVDD_1.8V
ADDRESS = 42h
ADDRESS = 40h
EXTERNAL
LOOP FILTER
10nF
TEST_0
SDATA
1.69kΩ
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
05700-048
22
33
19
82nF
SCLK
AGND
AGND
AGND
SDA
34
28
21
24
SCLK
ELPF
PWRDWN
DGND
DGND
DGND
DGND
18
POWER_DOWN
40
3
15
35
ALSB TIED HI
ALSB TIED LOW
≥ I2C
≥ I2C
Figure 57. 40-Lead LFCSP Typical Connection Diagram
Rev. J | Page 108 of 114
Data Sheet
0.1µF
10nF
36Ω
ANALOG_INPUT_6
YC_C
36Ω
10nF
DVDDIO_3.3V
AVDD _1.8V
0.1µF
10nF
0.1µF
39Ω
0.1µF
AIN5
35
AIN1
39Ω
36
AIN2
46
AIN3
0.1µF
47
AIN4
AIN6
39Ω
48
AIN5
49
AIN6
KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME
39
SIDE OF THE PCB AS THE ADV7180.
AIN1
AIN2
AIN3
AIN4
AIN5
ADV7180BSTZ
AIN6
LQFP–64
38
22
47pF
P[0:7]
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
VREFN
0.1µF
INTRQ
VREFP
GPO3
GPO2
GPO1
GPO0
XTAL
FIELD
28.63636MHz
1MΩ
VS
21
47pF
HS
XTAL1
SFL
51
RESET
29
POWER_DOWN
RESET
10nF
10nF
31
0.1µF
AIN4
PVDD_1.8V
AVDD
0.1µF
0.1µF
DVDDIO _3.3V
10nF
PVDD
AIN3
39Ω
DVDDIO
ANALOG_INPUT_5
Cb
0.1µF
0.1µF
4
36Ω
AIN2
39Ω
58
ANALOG_INPUT_4
Cr
0.1µF
40
36Ω
DVDD _1.8V
DVDD
ANALOG_INPUT_3
YC_Y
DVDD _1.8V
DVDD
36Ω
39Ω
11
ANALOG_INPUT_2
CVBS
AIN1
THE SUGGESTED INPUT ARRANGEMENT
IS AS SEEN ON THE EVAL BOARD AND IS
DIRECTLY SUPPORTED BY INSEL.
23
36Ω
0.1µF
DVDDIO
ANALOG_INPUT_1
Y
ADV7180
NC
PWRDWN
ELPF
26
25
19
18
17
16
15
14
DATA BUS
P[0:7]
P0
P1
P2
P3
P4
P5
P6
P7
P[8:15]
656/601 YCbCr
Y
P[8:15]
8
7
6
5
62
61
60
59
P8
P9
P10
P11
P12
P13
P14
P15
1
INT
55
56
12
13
GPO3
GPO2
GPO1
GPO0
63
FIELD
64
VSYNC
2
HS
9
SFL
27, 28, 33,
41, 42, 44,
45, 50
30
8-BIT
16-BIT
OUTPUT MODE OUTPUT MODE
N/A
CbCr
PVDD_1.8V
EXTERNAL
LOOP FILTER
10nF
DVDDIO _3.3V
82nF
4kΩ
52
1.69kΩ
ALSB
TIE HI: I2C ADDRESS = 42
TIE LOW: I2C ADDRESS = 40
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
SDATA
20
LLC
AGND
AGND
AGND
TEST_0
53
33Ω
LLC
SCLK
05700-049
32
37
43
34
54
3
10
24
57
SDA
33Ω
DGND
DGND
DGND
DGND
SCLK
NC = NO CONNECT
Figure 58. 64-Lead LQFP Typical Connection Diagram
Rev. J | Page 109 of 114
ADV7180
Data Sheet
ANALOG_INPUT_1
Y
0.1µF
AIN1
36Ω
THE SUGGESTED INPUT ARRANGEMENT
IS AS SEEN ON THE EVAL BOARD AND IS
DIRECTLY SUPPORTED BY INSEL.
39Ω
ANALOG_INPUT_2
CVBS
DVDD _1.8V
DVDD _1.8V
0.1µF
0.1µF
AIN2
36Ω
10nF
0.1µF
10nF
39Ω
DVDDIO_3.3V
ANALOG_INPUT_3
YC_Y
AVDD _1.8V
0.1µF
AIN3
36Ω
0.1µF
ANALOG_INPUT_4
Cr
PVDD_1.8V
10nF
0.1µF
0.1µF
0.1µF
DVDDIO_3.3V
10nF
39Ω
0.1µF
10nF
10nF
36Ω
27
AIN2
39Ω
33
AIN3
ANALOG_INPUT_6
YC_C
0.1µF
AIN4
AIN6
36Ω
34
35
AIN5
39Ω
36
AIN6
AVDD
25
18
31
2
P[0:7]
PVDD
AIN1
DVDD
26
AIN1
AIN5
DVDD
0.1µF
DVDDIO
ANALOG_INPUT_5
Cb
4
39Ω
DVDDIO
36Ω
44
AIN4
P0
P1
P2
P3
P4
P5
P6
P7
AIN2
AIN3
AIN4
AIN5
22
20
12
11
10
9
8
7
P0
P1
P2
P3
P4
P5
P6
P7
AIN6
ADV7180WBST48Z
LQFP–48
KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME
30
SIDE OF THE PCB AS THE ADV7180.
VREFN
0.1µF
29
17
47pF
INTRQ
VREFP
GPO3
GPO2
GPO1
GPO0
XTAL
VS/FIELD
28.63636MHz
*
46
41
42
6
5
45
INT
GPO3
GPO2
GPO1
GPO0
VS/FIELD
1MΩ
16
47pF
HS
XTAL1
SFL
37
RESET
21
POWER_DOWN
RESET
NC
PWRDWN
ELPF
47
3
15, 48
24
HS
SFL
PVDD_1.8V
EXTERNAL
LOOP FILTER
10nF
DVDDIO _3.3V
82nF
4kΩ
38
1.69kΩ
ALSB
TIE HI: I2C ADDRESS = 42
TIE LOW: I2C ADDRESS = 40
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
14
LLC
NOTES
1. NC = NO CONNECT.
*REFER TO ANALOG DEVICES CRYSTAL APPLICATION NOTE FOR PROPER CAPACITOR LOADING
Figure 59. 48-Lead LQFP Typical Connection Diagram
Rev. J | Page 110 of 114
05700-061
32
SDATA
AGND
AGND
AGND
39
33Ω
LLC
SCLK
23
28
40
1
13
19
43
SDA
33Ω
DGND
DGND
DGND
DGND
SCLK
Data Sheet
ADV7180
ANALOG_INPUT_1
36Ω
ANALOG_INPUT_2
36Ω
DVDD _1.8V
0.1µF
DVDDIO
0.1µF
39Ω
0.1µF
10nF
10nF
0.1µF
AIN2
PVDD _1.8V
DVDDIO_3.3V
39Ω
0.1µF
AVDD _1.8V
10nF
23
AIN2
24
AIN3
25
RESET
AIN1
AIN2
18
22
30
AIN3
RESET
ADV7180KCP32Z
KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE
21
OF THE PCB AS THE ADV7180.
LFCSP–32
P[0:7]
PVDD
AIN1
AVDD
19
DVDD
39Ω
DVDD
3
AIN3
14
0.1µF
DVDDIO
36Ω
0.1µF
10nF
DVDD_1.8V
ANALOG_INPUT_3
AVDD_1.8V
AIN1
P0
P1
P2
P3
P4
P5
P6
P7
16
15
10
9
8
7
6
5
P0
P1
P2
P3
P4
P5
P6
P7
YCrCb
8-BIT
656 DATA
VREFN
0.1µF
20
VREFP
LLC
INTRQ
LOCATE CLOSE TO, AND ON THE
SAME SIDE AS, THE ADV7180.
13
47pF
28.63636MHz
SFL
XTAL
VS/FIELD
1MΩ
HS
12
47pF
11
32
4
31
1
LLC
INTRQ
SFL
VS/FIELD
HS
XTAL1
DVDDIO
4kΩ
26
ALSB
PVDD _1.8V
ALSB TIED HI ≥ I2C ADDRESS = 42h
ALSB TIED LOW ≥ I2C ADDRESS = 40h
EXTERNAL
LOOP FILTER
ELPF
DGND
SDATA
1.69kΩ
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
05700-056
29
27
10nF
82nF
SCLK
DGND
SDA
28
2
SCLK
17
Figure 60. 32-Lead LFCSP Typical Connection Diagram
Rev. J | Page 111 of 114
ADV7180
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
0.30
0.25
0.18
32
25
1
24
0.50
BSC
*3.75
3.60 SQ
3.55
EXPOSED
PAD
17
0.80
0.75
0.70
8
16
9
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
08-16-2010-B
TOP VIEW
0.50
0.40
0.30
PIN 1
INDICATOR
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 61. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
0.30
0.25
0.18
31
40
30
0.50
BSC
1
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
4.25
4.10 SQ
3.95
EXPOSED
PAD
21
0.45
0.40
0.35
10
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 62. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-9)
Dimensions shown in millimeters
Rev. J | Page 112 of 114
PIN 1
INDICATOR
05-06-2011-A
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Data Sheet
ADV7180
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
16
33
32
17
0.08
COPLANARITY
VIEW A
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
051706-A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 63. 64-Lead Low Profile Quad Flat Package [LQFP]
10 mm × 10 mm Body
(ST-64-2)
Dimensions shown in millimeters
0.75
0.60
0.45
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 64. 48-Lead Low Profile Quad Flat Package [LQFP]
7 mm × 7 mm Body
(ST-48)
Dimensions shown in millimeters
Rev. J | Page 113 of 114
24
0.27
0.22
0.17
051706-A
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
ADV7180
Data Sheet
ORDERING GUIDE
Model1, 2
ADV7180KCP32Z
ADV7180KCP32Z-RL
ADV7180BCPZ
ADV7180BCPZ-REEL
ADV7180BSTZ
ADV7180BSTZ-REEL
ADV7180WBCP32Z
ADV7180WBCP32Z-RL
ADV7180WBCPZ
ADV7180WBCPZ-REEL
ADV7180WBSTZ
ADV7180WBSTZ-REEL
ADV7180WBST48Z
ADV7180WBST48Z-RL
ADV7180KST48Z
ADV7180KST48Z-RL
ADV7180BST48Z
ADV7180BST48Z-RL
ADV7180BCP32Z
ADV7180BCP32Z-RL
EVAL-ADV7180LQEBZ
EVAL-ADV7180LFEBZ
EVAL-ADV7180-32EBZ
1
2
Temperature Range
−10°C to +70°C
−10°C to +70°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−10°C to +70°C
−10°C to +70°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board for the 64-Lead LQFP
Evaluation Board for the 40-Lead LFCSP
Evaluation Board for the 32-Lead LFCSP
Package Option
CP-32-12
CP-32-12
CP-40-9
CP-40-9
ST-64-2
ST-64-2
CP-32-12
CP-32-12
CP-40-9
CP-40-9
ST-64-2
ST-64-2
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
CP-32-12
CP-32-12
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADV7180W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models, and designers should
review the product Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific automotive reliability reports for these models.
Note that the ADV7180 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and
processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can
withstand surface-mount soldering at up to 255°C (±5°C).
In addition, it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be
soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2006-2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05700-0-1/15(J)
Rev. J | Page 114 of 114