NCP4894 1.8 Watt Differential Audio Power Amplifier with Selectable Shutdown The NCP4894 is a differential audio power amplifier designed for portable communication device applications. This feature and the excellent audio characteristics of the NCP4894 are a guarantee of a high quality sound, for example, in mobile phones applications. With a 10% THD+N value the NCP4894 is capable of delivering 1.8 W of continuous average power to an 8.0 W load from a 5.5 V power supply. With the same load conditions and a 5.0 V battery voltage, it ensures 1.0 W to be delivered with less than 0.01% distortion. The NCP4894 provides high quality audio while requiring few external components and minimal power consumption. It features a low−power consumption shutdown mode. To be flexible, shutdown may be enabled by either a logic high or low depending on the voltage applied on the SD MODE pin. The NCP4894 contains circuitry to prevent from “pop and click” noise that would otherwise occur during turn−on and turn−off transitions. For maximum flexibility, the NCP4894 provides an externally controlled gain (with resistors), as well as an externally controlled turn−on time (with bypass capacitor). Due to its excellent PSRR, it can be directly connected to the battery, saving the use of an LDO. This device is available in 9−Pin Flip−Chip, Micro−10 and DFN10 3x3 mm packages. Features • • • • • • • • • • • http://onsemi.com MARKING DIAGRAMS 1 9−PIN FLIP−CHIP FC SUFFIX CASE 499AL A3 xxxG AYWW C1 A1 xxxx AYWG G Micro−10 DM SUFFIX CASE 846B 8 1 DFN10 MN SUFFIX CASE 485C 1 1 xxx ALYWG G xxxx = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W, WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) Differential Amplification Shutdown High or Low Selectivity 1.0 W to an 8.0 W Load from a 5.0 V Power Supply Superior PSRR: Direct Connection to the Battery “Pop and Click” Noise Protection Circuit Ultra Low Current Shutdown Mode 2.2 V−5.5 V Operation External Gain Configuration Capability External Turn−on Configuration Capability Thermal Overload Protection Circuitry Pb−Free Packages are Available ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. Typical Applications • Portable Electronic Devices • PDAs • Mobile Phones © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 9 1 Publication Order Number: NCP4894/D NCP4894 Rf1 20 kW VP Cs Ci1 Negative Diff Input from DAC Ri1 VP INM 390 nF 20 kW 1 mF − + BYPASS OUTA VP BYPASS Cb VMC BRIDGE 1 mF RL 8W SHUTDOWN CONTROL SD MODE 0 0 1 1 SD SELECT 0 1 0 1 Positive Diff Input from DAC Ci2 Status Shutdown On On Shutdown Ri2 SD SELECT SHUTDOWN CONTROL SD MODE INP BYPASS + − 390 nF 20 kW OUTB VM 20 kW Rf2 Figure 1. Typical NCP4894 Application Circuit with Differential Input http://onsemi.com 2 NCP4894 Rf2 20 kW VP Cs 1 mF VP Ci1 Left Channel Input 390nF Ri1 INM 20 kW − OUTA + BYPASS Co1 47uF VP BYPASS Cb SHUTDOWN CONTROL SD MODE SD SELECT Status 0 Shutdown 0 0 1 On 1 On 0 Shutdown 1 1 Ci2 Right Channel Input 390nF Ri2 32W / 16W VMC BRIDGE 1 mF Earpiece SD SELECT SHUTDOWN CONTROL SD MODE INP Co2 + BYPASS − 20 kW OUTB 47uF VM Rf1 20 kW Figure 2. Typical NCP4894 Application Circuit for Driving Earpiece http://onsemi.com 3 32W / 16W NCP4894 PIN CONNECTIONS 9−Pin Flip−Chip A1 INP A2 Micro−10 DFN10 A3 BYPASS OUTB B1 B2 B3 VP SD MODE VM C1 C2 C3 SD SELECT 1 1 10 OUTA INM 2 9 VP INM 2 9 VP SD MODE INP 3 4 8 7 NC VM SD MODE 3 8 NC BYPASS 5 6 OUTB INP 4 7 VM BYPASS 5 6 OUTB (Top View) INM 10 OUTA SD SELECT SD SELECT OUTA (Top View) (Top View) PIN DESCRIPTION 9−Pin Flip−Chip Micro−10/DFN10 Type Symbol Description A1 4 I INP A2 5 O BYPASS A3 6 I OUTB B1 9 I VP B2 3 I SD MODE B3 7 I VM Ground C1 2 I INM Negative Differential Input C2 1 O SD SELECT C3 10 I OUTA Positive Differential Input Bypass Capacitor Pin which Provides the Common Mode Voltage Negative BTL Output Positive Analog Supply of the Cell Shutdown High or Low Selectivity (Note 1) (Note 1) Positive BTL Output 1. The SD SELECT pin must be toggled to the same state as the SD MODE pin to force the device in shutdown mode. http://onsemi.com 4 NCP4894 MAXIMUM RATINGS (Note 2) Rating Symbol Value Unit VP 6.0 V Supply Voltage Operating Supply Voltage Op VP 2.2 to 5.5 V − Input Voltage Vin −0.3 to Vcc +0.3 V Max Output Current Iout 500 mA Power Dissipation (Note 3) Pd Internally Limited − Operating Ambient Temperature TA −40 to +85 °C Max Junction Temperature TJ 150 °C Storage Temperature Range Thermal Resistance Junction−to−Air ESD Protection Micro−10 DFN 3x3 mm 9−Pin Flip−Chip Human Body Model (HBM) (Note 5) Machine Model (MM) (Note 6) Latchup Current at TA = 85°C (Note 7) Tstg −65 to +150 °C RqJA 200 70 (Note 4) °C/W − > 2000 > 200 V − 100 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C. 3. The thermal shutdown set to 160°C (typical) avoids irreversible damage on the device due to power dissipation. For further information see page 7. 4. For the 9−Pin Flip−Chip CSP package, the RqJA is highly dependent of the PCB Heatsink area. For example, RqJA can equal 195°C/W with 50 mm2 total area and also 135°C/W with 500 mm2. For further information see page 10. The bumps have the same thermal resistance and all need to be connected to optimize the power dissipation. 5. Human Body Model, 100 pF discharge through a 1.5 kW resistor following specification JESD22/A114. 6. Machine Model, 200 pF discharged through all pins following specification JESD22/A115. 7. Maximum ratings per JEDEC standard JESD78. http://onsemi.com 5 NCP4894 ELECTRICAL CHARACTERISTICS Limits apply for TA between −40°C to +85°C (Unless otherwise noted). Characteristic Supply Quiescent Current Symbol Conditions Min (Note 8) Typ Max (Note 8) Idd VP = 3.0 V, No Load VP = 5.0 V, No Load − − 1.9 2.1 − − VP = 3.0 V, 8.0 W VP = 5.0 V, 8.0 W − − 2.0 2.2 − 4.0 Unit mA Common Mode Voltage Vcm − − VP/2 − V Shutdown Current ISD For VP between 2.2 V to 5.5 V SDM = SDS = GND TA = 25°C TA = −40°C to +85°C − − 20 − 600 2.0 nA mA SD SELECT Threshold High VSDIH − 1.4 − − V SD SELECT Threshold Low VSDIL − − − 0.4 V Turning On Time (Note 10) TWU Cby = 1.0 mF − 140 − ms Turning Off Time (Note 10) TSD − − 20 − ms Vloadpeak VP = 3.0 V, RL = 8.0 W − 2.5 − V VP = 5.0 V, RL = 8.0 W (Note 9) TA = 25°C TA = −40°C to +85°C 4.0 3.85 4.3 − − − VP = 3.0 V, RL = 8.0 W THD + N < 0.1% VP = 3.3 V, RL = 8.0 W THD + N < 0.1% VP = 5.0 V, RL = 8.0 W THD + N < 0.1% − 0.39 − − 0.48 − − 1.08 − VOS For VP between 2.2 V to 5.5 V −30 1.0 30 PSRR V+ G = 2.0, RL = 8.0 W VPripple_pp = 200 mV Cby = 1.0 mF Input Terminated with 10 W Output Swing Rms Output Power Output Offset Voltage Power Supply Rejection Ratio Efficiency Thermal Shutdown Temperature Total Harmonic Distortion PO h W mV dB F = 217 Hz VP = 5.0 V VP = 3.0 V − − −80 −80 − − F = 1.0 kHz VP = 5.0 V VP = 3.0 V − − −85 −85 − − VP = 3.0 V, Porms = 380 mW VP = 5.0 V, Porms = 1.0 W − − 64 63 − − % − 160 − °C VP = 3.0 V, F = 1.0 kHz RL = 8.0 W, AV = 2.0 PO = 0.32 W − − − − 0.007 − − − − % VP = 5.0 V, F = 1.0 kHz RL = 8.0 W, AV = 2.0 PO = 1.0 W − − − − 0.006 − − − − Tsd THD V 8. Min/Max limits are guaranteed by design, test or statistical analysis. 9. This parameter is not tested in production for 9−Pin Flip−Chip CSP package in case of a 5.0 V power supply, however it is correlated based on a 3.0 V power supply testing. 10. See page 12 for a theoretical approach of these parameters. http://onsemi.com 6 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS 0.100 0.100 VP = 3 V RL = 8 W Pout = 250 mW THD+N(%) THD+N(%) VP = 5 V RL = 8 W Pout = 400 mW 0.010 0.010 0.001 0.001 10 100 1000 10000 100000 10 100000 Figure 4. THDN versus Frequency 0.100 0.100 VP = 3.6 V RL = 4 W Pout = 300 mW THD+N(%) VP = 2.6 V RL = 8 W Pout = 150 mW THD+N(%) 10000 FREQUENCY (Hz) Figure 3. THDN versus Frequency 0.010 0.010 0.001 0.001 10 100 1000 10000 100000 10 100 FREQUENCY (Hz) 1000 10000 100000 FREQUENCY (Hz) Figure 5. THDN versus Frequency Figure 6. THDN versus Frequency 10 10 VP = 5 V RL = 8 W f = 1 kHz VP = 3 V RL = 8 W f = 1 kHz 1 THD+N(%) 1 THD+N(%) 1000 100 FREQUENCY (Hz) 0.1 0.01 0.1 0.01 0.001 0.001 0 200 400 600 800 1000 1200 0 OUTPUT POWER (mW) 100 200 300 400 OUTPUT POWER (mW) Figure 7. THDN versus Output Power Figure 8. THDN versus Output Power http://onsemi.com 7 500 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS 10 10 VP = 2.6 V RL = 8 W f = 1 kHz VP = 3.6 V RL = 4 W f = 1 kHz 1 THD+N(%) THD+N(%) 1 0.1 0.1 0.01 0.01 0.001 0.001 0 100 200 0 300 Figure 9. THDN versus Output Power −20 1400 −30 PSSR(dB) OUTPUT POWER (mW) −10 1600 THD+N = 10% 1200 1000 800 THD+N = 1% −40 −50 −70 400 −80 0 2.5 3.0 3.5 4.0 4.5 5.0 −100 100 5.5 Figure 11. THDN versus Output Power 10000 100000 0 VP = 3 V RL = 8 W Vripple = 200 mV pk=pk Inputs grounded with 10 W Av = 1 Cb = 1 mF −10 −20 −30 PSSR(dB) PSSR(dB) 1000 Figure 12. PSRR @ VP = 5 V 0 −60 −40 −50 −70 −80 −80 −90 VP = 2.2 V RL = 8 W Vripple = 200 mV pk−pk Inputs grounded with 10 W Av = 1 Cb = 1 mF −60 −70 −100 100 VP = 5 V RL = 8 W Vripple = 200 mV pk−pk Inputs grounded with 10 W Av = 1 Cb = 1 mF FREQUENCY (Hz) POIWER SUPPLY (V) −50 1000 −90 200 −40 800 −60 600 −30 600 0 RL = 8 W f = 1 kHz 1800 −20 400 Figure 10. THDN versus Output Power 2000 −10 200 OUTPUT POWER (mW) OUTPUT POWER (mW) −90 1000 10000 100000 −100 100 FREQUENCY (Hz) 1000 10000 FREQUENCY (Hz) Figure 13. PSRR @ VP = 3 V Figure 14. PSRR @ VP = 2.2 V http://onsemi.com 8 100000 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS 0 −20 PSSR(dB) −30 −40 −10 −20 −30 PSRR(dB) −10 0 VP = 3 V RL = 8 W Vripple = 200 mV pk−pk Inputs grounded with 10 W Av = 1 −50 −60 −70 Cb = 4.7 mF −50 −60 Cb = 1 mF −70 −80 −90 1000 Av = 1 −90 Cb = 0.47 mF −100 100 10000 −100 100 100000 1000 Figure 20. PSRR versus Cb @ VP = 3 V Figure 15. PSRR versus Av @ VP = 3 V −20 VP = 5 V RL = 8 W Av = 1 Cb = 1 mF CMRR(dB) −30 VP = 3 V RL = 8 W Av = 1 Cb = 1 mF −40 −50 −50 −60 100 1000 10000 −60 100 100000 1000 Figure 16. CMRR @ VP = 5 V 100000 Figure 17. CMRR @ VP = 3 V −20 100 OUTPUT NOISE VOLTAGE (mVrms) CMRR(dB) 10000 FREQUENCY (Hz) FREQUENCY (Hz) VP = 2.2V RL = 8 W Av = 1 Cb = 1 mF −40 −50 −60 100 100000 FREQUENCY (Hz) −40 −30 10000 FREQUENCY (Hz) −20 CMRR(dB) Av = 5 −40 −80 −30 VP = 3 V RL = 8 W Vripple = 200 mV pk−pk Inputs grounded with 10 W 1000 10000 100000 VP = 3.6 V RL = 8 W Av = 1 Cb = 1 mF NCP4894 ON 10 NCP4894 OFF 1 10 100 1000 10000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 18. CMMR @ VP = 2.2 V Figure 19. Noise Floor @ VP = 3.6 V http://onsemi.com 9 100000 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS Ch1 = OUTA Ch2 = OUTB Ch3 = Shutdown & Math1 = OUTA−OUTB Ch1 = OUTA Ch2 = OUTB Ch3 = Shutdown & Math1 = OUTA−OUTB Figure 21. Turning−on Sequence @ VP = 5 V and f = 1 kHz Figure 22. Turning−on Sequence Zoom @ VP = 5 V and f = 1 kHz Ch1 = OUTA Ch2 = OUTB Ch3 = Shutdown & Math1 = OUTA−OUTB Ch1 = OUTA Ch2 = OUTB Ch3 = Shutdown & Math1 = OUTA−OUTB Figure 23. Turning−off Sequence @ VP = 5 V and f = 1 kHz Figure 24. Turning−off Sequence Zoom @ VP = 5 V and f = 1 kHz http://onsemi.com 10 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS 0.3 PD, POWER DISSIPATION (W) PD, POWER DISSIPATION (W) 0.7 0.6 0.5 0.4 VP = 5 V RL = 8 W F = 1 kHz THD + N < 0.1% 0.3 0.2 0.1 0 0.25 0.2 0.15 VP = 3.3 V RL = 8 W F = 1 kHz THD + N < 0.1% 0.1 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 Pout, OUTPUT POWER (W) Figure 25. Power Dissipation versus Output Power 0.4 0.5 0.4 PD, POWER DISSIPATION (W) PD, POWER DISSIPATION (W) 0.3 Figure 26. Power Dissipation versus Output Power 0.25 0.2 0.15 VP = 3 V RL = 8 W F = 1 kHz THD + N < 0.1% 0.1 0.05 0 0.35 RL = 4 W 0.3 0.25 0.2 RL = 8 W 0.15 0.1 VP = 2.6 V F = 1 kHz THD + N < 0.1% 0.05 0 0 0.1 0.2 0.3 0.4 0 0.05 0.1 Pout, OUTPUT POWER (W) 0.15 0.2 0.25 0.3 0.35 0.4 Pout, OUTPUT POWER (W) Figure 27. Power Dissipation versus Output Power Figure 28. Power Dissipation versus Output Power 180 DIE TEMPERATURE (°C) @ AMBIENT TEMPERATURE 25°C 700 PD, POWER DISSIPATION (mW) 0.2 Pout, OUTPUT POWER (W) PCB Heatsink Area 600 200 mm2 500 50 mm2 500 mm2 400 300 200 PDmax = 633 mW for VP = 5 V, RL = 8 W 100 0 0 20 40 Maximum Die Temperature 150°C 160 140 120 VP = 4.2 V 100 80 80 100 120 140 160 VP = 3.3 V 60 40 60 VP = 5 V VP = 2.6 V 50 100 150 200 250 PCB HEATSINK AREA (mm2) TA, AMBIENT TEMPERATURE (°C) Figure 29. Power Derating − 9−Pin Flip−Chip CSP Figure 30. Maximum Die Temperature versus PCB Heatsink Area http://onsemi.com 11 300 NCP4894 APPLICATION INFORMATION Detailed Description During the shutdown state, the DC quiescent current has a typical value of 10 nA. The NCP4894 audio amplifier can operate under 2.6 V until 5.5 V power supply. It delivers 320 mW rms output power to 4.0 W load (VP = 2.6 V) and 1.0 W rms output power to 8.0 W load (VP = 5.0 V). The structure of the NCP4894 is basically composed of two identical internal power amplifiers. Both are externally configurable with gain−setting resistors Rin and Rf (the closed−loop gain is fixed by the ratios of these resistors). The load is driven differentially through OUTA and OUTB outputs. This configuration eliminates the need for an output coupling capacitor. Current Limit Circuit The maximum output power of the circuit (Porms = 1.0 W, VP = 5.0 V, RL = 8.0 W) requires a peak current in the load of 500 mA. In order to limit the excessive power dissipation in the load when a short−circuit occurs between both outputs, the current limit in the load is fixed to 800 mA. Thermal Overload Protection Internal amplifiers are switched off when the temperature exceeds 160°C, and will be switched on again only when the temperature decreases below 140°C. The NCP4894 is unity−gain stable and requires no external components besides gain−setting resistors, an input coupling capacitor and a proper bypassing capacitor in the typical application. Both internal amplifiers are externally configurable (Rf and Rin) with gain configuration. The differential−ended amplifier presents two major advantages: − The possible output power is four times larger (the output swing is doubled) as compared to a single−ended amplifier under the same conditions. − Output pins (OUTA and OUTB) are biased at the same potential VP/2, this eliminates the need for an output coupling capacitor required with a single−ended amplifier configuration. The differential closed loop−gain of the amplifier is Internal Power Amplifier The output PMOS and NMOS transistors of the amplifier were designed to deliver the output power of the specifications without clipping. The channel resistance (Ron) of the NMOS and PMOS transistors does not exceed 0.6 W when they drive current. The structure of the internal power amplifier is composed of three symmetrical gain stages, first and medium gain stages are transconductance gain stages to obtain maximum bandwidth and DC gain. Turn−On and Turn−Off Transitions A cycle with a turn−on and turn−off transition is illustrated with plots that show both single ended signals on the previous page. In order to eliminate “pop and click” noises during transitions, output power in the load must be slowly established or cut. When logic high is applied to the shutdown pin, the bypass voltage begins to rise exponentially and once the output DC level is around the common mode voltage, the gain is established slowly (20 ms). Using this turn−on mode, the device is optimized in terms of rejection of “pop and click” noises. A theoretical value of turn−on time at 25°C is given by the following formula. Cby: bypass capacitor R: internal 150 k resistor with a 25% accuracy Ton = 0.95 * R * Cby The device has the same behavior when it is turned−off by a logic low on the shutdown pin. During the shutdown mode, amplifier outputs are connected to the ground. However, to totally cut the output audio signal, you only need to wait for 20 ms. given by Avd + * V Rf + orms . Vorms is the rms value of Rin Vinrms the voltage seen by the load and Vinrms is the rms value of the input differential signal. Output power delivered to the load is given by Porms + (Vopeak)2 (Vopeak is the peak differential 2 * RL output voltage). When choosing gain configuration to obtain the desired output power, check that the amplifier is not current limited or clipped. The maximum current which can be delivered to the load is 500 mA Iopeak + Shutdown Function The device enters shutdown mode once the SD SELECT and SD MODE pins are in the same logic state. This brings flexibility to the design, as the SD MODE pin must be permanently connected to VP or GND on the PCB. If the SD SELECT pin is not connected to the output of a microcontroller or microprocessor, it’s not advisable to let it float. A pulldown or pullup resistor is then suitable. http://onsemi.com 12 Vopeak . RL NCP4894 Gain−Setting Resistor Selection (Rin and Rf) The size of the capacitor must be large enough to couple in low frequencies without severe attenuation. However a large input coupling capacitor requires more time to reach its quiescent DC voltage (VP/2) and can increase the turn−on pops. An input capacitor value between 0.1 m and 0.39 mF performs well in many applications (With Rin = 22 kW). Rin and Rf set the closed−loop gain of both amplifiers. In order to optimize device and system performance, the NCP4894 should be used in low gain configurations. The low gain configuration minimizes THD + noise values and maximizes the signal to noise ratio, and the amplifier can still be used without running into the bandwidth limitations. A closed loop gain in the range from 2 to 5 is recommended to optimize overall system performance. An input resistor (Rin) value of 22 kW is realistic in most applications, and doesn’t require the use of a very large capacitor Cin. Bypass Capacitor Selection (Cby) The bypass capacitor Cby provides half−supply filtering and determines how fast the NCP4894 turns on. This capacitor is a critical component to minimize the turn−on pop. A 1.0 mF bypass capacitor value (Cin = < 0.39 mF) should produce clickless and popless shutdown transitions. The amplifier is still functional with a 0.1 mF capacitor value but is more susceptible to “pop and click” noises. Thus, a 1.0 mF bypassing capacitor is recommended. Input Capacitor Selection (Cin) The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a high−pass filter with Rin, the cut−off frequency is given by fc + 1 . 2 * P * Rin * Cin R4 VP J1 20 kW VP C4 1 mF GND C2 R2 1 mF 20 kW VP INM − + BYPASS OUTA VP BYPASS C3 J2 VP 100 kW R3 J5 VMC BRIDGE 1 mF J3 RL 8W J4 SD SELECT SHUTDOWN CONTROL SD MODE C1 R1 1 mF 20 kW INP BYPASS + − VM 20 kW J10 R5 Figure 31. Demonstration Board Schematic http://onsemi.com 13 OUTB NCP4894 Silkscreen Layer Top Layer Bottom Layer Figure 32. Demonstration Board for 9−Pin Flip−Chip CSP Device − PCB Layers http://onsemi.com 14 NCP4894 BILL OF MATERIAL Item Part Description Ref PCB Footprint Manufacturer Manufacturer Reference 1 NCP4894 Audio Amplifier − − ON Semiconductor NCP4894 2 SMD Resistor 100 kW R3 0603 Vishay−Draloric CRCW0603 Series 3 SMD Resistor 20 kW R1, R2 R4, R5 0603 Vishay−Draloric CRCW0603 Series 4 Ceramic Capacitor 1.0 mF 6.3 V X5R C1, C2 C3, C4 0603 Murata GRM188 Series 5 Jumper Header Vertical Mount, 2*1, 100 mils J4, J5 − − − 6 Jumper Connector, 400 mils J10 − − − 7 I/O Connector. It can be plugged by MC−1,5/3−ST−3,81 (Phoenix Contact Reference) J2 − Phoenix Contact MC−1,5/3−G 8 I/O Connector. It can be plugged by BLZ5.08/2 (Weidmüller Reference) J1, J3 − Weidmüller SL5.08/2/90B ORDERING INFORMATION Marking Package Shipping† NCP4894FCT1 Device MAI 9−Pin Flip−Chip 3000 / Tape & Reel NCP4894FCT1G MAI 9−Pin Flip−Chip (Pb−Free) 3000 / Tape & Reel NCP4894DMR2 MAK Micro−10 4000 / Tape & Reel NCP4894DMR2G MAK Micro−10 (Pb−Free) 4000 / Tape & Reel NCP4894MNR2 4894 DFN10 3000 / Tape & Reel NCP4894MNR2G 4894 DFN10 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NOTE: This product is offered with either autectic (SnPb−tin/lead) or lead−free solder bumps (G suffix) depending on the PCB assembly process. The NCP4894FCT1G, NCP4894DMR2G, NCP4894MNR2G version requires a lead−free solder paste and should not be used with a SnPb solder paste. http://onsemi.com 15 NCP4894 PACKAGE DIMENSIONS 9−PIN FLIP−CHIP FC SUFFIX CASE 499AL−01 ISSUE O −A− 4X NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. D 0.10 C −B− E DIM A A1 A2 D E b e D1 E1 TOP VIEW A 0.10 C 0.05 C −C− A2 A1 SIDE VIEW SEATING PLANE MILLIMETERS MIN MAX 0.540 0.660 0.210 0.270 0.330 0.390 1.450 BSC 1.450 BSC 0.290 0.340 0.500 BSC 1.000 BSC 1.000 BSC SOLDERING FOOTPRINT* 0.50 0.0197 D1 e C B e E1 0.50 0.0197 A 9X b 1 2 3 0.05 C A B 0.03 C BOTTOM VIEW 0.265 0.01 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 16 NCP4894 PACKAGE DIMENSIONS Micro−10 DM SUFFIX CASE 846B−03 ISSUE D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION “A” DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION “B” DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B−01 OBSOLETE. NEW STANDARD 846B−02 −A− −B− K D 8 PL 0.08 (0.003) PIN 1 ID G 0.038 (0.0015) −T− SEATING PLANE M T B S A S DIM A B C D G H J K L C H L J MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.30 0.50 BSC 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 SOLDERING FOOTPRINT* 10X 1.04 0.041 0.32 0.0126 3.20 0.126 8X 10X 4.24 0.167 0.50 0.0196 SCALE 8:1 5.28 0.208 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 17 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.012 0.020 BSC 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028 NCP4894 PACKAGE DIMENSIONS DFN10 MN SUFFIX CASE 485C−01 ISSUE A D PIN 1 REFERENCE A B ÇÇÇ ÇÇÇ ÇÇÇ EDGE OF PACKAGE L1 E DETAIL A Bottom View (Optional) 0.15 C 2X TOP VIEW 0.15 C 2X DIM A A1 A3 b D D2 E E2 e K L L1 (A3) DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. A 10X 0.08 C SIDE VIEW SEATING PLANE A1 C EXPOSED Cu D2 10X DETAIL A MOLD CMPD e L 1 5 A1 A3 DETAIL B Side View (Optional) E2 10X ÉÉ ÉÉ MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.45 2.55 3.00 BSC 1.75 1.85 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 K SOLDERING FOOTPRINT* 10 10X b 0.10 C A B 0.05 C 6 2.6016 BOTTOM VIEW NOTE 3 2.1746 1.8508 3.3048 10X 0.5651 10X 0.3008 0.5000 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 18 NCP4894 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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