STMicroelectronics M95010-BN6TG/W 4kbit, 2kbit and 1kbit serial spi bus eeprom with high speed clock Datasheet

M95040
M95020, M95010
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
Single Supply Voltage:
– 4.5 to 5.5V for M950x0
– 2.5 to 5.5V for M950x0-W
– 1.8 to 5.5V for M950x0-R
High Speed
– 10MHz Clock Rate, 5ms Write Time
Status Register
BYTE and PAGE WRITE (up to 16 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
Table 1. Product List
Reference
Part Number
M95040
M95040
M95040-W
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
M95040-R
M95020
M95020
M95020-W
M95020-R
TSSOP8 (DW)
169 mil width
M95010
M95010
M95010-W
M95010-R
October 2004
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M95040, M95020, M95010
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M95040, M95020, M95010
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Write Status Register (WRSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Address Range Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12.Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13.Byte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Operating Conditions (M950x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating Conditions (M950x0-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Operating Conditions (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. DC Characteristics (M950x0, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. DC Characteristics (M950x0, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. DC Characteristics (M950x0-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. DC Characteristics (M950x0-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. DC Characteristics (M950x0-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. AC Characteristics (M950x0, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. AC Characteristics (M950x0, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. AC Characteristics (M950x0-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 21. AC Characteristics (M950x0-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 22. AC Characteristics (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 32
3/37
M95040, M95020, M95010
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 32
Figure 20.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 33
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
33
Figure 21.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 34
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 34
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27. How to Identify Present and Previous Products by the Process Identification Letter . . . 35
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4/37
M95040, M95020, M95010
SUMMARY DESCRIPTION
The M95040 is a 4 Kbit (512 x 8) electrically erasable programmable memory (EEPROM), accessed by a high speed SPI-compatible bus. The other
members of the family (M95020 and M95010) are
identical, though proportionally smaller (2 and 1
Kbit, respectively).
Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C,
D and Q, as shown in Table 2. and Figure 2..
The device is selected when Chip Select (S) is taken Low. Communications with the device can be
interrupted using Hold (HOLD). WRITE instructions are disabled by Write Protect (W).
Figure 3. DIP, SO and TSSOP Connections
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI01790D
Figure 2. Logic Diagram
Note: See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
VCC
Table 2. Signal Names
D
C
S
C
Serial Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
W
Write Protect
HOLD
Hold
VCC
Supply Voltage
VSS
Ground
Q
M95xxx
W
HOLD
VSS
AI01789C
5/37
M95040, M95020, M95010
SIGNAL DESCRIPTION
During all operations, V CC must be held stable and
within the specified valid range: VCC(min) to
VCC(max).
All of the input and output signals can be held High
or Low (according to voltages of VIH, VOH, VIL or
VOL, as specified in Table 13. to Table 17.). These
signals are described next.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives instructions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
6/37
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Write Protect (W). This input signal is used to
control whether the memory is write protected.
When Write Protect (W) is held Low, writes to the
memory are disabled, but other operations remain
enabled. Write Protect (W) must either be driven
High or Low, but must not be left floating.
M95040, M95020, M95010
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register instructions) have been clocked into the device.
Figure 4. shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
C Q D
C Q D
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
Bus Master
(ST6, ST7, ST9,
ST10, Others)
CS3
CS2
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI03746D
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
7/37
M95040, M95020, M95010
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. SPI Modes Supported
CPOL
CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
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M95040, M95020, M95010
OPERATING FEATURES
Power-up
When the power supply is turned on, V CC rises
from VSS to VCC.
During this time, the Chip Select (S) must be allowed to follow the V CC voltage. It must not be allowed to float, but should be connected to VCC via
a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Powerup, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first operation.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on V CC.
Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The device
consumes ICC, as specified in Table 13. to Table
17..
When Chip Select (S) is High, the device is deselected. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Standby
Power mode, and the device consumption drops
to ICC1.
Hold Condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect
of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
6.).
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 6. also shows what happens if the rising
and falling edges are not timed to coincide with
Serial Clock (C) being Low.
Figure 6. Hold Condition Activation
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
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M95040, M95020, M95010
Status Register
Figure 7. shows the position of the Status Register
in the control logic of the device. This register contains a number of control bits and status bits, as
shown in Table 3..
Bits b7, b6, b5 and b4 are always read as 1.
WIP bit. The Write In Progress bit is a volatile
read-only bit that is automatically set and reset by
the internal logic of the device. When set to a 1, it
indicates that the memory is busy with a Write cycle.
WEL bit. The Write Enable Latch bit is a volatile
read-only bit that is set and reset by specific instructions. When reset to 0, no WRITE or WRSR
instructions are accepted by the device.
BP1, BP0 bits. The Block Protect bits are nonvolatile read-write bits. These bits define the area
of memory that is protected against the execution
of Write cycles, as summarized in Table 4..
Table 3. Status Register Format
b7
b0
1
1
1
1
BP1
BP0
WEL
WIP
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Data Protection and Protocol Control
To help protect the device from data corruption in
noisy or poorly controlled environments, a number
of safety features have been built in to the device.
The main security measures can be summarized
as follows:
– The WEL bit is reset at power-up.
– Chip Select (S) must rise after the eighth clock
count (or multiple thereof) in order to start a
non-volatile Write cycle (in the memory array
or in the Status Register).
– Accesses to the memory array are ignored
during the non-volatile programming cycle,
and the programming cycle continues
unaffected.
– Invalid Chip Select (S) and Hold (HOLD)
transitions are ignored.
For any instruction to be accepted and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches the last bit of
the instruction, and before the next rising edge of
Serial Clock (C).
For this, “the last bit of the instruction” can be the
eighth bit of the instruction code, or the eighth bit
of a data byte, depending on the instruction (except in the case of RDSR and READ instructions).
Moreover, the "next rising edge of CLOCK" might
(or might not) be the next bus transaction for some
other device on the bus.
When a Write cycle is in progress, the device protects it against external interruption by ignoring
any subsequent READ, WRITE or WRSR instruction until the present cycle is complete.
Table 4. Write-Protected Block Size
Status Register Bits
Array Addresses Protected
Protected Block
BP1
BP0
0
0
0
10/37
M95040
M95020
M95010
none
none
none
none
1
Upper quarter
180h - 1FFh
C0h - FFh
60h - 7Fh
1
0
Upper half
100h - 1FFh
80h - FFh
40h - 7Fh
1
1
Whole memory
000h - 1FFh
00h - FFh
00h - 7Fh
M95040, M95020, M95010
MEMORY ORGANIZATION
The memory is organized as shown in Figure 7..
Figure 7. Block Diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Size of the
Read only
EEPROM
area
Y Decoder
Status
Register
1 Page
X Decoder
AI01272C
11/37
M95040, M95020, M95010
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 5..
If an invalid instruction is sent (one not contained
in Table 5.), the device automatically deselects itself.
Table 5. Instruction Set
Instruc
tion
Description
Instruction
Format
WREN
Write Enable
0000 X110
WRDI
Write Disable
0000 X100
RDSR
Read Status Register
0000 X101
WRSR
Write Status Register
0000 X001
READ
Read from Memory Array
0000 A8011
WRITE
Write to Memory Array
0000 A8010
Note: 1. A8 = 1 for the upper half of the memory array of the
M95040, and 0 for the lower half, and is Don’t Care for
other devices.
2. X = Don’t Care.
12/37
M95040, M95020, M95010
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in Figure 8., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
Figure 8. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI01441D
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 9., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
– Power-up
– WRDI instruction execution
– WRSR instruction completion
– WRITE instruction completion
– Write Protect (W) line being held Low.
Figure 9. Write Disable (WRDI) Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03790D
13/37
M95040, M95020, M95010
Read Status Register (RDSR)
One of the major uses of this instruction is to allow
the MCU to poll the state of the Write In Progress
(WIP) bit. This is needed because the device will
not accept further WRITE or WRSR instructions
when the previous Write cycle is not yet finished.
As shown in Figure 10., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte are then shifted in, on
Serial Data Input (D). The current state of the bits
in the Status Register is shifted out, on Serial Data
Out (Q). The Read Cycle is terminated by driving
Chip Select (S) High.
The Status Register may be read at any time, even
during a Write cycle (whether it be to the memory
area or to the Status Register). All bits of the Status Register remain valid, and can be read using
the RDSR instruction. However, during the current
Write cycle, the values of the non-volatile bits
(BP0, BP1) become frozen at a constant value.
The updated value of these bits becomes available when a new RDSR instruction is executed, after completion of the Write cycle. On the other
hand, the two read-only bits (Write Enable Latch
(WEL), Write In Progress (WIP)) are dynamically
updated during the on-going Write cycle.
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register instruction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Register (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 4.) becomes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protected mode has not been set.
Figure 10. Read Status Register (RDSR) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI01444D
14/37
M95040, M95020, M95010
Write Status Register (WRSR)
This instruction has no effect on bits b7, b6, b5, b4,
b1 and b0 of the Status Register.
As shown in Figure 11., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and data byte are then
shifted in on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High. Chip Select (S) must be driven High
after the rising edge of Serial Clock (C) that latches the eighth bit of the data byte, and before the
the next rising edge of Serial Clock (C). If this condition is not met, the Write Status Register
(WRSR) instruction is not executed. The selftimed Write Cycle starts, and continues for a peri-
od tW (as specified in Table 18. to Table 22.), at
the end of which the Write in Progress (WIP) bit is
reset to 0.
The instruction is not accepted, and is not executed, under the following conditions:
– if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
– if a Write Cycle is already in progress
– if the device has not been deselected, by Chip
Select (S) being driven High, after the eighth
bit, b0, of the data byte has been latched in
– if Write Protect (W) is Low.
Figure 11. Write Status Register (WRSR) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI01445B
15/37
M95040, M95020, M95010
Read from Memory Array (READ)
As shown in Figure 12., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address byte are
then shifted in, on Serial Data Input (D). For the
M95040, the most significant address bit, A8, is incorporated as bit b3 of the instruction byte, as
shown in Table 5.. The address is loaded into an
internal address register, and the byte of data at
that address is shifted out, on Serial Data Output
(Q).
If Chip Select (S) continues to be driven Low, an
internal bit-pointer is automatically incremented at
each clock cycle, and the corresponding data bit is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Table 6. Address Range Bits
Device
Address Bits
M95040
M95020
M95010
A8-A0
A7-A0
A6-A0
Figure 12. Read from Memory Array (READ) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
C
Instruction
D
A8
Byte Address
A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High Impedance
Q
7
6
5
4
3
2
1
0
AI01440E
Note: Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
16/37
M95040, M95020, M95010
Write to Memory Array (WRITE)
As shown in Figure 13., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Select (S) High after the rising edge of Serial Clock
(C) that latches the last data bit, and before the
next rising edge of Serial Clock (C) occurs anywhere on the bus. In the case of Figure 13., this
occurs after the eighth bit of the data byte has
been latched in, indicating that the instruction is
being used to write a single byte. The self-timed
Write cycle starts, and continues for a period tWC
(as specified in Table 18. to Table 22.), at the end
of which the Write in Progress (WIP) bit is reset to
0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 14., the next byte of input
data is shifted in. In this way, all the bytes from the
given address to the end of the same page can be
programmed in a single instruction.
If Chip Select (S) still continues to be driven Low,
the next byte of input data is shifted in, and is used
to overwrite the byte at the start of the current
page.
The instruction is not accepted, and is not executed, under the following conditions:
– if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
– if a Write cycle is already in progress
– if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the rising edge of Serial Clock
(C) that latches the last data bit, and before
the next rising edge of Serial Clock (C) occurs
anywhere on the bus)
– if Write Protect (W) is Low or if the addressed
page is in the region protected by the Block
Protect (BP1 and BP0) bits.
Figure 13. Byte Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction
D
A8
Byte Address
A7 A6 A5 A4 A3 A2 A1 A0 7
Data Byte
6
5
4
3
2
1
0
High Impedance
Q
AI01442D
Note: Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
17/37
M95040, M95020, M95010
Figure 14. Page Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction
Byte Address
A8
D
Data Byte 1
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
7
143
142
141
140
139
138
137
136
15+8N
14+8N
13+8N
12+8N
11+8N
10+8N
9+8N
24 25 26 27 28 29 30 31
8+8N
S
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte N
1
0
7
6
5
4
3
2
Data Byte 16
1
0
7
6
5
4
3
2
1
0
AI01443D
Note: Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
18/37
M95040, M95020, M95010
POWER-UP AND DELIVERY STATE
Power-up State
After Power-up, the device is in the following state:
– low power Standby Power mode
– deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be started).
– not in the Hold Condition
– the Write Enable Latch (WEL) is reset to 0
– Write In Progress (WIP) is reset to 0
The BP1 and BP0 bits of the Status Register are
unchanged from the previous power-down (they
are non-volatile bits).
Initial Delivery State
The device is delivered with the memory array set
at all 1s (FFh). The Block Protect (BP1 and BP0)
bits are initialized to 0.
19/37
M95040, M95020, M95010
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 7. may cause permanent damage to the device. These are stress ratings only, and operation
of the device at these, or any other conditions outside those indicated in the Operating sections of
this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 7. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering 1
Min.
Max.
Unit
–65
150
°C
See note 1
°C
VO
Output Voltage
–0.50
VCC+0.6
V
VI
Input Voltage
–0.50
6.5
V
VCC
Supply Voltage
–0.50
6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
–4000
4000
V
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
20/37
M95040, M95020, M95010
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 8. Operating Conditions (M950x0)
Symbol
VCC
Parameter
Min.
Max.
Unit
Supply Voltage
4.5
5.5
V
Ambient Operating Temperature (Device Grade 6)
–40
85
°C
Ambient Operating Temperature (Device Grade 3)
–40
125
°C
Min.
Max.
Unit
Supply Voltage
2.5
5.5
V
Ambient Operating Temperature (Device Grade 6)
–40
85
°C
Ambient Operating Temperature (Device Grade 3)
–40
125
°C
Min.
Max.
Unit
Supply Voltage
1.8
5.5
V
Ambient Operating Temperature
–40
85
°C
Min.
Max.
Unit
TA
Table 9. Operating Conditions (M950x0-W)
Symbol
VCC
Parameter
TA
Table 10. Operating Conditions (M950x0-R)
Symbol
VCC
TA
Parameter
Table 11. AC Measurement Conditions
Symbol
CL
Parameter
Load Capacitance
100
Input Rise and Fall Times
pF
50
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input and Output Timing Reference Voltages
0.3VCC to 0.7VCC
V
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 15. AC Measurement I/O Waveform
Input Levels
0.8VCC
0.2VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
AI00825B
21/37
M95040, M95020, M95010
Table 12. Capacitance
Symbol
COUT
CIN
Parameter
Test Condition
Max.
Unit
VOUT = 0V
8
pF
Input Capacitance (D)
VIN = 0V
8
pF
Input Capacitance (other pins)
VIN = 0V
6
pF
Output Capacitance (Q)
Min.
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 5MHz.
Table 13. DC Characteristics (M950x0, Device Grade 6)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
ICC1
Supply Current
Supply Current
(Standby Power mode)
Test Condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 5MHz,
VCC = 5 V, Q = open, Previous Product 2
5
mA
C = 0.1VCC/0.9VCC at 10MHz,
VCC = 5 V, Q = open, Present Product 3
5
mA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, Previous Product 2
10
µA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, Present Product 3
2
µA
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL1
Output Low Voltage
IOL = 2 mA, VCC = 5 V
0.4
V
VOH1
Output High Voltage
IOH = –2 mA, VCC = 5 V
0.8 VCC
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Previous product: identified by Process Identification letter K.
3. Present product: identified by Process Identification letter W or G.
22/37
V
M95040, M95020, M95010
Table 14. DC Characteristics (M950x0, Device Grade 3)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
ICC1
Supply Current
Supply Current
(Standby Power mode)
Test Condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 5 V, Q = open, Previous Product 2
5
mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open, Present Product 3
3
mA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, Previous Product 2
10
µA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, Present Product 3
5
µA
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL1
Output Low Voltage
IOL = 2 mA, VCC = 5 V
0.4
V
VOH1
Output High Voltage
IOH = –2 mA, VCC = 5 V
0.8 VCC
V
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Previous product: identified by Process Identification letter K.
3. Present product: identified by Process Identification letter W or G.
Table 15. DC Characteristics (M950x0-W, Device Grade 6)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
ICC1
Test Condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 2.5 V, Q = open, Previous Product 1
2
mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open, Present Product 2
2
mA
S = VCC , VCC = 2.5 V,
VIN = VSS or VCC, Previous Product 1
2
µA
S = VCC , VCC = 2.5 V
VIN = VSS or VCC, Present Product 2
1
µA
Supply Current
Supply Current
(Standby Power mode)
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL
Output Low Voltage
IOL = 1.5 mA, VCC = 2.5 V
0.4
V
VOH
Output High Voltage
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
V
Note: 1. Previous product: identified by Process Identification letter K.
2. Present product: identified by Process Identification letter W or G.
23/37
M95040, M95020, M95010
Table 16. DC Characteristics (M950x0-W, Device Grade 3)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
Test Condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 2.5 V, Q = open, Previous Product 1
2
mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open, Present Product 2
2
mA
S = VCC , VCC = 2.5 V, VIN = VSS or VCC
2
µA
ICC1
Supply Current
(Standby Power mode)
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL
Output Low Voltage
IOL = 1.5 mA, VCC = 2.5 V
0.4
V
VOH
Output High Voltage
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
V
Note: 1. Previous product: identified by Process Identification letter K.
2. Present product: identified by Process Identification letter W or G.
Table 17. DC Characteristics (M950x0-R)
Symbol
Parameter
Max.1
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1 VCC/0.9. VCC at 1 MHz,
VCC = 1.8 V, Q = open
1
mA
S = VCC, VIN = VSS or VCC , VCC = 1.8 V
0.5
µA
Test Condition
Min.1
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current
(Standby Power mode)
VIL
Input Low Voltage
–0.45
0.25 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC+1
V
VOL
Output Low Voltage
IOL = 0.15 mA, VCC = 1.8 V
0.3
V
VOH
Output High Voltage
IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
Note: 1. Preliminary data: Product under development. Please contact your nearest ST sales office for information.
24/37
V
M95040, M95020, M95010
Table 18. AC Characteristics (M950x0, Device Grade 6)
Test conditions specified in Table 11. and Table 8.
Max.3
Min.4
Max.4
Unit
D.C.
5
D.C.
10
MHz
Alt.
fC
fSCK
Clock Frequency
tSLCH
tCSS1
S Active Setup Time
90
15
ns
tSHCH
tCSS2
S Not Active Setup Time
90
15
ns
tSHSL
tCS
S Deselect Time
100
40
ns
tCHSH
tCSH
S Active Hold Time
90
25
ns
S Not Active Hold Time
90
15
ns
tCHSL
Parameter
Min.3
Symbol
tCH 1
tCLH
Clock High Time
90
40
ns
tCL 1
tCLL
Clock Low Time
90
40
ns
tCLCH 2
tRC
Clock Rise Time
1
1
µs
tCHCL 2
tFC
Clock Fall Time
1
1
µs
tDVCH
tDSU
Data In Setup Time
20
15
ns
tCHDX
tDH
Data In Hold Time
30
15
ns
tHHCH
Clock Low Hold Time after HOLD not Active
70
15
ns
tHLCH
Clock Low Hold Time after HOLD Active
40
20
ns
tCHHL
Clock High Set-up Time before HOLD Active
tCH
30
ns
tCHHH
Clock High Set-up Time before HOLD not Active
tCH
30
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
50
20
ns
tQHQL 2
tFO
Output Fall Time
50
20
ns
tHHQV
tLZ
HOLD High to Output Valid
50
25
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
100
35
ns
tW
tWC
Write Time
10
5
ms
Note: 1.
2.
3.
4.
Output Disable Time
100
25
ns
Clock Low to Output Valid
60
35
ns
0
0
ns
tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
Value guaranteed by characterization, not 100% tested in production.
Previous product: identified by Process Identification letter K.
Present product: identified by Process Identification letter W or G.
25/37
M95040, M95020, M95010
Table 19. AC Characteristics (M950x0, Device Grade 3)
Test conditions specified in Table 11. and Table 8.
Min.3
Max.3
Min.4
Max.4
Unit
Clock Frequency
D.C.
2
D.C.
5
MHz
tCSS1
S Active Setup Time
200
90
ns
tSHCH
tCSS2
S Not Active Setup Time
200
90
ns
tSHSL
tCS
S Deselect Time
200
100
ns
tCHSH
tCSH
S Active Hold Time
200
90
ns
S Not Active Hold Time
200
90
ns
Symbol
Alt.
fC
fSCK
tSLCH
tCHSL
Parameter
tCH 1
tCLH
Clock High Time
200
90
ns
tCL 1
tCLL
Clock Low Time
200
90
ns
tCLCH 2
tRC
Clock Rise Time
1
1
µs
tCHCL 2
tFC
Clock Fall Time
1
1
µs
tDVCH
tDSU
Data In Setup Time
40
20
ns
tCHDX
tDH
Data In Hold Time
50
30
ns
tHHCH
Clock Low Hold Time after HOLD not Active
140
70
ns
tHLCH
Clock Low Hold Time after HOLD Active
90
40
ns
tCHHL
Clock High Set-up Time before HOLD Active
tCH
60
ns
tCHHH
Clock High Set-up Time before HOLD not
Active
tCH
60
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
100
50
ns
tQHQL 2
tFO
Output Fall Time
100
50
ns
tHHQV
tLZ
HOLD High to Output Valid
100
50
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
250
100
ns
tW
tWC
Write Time
10
5
ms
Note: 1.
2.
3.
4.
26/37
Output Disable Time
250
100
ns
Clock Low to Output Valid
150
60
ns
0
tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
Value guaranteed by characterization, not 100% tested in production.
Previous product: identified by Process Identification letter K.
Present product: identified by Process Identification letter W or G.
0
ns
M95040, M95020, M95010
Table 20. AC Characteristics (M950x0-W, Device Grade 6)
Test conditions specified in Table 11. and Table 9.
Min.3
Max.3
Min.4
Max.4
Unit
Clock Frequency
D.C.
2
D.C.
5
MHz
tCSS1
S Active Setup Time
200
90
ns
tSHCH
tCSS2
S Not Active Setup Time
200
90
ns
tSHSL
tCS
S Deselect Time
200
100
ns
tCHSH
tCSH
S Active Hold Time
200
90
ns
S Not Active Hold Time
200
90
ns
Symbol
Alt.
fC
fSCK
tSLCH
tCHSL
Parameter
tCH 1
tCLH
Clock High Time
200
90
ns
tCL 1
tCLL
Clock Low Time
200
90
ns
tCLCH 2
tRC
Clock Rise Time
1
1
µs
tCHCL 2
tFC
Clock Fall Time
1
1
µs
tDVCH
tDSU
Data In Setup Time
40
20
ns
tCHDX
tDH
Data In Hold Time
50
30
ns
tHHCH
Clock Low Hold Time after HOLD not Active
140
70
ns
tHLCH
Clock Low Hold Time after HOLD Active
90
40
ns
tCHHL
Clock High Set-up Time before HOLD Active
tCH
60
ns
tCHHH
Clock High Set-up Time before HOLD not Active
tCH
60
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
100
50
ns
tQHQL 2
tFO
Output Fall Time
100
50
ns
tHHQV
tLZ
HOLD High to Output Valid
100
50
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
250
100
ns
tW
tWC
Write Time
10
5
ms
Note: 1.
2.
3.
4.
Output Disable Time
250
100
ns
Clock Low to Output Valid
150
60
ns
0
0
ns
tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
Value guaranteed by characterization, not 100% tested in production.
Previous product: identified by Process Identification letter K.
Present product: identified by Process Identification letter W or G.
27/37
M95040, M95020, M95010
Table 21. AC Characteristics (M950x0-W, Device Grade 3)
Test conditions specified in Table 11. and Table 9.
Min.3
Max.3
Min.4
Max.4
Unit
Clock Frequency
D.C.
2
D.C.
5
MHz
tCSS1
S Active Setup Time
200
90
ns
tSHCH
tCSS2
S Not Active Setup Time
200
90
ns
tSHSL
tCS
S Deselect Time
200
100
ns
tCHSH
tCSH
S Active Hold Time
200
90
ns
S Not Active Hold Time
200
90
ns
Symbol
Alt.
fC
fSCK
tSLCH
tCHSL
Parameter
tCH 1
tCLH
Clock High Time
200
90
ns
tCL 1
tCLL
Clock Low Time
200
90
ns
tCLCH 2
tRC
Clock Rise Time
1
1
µs
tCHCL 2
tFC
Clock Fall Time
1
1
µs
tDVCH
tDSU
Data In Setup Time
40
20
ns
tCHDX
tDH
Data In Hold Time
50
30
ns
tHHCH
Clock Low Hold Time after HOLD not Active
140
70
ns
tHLCH
Clock Low Hold Time after HOLD Active
90
40
ns
tCHHL
Clock High Set-up Time before HOLD Active
tCH
60
ns
tCHHH
Clock High Set-up Time before HOLD not
Active
tCH
60
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
100
50
ns
tQHQL 2
tFO
Output Fall Time
100
50
ns
tHHQV
tLZ
HOLD High to Output Valid
100
50
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
250
100
ns
tW
tWC
Write Time
10
5
ms
Note: 1.
2.
3.
4.
28/37
Output Disable Time
250
100
ns
Clock Low to Output Valid
150
60
ns
0
tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
Value guaranteed by characterization, not 100% tested in production.
Previous product: identified by Process Identification letter K.
Present product: identified by Process Identification letter W or G.
0
ns
M95040, M95020, M95010
Table 22. AC Characteristics (M950x0-R)
Test conditions specified in Table 11. and Table 10.
Symbol
Alt.
fC
fSCK
tSLCH
Min.
Max.
Unit
Clock Frequency
D.C.
2
MHz
tCSS1
S Active Setup Time
200
ns
tSHCH
tCSS2
S Not Active Setup Time
200
ns
tSHSL
tCS
S Deselect Time
200
ns
tCHSH
tCSH
S Active Hold Time
200
ns
S Not Active Hold Time
200
ns
tCHSL
Parameter
tCH 1
tCLH
Clock High Time
200
ns
tCL 1
tCLL
Clock Low Time
200
ns
tCLCH 2
tRC
Clock Rise Time
1
µs
tCHCL 2
tFC
Clock Fall Time
1
µs
tDVCH
tDSU
Data In Setup Time
40
ns
tCHDX
tDH
Data In Hold Time
50
ns
tHHCH
Clock Low Hold Time after HOLD not Active
140
ns
tHLCH
Clock Low Hold Time after HOLD Active
90
ns
tCHHL
Clock High Set-up Time before HOLD Active
120
ns
tCHHH
Clock High Set-up Time before HOLD not Active
120
ns
tSHQZ 2
tDIS
tCLQV
tV
tCLQX
tHO
Output Hold Time
tQLQH 2
tRO
Output Rise Time
100
ns
tQHQL 2
tFO
Output Fall Time
100
ns
tHHQV
tLZ
HOLD High to Output Valid
100
ns
tHLQZ 2
tHZ
HOLD Low to Output High-Z
250
ns
tW
tWC
Write Time
10
ms
Output Disable Time
250
ns
Clock Low to Output Valid
180
ns
0
ns
Note: 1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data: Product under development. Please contact your nearest ST sales office for information.
29/37
M95040, M95020, M95010
Figure 16. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
D
Q
tCLCH
LSB IN
MSB IN
High Impedance
AI01447C
Figure 17. Hold Timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQV
Q
D
HOLD
AI02032B
30/37
M95040, M95020, M95010
Figure 18. Output Timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D ADDR.LSB IN
AI01449D
31/37
M95040, M95020, M95010
PACKAGE MECHANICAL
Figure 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
b
A
L
c
e
eA
eB
D
8
E1
1
PDIP-B
Note: Drawing is not to scale.
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
A
Typ.
Min.
5.33
A1
Max.
0.210
0.38
0.015
A2
3.30
2.92
4.95
0.130
0.115
0.195
b
0.46
0.36
0.56
0.018
0.014
0.022
b2
1.52
1.14
1.78
0.060
0.045
0.070
c
0.25
0.20
0.36
0.010
0.008
0.014
D
9.27
9.02
10.16
0.365
0.355
0.400
E
7.87
7.62
8.26
0.310
0.300
0.325
E1
6.35
6.10
7.11
0.250
0.240
0.280
e
2.54
–
–
0.100
–
–
eA
7.62
–
–
0.300
–
–
eB
L
32/37
Max.
10.92
3.30
2.92
3.81
0.430
0.130
0.115
0.150
M95040, M95020, M95010
Figure 20. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
Max.
A
1.35
A1
Min.
Max.
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
CP
1.27
Typ.
0.050
8
0.10
0.004
33/37
M95040, M95020, M95010
Figure 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Symbol
Typ.
Min.
A
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
Min.
1.200
A1
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
α
34/37
Max.
0.0394
0°
8°
M95040, M95020, M95010
PART NUMBERING
Table 26. Ordering Information Scheme
Example:
M95040
–
W MN
6
T
P
/W
Device Type
M95 = SPI serial access EEPROM
Device Function
040 = 4 Kbit (512 x 8)
020 = 2 Kbit (256 x 8)
010 = 1 Kbit (128 x 8)
Operating Voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow 1.
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
Process2
blank = F6SP20%
/W = F6SP36%
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. Used only for Device Grade 3
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
Table 27. How to Identify Present and Previous Products by the Process Identification Letter
Markings on Present Products1
Markings on Previous Products1
95040W6
AYWWW (or AYWWG)
95040W6
AYWWK
35/37
M95040, M95020, M95010
REVISION HISTORY
Table 28. Document Revision History
Date
Version
10-May-2000
2.2
s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation
16-Mar-2001
2.3
Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & Tab
9. Wording changes, according to the standard glossary
Illustrations and Package Mechanical data updated
19-Jul-2001
2.4
Temperature range ‘3’ added to the -W supply voltage range in DC and AC characteristics
11-Oct-2001
3.0
Document reformatted using the new template
26-Feb-2002
3.1
Description of chip deselect after 8th clock pulse made more explicit
27-Sep-2002
3.2
Position of A8 in Read Instruction Sequence Figure corrected. Load Capacitance CL
changed
24-Oct-2002
3.3
Minimum values for tCHHL and tCHHH changed.
24-Feb-2003
3.4
Description of Read from Memory Array (READ) instruction corrected, and clarified
28-May-2003
3.5
New products, identified by the process letter W, added
25-Jun-2003
3.6
Correction to current products, identified by the process letter K not L.
ICC changed in DC characteristics, and tCHHL, tCHHH substituted in AC characteristics
Voltage range -S upgraded by removing it, and adding the -R voltage range in its place
Temperature range 5 removed.
21-Nov-2003
4.0
Table of contents, and Pb-free options added. VIL(min) improved to -0.45V
02-Feb-2004
4.1
VIL(max) and tCLQV(max) changed
5.0
Absolute Maximum Ratings for VIO(min) and VCC(min) improved. Soldering temperature
information clarified for RoHS compliant devices. New 5V and 2.5V devices, with process
letter W, promoted from preliminary data to full data. Device Grade 3 clarified, with reference
to HRCF and automotive environments
6.0
Product List summary table added. Process identification letter “G” information added. Order
information for Tape and Reel changed to T. AEC-Q100-002 compliance. Device Grade
informaton clarified. tHHQX corrected to tHHQV. Signal Description updated.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified
01-Mar-2004
05-Oct-2004
36/37
Description of Revision
M95040, M95020, M95010
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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37/37