SN74LS257B SN74LS258B Quad 2-Input Multiplexer with 3-State Outputs The LSTTL / MSI SN74LS257B and the SN74LS258B are Quad 2-Input Multiplexers with 3-state outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (non-inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (EO) Input, allowing the outputs to interface directly with bus oriented systems. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. • • • • • • http://onsemi.com LOW POWER SCHOTTKY Schottky Process For High Speed Multiplexer Expansion By Tying Outputs Together Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects Special Circuitry Ensures Glitch Free Multiplexing ESD > 3500 Volts 16 1 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max 4.75 5.0 5.25 V 0 25 70 °C PLASTIC N SUFFIX CASE 648 Unit TA Operating Ambient Temperature Range IOH Output Current – High – 2.6 mA IOL Output Current – Low 24 mA 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Device Package Shipping SN74LS257BN 16 Pin DIP 2000 Units/Box SN74LS257BD 16 Pin 2500/Tape & Reel SN74LS258BN 16 Pin DIP 2000 Units/Box SN74LS258BD 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS257B/D SN74LS257B SN74LS258B CONNECTION DIAGRAM DIP (TOP VIEW) VCC E0 I0c I1c Zc I0d I1d Zd 16 15 14 13 12 11 10 9 VCC = PIN 16 GND = PIN 8 SN74LS257B 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b 7 Zb 8 GND VCC E0 I0c I1c Zc I0d I1d Zd 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. SN74LS258B 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b http://onsemi.com 2 7 Zb 8 GND SN74LS257B SN74LS258B LOGIC DIAGRAMS SN74LS257B E0 I0a 15 I1a 2 I0b 3 I1b I0c I1c 14 6 5 7 4 I1d S 10 11 12 Zb Za I0d 13 1 9 Zc Zd SN74LS258B E0 I0a 15 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS I1a 2 I0b 3 I1b I1c 14 I0d 13 7 4 Za I0c 6 5 I1d 12 Zb Zc http://onsemi.com 3 S 10 11 9 Zd 1 SN74LS257B SN74LS258B FUNCTIONAL DESCRIPTION The LS257B and LS258B are Quad 2-Input Multiplexers with 3-state outputs. They select four bits of data from two sources each under control of a Common Data Select Input. When the Select Input is LOW, the I0 inputs are selected and when Select is HIGH, the I1 inputs are selected. The data on the selected inputs appears at the outputs in true (non-inverted) form for the LS257B and in the inverted form for the LS258B. The LS257B and LS258B are the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select Input. The logic equations for the outputs are shown below: When the Output Enable Input (E0) is HIGH, the outputs are forced to a high impedance “off” state. If the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap. LS257B Za = E 0 • Zc = E0 • LS258B Za = E 0 • Zc = E0 • (I1a • S + I0a • S) Zb = E0 • (I1b • S + I0b • S) (I1c • S + I0c • S) Zd = E0 • (I1d • S + I0d • S) (I1a • S + I0a • S) Zb = E0 • (I1c • S + I0c • S) Zd = E0 • TRUTH TABLE OUTPUT ENABLE SELECT INPUT DATA INPUTS EO S I0 H L L L L X H H L L X X X L H OUTPUTS LS257B OUTPUTS LS258B I1 Z Z X L H X X (Z) L H L H (Z) H L H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care (Z) = High Impedance (off) http://onsemi.com 4 (I1b • S + I0b • S) (I1d • S + I0d • S) SN74LS257B SN74LS258B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage Typ Max 2.0 0.8 – 0.65 2.4 – 1.5 3.1 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 0.25 0.4 V IOL = 12 mA 0.35 0.5 V IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table IOZH Output Off Current — HIGH 20 µA VCC = MAX, VOUT = 2.7 V IOZL Output Off Current — LOW – 20 µA VCC = MAX, VOUT = 0.4 V 20 40 µA VCC = MAX, VIN = 2.7 V 0.1 0.2 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 130 mA VCC = MAX mA IIH Input HIGH Current Other Inputs S Inputs Other Inputs S Inputs IIL Input LOW Current All Inputs IOS Short Circuit Current (Note 1) – 30 Power Supply Current ICC Total, Output HIGH LS257B LS258B 10 9.0 Total, Output LOW LS257B LS258B 16 14 mA Total, Output 3-State LS257B LS258B 19 16 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) See SN74LS251 for Waveforms Limits Symbol Typ Max Unit Propagation Delay, Data to Output 10 12 13 15 ns Figures 1 & 2 tPLH tPHL Propagation Delay, Select to Output 14 14 21 21 ns Figures 1 & 2 tPZH Output Enable Time to HIGH Level 20 25 ns Figures 4 & 5 tPZL Output Enable Time to LOW Level 20 25 ns Figures 3 & 5 tPLZ Output Disable Time to LOW Level 16 25 ns Figures 3 & 5 tPHZ Output Disable Time from HIGH Level 18 25 ns Figures 4 & 5 tPLH tPHL Parameter Min http://onsemi.com 5 Test Conditions CL = 45 pF CL = 45 pF RL = 667 Ω CL = 5.0 pF RL = 667 Ω SN74LS257B SN74LS258B PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 6 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SN74LS257B SN74LS258B PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS257B SN74LS258B ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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