Semiconductor March 1998 RN D FO 1 5 E D EN P81 O M M Se e H M C E R NOT E ES WD S IGN HMP8112A NTSC/PAL Video Decoder Features Description • Supports ITU-R BT.601 (CCIR601) and Square Pixel The HMP8112A is a high quality, digital video, color decoder with internal A/D converters. The A/D function includes a 3:1 analog input mux, Sync Tip AGC, Black clamping and two 8bit A/D Converters. The high quality A/D converters minimize pixel jitter and crosstalk. • 3 Composite Analog Inputs with Sync Tip AGC, Black Clamping and White Peak Control • Patented Decoding Scheme with Improved 2-Line Comb Filter, Y/C Separation The decoder function is compatible with NTSC M, PAL B, D, G, H, I, M, N and special combination PAL N video standards. Both composite (CVBS) and S-Video (Y/C) input formats are supported. A 2-line comb filter plus a user selectable Chrominance trap filter provide high quality Y/C separation. Various adjustments are available to optimize the image such as Brightness, Contrast, Saturation, Hue and Sharpness controls. Video synchronization is achieved with a 4xfSC chroma burst lock PLL for color demodulation and line lock PLL for correct pixel alignment. A chrominance subsampling 4:2:2 scheme is provided to reduce chrominance bandwidth. • NTSC M and PAL (B, D, G, H, I, M, N, CN) Operation • Composite or S-Video Input • User-Selectable Color Trap and Low Pass Video Filters • User Selectable Hue, Saturation, Contrast, Sharpness, and Brightness Controls • User Selectable Data Transfer Output Modes • 16-Bit 4:2:2 YCbCr • 8-Bit 4:2:2 YCbCr The HMP8112A is ideally suited as the analog video interface to VCR’s and camera’s in any multimedia or video system. The high quality Y/C separation, user flexibility and integrated phase locked loops are ideal for use with today’s powerful compression processors. The HMP8112A operates from a single 5V supply and is TTL/CMOS compatible. • User Selectable Clock Range from 20MHz - 30MHz • I2C Interface • VMI Compatible Video Data Bus Applications Ordering Information • Multimedia PCs PART NUMBER • Video Conferencing HMP8112ACN • Video Editing • Video Security Systems • Digital VCRs TEMP. RANGE (oC) 0 to 70 PACKAGE PKG.NO. 80 Ld PQFP† Q80.14x20 HMP8112EVAL2 PCI Reference Design (Includes Part) HMP8156EVAL2 Frame Grabber Evaluation Board (Includes Part) † PQFP is also known as QFP and MQFP • Related Products - NTSC/PAL Encoders: HMP8154, HMP8156A, HMP8170/1, HMP8172/3 - NTSC/PAL Decoders: HMP8115, HMP8130/1 Table of Contents Page Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Operation Introduction . . . . . . . . . . . . . . . . . . 5 Internal Register Description Tables. . . . . . . . . . . . . . . . 15 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC and DC Electrical Specifications. . . . . . . . . . . . . . . . 25 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . 28 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . 39 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 1 File Number 4407.2 4-2 EXTERNAL ANTIALIASING FILTER CCLAMP_CAP GAIN_CTRL LAGC_CAP LCLAMP_CAP LIN2/Y LIN1 LIN0 CIN CLAMP LOGIC AND GAIN CONTROL AGC AND CLAMP LOGIC INPUT MUX + + - L_ADIN 8-BIT ADC CLAMP 8-BIT ADC DIGITAL COMPARATOR SYNC LEVEL BLACK LEVEL WHITE PEAK LEVEL DIGITAL COMPARATORS L_OUT EXTERNAL ANTIALIASING FILTER INPUT SAMPLE RATE CONVERTER VSYNC DETECT CHROMA PLL FIELD VSYNC STD_ERR COLOR TRAP LINE LOCK PLL HSYNC COLOR ADJUST USER ADJUST. HSYNC DETECT LOCKED COLOR DEMODULATION Y/C SEPARATION RESET MICROPROCESSOR INTERFACE AND CONTROL OUTPUT SAMPLE RATE CONVERTER SDA SCL CbCr[7:0] Y[7:0] DVLD ACTIVE HMP8112A Functional Block Diagrams VIDEO DECODER 4-3 Y,CVBS L[7:0] CR[7:0] C M U X Y DATA C,CVBS DATA INPUT SAMPLE RATE CONVERTER C,CVBS DATA CHROMA PLL LOOP FILTER U,V ISL SHARPNESS ADJUST VSYNC DETECT CHROMA TRAP ENABLE CHROMA TRAP U,V TO CbCr COLOR SPACE CONVERTER AND COLOR KILLER SATURATION ADJUST UV UV AGC SATURATION ADJUST AGC ADJUST CHROMA PHASE DETECTOR HORIZONTAL M Y DATA AND VERTICAL U Y DATA SHARPNESS X ADJUST Y DATA CHROMA DEMODULATOR C DATA LINE DELAY COMB FILTER CLK TO 4FSC RATIO CHROMA PLL NCO HUE ADJUST LOW PASS FILTER ENABLE LP FILTER HSYNC DETECT STANDARD SELECT OUTPUT SAMPLE RATE CONVERTER LINE LOCKED NCO LINE LOCKED PLL LOOP FILTER FIELD VSYNC STANDARD ERROR CbCr DATA Y SYNC DATA STRIPPER, BRIGHTNESS, & CONTRAST ADJUST LOCKED HSYNC Functional Block Diagrams ISL 4FSC CLOCK CLK (20MHz - 30MHZ) HMP8112A (Continued) HMP8112A Functional Block Diagrams (Continued) CONTROL REGISTERS .... .... .... .... ADDRESS POINTER ADDRESS POINTER OEN 0x00 0x01 . . . . CbCr[7:0] 0x1B CONTROL DATA BUS R E G I S T E R 8/16 OUTPUT SELECT CbCr[7:0] 8 32 X 16 DEEP FIFO SERIAL SHIFT REGISTER R E G I S T E R M U X Y[7:0] Y[7:0] 8 DVLD A0 ACTIVE SCL SDA I2C CONTROL INTERFACE OUTPUT INTERFACE Schematic U1 LUMA0 C1 1.0µF LUMA1 R3 75 6 C2 1.0µF LUMA2/Y LIN0 LIN1 5 LIN2 C3 1.0µF R2 75 7 R1 75 ANTI-ALIAS FILTER CHROMA R4 75 C4 1.0µF 19 ANTI-ALIAS FILTER 8 9 77 C5 0.01µF C6 0.047µF C7 0.047µF C9 0.01µF C10 0.1µF L_ADIN L_OUT CbCr7 CbCr6 CbCr5 CbCr4 CbCr3 CbCr2 CbCr1 CbCr0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 ACTIVE DVLD 64 63 60 58 57 56 55 54 65 66 CB_CR7 CB_CR6 CB_CR5 CB_CR4 CB_CR3 CB_CR2 CB_CR1 CB_CR0 30 Y[0..7] Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y[0..7] VCC VCC VCC VCC VCC VCC VCC R9 10K R10 10K R11 10K R12 10K R13 10K R14 4K DEC_T DEC_L 34 RESET 40 SDA 41 SCL 38 CLK 13 CLK 36 TEST DVLD FIELD HDRIVE VDRIVE RESET 27MHz VAA VAA 28 GAIN_CNTL WPE R6 750 27 R7 10K JP1 JUMPER 4-4 R15 4K ACTIVE LAGC_CAP C11 0.01µF R5 1K CB_CR[0..7] 67 FIELD 71 76 LCLAMP_CAP HSYNC 70 29 VSYNC CCLAMP_CAP 78 C8 0.1µF CIN CB_CR[0..7] 51 50 49 48 47 45 43 42 R8 50 C12 15pF SDA SCL 27MHz HMP8112A Introduction The HMP8112A is designed to decode baseband composite or s-video NTSC and PAL signals, and convert them to either digital YCbCr or RGB data. The digital PLLs are designed to synchronize to all NTSC and PAL standards. A chroma PLL is used to maintain chroma lock for demodulation of the color information; a linelocked PLL is used to maintain vertical spatial alignment. The PLLs are designed to maintain lock even in the event of VCR headswitches. tip to maintain an average ADC code of 0. The DC RESTORE circuit clamps the video signal during the back porch to maintain an average ADC code of 64. Reference Figure 2 for timing information and Table 5 for the recommended register values to use for different video standards. The START and END times of the HSYNC output are also programmable and can be used as a reference for confirming proper HAGC and DC RESTORE timing. 0HSYNC The HMP8112A contains two 8-bit A/D converters and an I2C port for programming internal registers Analog Video Inputs VIDEO INPUT The HMP8112A supports either three composite or two composite and one S-Video input. Three analog video inputs (LIN0, LIN1, LIN2) are used to select which one of three composite video sources are to be decoded. To support S-video applications, the Y channel drives the LIN2 analog input, and the C channel drives the CIN analog input. DC RESTORE START TIME The analog inputs must be AC-coupled to the video signals, as shown in the Applications section. END TIME HAGC START TIME Anti-Aliasing Filter An external anti-alias filter is required to achieve optimum performance and prevent high frequency components from being aliased back into the video image. HSYNC For the LIN0-2 inputs, a single filter is connected to L_OUT and L_ADIN. For CIN the anti-aliasing filter should be connected to the CIN input. A recommended filter is shown below in Figure 1. START TIME END TIME END TIME FIGURE 2. DC RESTORE AND HAGC TIMING White Peak Enable R1 L1 332 8.2µH C1 33pF C2 82pF The white peak enable input, (WPE) enables or disables the white peak control of the luminance input. If enabled, the AGC will reduce the gain of the video amplifier when the digital outputs exceed code 248 to prevent over-ranging the A/D. If disabled, the AGC operates normally, keeping the horizontal sync tip at code 0 and allowing the A/D’s range to go to 255 at the maximum peak input. R2 4.02K FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER Luminance AGC And DC RESTORE Circuits Chrominance Input After a RESET, a change of the video standard, or a PLL Chrominance Subcarrier Ratio Register load, the decoder enters Acquisition Mode by attempting to lock to a new video source. During this mode, the HAGC and DC RESTORE circuits perform continuous gain and bias adjustments until the PLL is LOCKED onto the video signal. Once LOCKED, the HAGC and DC RESTORE functions are performed during programmable window periods for each horizontal video line. The digital PLL zeroes a 10-bit pixel clock counter during each horizontal sync tip and increments the count for each pixel of the entire video line. The AGC amplifier attenuates or amplifies the analog video signal during the horizontal sync The chrominance amplifier gain control is manually set by a voltage applied to the GAIN_CNTL pin. Refer to Figure 3 below for gain characteristics. The chrominance channel also has a digital AGC which can drive the color reference burst to a nominal +-20 IRE. This function is enabled by default on reset, but can be disabled using the Video Input Control register. The chrominance input is clamped during the DC RESTORE window to maintain an average ADC code of 128. 4-5 HMP8112A 7 6 The input sample rate converter will interpolate between existing CLK samples to create the chroma locked (4xfSC) samples needed for the color decoder. An interpolation is done to create the 4xfSC pixel and a correction factor is then applied. TEMPERATURE = 25oC VCC = 5V LINEAR GAIN 5 INCOMING VIDEO SAMPLES 4 3 2 TIME 1 0 1.6 RESAMPLED VIDEO 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 GAIN CONTROL VOLTAGE FIGURE 3. CHROMINANCE AMPLIFIER GAIN TIME Reset 4xfSC The RESET pin is used to return the decoder to an initialization state. This pin should be used after a power-up to set the part into a known state. The internal registers are returned to their RESET state and the Serial I2C port is returned to inactive state. The RESET pin is an active low signal and should be asserted for minimum of 1 CLK cycle. After a RESET or a software reset has occurred all output pins are three-stated. The VSYNC, HSYNC, DVLD, ACTIVE and FIELD output pins must be pulled high to ensure proper operation. A 10K or smaller pullup resistor to VCC is recommended. NTSC/PAL Decoder The NTSC/PAL decoder is designed to convert incoming Composite or Separated (SVHS, Y/C) video into it’s YCbCr component parts. The digital phase locked loops are designed to synchronize to the various NTSC/PAL standards. They provide a stable internal 4xfSC (Frequency of the Color Sub-Carrier) video clock for color demodulation, and a line locked clock for vertical spatial pixel alignment. The decoder uses the CLK to run the A/D converters and the phase locked loops. This asynchronous master clock for the decoder eliminates the need for a unique clock source in a Multimedia application. CLK can run from 20MHz to 30MHz when using the 16-bit Synchronous Data output Mode. The user must program the CLK to Color Sub-Carrier Ratio to match the CLK frequency used (see Internal Phase Locked Loops discussion). When using the 8-bit Burst Data Output Mode the CLK should be a 24.54MHz, 27MHz or 29.5MHz depending on the output video standard chosen. The crystal oscillator must have a ±50ppm accuracy and a 60/40% duty cycle symmetry to ensure proper operation. Since the video data from the external A/D’s are sampled at the CLK frequency a sample rate converter is employed to convert the data from the CLK rate to the internal decoding frequency of 4xfSC. FIGURE 4. SAMPLE RATE CONVERSION The decoder can be used with the following video sources: Analog Composite - NTSC M, - PAL B, D, G, H, I, N And Special Combination PAL N Analog S - VHS (Y/C) - NTSC M, PAL B, D, G, H, I, N And Special Combination PAL N Color Separation, and Demodulation To separate the chrominance modulated color information from the baseband luminance signal, a 2-Line comb filter is employed. In NTSC signals the color information changes phase 180o from one line to the next. This interleaves the chrominance information at half line intervals throughout the NTSC video spectrum. Therefore, NTSC has 227.5 cycles of chrominance per NTSC line. The half of a cycle causes the next reference burst to be 180o out of phase with the previous line’s burst. The 2-Line comb efficiently removes the chrominance information from the baseband luminance signal. When decoding NTSC, the decoder maintains full luminance bandwidth horizontally throughout the chrominance carrier frequency range. Unlike most 2 line comb filter separation techniques, vertical bandwidth is maintained by means of a proprietary transform technique. Reset The RESET pin is used to return the decoder to an initialization state. This pin should be used after a power-up to set the part into a known state. The internal registers are returned to their RESET state and the Serial I2C port is returned to inactive state. The RESET pin is an active low signal and should be asserted for minimum of 1 CLK cycle. After a RESET or a software reset has occurred all output pins are three-stated. The VSYNC, HSYNC, DVLD, ACTIVE and FIELD output pins must be pulled high to ensure proper operation. A 10K or smaller pullup resistor to VCC is recommended. 4-6 HMP8112A Y 255 248 Y I, Q WHITE 100% 255 240 BLUE 100% BLUE 75% 212 255 240 RED 100% RED 75% 212 AMPLITUDE 128 128 44 fH/2 16 fH/2 fH FREQUENCY BLACK Y DATA RANGE 16 0 128 YELLOW 75% YELLOW 100% CYAN 75% CYAN 100% 44 16 0 Cb DATA RANGE Cr DATA RANGE FIGURE 7. YCbCr DATA RANGES Y Y I, Q The decoder is compatible with all NTSC and PAL video formats available throughout the world. Table 2 shows the compatible video standards. AMPLITUDE Horizontal Sync Detection FREQUENCY FIGURE 5. COMPOSITE NTSC INTERLEAVE SCHEME For PAL systems there are 283.75 cycles of chrominance per line. Chrominance information is spaced at quarter line intervals with a reference phase of 135o. The reference phase alternates from line to line by 90o. To fully separate the PAL chrominance and luminance signals the user selectable filters should be enabled. The chroma notch filter built into the luminance channel should be enabled for PAL systems to reduce cross luminance effects. The low pass filter in the chrominance processing chain helps to reduce cross color products. Horizontal sync is detected in the Output Sample Rate converter (OSR). The OSR spatially aligns the pixels in the vertical direction by using the horizontal sync information embedded in the digital video data stream. The HSYNC sync pulse out of the decoder is a video synchronous output pin. This signal follows the horizontal sync of an input video source. If there is no source the HSYNC pin will continue to run at video rates due to the Line Locked PLL free-running. HSYNC can be moved throughout the video line using the HSYNC Start and End time registers. This 10-bit register allows the HSYNC to be moved in OSR clock increments (12.27MHZ, 13.5MHz or 14.75MHz). Vertical Sync and Field Detection Y I, Q I, Q Y The vertical sync and field detect circuit of the decoder uses a low time counter to detect the vertical sync sequence in the video data stream. The low time counter accumulates the low time encounted after the horizontal sync edge or at the start of each line. When the low time count exceeds the vertical sync detect threshold, VSYNC is asserted immediately. VSYNC will remain asserted for a minimum of 1 line. The FIELD flag is updated at the same time as the VSYNC line. The FIELD pin is a ‘0’ for ODD fields and a ‘1’ for even fields. AMPLITUDE fH/4 fH/4 fH FREQUENCY Y I, Q I, Q In the case of lost vertical sync or excessive noise that would prevent the detection of vertical sync, the FIELD flag will continue to toggle. Lost vertical sync is declared if after 337 lines a vertical sync period was not detected for 3 successive lines. When this occurs the phase locked loops are initialized to the acquisition state. Y AMPLITUDE FREQUENCY FIGURE 6. COMPOSITE PAL INTERLEAVE SCHEME The demodulator in the decoder decodes the color components into U and V. The U and V components are converted to Cb and Cr components after the decoding process. YCbCr has a usable data range as shown in Figure 7. The data range for Y is limited to a minimum of 16. The VSYNC pulse out of the decoder follows the vertical sync detection and is typically 6.5 lines long. The VSYNC will run at the field rate of the selected video standard selected. For NTSC the field rate is 60Hz and for PAL the field rate is 50Hz. This signal will continue to run even in the event of no incoming video signal. 4-7 HMP8112A LINE # 524 525 1 2 3 4 5 6 7 8 9 10 VIDEO INPUT OV VSYNC DETECT THRESHOLD LOW TIME COUNTER HSYNC 5 VSYNC 4 3 2 1 APPROX. 5.75 LINES FIELD ‘ODD’ FIELD ‘EVEN’ FIELD FIGURE 8. VSYNC TIMING AND THE EVEN TO ODD FIELD TRANSITION LINE # 262 263 264 265 266 267 268 269 270 271 272 5 4 3 2 1 273 VIDEO INPUT LOW TIME COUNTER VSYNC DETECT THRESHOLD OV HSYNC 6 VSYNC FIELD APPROX. 6.25 LINES ‘ODD’ FIELD ‘EVEN’ FIELD FIGURE 9. VSYNC TIMING AND THE ODD TO EVEN FIELD TRANSITION Internal Phase Locked Loops The HMP8112A has two independent digital phase locked loops on chip. A chroma phase-locked loop is implemented to maintain chroma lock for demodulation of the color channel, and a line locked phase lock loop is implemented to maintain vertical spatial alignment. The phase locked loops are designed to maintain lock even in the event of VCR headswitches. The HMP8112A can use a main crystal (CLK) of 20MHz to 30MHz. The crystal is used as a reference frequency for the internal phase locked loops. The ratio of the crystal frequency to the video standard is programmed into an internal register for the PLLs to correctly decode video. The HMP8112A decoder contains 2 sample rate converters and 2 phase locked loops that lock to the incoming video. The input sample rate converter synchronizes the digitized video from the CLK rate to a 4xfSC rate. The chrominance is separated from the luminance and then demodulated. The Chroma PLL uses the CLK source as a reference frequency. To initialize the Chroma PLL, the CLK to 4xfSC ratio value must be loaded into the Chroma PLL Ratio Register pair. A default 16-Bit Fractional Chroma PLL Ratio Value of 0x87C1 is used after a system RESET is applied. Refer to Table 1 for example PLL Ratio values to use with the sup- ported video standards 27MHz or 24.54MHz clocks. Using a different CLK will require different values to be calculated per the method shown below. The default assumes a CLK of 27MHz and NTSC as the video standard, and is calculated as follows: Ratio = = = Register Data: Hex Conversion: (4 x fSC) / CLK (4 x 3.579545MHz) / 27MHz 0.530303 Ratio * 65536 0.530303 * 65536 = 34753.94 0x87C1 The Output Sample Rate converter is locked to the horizontal line frequency and is used to spatially align pixels in a field. The LOCKED flag signals when the phase locked loop is within a ±4 pixel range of the horizontal sync edge. When line errors exceed that range the LOCKED flag is cleared. In cases where VCRs are used in Pause, Fast Forward or Fast Reverse, lines are typically dropped or added by the VCR. In a worst case scenario a VCR line tolerance will vary by ±8%. The standard detect logic checks the line count against the given standard to determine an error. VCRs in trick mode cannot cause a standard error. With an NTSC standard VCR the number of lines in a field should not 4-8 HMP8112A TABLE 1. COMPATIBLE VIDEO INPUT STANDARDS COLOR SUBCARRIER fSC 27MHz PLL Ratio 24.54MHz PLL Ratio FIELDS/ SECOND VERTICAL LINES LINE FREQUENCY NOMINAL BANDWIDTH BLACK SETUP TO BLANK NTSC (M) 3.579545MHz 0x87C1 0x955D 60Hz 525 15,734 (± 0.0003%) 4.2MHz 7.5 IRE PAL (B, D, G, H, I) 4.43361875MHz 0xA826 0xB901 50Hz 625 15,625 (± 0.02%) 5.0MHz 0 IRE PAL (M) 3.57561149MHz 0x879B 0x9533 60Hz 525 15,750 (± 0.0003%) 4.2MHz 7.5 IRE PAL (N) 4.43361875MHz 0xA826 0xB901 50Hz 625 15,625 (± 0.15%) 4.2MHz 7.5 IRE PAL Special Combination N 3.58205625MHz 0x97DA 0x9578 50Hz 625 15,750 (± 0.15%) 4.2MHz 7.5 IRE STANDARD exceed 285. Greater than 285 lines in a field is interpreted as a PAL video source. An ideal NTSC source should have 262.5 lines per field and a PAL source should have 312.5 lines per field. The HMP8112A can detect a STANDARD ERROR that signals when the video received does not match the standard that was programmed into the Video Input Control Register. This flag, when asserted, tells the user that the video standard that was expected was not found and a different standard should be selected in the Video Input Control register. The error flag is cleared after a RESET or after the Chroma PLL Clock Ratio register has been loaded via the I2C bus. After the flag is cleared the standard error logic verifies the video standard. The error flag is set after 2 vertical sync periods have passed and the line count did not match the expected line count. Video Adjustments The HMP8112A allows the user to vary such video parameters as Contrast, Brightness, Sharpness, Hue and Color Saturation. These adjustments can be made via the I2C interface. Contrast, brightness and sharpness are luminance controls. The full dynamic range of the luminance channel can be used by selecting the IRE setup cancellation mode. This mode will remove the IRE setup and blanking level offset to take advantage of the full dynamic range of the luminance processing path. The sharpening filters allow the enhancement of low, mid and high frequency components of the luminance signal to compensate for low amplitude video. Vertical sharpness is also controlled via the I2C interface. Hue and Color saturation controls enhance the CbCr components of the incoming video, all under user control. Luminance Adjustments YOUT = (Y - IRE Setup + BRIGHTNESS) x CONTRAST BRIGHTNESS (-64 TO +63) Y DATA FROM DECODER + + X 8 IRE BLACK SETUP (NTSC = 73, PAL = 64) Y’ CONTRAST (0 TO 1.999) FIGURE 10. LUMINANCE CONTROL SETTINGS PATH Brightness The user can control the brightness of the incoming video by programming the Brightness register. The brightness adjustment will offset the Y component. The brightness register is an 8-bit register where the bottom 7 bits are brightness control and the top bit enables NTSC 7.5 IRE black setup cancellation. When the IRE bit is set (1) for NTSC, then 73 is subtracted from the Y data. If the IRE bit is cleared (0) for PAL, then 64 is subtracted. The brightness control bits BR[6-0] will brighten the picture as the value is increased. BR = -64 is the darkest and BR = +63 is the brightest. The default value of the register after a RESET is 0 (80H). Contrast The contrast adjustment will allow the user to increase and decrease the gain of the Y data. The contrast factor is an 8bit number (as shown below) that ranges from 0 to 1.992. X.XXXXXXX The Luminance data can be adjusted in the HMP8112A. The user can adjust brightness and contrast of the Y or luminance data. The user can also set the IRE or setup subtraction value to eliminate the black pedestal offset from NTSC signals. The Contrast adjustment range can exceed a value of one so as to take full advantage of the 8-bit dynamic range for Y. The user control settings executes the equation The default register value of 1.4766 (0xBD) is calculated as follows: 4-9 Register = Factor * 128 = 1.4766 * 128 = 189 = 0xBD HMP8112A Hue or Tint Adjust The Hue adjustment is applied to the U and the V color difference signal. The Hue adjusts the phase of the given UV data. The Hue can be adjusted by ±30 degrees in 1/4 degree increments. This is achieved by changing the Burst Phase Locked reference point. Figure 11 shows the block diagram for the color adjustment section. This default value for this register is 0. VIDEO DATA COLOR DECODER DEMODULATED UV DATA CHROMA AGC AND USER SETTINGS UV DATA + HUE ADJUST HUE OFFSET TO INPUT SAMPLE RATE CONVERTER The Color Killer (AGC Hysteresis and Loop Limits) The color killer will disable the color difference path and set the U and V components to zero. The automatic color killer circuitry uses the AGC threshold to determine the maximum and minimum gain factor limits. The loop filter determines how much the AGC gain factor can be changed within one line. The maximum gain factor (Max = 8) and the minimum gain factor (Min = 0.5) will limit the range of the AGC. When the gain factor exceeds the maximum gain factor of 8, the gain factor is limited to 8. Once the signal has an amplitude of 1/16th, the nominal video the color killer is enabled and the chroma phase locked loop holds it’s last phase reference. While the color killer is enabled, the U and V components are forced to zero. Once the input video signal reaches 1/7th the optimum amplitude the color killer is disabled and the color is returned. UV DATA CHROMA PHASE LOCKED LOOP ÷4096 FIGURE 11. HUE ADJUST BLOCK DIAGRAM I2C MAX GAIN FACTOR MIN GAIN FACTOR COLOR KILLER AGC GAIN FACTOR AGC ENABLE LINE COUNT Horizontal/Vertical Sharpness The frequency characteristics of the video waveform can be altered to enhance the sharpness of the picture. The Horizontal Sharpness register acts as a 4 band equalizer where the amplitude of specific frequency ranges can be enhanced or diminished. The Sharpness Control Register allows the Low (LF), Mid (MF) and High Frequency (HF) bands of the luminance signal to be enhanced. Vertical Sharpness can be adjusted to 1 or a factor of 0. The RESET default is a factor of 1.0 The 2-bit values allow 4 choices of scaling factors. The sharpness control helps to compensate for losses in the scaling interpolators that can reduce the amplitude of high frequency components. FIGURE 12. LOOP FILTER BLOCK DIAGRAM (HYSTERESIS) The dynamic range of the AGC allows it to compensate for video that is 1/8 to 2 times the specified nominal of 1VP-P. Saturation The color saturation component is controlled via the Color Saturation Registers. The color saturation is applied to the UV components after the AGC function. The saturation value is multiplied by the UV data to increase the color intensity. This is an 8-bit number (as shown below) that ranges from 0 to 1.992. X.XXXXXXX TABLE 2. SHARPNESS GAIN FACTOR SELECTS XF1 XF0 GAIN FACTOR 0 0 Scaled By 1.0 0 1 Scaled By 2.0 1 0 Scaled By 4.0 1 1 Scaled By 0 The default register value of 1.2266 (0x9D) is calculated as follows: Register = Factor * 128 = 1.2266 * 128 = 157 = 0x9D 4-10 HMP8112A NTSC M, PAL M PAL B, D, G, H, I, N, COMB N LINES 1 - 22 NOT ACTIVE LINES 1 - 22 NOT ACTIVE ODD FIELD SYNC AND BACK PORCH 240 ACTIVE LINES PER FIELD (LINES 23-262) 288 ACTIVE LINES PER FIELD (LINES 23 - 310) VERTICAL BLANKING 480 ACTIVE LINES/FRAME (NTSC, PAL M) EVEN FIELD LINES 263 - 284 NOT ACTIVE 240 ACTIVE LINES PER FIELD (LINES 285 - 524) LINE 525 NOT ACTIVE LINES 311 - 335 NOT ACTIVE FRONT PORCH 576 ACTIVE LINES/FRAME (PAL) 288 ACTIVE LINES PER FIELD (LINES 336 - 623) NUMBER OF PIXELS RECTANGULAR (SQUARE) NTSC LINES 624-625 NOT ACTIVE PAL TOTAL PIXELS 858 (780) 864 (944) TOTAL PIXELS ACTIVE PIXELS 720 (640) 720 (768) ACTIVE PIXELS FIGURE 13. ACTIVE VIDEO REGIONS Output Data Port Modes 8-Bit Pixel Transfer Mode The HMP8112A can output data in 2 formats, an 8-bit Pixel Transfer Mode and a 16-bit Pixel Transfer mode. For 8-Bit Pixel Transfer Mode the Y[7:0] output bus is used to transfer all YCbCr data. The data is 4:2:2 subsampled but will only contain the active video portion of the line. See Figure 15 for 8-Bit Pixel Transfer Mode timing. In this mode, the data is clocked out at the CLK rate and only clock frequencies of 24.54MHz, 27MHz and 29.5MHz can be used. In 8bit Mode, the data is sequenced on the Y[7:0] bus in Cb, Y, Cr, Y format. ACTIVE is asserted as soon as the mode is selected. DVLD when asserted, indicates a valid active pixel is available. Pixels during the horizontal and vertical blanking are not available. Only the active portions of the video line are output. 16-Bit Pixel Transfer Mode In 16-bit Pixel Transfer Mode pixel data is output at the CLK frequency and Table 3 shows the number of data points per video line to expect for a given standard. Data is output as 4:2:2 subsampled data in a Y-Cb/Y-Cr 16-bit sequence. The Data Valid (DVLD) flag is asserted when video data is present on the 16-bit output port (Y[7:0], CbCr[7:0]). The luminance data is output on Y[7:0] bus. Chrominance data is sequenced on the CbCr[7:0] bus, starting with Cb and then Cr. Per Figure 13, the ACTIVE flag is asserted when the active video portion of the horizontal scan line is present on the data output port. See Figure 14 for 16-Bit Pixel Transfer Mode timing. DVLD is asserted every time the output sample rate converter has a valid output. When DVLD and ACTIVE are used together the visual portion of the image can be captured. When DVLD is used alone all valid data during the Horizontal, Vertical and Reference Burst Timing are available. The CLK can be run on a 20MHz - 30MHz clock source. Data will be output (on average) at the Output Data Rate shown in Table 3 for a given standard. Data is clocked out synchronous to CLK and will come in bursts. To smooth out the data output to a regular rate, a CLK of 2X the average output data rate can be used. TABLE 3. OUTPUT MODE STANDARDS OUTPUT DATA RATE TOTAL PIXELS (WITH SYNCS) ACTIVE PIXELS NTSC Square Pixel 12.27MHz 780 x 525 640 x 480 NTSC CCIR 601 13.5MHz 858 x 525 720 x 480 PAL B, D, G, H, I, N, COMB N, CCIR601 13.5MHz 864 x 625 720 x 576 PAL M CCIR 601 13.5MHz 858 x 525 720 x 480 PAL B, D, G, H, I, N Square Pixel 14.74MHz 944 x 625 768 x 576 PAL M Square Pixel 14.74MHz 780 x 525 640 x 480 STANDARD 4-11 HMP8112A CLK NOTE 3 DVLD ACTIVE NOTE 2 YN Y[7-0] Y0 Y1 Y2 Y3 Y4 Cr0 Cb2 Cr2 Cb4 NOTE 1 CbCr[7-0] CrN Cb0 tDVLD NOTES: 1. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due to the 4:2:2 subsampling. YN the last valid pixel in the blanking period. 2. ACTIVE is asserted per Figure 13. 3. DVLD is asserted for every valid pixel during both active and blanking regions. DVLD is not a 50% duty cycle synchronous output and will appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs. FIGURE 14. OUTPUT TIMING 16-BIT MODE CLK NOTE 6 DVLD ACTIVE NOTE 5 Cb0 Y[7-0] Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 NOTE 4 tDVLD NOTES: 4. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period. 5. ACTIVE stays asserted as soon as 8-Bit mode is selected. 6. DVLD is asserted for every valid pixel during the active region only per Figure 13. DVLD may deassert briefly during the active video region as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs. FIGURE 15. OUTPUT TIMING 8-BIT MODE 4-12 HMP8112A I 2C Control Interface register pointer is loaded and a series of registers can be written. If multiple registers are written, the pointer register will autoincrement up through the register address space. A stop cycle is used to end the transfer after the desired number of registers are programmed. The HMP8112A utilizes an I2C control bus interface to program the internal configuration registers. This standard mode (up to 100 KBPS) interface consists of the bidirectional Serial Data Line (SDA) and the Serial Clock Line (SCL). The implementation on the HMP8112A is a simple slave interface that will not respond to general calls and cannot initiate a transfer. The SDA and SCL control pins should be pulled high through external 4kΩ pullup resistors to VCC. For a read transfer, the I2C device address is the first part of the serial transfer. Then the internal register pointer is loaded. At this point another start cycle is initiated to access the individual registers. Figure 18 shows the programming flow for read transfer of the internal registers. Multiple registers can be read and the pointer register will autoincrement up through the pointer register address space. On the last data read, an acknowledge should not be issued. A stop cycle is used to end the transfer after the desired number of registers are read. The I2C clock/data timing is shown below in Figure 16. The HMP8112A always uses chip address 0x88. There are 28 internal registers used to program and configure the decoder. The I2C control port contains a pointer register that auto-increments through the entire register space and can be written. The autoincrement pointer will wrap after the last register has been accessed (Product ID Register) and should be set to the desired starting address each time an access is started. For a write transfer, the I2C device base address is the first part of a serial transfer. Then the internal The HMP8112A contains a product ID register that can be used to identify the presence of a board during a Plug ’n Play detection software algorithm. The Product ID Code register is at sub address 0x1B and always returns a data value of 0x12. tSU:DATA tBUF SDA tHD:DATA SCL tLOW tHIGH tR tF tSU:STOP FIGURE 16. I2C TIMING DIAGRAM SDA SCL 1-7 S START CONDITION 8 ADDRESS 9 R/W 1-7 ACK 8 DATA 9 P ACK STOP CONDITION FIGURE 17. I2C SERIAL DATA FLOW DATA WRITE 1000 1000 S CHIP ADDR FROM MASTER A SUB ADDR A 0x88 DATA READ S DATA A REGISTER POINTED TO BY SUB ADDR DATA A P FROM HMP8112A OPTIONAL FRAME MAY BE REPEATED n TIMES 1000 1000 (R/W) CHIP ADDR 0x88 A SUB ADDR A S CHIP ADDR A 0x89 DATA REGISTER POINTED TO BY SUB ADDR A DATA OPTIONAL FRAME MAY BE REPEATED n TIMES FIGURE 18. REGISTER WRITE/READ FLOW 4-13 NA P S = START CYCLE P = STOP CYCLE A = ACKNOWLEDGE NA = NO ACKNOWLEDGE HMP8112A TABLE 4. DEFAULT REGISTER VALUES SUB ADDR (HEX) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B REGISTER NAME Video Input Control Luminance Brightness Control Luminance Contrast Adjust Hue Adjust Luminance Sharpness Control Color Saturation Adjust PLL Clock Frequency Ratio (LSB) PLL Clock Frequency Ratio (MSB) HAGC Start Time (LSB) HAGC Start Time (MSB) HAGC End Time (LSB) HAGC End Time (MSB) HSYNC Start Time (LSB) HSYNC Start Time (MSB) HSYNC End Time (LSB) HSYNC End Time (MSB) PLL Adjust PLL Sync Detect Window DC RESTORE Start Time (LSB) DC RESTORE Start Time (MSB) DC RESTORE End Time (LSB) DC RESTORE End Time (MSB) Output Format Control Software Reset and Video Status Reserved Reserved Reserved Product ID DEFAULT VALUE (HEX) 0xF8 0x80 0xBD 0x00 0x00 0x9D 0xC1 0x87 0x3F 0x03 0x00 0x00 0x3B 0x03 0x20 0x00 0x00 0xDD 0x37 0x00 0x52 0x00 0x00 0x00 0x00 0x00 0x00 0x12 USE VALUE (HEX) Comments Defaults to NTSC and Mux = LIN0 Table 1 Table 1 Table 5 Table 5 Table 5 Table 5 Table 5 Table 5 Table 5 Table 5 0x20 0x20 Table 5 Table 5 Table 5 Table 5 Defaults to NTSC with 27MHz Clock Ratio Recommend PLL Adjust = 0x20 Recommend PLL Sync Detect Window = 0x20 Bits 6-2 define Output Mode. Set Bit 7 to Reset. / TABLE 5. RECOMMENDED TIMING REGISTER CONFIGURATION HAGC WINDOW (SYNC TIP) DC RESTORE WINDOW (BACK PORCH) HSYNC WINDOW (BLANKING INTERVAL) START END START END START END TOTAL PIXELS PER LINE LAST PIXEL COUNT (HEX) REGISTERS MSB/LSB 0x09/0x08 REGISTERS MSB/LSB 0x0B/0x0A REGISTERS MSB/LSB 0x13/0x12 REGISTERS MSB/LSB 0x15/0x14 REGISTERS MSB/LSB 0x0D/0x0C REGISTERS MSB/LSB 0x0F/0x0E NTSC, CCIR601 Rectangular Pixel (720 x 480) 858 0x0359 0x033B 0x001B 0x002D 0x0048 0x033B 0x0060 NTSC Square Pixel (640 x 480) 780 0x030B 0x02F0 0x0014 0x0028 0x0040 0x02F0 0x0050 PAL-B, CCIR601 Rectangular Pixel (720 x 576) 864 0x035F 0x0345 0x001A 0x0032 0x0050 0x0345 0x0070 PAL-B Square Pixel (768 x 576) 944 0x03AF 0x0392 0x001C 0x0044 0x0056 0x0392 0x0070 VIDEO STANDARD (ACTIVE PIXELS) 4-14 HMP8112A TABLE 6. VIDEO INPUT CONTROL SUB ADDRESS = 0x00 BIT NUMBER 7-6 5 FUNCTION DESCRIPTION Video Input Standard These bits select the video input standard. Color Trap Filter Disable This bit enables the color subcarrier trap filter. The filter removes the color subcarrier information from the luminance channel. The filter should be enabled for PAL Standard systems. RESET STATE 11B 00 = PAL B, G, H, I, N; 4.43MHz subcarrier; 50fps; 625 lines/frame; 01 = PAL M; 3.58MHz subcarrier; 60fps; 525 lines/frame; 10 = Special PAL N; 3.58MHz subcarrier; 50fps; 625 lines/frame; 11 = NTSC M; 3.58MHz subcarrier; 60fps; 525 lines/frame (default); 1B 0 = Enabled 1 = Disabled (default) 4 Chrominance Low Pass Filter Disable This bit enables the chrominance low pass filter. This filter band limits the chrominance channel to remove luminance artifacts. This filter should be enabled for PAL Standard systems. 1B 0 = Enabled 1 = Disabled (default) 3 Automatic Color Gain Control This bit enables the color AGC function. When this bit is set the color AGC will automatically adjust the chrominance channel gain, to drive the color reference burst to a nominal ±20 IRE’s. When this bit is cleared the color AGC gain factor is set to 1.0 and the color saturation must be adjusted to obtain nominal CrCb values. 1B 0 = Disabled 1 = Enabled (default) 2-1 A/D Converter Multiplexer Selects These bits control the A/D input select multiplexers and whether S-Video is being input as follows: 00B 0, 0 = Select Composite Video Input = LIN0 (Pin 7), set decoder for Composite 1, 0 = Select Composite Video Input = LIN1 (Pin 6), set decoder for Composite 0, 1 = Select Composite Video Input = LIN2 (Pin 5), set decoder for Composite 1, 1 = Select S-Video Y Input = LIN2 (Pin 5) and C Input = CIN (Pin 19) 0 Not Used Write Ignored, Read 0’s 0B TABLE 7. LUMINANCE BRIGHTNESS CONTROL SUB ADDRESS = 0x01 BIT NUMBER 7 FUNCTION DESCRIPTION IRE Setup This bit enables the black setup cancellation circuit for NTSC sources. When this bit is set Cancellation Control a value of 73 is used to strip the sync information from the video signal. When this bit is cleared a value of 64 is used to strip the sync information. RESET STATE 1B 0 = subtract 64 from the luminance signal 1 = subtract 73 from the luminance signal 6-0 Luminance Brightness Control These bits control the brightness adjustment to the luminance channel. The brightness adjustment value is a number that ranges from +63 to -64. This register is in the two’s complement format, where bit 6 is the sign bit. 4-15 000 0000B HMP8112A TABLE 8. LUMINANCE CONTRAST ADJUST REGISTER SUB ADDRESS = 0x02 BIT NUMBER 7-0 FUNCTION DESCRIPTION Luminance Contrast This register sets the contrast adjust factor which is applied after the brightness. This valAdjust Factor ue is multiplied by the luminance data and allows the data to be scaled from 0 to a factor of +1.996. This 8-bit number is a fractional number as shown below: 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 The default contrast factor of 1.4766 is calculated as follows: Register Data = Factor * 128 = 1.4766 * 128 = 189 = 0xBD RESET STATE 1011 1101B (0xBD) TABLE 9. HUE ADJUST REGISTER SUB ADDRESS = 0x03 BIT NUMBER 7-0 FUNCTION Hue Phase Adjust DESCRIPTION This register sets the hue phase offset adjustment. This 8-bit number is applied as a phase offset to the CbCr data coming out of the demodulator. This 8-bit number is a in the range of +127 to -128. The hue adjust has as range of 30o with each count in this register allowing a 0.25o phase adjustment. This register is in two’s complement format, where bit 7 is the sign bit. RESET STATE 0000 0000B (0x00) TABLE 10. LUMINANCE SHARPNESS CONTROL REGISTER SUB ADDRESS = 0x04 BIT NUMBER 7-6 FUNCTION DESCRIPTION High Frequency These bits adjust the amplitude of high frequency components in the luminance video Enhancement Factor signal. The attenuation or multiplication of the high frequency components is adjusted as shown below: RESET STATE 00B 00 = Multiply high frequency components by 1.0 01 = Multiply high frequency components by 2.0 10 = Multiply high frequency components by 4.0 11 = Zero out high frequency components. 5-4 Middle Frequency Enhancement Factor These bits adjust the amplitude of middle frequency components in the luminance video signal. The attenuation or multiplication of the middle frequency components is adjusted as shown below: 00B 00 = Multiply middle frequency components by 1.0 01 = Multiply middle frequency components by 2.0 10 = Multiply middle frequency components by 4.0 11 = Zero out middle frequency components. 3-2 Low Frequency Enhancement Factor These bits adjust the amplitude of low frequency components in the luminance video signal. The attenuation or multiplication of the low frequency components is adjusted as shown below: 00B 00 = Multiply low frequency components by 1.0 01 = Multiply low frequency components by 2.0 10 = Multiply low frequency components by 4.0 11 = Zero out low frequency components. 1-0 Vertical High Frequency Enhancement Factor These bits adjust the amplitude of vertical high frequency components in the luminance video signal. The attenuation or multiplication of the vertical high frequency components is adjusted as shown below: 00 = Multiply vertical high frequency components by 1.0 01 = Reserved. 10 = Reserved. 11 = Zero out vertical high frequency components. 4-16 00B HMP8112A TABLE 11. COLOR SATURATION ADJUST FACTOR SUB ADDRESS = 0x05 BIT NUMBER 7-0 FUNCTION Color Saturation Adjust Factor DESCRIPTION This register sets the color saturation adjust factor. This value is multiplied by the chrominance (CbCr) data and allows the data to be scaled from 0 to a factor of +1.996. This 8-bit number is a fractional number as shown below: RESET STATE 1001 1101B (0x9D) 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 The default saturation factor of 1.2266 is calculated as follows: Register Data = Factor * 128 = 1.2266 * 128 = 157 = 0x9D TABLE 12. PLL CLOCK FREQUENCY RATIO (LSB) SUB ADDRESS = 0x06 BIT NUMBER 7-0 FUNCTION PLL Clock Frequency Ratio (LSB) DESCRIPTION These bits are used to program the ratio of the incoming video chrominance color subcarrier frequency to the input clock (CLK) used. This number serves as the reference frequency of the chrominance PLL. This is the lower byte (LSB) of the ratio and encompasses the following range: RESET STATE 1100 0001B (0xC1) 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 The default value is for a CLK frequency of 27MHz and a color subcarrier of 3.579545 MHz. The register data is calculated as follows: Ratio =(4 x fSC) / CLK =(4 x 3.579545MHz) / 27MHz =0.530303 Register Data: Ratio * 65536 0.530303 * 65536 34753.94 Convert to Hex:0x87C1 Reg 0x06 LSB =0xC1 Reg 0x07 MSB =0x87 Refer to Table 1 for common PLL Ratio values with CLKs of 27MHz or 24.54Hz TABLE 13. PLL CLOCK FREQUENCY RATIO (MSB) SUB ADDRESS = 0x07 BIT NUMBER 15 - 8 DESCRIPTION RESET STATE This is the upper data byte (MSB) of the PLL Clock Freq as described in Reg 0x06 above and encompasses the following range: 1000 0111B (0x87) FUNCTION PLL Clock Frequency Ratio (MSB) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 4-17 HMP8112A TABLE 14. HAGC START TIME (LSB) REGISTER SUB ADDRESS = 0x08 BIT NUMBER 7-0 FUNCTION HAGC START Time (LSB) DESCRIPTION This register provides a programmable delay for the HAGC pulse that control the sync tip AGC in the A/D converters. This is the lower byte of the 10-bit word. RESET STATE 0011 1111B (0x3F) TABLE 15. HAGC START TIME (MSB) REGISTER SUB ADDRESS = 0x09 BIT NUMBER 15 - 10 9-8 FUNCTION DESCRIPTION Not Used Write Ignored, Read 0’s. HAGC START Time (MSB) This register provides a programmable delay for the HAGC pulse that control the sync tip AGC in the A/D converters. This is the upper byte of the 10-bit word. RESET STATE 0000 0011B (0x03) TABLE 16. HAGC END TIME (LSB) REGISTER SUB ADDRESS = 0x0A BIT NUMBER 7-0 FUNCTION HAGC END Time (LSB) DESCRIPTION This register provides a programmable delay for the HAGC pulse that control the sync tip AGC in the A/D converters. This is the lower byte of the 10-bit word. RESET STATE 0000 0000B (0x00) TABLE 17. HAGC END TIME (MSB) REGISTER SUB ADDRESS = 0x0B BIT NUMBER 15 - 10 9-8 FUNCTION DESCRIPTION Not Used Write Ignored, Read 0’s HAGC END Time (MSB) This register provides a programmable delay for the HAGC pulse that controls the sync tip AGC in the A/D converters. This is the upper byte of the 10-bit word. RESET STATE 0000 0000B (0x00) TABLE 18. HSYNC START TIME (LSB) REGISTER SUB ADDRESS = 0x0C BIT NUMBER 7-0 FUNCTION DESCRIPTION RESET STATE HSYNC Pulse START Time (LSB) This register provides a programmable delay for the external HSYNC pulse. This is the lower byte of the 10-bit word. 0011 1011B (0x3B) TABLE 19. HSYNC START TIME (MSB) REGISTER SUB ADDRESS = 0x0D BIT NUMBER 15 - 10 9-8 FUNCTION Not Used DESCRIPTION RESET STATE Write Ignored, Read 0’s This register provides a programmable delay for the external HSYNC pulse. This is the HSYNC Pulse START Time (MSB) upper byte of the 10-bit word. 4-18 0000 0011B (0x03) HMP8112A TABLE 20. HSYNC END TIME (LSB) REGISTER SUB ADDRESS = 0x0E BIT NUMBER 7-0 DESCRIPTION RESET STATE This register provides a programmable delay for the external HSYNC pulse. This is the lower byte of the 10-bit word. 0010 0000B (0x20) FUNCTION HSYNC Pulse END Time (LSB) TABLE 21. HSYNC END TIME (MSB) REGISTER SUB ADDRESS = 0x0F BIT NUMBER 15 - 10 9-8 FUNCTION DESCRIPTION Not Used Write Ignored, Read 0’s HSYNC Pulse END Time (MSB) This register provides a programmable delay for the external HSYNC pulse. This is the upper byte of the 10-bit word. RESET STATE 0000 0000B (0x00) TABLE 22. PLL FILTER ADJUST REGISTER SUB ADDRESS = 0x10 BIT NUMBER 7-0 DESCRIPTION RESET STATE The Phase Locked Loop (PLL) time constants can be changed for testing purposes. It is recommended that the default value of 0x20 always be used. The reset state is 0x00. 0000 0000B (0x00) FUNCTION PLL Filter Adjust Register TABLE 23. PLL SYNC DETECT WINDOW REGISTER SUB ADDRESS = 0x11 BIT NUMBER 7-0 FUNCTION DESCRIPTION PLL Horizontal Sync These bits control the PLL horizontal sync detect window. This window sets the length Detect Window of time that the line lock PLL will allow the detection of the HSYNC. HSYNC outside of this window are declared missing and will cause the missing sync logic to start counting missing syncs. RESET STATE 1101 1101B (0xDD) TABLE 24. DC RESTORE START TIME (LSB) REGISTER SUB ADDRESS = 0x12 BIT NUMBER 7-0 FUNCTION DESCRIPTION RESET STATE DC RESTORE START Time (LSB) This register provides a programmable delay for the internal DC RESTORE signal. This is the lower byte of the 10-bit word. 0011 0111B (0x3F) TABLE 25. DC RESTORE START TIME (MSB) REGISTER SUB ADDRESS = 0x13 BIT NUMBER 15 - 10 9-8 FUNCTION Not Used DESCRIPTION RESET STATE Write Ignored, Read 0’s DC RESTORE This register provides a programmable delay for the internal DC RESTORE signal. This START Time (MSB) is the upper byte of the 10-bit word. 4-19 0000 0000B (0x00) HMP8112A TABLE 26. DC RESTORE END TIME (LSB) REGISTER SUB ADDRESS = 0x14 BIT NUMBER 7-0 DESCRIPTION RESET STATE This register provides a programmable delay for the internal DC RESTORE signal. This is the lower byte of the 10-bit word. 0101 0010B (0x52) FUNCTION DC RESTORE END Time (LSB) TABLE 27. DC RESTORE END TIME (MSB) REGISTER SUB ADDRESS = 0x15 BIT NUMBER 15 - 10 9-8 FUNCTION DESCRIPTION Not Used Write Ignored, Read 0’s DC RESTORE END Time (MSB) This register provides a programmable delay for the internal DC RESTORE signal. This is the upper byte of the 10-bit word. RESET STATE 0000 0000B (0x00) TABLE 28. OUTPUT FORMAT CONTROL REGISTER SUB ADDRESS = 0x16 BIT NUMBER 7 6, 5, 4 FUNCTION DESCRIPTION RESET STATE Square Pixel/ITU-R BT601 Select When “1”, Square pixel output is selected, when “0” ITU-R BT601 output rate is selected. 0B Output Field Control These bits control the field capture rate of the HMP8112A. The user can select every 4th “FLD_CONT(2-0)” field, every other field or every field of video to be output to the data port. 000B 000 = No Capture Enabled 001 = Capture every 4th field 010 = Capture every 2nd field 011 = Capture every 2nd odd field 100 = Capture every 2nd even field 101 = Capture every odd field 110 = Capture every even field 111 = Capture all fields 3 8/16 output Select When “1”, the 8-bit Burst Transfer output mode is selected. When “0”, the 16-bit Synchronous Pixel Transfer output mode is selected. 0B 2 OEN This bit enables the Y(7-0), CbCr(7-0), ACTIVE, FIELD, HSYNC, VSYNC and DVLD outputs. 1 = Outputs enabled; 0 = three-stated. 0B 1 Vertical Pixel Siting When this bit is cleared (‘0’) the chrominance pixels have a 1/2 line pixel offset from their associated luminance pixel in a 4:2:2 subsampled scheme. When this bit is set (‘1’) the pixel siting is line aligned with the luminance pixels in a 4:2:2 subsampled scheme. The bit is cleared by a RESET. 0B 0 Not Used Write Ignored, Read 0’s 0B 4-20 HMP8112A TABLE 29. SOFTWARE RESET AND VIDEO STATUS REGISTER SUB ADDRESS = 0x17 BIT NUMBER FUNCTION DESCRIPTION RESET STATE 7 Software Reset When this bit is set to 1, the entire device except the I2C bus is reset to a known state exactly like the RESET input. The software reset will initialize all register bits to their reset state. Once set this bit is self clearing after only 4 CLK periods. This bit is cleared on power-up by the external RESET pin. 0B 6 Black Screen This flag when set (‘1’) will set the output video to black when a lost vertical sync has been detect. This flag is cleared after a RESET. 0B 5 Line LOCKED Flag This flag when set (‘1’) indicates that the Line Locked-Phase Locked Loop has locked to the video data. This flag is read only and cleared after a RESET or Software Reset. 0B 4 Standard Error Flag This flag when set (‘1’) indicates that the Standard detected does not match the one selected in the Video Input Control Register. The standard is checked against a line count and if the line count is significantly different than the expected value then this flag is triggered. This flag is read only and cleared after a RESET or Software Reset. 0B 3-0 Not Used Write ignored, Read 0’s. 0000B TABLE 30. RESERVED SUB ADDRESS = 0x18 BIT NUMBER 7-0 FUNCTION Reserved DESCRIPTION This register is reserved. This register will read all zero’s and is write ignored. RESET STATE 0000 0000B TABLE 31. RESERVED SUB ADDRESS = 0x19 BIT NUMBER 7-6 5 4-0 FUNCTION DESCRIPTION RESET STATE Reserved This register is reserved. This register will read all zero’s and is write ignored. 00B Lost HSYNC Control (SNAP Bit) This bit controls when the PLL will declare lost horizontal sync, leave track mode and return to acquisition to acquire a new HSYNC reference. When this bit is cleared, lost line lock is declared after 12 missing horizontal syncs. When this bit is set, lost line lock is declared after one missing horizontal sync. This bit is cleared by RESET. 0B Reserved This register is reserved. This register will read all zero’s and is write ignored. 0 0000B TABLE 32. RESERVED SUB ADDRESS = 0x1A BIT NUMBER 7-0 FUNCTION Reserved DESCRIPTION This register is reserved. This register will read all zero’s and is write ignored. RESET STATE 0000 0000B TABLE 33. PRODUCT ID REGISTER SUB ADDRESS = 0x1B BIT NUMBER 7-0 DESCRIPTION RESET STATE This register contains the last two digits of the product part number for use as a software ID. These bits are read only and always read 0x12. 0001 0010B (0x12) FUNCTION Product ID Code 4-21 HMP8112A Pinout GND VCC DEC_T LAGC_CAP LCLAMP_CAP VCC NC NC GND HSYNC VSYNC GND VCC FIELD DVLD ACTIVE 80 LEAD PQFP TOP VIEW 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AGND VAA AGND NC LIN2 LIN1 LIN0 L_ADIN L_OUT AGND AGND VAA CLK VAA AGND AGND A/D_TEST NC CIN NC AGND AGND AGND AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 WPE GAIN_CNTL CCLAMP_CAP DEC_L VCC NC GND RESET GND TEST VCC CLK GND SDA GND VCC 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NOTE: 7. Refer to Pin Description for this pin. 4-22 Y7 Y6 GND NC (NOTE 7) Y5 VCC Y4 Y3 Y2 Y1 Y0 GND VCC CbCr7 CbCr6 CbCr5 CbCr4 CbCr3 GND CbCr2 NC (NOTE 7) CbCr1 CbCr0 SCL HMP8112A Pin Description NAME PQFP PIN NUMBER INPUT/ OUTPUT LIN0 7 Input Composite video input. This input must be AC-coupled to the video signal using a 1.0 µF capacitor and terminated with a 75-ohm resistor. These components should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND thru a 0.1 µF capacitor. LIN1 6 Input Composite video input. This input must be AC-coupled to the video signal using a 1.0 µF capacitor and terminated with a 75-ohm resistor. These components should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND thru a 0.1 µF capacitor. LIN2 5 Input Composite video or Luminance (Y) video input. This input must be AC-coupled to the video signal using a 1.0 µF capacitor and terminated with a 75-ohm resistor. These components should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND thru a 0.1 µF capacitor. CIN 19 Input Chrominance (C) video Input. This input must be AC-coupled to the video signal using a 1.0 µF capacitor and terminated with a 75-ohm resistor. These components, and corresponding anti-aliasing low-pass filter, should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND thru a 0.1 µF capacitor. WPE 27 Input White Peak Enable. When enabled (‘1’), the video amplifiers gain is reduced when the digital output code exceeds 248. When disabled (‘0’) the video amplifier will clip when the A/D reaches code 255. GAIN_CTRL 28 Input Gain Control Input. DC voltage to set the S-Video CIN chrominance video amplifier’s gain. Reference Figure 3 for gain control curve. DEC_T 78 Input Decoupling for upper A/D Converter Reference. Recommend connecting 0.1 µF and 0.01µF ceramic capacitors in parallel to AGND. DEC_L 30 Input Decoupling for lower A/D Converter Reference. Recommend connecting 0.1 µF and 0.01µF ceramic capacitors in parallel to AGND. LAGC_CAP 77 Input Capacitor Connection for Luminance AGC Circuit. Controls the AGC loop time constant. Recommend connecting a 0.01 µF ceramic capacitor to AGND. LCLAMP_CAP 76 Input Capacitor Connection for Luminance Clamp Circuit. Controls the clamp loop time constant. Recommend connecting a 0.047 µF ceramic capacitor to AGND. CCLAMP_CAP 29 Input Capacitor Connection for Chrominance Clamp Circuit. Controls the clamp loop time constant. Recommend connecting a 0.047 µF ceramic capacitor to AGND. L_ADIN 8 Input Luminance A/D Converter input from external anti-alias filter. Reference Figure 1. L_OUT 9 Output Analog output of the video multiplexer. This output should connect to an external anti-alias filter and return to L_ADIN input. Reference Figure 1. SDA 40 Input/ Output The serial I2C serial input/output data line. SCL 41 Input The serial I2C serial bus clock line. CLK 13, 38 Input Master clock for the decoder. This clock is used to run the internal logic, A/D converters, and Phase Locked Loops. All I/O pins (except the I2C) are synchronous to this master clock. A ±50ppm crystal should be used with a waveform symmetry of 60/40% or better. RESET 34 Input Asynchronous Reset pin. Master Chip reset to initialize the internal states and set the internal registers to a known state. DESCRIPTION 4-23 HMP8112A Pin Description (Continued) PQFP PIN NUMBER INPUT/ OUTPUT CbCr[0:7] 42, 43, 45, 47-51 Output CbCr Data Output Port. The chrominance data output port of the decoder. Data is in unsigned format and can range from 0 to 255. The CbCr data is subsampled to 4:2:2 format. In 4:2:2 format the CbCr bus toggles between Cb and Cr samples with the first sample of a line always being Cb. The port is designed to minimize external logic needed to interface to a VRAM Serial Access Port, DRAM or FIFO. Y[0:7] 54-58, 60, 63, 64 Output Y Data Output Port. The luminance data output port of the decoder. Data is in unsigned format and can range from 16 to 255. The port is designed to minimize external logic needed to interface to a VRAM Serial Access Port, DRAM or FIFO. DVLD 66 Output Data Valid. This pin signals when valid data is available on the data output ports. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. HSYNC 71 Output Horizontal Sync. This video synchronous pulse is generated by the detection of horizontal sync on the video input. In the absence of video, the HSYNC rate is set when the internal PLL counters overflow. The HSYNC START and END time can be programmed. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. VSYNC 70 Output Vertical Sync. This video synchronous pulse is generated by the detection of a vertical sync on the video input. In the absence of video the VSYNC rate is set by the over flow of the internal line rate counter. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. FIELD 67 Output Field Flag. When set (‘0’) this signals that an ODD field is presently being output from the decoder. When cleared (‘1’) this signals an EVEN field. This flag will toggle when no vertical sync is detected and 337 lines have elapsed. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. ACTIVE 65 Output Active Video Flag. This flag is asserted (‘1’) when the active portion of the video line is available on the output port. This signal is always set during Burst Output data mode. This flag is free running and synchronous to CLK. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. TEST 36 Input Test input. This pin is used for production test and should be connected to digital ground. VCC 26, 31, 37, 52, 59, 68, 75, 79 Input 5V Logic Supply Pins GND 25, 33, 35, 39, 46, 53, 62, 69, 72, 80 Input Digital Ground Pins VAA 2, 12,14 Input 5V Analog Supply Pins AGND 1, 3, 10, 11, 15,16, 21, 22, 23, 24 Input Analog GND A/D TEST 17 Output NC 44, 61 NA Pins used as logic outputs on later decoders. Refer to HMP8115 data sheet for details. NC 4, 18, 20, 32, 73, 74 NA No Connect. These pins should be left open. NAME DESCRIPTION Chrominance ADC Test Pin. This pin should be left open. 4-24 HMP8112A Absolute Maximum Ratings Thermal Information Digital Supply Voltage (VCC to GND) . . . . . . . . . . . . . . . . . . . . 7.0V Digital Input Voltages . . . . . . . . . . . . . . . . . GND -0.5V to VCC 0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, See Note 8) Operating Conditions Temperature Range, HMP8112ACN . . . . . . . . . . . . . . 0oC to 70oC θJA (oC/W) PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Maximum Power Dissipation HMP8112ACN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9W Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 8. θJA is measured with the component mounted on an evaluation PC board in free air. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board Electrical Specifications VCC = 5.0V, TA = 25oC HMP8112AC PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNITS 4.75 5 5.25 V POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range VCC, VAA Note 9 Digital ICCOP fCLK = 30MHz, VCC = 5.25V, Outputs Not Loaded - 45 60 mA Analog ICAOP fCLK = 30MHz, VAA = 5.25V - 190 220 mA PTOT fCLK = 30MHz, VCC = VAA = 5.25, Outputs Not Loaded - 1.11 1.47 W Bus Clock Frequency CLK Note 9 20 - 30 MHz Clock Cycle Time CLK 33 - 50 ns 40 - 60 % Power Supply Current Total Power Dissipation DIGITAL I/O Clock Waveform Symmetry Clock Pulse Width High tPWH 8 - - ns Clock Pulse Width tPWL 13 - - ns Input Logic High Voltage VIH CLK VCC = Max 2.8 - - V Input Logic Low Voltage VIL CLK VCC = Min - - 0.8 V VCC = Max Input = 0V or VCC - - 10 µA -450 - - µA Input Leakage Current IIH IIL Input/Output Capacitance CIN CLK Frequency = 1MHz, Note 9, All Measurements Referenced to Ground TA = 25oC - - 8 pF Rise/Fall Time tr, tf Note 9 - - 2.0 ns Input Logic High Voltage VIH VCC = Max 2.0 - - V Input Logic Low Voltage VIL VCC = Min - - 0.8 V VCC = Max Input = 0V or 5V - - ±10 µA Input Logic Current IIH, IIL 4-25 HMP8112A Electrical Specifications VCC = 5.0V, TA = 25oC (Continued) HMP8112AC PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNITS 2.4 - - V Output Logic High Voltage VOH IOH = -4mA, VCC = Max Output Logic Low Voltage VOL IOL = 4mA, VCC = Min - - 0.4 V Output Logic Current IOH VCC = Max, Input = 0V or 5V - - 4 mA Three-State Output Current Leakage IOZ - - 10 µA I2C DIGITAL I/O (SDA, SCL, Fast Mode) Input Logic High Voltage VIH VCC = Max 0.7x VCC - - V Input Logic Low Voltage VIL VCC = Min - - 0.3xVCC V VCC = Max Input = 0V or 5V - - 10 µA - - 8 pF 3.0 - - V Input Logic Current IIH, IIL Input/Output Capacitance CIN CLK Frequency = 400kHz, Note 9, All Measurements Referenced to GND TA = 25oC Output Logic High Voltage VOH IOH = -1mA, VCC = Max Output Logic Low Voltage VOL IOL = 3mA, VCC = Min 0 - 0.4 V SCL Clock Frequency fSCL Note 9 0 - 100 kHz SCL Minimum Low Pulse Width tLOW 4.7 - - µs SCL Minimum High Pulse Width tHIGH 4.0 - - µs Data Hold Time tHD:DATA 0 - - ns Data Setup Time tSU:DATA 250 - - ns - - 1000 ns - - 300 ns 10 - - ns Rise Time tR Fall Time tF Note 9 TIMING CHARACTERISTICS Data Setup Time tSU Data Hold Time tHD 0 - - ns tDVLD - - 8.0 ns Input Termination of 75Ω and 1.0µF AC Coupling, Note 9 0.5 1.0 2.0 VP-P Note 9 200 - - kΩ -6 - +18 dB 1VP-P Sine Wave Input to -3dBc Reduction, Note 9 - 15 - MHz Note 9 - VAA - 1.9 - V AIN Offset/Zero - VAA -3.4 - V BA/D 6 - - MHz Clock to Out Notes 9, 10 ANALOG PERFORMANCE Video Input Amplifier Voltage Range Video Input Amplifier Impedance Color Sub-carrier AGC Range Video Input Amplifier Analog Bandwidth A/D Input Range A/D Input Bandwidth VLIN[0:2], VCIN RAIN SCAGC B AIN Full Scale 4-26 HMP8112A Electrical Specifications VCC = 5.0V, TA = 25oC (Continued) HMP8112AC PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNITS - 2 - % - 1 - o - 2 - LSB - 0.35 1.0 LSB Note 9 - 49.9 - dB In Composite Input Mode, Note 9 - 40 - dB - 40 - dB Time from Initial Lock Acquisition to an Error of 1 Pixel, Note 9 - 30 - Lines Note 9 - - 12 # - - 3 # 400 - - Hz - 1/ 8 - Pixel - 10 - ns Color Saturation Adjustment Range - - 10 dB Hue Accuracy - - 2 oC Hue Adjustment Range - - 30 oC Brightness Adjustment Range - - 10 dB VIDEO PERFORMANCE Differential Gain AV DIFF Differential Phase Θ DIFF Integral Linearity INL Differential Linearity DNL SNR SNRL WEIGHTED Luminance to Chrominance Crosstalk XLUMA Chrominance to Luminance Crosstalk XCHROMA Horizontal Locking and Recovery Time tLOCK # of Missing Horizontal Syncs Before Lost Lock Declared HSYNC LOST # of Missing Vertical Syncs Before Lost Lock Declared VSYNC LOST EBU 75% Color Bars, Note 9 Best Fit Linearity Subcarrier Lock in Range Pixel Jitter NOTES: 9. Guaranteed by design or characterization. 10. Test performed with CL = 40pF, IOL = 4mA, IOH = -4mA. Input reference level is 1.5V for all inputs. VIH = 3.0V, VIL = 0V. 4-27 HMP8112A Typical Performance Curves NTSC Composite Phase FIGURE 19. COLOR BARS NTSC 100% (EIA) FIGURE 20. COLOR BARS VECTORSCOPE 4-28 HMP8112A Typical Performance Curves (Continued) NTSC Composite Phase (Continued) FIGURE 21. COLOR BARS VM700 TEST FIGURE 22. DIFFERENTIAL PHASE AND GAIN 4-29 HMP8112A Typical Performance Curves (Continued) NTSC Frequency Response FIGURE 23. MULTIBURST FIGURE 24. MULTIBURST VM700 FREQUENCY ROLL-OFF TEST 4-30 HMP8112A Typical Performance Curves (Continued) NTSC Noise Measurements FIGURE 25. SIGNAL TO NOISE RATIO - FLAT FREQUENCY RESPONSE FIGURE 26. SIGNAL TO NOISE RATIO - 5.0MHz LOW PASS FILTERED 4-31 HMP8112A Typical Performance Curves (Continued) NTSC Noise Measurements (Continued) FIGURE 27. SIGNAL TO NOISE RATIO - 4.2MHz LOW PASS FILTERED Pixel Jitter Test FIGURE 28. LONG TERM JITTER - 20 PULSE BAR 2T 4-32 HMP8112A Typical Performance Curves (Continued) PAL Composite Phase FIGURE 29. COLOR BARS NTSC 100% (EIA) FIGURE 30. COLOR BARS VECTORSCOPE 4-33 HMP8112A Typical Performance Curves PAL Composite Phase (Continued) (Continued) FIGURE 31. COLOR BARS VM700 TEST FIGURE 32. DIFFERENTIAL PHASE AND GAIN 4-34 HMP8112A Typical Performance Curves (Continued) PAL Frequency Response FIGURE 33. MULTIBURST FIGURE 34. NTSC MULTI-TEST PATTERN 4-35 HMP8112A Typical Performance Curves (Continued) FIGURE 35. NTSC CONVERGENCE TEST PATTERN FIGURE 36. NTSC MULTIBURST TEST PATTERN 4-36 HMP8112A Typical Performance Curves (Continued) FIGURE 37. NTSC SMPTE COLORBARS TEST PATTERN FIGURE 38. PAL CONVERGENCE TEST PATTERN 4-37 HMP8112A Typical Performance Curves (Continued) FIGURE 39. PAL MULTIBURST TEST PATTERN FIGURE 40. PAL SMPTE COLORBARS TEST PATTERN 4-38 HMP8112A PCB Layout Considerations A PCB board with a minimum of 4 layers is recommended, with layers 1 and 4 (top and bottom) for signals and layers 2 and 3 for power and ground. The PCB layout should implement the lowest possible noise on the power and ground planes by providing excellent decoupling. PCB trace lengths between groups of VCC and GND pins should be as short as possible. If a separate linear regulator is used to provide power to the analog power plane, the power-up sequence should be designed to ensure latchup will not occur. A separate linear regulator is recommended if the power supply noise on the VAA pins exceeds 200mV. The optimum layout places the HMP8112A as close as possible to the power supply connector and the video output connector. Traces containing digital signals should not be routed over, under, or adjacent to the analog output traces to minimize crosstalk. If this is not possible, coupling can be minimized by routing the digital signals at a 90 degree angle to the analog signals. The analog input traces should also not overlay the VAA power plane to maximize high-frequency power supply rejection. Component Placement External components should be positioned as close as possible to the appropriate pin, ideally such that traces can be connected point to point. Chip capacitors are recommended where possible, with radial lead ceramic capacitors the second-best choice. Power supply decoupling should be done using a 0.1µF ceramic capacitor in parallel with a 0.01µF chip capacitor for each group of VAA and VCC pins to ground. These capacitors should be located as close to the power and ground pins as possible, using short, wide traces. Digital Ground Plane All GND pins on the HMP8112A should be connected to the digital ground plane of the board. Analog Ground Plane A separate analog ground plane for the HMP8112A is recommended. All AGND pins on the HMP8112A should be connected to the analog ground plane. This analog ground plane should be connected to the board’s digital ground plane at a single point. Analog Signals Evaluation Boards The HMP8156EVAL2 stand-alone evaluation board allows connecting the NTSC/PAL decoder into an IBM PC ISA slot for evaluation. The board contains the HMP8112A NTSC/PAL decoder, 2 Mbytes of VRAM and a encoder. The board can accept Composite or S-Video input and display video on a stand composite or S-Video display. The ISA bus and Windows 95 evaluation software allows easy plug and play of the decoder for analysis with such tools as a VM700 video test system. Related Application Notes Application Notes are also available on the Harris Multimedia web site at: http://www.semi.harris.com/datasheets/mmedia. AN9644: Composite Video Separation Techniques AN9716: Widescreen Signalling Analog Power Plane AN9717: YCbCr to RGB Considerations The HMP8112A should have its own VAA power plane that is isolated from the common power plane of the board, with a gap between the two power planes of at least 1/8 inch. All VAA pins on the HMP8112A must be connected to this analog power plane. The analog power plane should be connected to the board’s normal VCC power plane at a single point though a low-resistance ferrite bead, such as a Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. The ferrite bead provides resistance to switching currents, improving the performance of HMP8112A. A single 47µF capacitor should also be used between the analog power plane and the ground plane to control low-frequency power supply ripple. AN9728: BT.656 Video Interface for ICs AN9738: VMI Video Interface for ICs 4-39 HMP8112A Metric Plastic Quad Flatpack Packages (MQFP/PQFP) Q80.14x20 (JEDEC MO-108CB-1 ISSUE A) 80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D D1 -D- -B- -AE E1 e PIN 1 SEATING A PLANE -H- 0.10 0.004 0.40 0.016 MIN -C- 5o-16o 0.20 A-B S 0.008 M C 0o MIN A2 A1 0o-7o L 5o-16o INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.134 - 3.40 - A1 0.010 - 0.25 - - A2 0.100 0.120 2.55 3.05 - B 0.012 0.018 0.30 0.45 6 B1 0.012 0.016 0.30 0.40 - D 0.904 0.923 22.95 23.45 3 D1 0.783 0.791 19.90 20.10 4, 5 E 0.667 0.687 16.95 17.45 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.026 0.037 0.65 0.95 N 80 80 7 e 0.032 BSC 0.80 BSC - ND 24 24 - NE 16 16 Rev. 0 1/94 NOTES: D S 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. B 2. All dimensions and tolerances per ANSI Y14.5M-1982. B1 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 0.13/0.17 0.005/0.007 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. BASE METAL WITH PLATING 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 0.13/0.23 0.005/0.009 7. “N” is the number of terminal positions. All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries. Sales Office Headquarters For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS NORTH AMERICA Harris Semiconductor P. O. Box 883, Mail Stop 53-210 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 EUROPE Harris Semiconductor Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 S E M I C O N D U C TO R 40 ASIA Harris Semiconductor PTE Ltd. No. 1 Tannery Road Cencon 1, #09-01 Singapore 1334 TEL: (65) 748-4200 FAX: (65) 748-0400