Intersil ISL6125EVAL1 Power sequencing controller Datasheet

ISL6123, ISL6124, ISL6125,
ISL6126, ISL6127, ISL6128, ISL6130
®
Data Sheet
February 5, 2007
FN9005.8
Power Sequencing Controllers
Features
The Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127,
ISL6128 and ISL6130 are integrated four channel
controlled-on/controlled-off power-supply sequencers with
supply monitoring, fault protection and a “sequence
completed” signal (RESET#). For larger systems, more than
four supplies can be sequenced by simply connecting a wire
between SYSRESET# pins of cascaded IC's. The ISL6125
uses four open-drain outputs to control the on/off sequencing
of four supplies, while the other sequencers use a patented,
micropower 7X charge pump to drive four external low-cost
NFET switch gates above the supply rail by 5.3V. These IC's
can be biased from any supply 5V down to 1.5V. Individual
product descriptions follow.
• Enables arbitrary turn-on and turn-off sequencing of up to
four power supplies (0.7V to 5V)
The four channel ISL6123 (ENABLE input), ISL6124
(ENABLE# input) and ISL6125 ICs offer the designer 4 rail
control when it is required that all four rails are in minimal
compliance prior to turn on and that compliance must be
maintained during operation. The ISL6123 and ISL6130
have a low power standby mode when disabled, suitable for
battery powered applications.
• Open drain version available (ISL6125)
• Operates from 1.5V to 5V supply voltage
• Supplies VDD +5.3V of charge pumped gate drive
• Adjustable voltage slew rate for each rail
• Multiple sequencers can be daisy-chained to sequence an
infinite number of independent supplies
• Glitch immunity
• Under voltage lockout for each supply
• 1µA Sleep State (ISL6123, ISL6130)
• Active high (ISL6123, ISL6130) or low (ISL6124, ISL6125,
ISL6126, ISL6127, ISL6128) ENABLE# input
• Voltage Determined Sequence (ISL6126, ISL6130)
• Pre-programmed Sequence available (ISL6127)
• Dual channel groupings (ISL6128)
• QFN package with Pb-free plus anneal option (RoHS
compliant)
The ISL6125 operates like the ISL6124 but instead of
charge pump driven gate drive outputs it has open drain
logic outputs for direct interface to other circuitry.
Applications
In contrast to the majority, for both the ISL6126 and ISL6130
each of the four channels operates independently so that the
various GATEs will turn on once its individually associated
input voltage requirements are met.
• Network routers
• Graphics cards
• FPGA/ASIC/microprocessor/PowerPC supply sequencing
• Telecommunications systems
1
SYSRST#
DLY_ON_A
UVLO_A
NC
21
20
19
1
18 DLY_OFF_A
GATE_A
2
17 UVLO_C
DLY_OFF_C
3
16 DLY_ON_C
4mmx4mm
15 DLY_ON_D
GATE_B
5
14 UVLO_D
GATE_C
6
13 DLY_OFF_B
7
8
9
10
11
12
UVLO_B
4
NC
DLY_OFF_D
GND
For volume applications, other programmable options and
features can be had. Contact the factory with your needs.
22
NC
Additional I/O is provided indicating and driving RESET state
in various configurations.
23
DLY_ON_B
External resistors provide flexible voltage threshold
programming of monitored rail voltages. Delay and
sequencing are provided by external capacitors for both
ramp up and ramp down.
24
ENABLE/
ENABLE#
GATE_D
The ISL6128 has two groups of two channels each with its
independent I/O and is ideal for voltage sequencing into
redundant capability loads as all four inputs need to be
satisfied prior to turn on but a single group fault is ignored by
the other group.
ISL6123, ISL6124, ISL6125,
ISL6126, ISL6127, ISL6128, ISL6130
(24 LD QFN)
TOP VIEW
VDD
The ISL6127 is a pre programmed A-B-C-D turn-on and
D-C-B-A turn-off sequenced IC. Once all inputs are in
compliance and ENABLE is asserted the sequencing starts
and each subsequent GATE will turn-on after the previous
one completes turning-on.
RESET#
Pinout
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2003-2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Ordering Information
PART NUMBER*
TEMP.
RANGE (°C)
PART MARKING
ISL6123IR
PKG.
DWG. #
PACKAGE
ISL6123IR
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6124IR
ISL6124IR
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6125IR
ISL6125IR
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6126IR
ISL6126IR
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6127IR
ISL6127IR
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6128IR
ISL6128IR
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6123IRZA (Note)
6123IRZ
-40 to +85
24 Ld 4x4 QFN (Pb-free)
L24.4x4
ISL6124IRZA (Note)
6124IRZ
-40 to +85
24 Ld 4x4 QFN (Pb-free)
L24.4x4
ISL6125IRZA (Note)
6125IRZ
-40 to +85
24 Ld 4x4 QFN (Pb-free)
L24.4x4
ISL6126IRZA (Note)
6126IRZ
-40 to +85
24 Ld 4x4 QFN (Pb-free)
L24.4x4
ISL6127IRZA (Note)
6127IRZ
-40 to +85
24 Ld 4x4 QFN (Pb-free)
L24.4x4
ISL6128IRZA (Note)
6128IRZ
-40 to +85
24 Ld 4x4 QFN (Pb-free)
L24.4x4
ISL6130IRZA (Note)
6130IRZ
-40 to +85
24 Ld 4x4 QFN (Pb-free)
L24.4x4
ISL612XSEQEVAL1
ISL612X Evaluation Platform
ISL6125EVAL1
ISL6125 Evaluation Platform
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which
are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
AIN
ISL6123 Block Diagram (1/4)
AOUT
BIN
BOUT
CIN
COUT
DIN
VDD
BIAS
VDD+5V
LOCK OUT
Q-PUMP
DOUT
VDD
ENABLE
AIN
BIN
CIN
DIN
GATE A
GATE B
GATE C
GATE D
1µA
1µA
DLY_ONX
UVLO_A
UVLO_B
SYSRST#
UVLO_C
RESET#
UVLO_D
1.26V
DLY_OFF_D
DLY_ON_D
DLY_OFF_C
DLY_ON_C
DLY_OFF_B
DLY_ON_B
DLY_OFF_A
DLY_ON_A
-1µA
1µA
GROUND
DLY_OFFX
10ms
RISING DELAY
1.26V
FIGURE 1. TYPICAL ISL6123 APPLICATION
USAGE
GATEX
30µs
FILTER
UVLOX
RESET#
LOGIC
0.633V
150ms
RISING DELAY
EN
SYSRST
2
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Descriptions
PIN #
PIN NAME
FUNCTION
23
VDD
Chip Bias
Bias IC from nominal 1.5V to 5V
10
GND
Bias Return
IC ground
1
ENABLE_1/ Input to start on/off
ENABLE#_1 sequencing.
11
ENABLE#_2
24
RESET#
9
RESET#_2
20
UVLO_A
12
UVLO_B
17
UVLO_C
14
UVLO_D
21
DLY_ON_A
8
DLY_ON_B
16
DLY_ON_C
DESCRIPTION
Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality
is disabled for 10ms after UVLO is satisfied. ISL6123 and ISL6130 have ENABLE. ISL6124,
ISL6125, ISL6126 and ISL6127 have ENABLE#. Only ISL6128 has 2 ENABLE# inputs, 1 for
each 2 channel grouping. EN_1# for (A, B), and EN_2# for (C, D).
RESET# Output
RESET# provides a low signal 150ms after all GATEs are fully enhanced. This delay is for
stabilization of output voltages. RESET# will assert low upon UVLO not being satisfied or
ENABLE/ENABLE# being deasserted. The RESET outputs are open drain N channel FET and is
guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on
VDD and UVLO_X.
RESET#_2 only exists on ISL6128 for (C, D) group I/O.
Under Voltage Lock
Out/Monitoring
Input
These inputs provide for a programmable UV lockout referenced to an internal 0.633V reference
and are filtered to ignore short (<30µs) transients below programmed UVLO level.
Gate On Delay
Timer Output
Allows for programming the delay and sequence for Vout turn-on using a capacitor to ground. Each
cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current
source providing delay to the associated FETs GATE turn-on.
These pins are NC on ISL6126, ISL6127 and ISL6130.
15
DLY_ON_D
18
13
DLY_OFF_A Gate Off Delay
Timer Output
DLY_OFF_B
3
DLY_OFF_C
Allows for programming the delay and sequence for Vout turn-off through ENABLE/ENABLE# via a
capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference
voltage causing the corresponding gate to be pulled down turning-off the FET.
These pins are NC on ISL6127.
4
DLY_OFF_D
2
GATE_A
5
GATE_B
6
GATE_C
7
GATE_D
22
SYSRST#
19
No Connect
FET Gate Drive
Output
ISL6125 Open
Drain Outputs
Drives the external FETs with a 1µA current source to soft start ramp into the load.
On the ISL6125 only, these are open drain outputs that can be pulled up to a maximum of
VDD voltage.
System Reset I/O
As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low.
This input can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms
stabilization delay) from input signal on this pin being driven high to first GATE. As an output when
there is a UV condition, this pin pulls low. If common to other SYSRST# pins in a multiple IC
configuration, it will cause immediate and unconditional latch-off of all other GATEs on all other
ISL612X sequencers. This pin is a NC on ISL6126 and ISL6128 and ISL6130.
No Connect
No Connect
3
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL612X Variant Feature Matrix
NUMBER OF
NUMBER OF CHANNELS
THAT
UVLO
TURN-OFF
INPUTS
GATE DRIVE REQUIRED
WHEN 1
OR OPEN CONDITIONS MONITORED
UVLO
BY EACH
FOR INITIAL
DRAIN
CMOS/
FAULTS
RESET#
START-UP
OUTPUTS
TTL
PRESET OR
ADJUSTABLE
SEQUENCE
NUMBER OF
UVLO AND
PAIRS OF I/O
PART
NAME
EN/EN#
ISL6123
EN
TTL
Gate Drive
4 UVLO
1 EN
4 UVLO
4 Gates
Time Adjustable 4 Monitors with Auto Restart,
On and Off
1 I/O
Low bias current
sleep
ISL6124
EN#
CMOS
Gate Drive
4 UVLO
1 EN
4 UVLO
4 Gates
Time Adjustable 4 Monitors with Auto Restart
On and Off
1 I/O
ISL6125
EN#
CMO
Open Drain
4 UVLO
1 EN
4 UVLO
ISL6126
EN#
CMOS
Gate Drive
1 UVLO
1 EN
4 UVLO
1 Gate
ISL6127
EN#
CMOS
Gate Drive
4 UVLO
1 EN
4 UVLO
4 Gates
Preset
ISL6128
EN#
CMOS
Gate Drive
4 UVLO
2 EN
2 UVLO
2 Gates
Preset
ISL6130
EN
TTL
Gate Drive
1 UVLO
1 EN
4 UVLO
1 Gates
4
FEATURES
4 Open Drain Time Adjustable 4 Monitors with Auto Restart, Open
On and Off
1 I/O
Drain Sequenced
Outputs
4 Monitors with Gates Independent
Voltage
1 I/O
On as UVLO Valid
Determined ON
Time
Adjustable Off
4 Monitors with Auto Restart
1 I/O
2 Monitors
with 2 I/O
4 Monitors with
Voltage
1 I/O
Determined ON
Time
Adjustable Off
Dual Redundant
Operation
Gates Independent
On as UVLO Valid
Low bias current
sleep
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Absolute Maximum Ratings
Thermal Information
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V
ISL6125 LOGIC OUT. . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to VDD +0.3V
RESET#, DLY_ON, DLYOFF . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Thermal Resistance (Typical, Notes 1, 2)
θJC (°C/W)
θJA (°C/W)
4 x 4 QFN Package . . . . . . . . . . . . . . .
48
9
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(QFN - Leads Only)
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +1.5V to +5.5V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
619
633
647
mV
UVLO
Falling Undervoltage Lockout Threshold
VUVLOvth
Undervoltage Lockout Threshold Tempco
TCUVLOvth
Undervoltage Lockout Hysteresis
VUVLOhys
Undervoltage Lockout Threshold Range
RUVLOvth
Undervoltage Lockout Delay
TUVLOdel
Transient Filter Duration
TFIL
TJ = +25°C
TJ = -40°C to +85°C
40
nV/°C
10
mV
Max VUVLOvth- Min VUVLOvth
7
mV
ENABLE satisfied
10
ms
VDD, UVLO, ENABLE glitch filter
30
μs
DELAY ON/OFF
Delay Charging Current
DLY_ichg
Delay Charging Current Range
DLY_ichg_r
Delay Charging Current Temp. Coeff.
VDLY = 0V
DLY_ichg(max) - DLY_ichg(min)
TC_DLY_ichg
Delay Threshold Voltage
DLY_Vth
Delay Threshold Voltage Temp. Coeff.
0.92
1.238
TC_DLY_Vth
1
μA
1.08
0.08
μA
0.2
nA/°C
1.266
1.294
V
0.2
mV/°C
ENABLE/ENABLE#, RESET# & SYSRST# I/O
ENABLE Threshold
VENh
1.2
V
ENABLE# Threshold
VENh
0.5 VDD
V
ENABLE/ENABLE# Hysteresis
VENh -VENl
Measured at VDD = 1.5V
0.2
V
ENABLE/ENABLE# Lockout Delay
TdelEN_LO
UVLO satisfied
10
ms
ENABLE/ENABLE# Input Capacitance
Cin_en
5
pF
RESET# Pull-up Voltage
Vpu_rst
VDD
V
RESET# Pull-Down Current
IRSTpd1
VDD = 1.5V, RST = 0.1V
5
mA
IRSTpd3
VDD = 3.3V, RST = 0.1V
13
mA
IRSTpd5
VDD = 5V, RST = 0.1V
17
mA
TRSTdel
GATE = VDD+5V
160
ms
RESET# Delay after GATE High
RESET# Output Low
VRSTl
RESET Output Capacitance
Cout_rst
5
Measured at VDD = 5V with 5k
pull-up resistors
0.1
10
V
pF
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Electrical Specifications
VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
SYSRST# Pull-Up Voltage
TEST CONDITIONS
MIN
Vpu_srst
SYSRST# Pull-Down Current
Ipu_1.5
Ipu_5
SYSRST# Low Output Voltage
Vol_srst
SYSRST# Output Capacitance
Cout_srst
SYSRST# Low to GATE Turn-Off
TdelSYS_G
TYP
MAX
UNIT
VDD
V
5
μA
VDD = 5V
100
μA
VDD = 1.5V, IOUT = 100μA
150
mV
10
pF
40
ns
VDD = 1.5V
GATE = 80% of VDD+5V
GATE
GATE Turn-On Current
IGATEon
GATE Turn-Off Current
IGATEoff_l
GATE Current Range
IGATE_range
GATE Turn-On/Off Current Temp. Coeff.
TC_IGATE
GATE Pull-Down High Current
IGATEoff_h
GATE High Voltage
GATE Low Voltage
GATE = 0V
0.8
1.1
1.4
μA
GATE = VDD, Disabled
-1.4
-1.05
-0.8
μA
0.35
μA
Within IC IGATE max-min
GATE = VDD, UVLO = 0V
VGATEh
VDD < 2V, TJ = +25°C
VGATEh
VDD > 2V
VGATEl
Gate Low Voltage, VDD = 1V
IVDD_5V
VDD+5V
0.2
nA/°C
88
mA
VDD+4.9V
V
VDD+5.3V
V
0
0.1
V
VDD = 5V
0.20
0.5
mA
IVDD_3.3V
VDD = 3.3V
0.14
mA
IVDD_1.5V
VDD = 1.5V
0.10
mA
BIAS
IC Supply Current
ISL6123, ISL6130 Stand By IC Supply
Current
VDD Power On Reset
IVDD_sb
VDD = 5V, ENABLE = 0V
VDD_POR
Descriptions and Operation
The ISL612X sequencer family consists of several four
channel voltage sequencing controllers in various
functional and personality configurations. All are designed
for use in multiple-voltage systems requiring power
sequencing of various supply voltages. Individual voltage
rails are gated on and off by external N-Channel MOSFETs,
the gates of which are driven by an internal charge pump to
VDD +5.3V (VQP) in a user programmed sequence.
With the four-channel ISL6123 the ENABLE must be
asserted high and all four voltages to be sequenced must
be above their respective user programmed Under Voltage
Lock Out (UVLO) levels before programmed output turn on
sequencing can begin. Sequencing and delay
determination is accomplished by the choice of external
cap values on the DLY_ON and DLY_OFF pins. Once all
four UVLO inputs and ENABLE are satisfied for 10ms, the
four DLY_ON caps are simultaneously charged with 1µA
current sources to the DLY_Vth level of 1.27V. As each
DLY_ON pin reaches the DLY_Vth level its associated
GATE will then turn-on with a 1µA source current to the
VQP voltage of VDD+5.3V. Thus all four GATEs will
sequentially turn on. Once at DLY_Vth the DLY_ON pins
6
1
μA
1
V
will discharge to be ready when next needed. After the
entire turn on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay is started to ensure stability after which the
RESET# output will be released to go high. Subsequent to
turn-on, if any input falls below its UVLO point for longer
than the glitch filter period (~30μs) this is considered a
fault. RESET# and SYSRST# are pulled low and all GATEs
are simultaneously also pulled low. In this mode the GATEs
are pulled low with 88mA. Normal shutdown mode is
entered when no UVLO is violated and the ENABLE is
deasserted. When ENABLE is deasserted, RESET# is
asserted and pulled low. Next, all four shutdown ramp caps
on the DLY_OFF pins are charged with a 1μA source and
when any ramp-cap reaches DLY_Vth, a latch is set and a
current is sunk on the respective GATE pin to turn off its
external MOSFET. When the GATE voltage is
approximately 0.6V, the GATE is pulled down the rest of the
way at a higher current level. Each individual external FET
is thus turned off removing the voltages from the load in the
programmed sequence.
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
The ISL6123 and ISL6124 have the same functionality
except for the ENABLE active polarity with the ISL6124
having an ENABLE# input. Additionally the ISL6123 and
ISL6130 also have an ultra low power sleep state when
ENABLE is low.
The ISL6125 has the same personality as the ISL6124 but
instead of charged pump driven GATE outputs it has open
drain outputs that can be pulled up to a maximum of VDD.
The ISL6126 and ISL6130 are different in that their
sequence on is not time determined but voltage
determined. Its personality is that each of the four channels
operates independently so that once the IC is biased and
any one of the UVLO inputs is greater than the 0.63V
internal reference, and the enable input is also satisfied the
GATE for the associated UVLO input will turn-on. In turn,
the other UVLO inputs need to be satisfied for the
associated GATEs to turn-on. 150ms after all GATEs are
fully on (GATE voltage = VQP), the RESET# is released to
go high. The UVLO inputs can be driven by either a
previously turned on output rail offering a voltage
determined sequence or by logic signal inputs. Any
subsequent UVLO level < its programmed level will pull the
associated GATE and RESET# output low (if previously
released), but will not latch-off the other GATEs.
Predetermined turn-off is accomplished by deasserting
enable, this will cause RESET# to latch low and all four
GATE outputs to follow the programmed turn off sequence
similar to a ISL6124.
The ISL6127 is a four-channel sequencer pre-programmed
for A-B-C-D turn-on and D-C-B-A turn-off. After all four
UVLO and ENABLE# inputs are satisfied for ~10ms, the
sequencing starts and the next GATE in the sequence
starts to ramp up once the previous GATE has reached
~VQP-1V. 160ms after the last GATE is at VQP the
RESET# output will be deasserted. Once any UVLO is
unsatisfied, RESET# is pulled low, SYSRST# is pulled low
and all GATEs are simultaneously turned off. When
ENABLE# is signaled high the D GATE will start to pull low
and once below 0.6V the next GATE will then start to pull
low and so on until all GATEs are at 0V. Unloaded, this turn
off sequence will complete in <1ms. This variant offers a
lower cost and size implementation as the external delay
caps are not used. Since the delay caps are not used this
IC can not delay the start of subsequent GATEs thus
necessary stabilization or system house keeping need to
be considered.
The ISL6128 is a four-channel device that groups the four
channels into two groups of two channels each, as A, B
and C, D, each group having its own ENABLE# and
RESET# I/IO pins. This requires all four UVLO and both
ENABLE#s to be satisfied for sequencing to start. The A, B
group will first turn on 10ms after the second ENABLE# is
pulled low with A then B turning on followed by C then D.
Once the preceding GATE = VQP the next DLY_ON pin
7
starts to charge its capacitor thus turning on all four GATEs.
Approximately 160ms after D GATE = VQP the RESET#
output is released to go high. Once any UVLO is unsatisfied,
only the related group’s RESET# and two GATEs are pulled
low. The related EN input has to be cycled for the faulted
group to be turned-on again. Normal shutdown is invoked by
either signaling both ENABLE# inputs high which will cause all
the two related GATEs to shutdown in reverse order from turnon. DLY_X caps adjust the delay between GATES during turn
on and off but not the order.
During bias up the RESET# output is guaranteed to be in the
correct state with VDD lower than 1V.
The SYSRST# pin follows the VDD upon power up with a
weak internal pull-up and is both an input and output
connection providing two functions. As an input, if it is pulled
low all GATEs will be unconditionally shut off and RESET#
pulls low, see Figure 6. This input can also be used as a no
wait enabling input, if all inputs (ENABLE and UVLO) are
satisfied it does not wait through the ~10ms enable delay to
initiate DLY_ON cap charging when released to go high. As
an output it is useful when implementing multiple sequencers
in a design needing simultaneous shutdown as with a kill
switch across all sequencers. Once any UVLO is unsatisfied
longer than TFIL the related SYSRST# will pull low and pull all
other SYSRST# inputs low that are on a common connection
thus unconditionally shutting down all outputs across multiple
sequencers.
Except for ISL6128 after a fault, restart of the turn on
sequence is automatic once all requirements are met. This
allows for no interaction between the sequencer and a
controller IC if desired. The ENABLE & RESET# I/O do allow
for a higher level of feedback and control if desired. The
ISL6128 requires that the related ENABLE# be cycled for
restart of its associated group GATEs. If no capacitors are
connected between DLY_ON or DLY_OFF pins and ground
then all such related GATEs start to turn on immediately after
the 10ms (TUVLOdel) ENABLE stabilization time out has
expired and the GATEs start to immediately turn off when
ENABLE is asserted.
If some of the rails are to be sequenced together, in order to
eliminate the effect of capacitor variance on the timing and to
reduce cost, a common capacitor can be connected to two or
more DLY_ON or DLY_OFF pins. In this case multiply the
capacitor value by the number of common DLY_X pins to
retain the desired timing.
Table 1 illustrates the nominal time delay from the start of
charging to the 1.27V reference for various capacitor values
on the DLY_X pins. This table does not include the 10ms of
enable lock out delay during a start up sequence but
represents the time from the end of the enable lock out delay
to the start of GATE transition. There is no enable lock out
delay for a sequence off, so this table illustrates the delay to
GATE transition from a disable signal.
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Figure 2 illustrates the turn-on and Figure 3 illustrates the
nominal turnoff timing diagram of the ISL6123 and ISL6124
product.
TABLE 1.
NOMINAL DELAY TO SEQUENCING THRESHOLD
DLY PIN CAPACITANCE
TIME(s)
Open
0.00006
100pF
0.00013
1000pF
0.0013
0.01μF
0.013
0.1μF
0.13
1μF
1.3
10μF
13
The ISL6125 is similar to the ISL6124 except that instead of
charge pumped GATE outputs, there are sequenced open
drain outputs that can be pulled up to a maximum of VDD.
Note the delay and flexible sequencing possibilities. Multiple
series, parallel or adjustable capacitors can be used to easily
fine tune timing between that offered by standard value
capacitors.
NOTE: Nom. TDEL_SEQ = Cap (μF) * 1.3MΩ.
l
VUVLOVth
<TFIL
UVLO_A
VUVLOVth
UVLO_B
VUVLOVth
UVLO_C
VUVLOVth
UVLO_D
ENABLE# (ISL6124)
TUVLOdel
VEN
ENABLE (ISL6123)
DLY_Vth
DLYON_B
DLY_Vth
DLYON_D
DLY_Vth
DLYON_A
DLY_Vth
DLYON_C
VQPUMP
VQPUMP
VQPUMP
GATE_B
VQPUMP
GATE_D
VQPUMP-1V
GATE_C
TRSTdel
GATE_A
RESET#
FIGURE 2. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM
8
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
UVLO_X>VUVLOVth
ENABLE (ISL6123)
VEN
ENABLE# (ISL6124)
DLY_Vth
DLYOFF_A
DLY_Vth
DLYOFF_B
DLY_Vth
DLYOFF_C
DLY_Vth
DLYOFF_D
GATE_C
GATE_D
GATE_A
GATE_B
RESET#
FIGURE 3. ISL6123, ISL6124 TURN-OFF TIMING DIAGRAM
Typical Performance Curves
1.04
634
1.03
VDD = 5V
632
DLY CURRENT SOURCE (µA)
UV THRESHOLD (mV)
633
631
630
VDD = 1.5V
629
628
627
626
-40
-20
0
20
40
60
TEMPERATURE (°C)
FIGURE 4. UVLO THRESHOLD VOLTAGE
9
80
100
1.02
1.01
1.00
VDD = 1.5V
0.99
DLY_OFF/ON
0.98
0.97
-40
VDD = +5V
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 5. DLY CHARGE CURRENT
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Typical Performance Curves
(Continued)
GATE
5VOUT
3.3VOUT
SYSRST#
1μs/DIV
2V/DIV
FIGURE 6. SYSRST# LOW TO OUTPUT LATCH OFF
Using the ISL612XSEQEVAL1 Platform
The ISL612XSEQEVAL1 platform is the primary evaluation
board for this family. The board has two complete, separate
and electrically identical circuits. See Figure 15 for its
schematic and photograph. Additionally, there is an ISL6125
specific eval platform, ISL6125EVAL1, due to its unique
open drain outputs for ease of evaluation. See Figure 16 for
its schematic and photograph.
In the top right hand corner of the board is a SMD layout with
a ISL6123 illustrating the full functionality and small
implementation size for an application having the highest
component count.
The majority of the board is given over to a socket and
discrete through-hole components circuit for ease of
evaluation flexibility through IC variant swapping and
modification of UVLO levels and sequencing order by
passive component substitution.
The board is shipped with the ISL6123 installed in both
locations and with two each of the other released variant
types loose packed. As this sequencer family has a common
function pinout there are no major modifications to the board
necessary to evaluate the other ICs.
To the left, right and above the socket are four test point
strips (TP1, TP2, TP3, TP4). These give access to the
labeled IC I/O pins during evaluation. Remember that
significant current or capacitive loading of particular I/O pins
will affect functionality and performance.
Attention to orientation and placement of variant ICs in the
socket must be paid to prevent IC damage or faulty
evaluation.
10
The default configuration of the ISL612XSEQEVAL1
circuitries was built around the following design
assumptions:
1. Using the ISL6123IR or ISL6124IR
2. The four supplies being sequenced are 5V (IN_A), 3.3V
(IN_B), 2.5V (IN_C) and 1.5V (IN_D), the UVLO levels
are ~80% of nominal voltages. Resistors chosen such
that the total resistance of each divider is ~10k using
standard value resistors to approximate 80% of
nominal = 0.63V on UVLO input.
Resistor choice is such that I x R2 = 0.633V at the desired
UV (undervoltage) level as the monitored voltage
decreases. Total resistance in the divider is a factor for
the designer to consider for accuracy of UV level and
efficiency vs electrical noise immunity trade-offs.
Vmonitored
R1
UVLO
R2
Vmon/0.633mV = R1+R2/R2
when Vmon = desired UV level as
Vmon decreases.
For example, a 5V supply with a
desired UV level at 4V would mean
R1+R2/R2 = 6.319. Ideally, any R1
and R2 combination that met this ratio
would work, but with only standard
value resistors available, small
deviations will occur.
3. The desired order turn-on sequence is first both 5V and
3.3V supplies together and then the 2.5V supply about
75ms later and lastly the 1.5V supply about 45ms later.
4. The desired turn-off sequence is first both 1.5V and 3.3V
supplies at the same time then the 2.5V supply about
50ms later and lastly the 5V supply about 72ms after that.
All scope shots are taken from ISL612XSEQEVAL1 board.
Figures 7 and 8 illustrate the desired turn-on and turn-off
sequences respectively. The sequencing order and delay
between voltages sequencing is set by external capacitance
values, so other than illustrated can be accomplished.
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Figures 9 and 10 illustrate the timing relationships between the
EN input, RESET#, DLY and GATE outputs and the VOUT
voltage for a single channel being turned on and off
respectively. RESET# is not shown in Figure 9 as it asserts
160ms after the last GATE goes high.
All IC family variants share similar function for DLY_X capacitor
charging, GATE and RESET# operation. Figures 11 through 14
illustrate the principal feature and functional differences for
each of the ISL6125, ISL6126, ISL6127 and ISL6128 variants.
Figure 11 features the ISL6125 open drain outputs being
sequenced on and off along with RESET# relationship which is
similar to all other family variants.
Figure 12 illustrates the independent input feature of the
ISL6126 which allows once the EN# is low for each UVLO to be
individually satisfied and for its associated GATE to turn-on.
Only when the last variable VIN is satisfied as shown does the
RESET# release to signal all input voltages are valid.
Figure 13 shows the ISL6127 pre-programmed ABCD on
DCBA off order of sequencing with minimal non-adjustable
delay between each.
Figure 14 demonstrates the independence of the redundant
two rail sequencer. It shows that either one of the two groups
can be turned off and the ABCD order of restart with
capacitor programmable delay once both EN inputs are
pulled low.
Using the ISL6125EVAL1 Platform
The ISL6125EVAL1 is the ISL6125 specific evaluation board
providing for easy evaluation of the ISL6125 with its unique
open drain outputs. The UVLO levels, sequence and delays
are programmed exactly like the other ISL612X ICs but the
ISL6125 has sequenced open drain outputs rather than
charge pumped driven GATE outputs. See Figure 16 for its
schematic and photograph.
Typical Performance Waveforms
5VOUT
5VOUT
RESET#
ENABLE#
3.3VOUT
3.3VOUTPUT
2.5VOUT
2.5VOUT
1.5VOUT
1.5VOUT
ENABLE#
1V/DIV
40ms/DIV
FIGURE 7. ISL6124 SEQUENCED TURN-ON
TdelENLO
GATE 2V/DIV
3.3VO 1V/DIV
DLY_Vth
1V/DIV
20ms/DIV
FIGURE 8. ISL6124 SEQUENCED TURN-OFF
GATE 2V/DIV
3.3VO 1V/DIV
DLY_Vth
RESET# 2V/DIV
EN 2V/DIV
DLY_ON 1V/DIV
DLY_OFF 1V/DIV
EN 2V/DIV
10ms/DIV
FIGURE 9. ISL6123 SINGLE CHANNEL TURN-ON
11
4ms/DIV
FIGURE 10. ISL6123 SINGLE CHANNEL TURN-OFF
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Typical Performance Waveforms
(Continued)
VIN_VAR
EN#
RESET#
STATIC EN/ALL OTHER VOUT
VOUT_VAR
LOGIC A -D
SEQUENCED
OUTPUTS
TRSTdel
RESET#
100ms/DIV
FIGURE 11. ISL6125 LOGIC OUTPUTS SEQUENCED ON AND
OFF AND RESET# RELATIONSHIP
100ms/DIV
FIGURE 12. ISL6126 UVLO INPUT/OUTPUT INDEPENDENCE
AND RESET# RELATIONSHIP
EN#_1 5V/DIV
A_VOUT
EN#_2 5V/DIV
B_VOUT
C_VOUT
A_VOUT
D_VOUT
B_VOUT
C_VOUT
D_VOUT
FIGURE 13. ISL6127 PREPROGRAMMED ABCD TURN-ON AND
DCBA TURN-OFF
12
FIGURE 14. ISL6128 GROUP INDEPENDENT TURN-OFF AND
DELAY ADJUSTABLE PRE PROGRAMMED TURN-ON
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
IND = +1.5V
INB = +3.3V
INC = +2.5V
INA and VDD = +5V
C1
23
VDD
1
EN1
11
EN2
1μF
ENABLE1
DLY_ON_B
ENABLE2
DLY_ON_D
DLY_ON_C
R1
7.681k
R3
4.99k
R5
6.98k
DLY_ON_A
R7
8.45k
12
14
17
20
R2
2.26k
R4
4.99k
R6
3.01k
S1
UVLO_B
DLY_OFF_C
UVLO_D
DLY_OFF_D
15
16
C2
0.01μF
C3
21 0.068μF
3
UVLO_C
4
DLY_OFF_A
ISL612XIR
GATE_A
C6
0.1μF
C7
0.01μF
C4
0.047μF
C5
DLY_OFF_B 13
18 0.01μF
UVLO_A
R8
1.47k
8
C8
0.01μF
C9
0.1μF
2
5
6
GATE_C
7
SYSRST#
19
SYSRST#
GND
7 8 SI4922DY
2
GATE_D
RESET#2
NC
Q3
3
GATE_B
22
5 6 SI4922DY
4
RESET#1
9
24
20
R10
1
R9 750
Q3
1
5 6
4
3
SI4922DY
Q4
SI4922DY
7 8
2
750
10
Q4
1
RL8
10
RL7
5
RL6
5
RL5
2
FIGURE 15. EVAL BOARD CHANNEL 1 SCHEMATIC AND ISL612xSEQEVAL1 PHOTOGRAPH
13
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
2.5V_(IND) 1.5V_(INC)
3.3V_(INB)
5.0V_(INA)
C1
23
1
ENABLE
VDD
DLY_ON_B
ENABLE
DLY_ON_D
DLY_ON_A
8.45k
R6
R4
4.99k
6.98k
R2
7.68k
R1
DLY_ON_C
12
14
17
20
U1
UVLO_B
DLY_OFF_C
UVLO_D
DLY_OFF_D
UVLO_C
DLY_OFF_B
DLY_OFF_A
UVLO_A
8
1µF
C2 0.01µF
15
C3 0.022µF
16
C4 0.068µF
21
C5 OPEN
3
C6 0.047µF
4
C7 OPEN
13
C8 0.01µF
18
C9 0.1µF
R12
1.47k
R5
4.99k
3.01k
R3
2.26k
R11
A
ISL612X
GATE_B
22
SYSRST
GATE_A
9
11
GATE_C
SYSRST
GATE_D
2
R8
10k
5
R9
10k
6
R10
10k
7
R13
10k
SEQ_A
SEQ_B
SEQ_C
SEQ_D
NC
NC
25
RESET
EP
10
GND
19
R7
24
D1
750
RESET
AGND
A
FIGURE 16. ISL6125EVAL1 SCHEMATIC AND PHOTOGRAPH
14
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 2. ISL612XSEQEVAL1 BOARD CHANNEL 1 COMPONENT LISTING
COMPONENT
DESIGNATOR
S1
COMPONENT FUNCTION
COMPONENT DESCRIPTION
ISL612X, 4 Supply Sequencer Socket
Intersil, ISL612X4 Supply Sequencer Socket
Voltage Rail Switches
SI4922DY or equivalent, Dual 8A, 30V, 0.018Ω, N-Channel
MOSFET
R7
5V to UVLO_A Resistor for Divider String
8.45kΩ 1%, 0402
R8
UVLO_A to GND Resistor for Divider String
1.47kΩ 1%, 0402
R1
3.3V to UVLO_B Resistor for Divider String
7.68kΩ 1%, 0402
R2
UVLO_B to GND Resistor for Divider String
2.26kΩ 1%, 0402
R5
2.5V to UVLO_C Resistor for Divider String
6.98kΩ 1%, 0402
R6
UVLO_C to GND Resistor for Divider String
3.01kΩ 1%, 0402
R3
1.5V to UVLO_D Resistor for Divider String
4.99kΩ 1%, 0402
R4
UVLO_D to GND Resistor for Divider String
4.99kΩ 1%, 0402
R9
RESET#1 LED Current Limiting Resistor
750Ω 10%, 0805
R10
RESET#2 LED Current Limiting Resistor
750Ω 10%, 0805
C7
5V turn-on Delay Cap. (13ms)
0.01µF 10%, 6.3V, 0402
C9
5V turn-off Delay Cap. (130ms)
0.1µF 10%, 6.3V, 0402
C2
3.3V turn-on Delay Cap. (13ms)
0.01µF 10%, 6.3V, 0402
C5
3.3V turn-off Delay Cap. (3ms)
0.01µF 10%, 6.3V, 0402
C3
2.5V turn-on Delay Cap. (88ms)
0.068µF 10%, 6.3V, 0402
C4
2.5V turn-off Delay Cap. (61ms)
0.047µF 10%, 6.3V, 0402
C6
1.5V turn-on Delay Cap. (130ms)
0.1µF 10%, 6.3V, 0402
C8
1.5V turn-off Delay Cap. (13ms)
0.01µF 10%, 6.3V, 0402
C1
Decoupling Capacitor
0.1µF, 0805
D1
RESET#1 Indicating LED
0805, SMD LEDs Red
D2
RESET#2 Indicating LED
0805, SMD LEDs Red
RL8
5V Load Resistor
10Ω 20%, 3W Carbon
RL7
3.3V Load Resistor
5Ω 20%, 3W Carbon
RL6
2.5V Load Resistor
5Ω 20%, 3W Carbon
RL5
1.5V Load Resistor
2Ω 20%, 3W Carbon
Q3, Q4
15
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 3. ISL6125EVAL1 COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT FUNCTION
COMPONENT DESCRIPTION
U1
ISL6125, Four Supply Sequencer
Intersil, ISL6125, Four Supply Sequencer with Open Drain
Outputs
R6
5V to UVLO_A Resistor for Divider String
8.45kΩ 1%, 0402
R12
UVLO_A to GND Resistor for Divider String
1.47kΩ 1%, 0402
R1
3.3V to UVLO_B Resistor for Divider String
7.68kΩ 1%, 0402
R11
UVLO_B to GND Resistor for Divider String
2.26kΩ 1%, 0402
R2
2.5V to UVLO_D Resistor for Divider String
6.98kΩ 1%, 0402
R3
UVLO_D to GND Resistor for Divider String
3.01kΩ 1%, 0402
R4
1.5V to UVLO_C Resistor for Divider String
4.99kΩ 1%, 0402
R5
UVLO_D to GND Resistor for Divider String
4.99kΩ 1%, 0402
R9
RESET LED Current Limiting Resistor
750Ω 10%, 0805
C5
5V turn-on Delay Cap. A
DNP, 0402
C9
5V turn-off Delay Cap. A (135ms)
0.1µF 10%, 6.3V, 0402
C2
3.3V turn-on Delay Cap.B (13.7ms)
0.01µF 10%, 6.3V, 0402
C8
3.3V turn-off Delay Cap. B (13.7ms)
0.01µF 10%, 6.3V, 0402
C3
2.5V turn-on Delay Cap.D (28ms)
0.022µF 10%, 6.3V, 0402
C7
2.5V turn-off Delay Cap. D
DNP, 0402
C4
1.5V turn-on Delay Cap. C (98ms)
0.068µF 10%, 6.3V, 0402
C6
1.5V turn-off Delay Cap. C (59ms)
0.047µF 10%, 6.3V, 0402
C1
Decoupling Capacitor
0.1µF, 0805
D1
RESET#1 Indicating LED
0805, SMD LED
R8
SEQ_OUTPUT_A Pull-Up Resistor
10kΩ, 0402
R9
SEQ_OUTPUT_B Pull-Up Resistor
10kΩ, 0402
R10
SEQ_OUTPUT_C Pull-Up Resistor
10kΩ, 0402
R13
SEQ_OUTPUT_D Pull-Up Resistor
10kΩ, 0402
Application Implementations
Multiple Sequencer Implementations
In order to control the sequencing of more than 4 voltages,
several of the ISL6123, ISL6124, ISL6125 or ISL6127
devices can be variously configured together to accomplish
this. There may be concerns of a particular implementation
that would make a particular configuration preferable over
another. The fundamental questions to answer to determine
which configuration is best suited for your applications are:
1. What level of voltage assurance is needed prior to
sequencing on and can the voltage supplies be grouped
into high and low criticality?
2. Is there a critical maximum time window all supplies must
be present at load or is there a first and a second group
preference possibly with some work done in between the
two groups of voltages being present?
16
Three configurations are described and illustrated here.
In applications where the integrity of critical voltages must be
assured prior to sequencing, additional monitoring of the
critical supplies is needed. If the compliance of the voltage is
critical for either undervoltage and/or overvoltage, the
ISL613X family of supervisors can be employed to provide
this additional assurance across multiple sequencers. See
document FN9115 for supervisor data sheet. Figure 17 is a
block diagram of this voltage compliant, high assurance, low
risk configuration showing the ISL613X supervisor and a mix
of FET switched outputs and logic output sequencers
(ISL6124 and ISL6125 ICs).
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL613Xs
MONITORING
ON ALL RAILS
VMON
PGOOD
OE
OE
LOW = RESET
LOW = RESET
UVLO
SYSRST#
ISL6124
#N
UVLO
en
RESET#
G
A
T
E
SYSRST#
ISL6124
#N
UVLO
en
ENABLE#
RESET#
G
A
T
E
ENABLE#
ENABLE#
RESET#
SYSRST#
ISL6125
# N+1
POWER
SUPPLY
RESET#
UVLO
ENABLE#
L
O
G
I
C
RESET#’
SYSRST#
ISL6125
# N+1
POWER
SUPPLY
RESET#
UVLO
L
O
G
I
C
FIGURE 17. ISL612X AND ISL613X VOLTAGE COMPLIANT
SEQUENCING BLOCK DIAGRAM
FIGURE 18. MULTIPLE ISL612X USING LOGIC GATES FOR
VOLTAGE PRESENCE DETECT
If the mere presence of some voltage potential is adequate
prior to sequencing on, then a small number of standard
logic AND gates can be used to accomplish this. The block
diagram in Figure 18 illustrates this voltage presence
configuration.
prevent the turn-on sequence from completing if there is one
unsatisfied UVLO input in a group. Using this configuration
involves waiting through the TUVLOdel and TRSTdel (total of
~160ms) for each sequencer IC in the chain for the final
RESET# to release. Once ENABLE on the first sequencer is
deasserted all the RESET# outputs will quickly pull low and
thus allow the sequenced turn-off of this configuration to
ripple through several banks as quickly as the user
programmed sequence as chosen by the DLY_OFF
capacitors allow. Once again with common bussed
SYSRTS# pins, simultaneous shut down of all GATEs and
LOGIC down upon an unsatisfied UVLO input is assured
once all FETs or LOGIC output are on. If a GATE drive
option IC is used to drive both FETs and logic signals then
care to ensure the charged pump GATE does not over drive
and damage the logic input must be taken. A simple resistor
divider can be used to lower the GATE voltage to a suitable
voltage for the logic input as shown in Figure 19.
In either case, the sequencing is straight forward across
multiple sequencers as all DLY_ON capacitors will
simultaneously start charging ~10ms after the common
ENABLE input signal is delivered. This allows the choice of
capacitors to be related to each other no different than using
a single sequencer. When the common enabling signal is
deasserted these configurations will then execute the
turn-off sequence across all sequencers as programmed by
the DLY_OFF capacitor values.
In both cases, with all the SYSRST# pins bussed together,
once the on sequence is complete, simultaneous shutdown
upon any UVLO input failure is assured as SYSRST# output
will momentarily pull low turning off all GATE and LOGIC
outputs.
There may be applications that require or allow groups of
supplies being brought up in sequence and supplies within
each group to be sequenced. Figure 19 illustrates such a
configuration that allows the first group of supplies to turn-on
before the second group starts. This arrangement does not
necessarily preclude adding the assurance of all supplies
prior to turn-on sequencing as previously shown but it will
17
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
OE
LOW = RESET
SYSRST#
ISL6124
#N
UVLO
ENABLE
ENABLE#
G
A
T
E
TO LOGIC
INPUT
RESET#
ENABLE#
SYSRST#
FIGURE 20. OUTPUT VOLTAGE ON LOW TO HIGH TRACKING
ISL6125
# N+1
POWER
SUPPLY
RESET#
UVLO
L
O
G
I
C
RESET#
RESET#
FIGURE 19. MULTIPLE ISL612X SERIAL CONFIGURATION
Voltage Tracking
In some applications the various voltages may have to track
each other as they ramp up and down, whereas others may
just need sequencing. In these cases tracking can be
accomplished and has been demonstrated over a wide
range of load current (1A to 10A) and load capacitance
(10µF to 3300µF) with the ISL612X family. Figure 20 and
Figure 21 illustrate output voltage ramping tracking
performance, note that differences are less than 0.5V. With
the relevant GATE pins tied together in a star pattern, so that
the resistance between any two GATE pins is equivalent (1k
to 10k) results in a sharing of the GATE ramping voltage and
with the same or similar enough FETs this behavior is
observed.
FIGURE 21. OUTPUT VOLTAGE HIGH TO LOW TRACKING
It is suggested that this circuit implementation be prototyped
and evaluated for the particular expected loads prior to
committing to manufacturing build.
18
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Negative Voltage Sequencing
+V
The ISL612X family can use the charged pump GATE output
to drive FETs that would control and sequence negative
voltages down to a nominal -5V with minimal additional
external circuitry. Figure 22 shows turn-on of 5V bipolar
supplies together, then the +2.5V and turn-off of both
positive supplies being turned off together after the -5V.
Figure 23 shows the minimal additional external circuitry to
accomplish this. The 5V zener diode is used to level shift the
GATE drive down 5V to prevent premature turn-on when
GATE = 0V. Once GATE drive voltage > Vz, then FET
Vgs > 5V, ensuring full turn-on once GATE gets to
VDD+5.3V. Turn-on and turn-off ramp rate can be adjusted
with FET gate series resistor value. Sequencing of the -V rail
is accomplished as normal via the DLY_X capacitor value
although adjustments in prototyping should be factored in to
fine tune for actual circuit requirements.
Figures 24 and 25 illustrate a high accuracy -V detection
circuit using the ISL6131 and a low cost low accuracy -V
detect circuit and respectively.
+BIAS
R1
VMON
R2
R3
(1k)
R5
(10k)
ISL6131
OR
ISL6536A PGOOD R4
(15K)
-BIAS
Q1 Si1300DL
OR EQUIV.
R6
-V
TO UVLO OF
ISL612X FOR
-V CONTROL AND
SEQUENCING
R1 and R2 define -V UVLO level
R3 ensures supervisor (ISL6131 or ISL6536A) PGOOD pull-up
R4 and R5 provide Q1 gate bias between 0V and +V
to 0V (resistor values suitable for -V = -5V and +V = +3.3V)
FIGURE 24. HGH ACCURACY -V LOCK OUT
+V
R1
TO UVLO OF ISL612X FOR CONTROL
AND SEQUENCING OF -V
R2
-V
Chose R1 and R2 values to drive UVLO
high when -V is sufficiently present
FIGURE 25. LOW ACCURACY -V PRESENCE DETECTION
Application Considerations
Timing Error Sources
In any system there are variance contributors, for the ISL612X
family the timing errors are mainly contributed by three sources.
Capacitor Timing Mismatch Error
Obviously, the absolute capacitor value is an error source,
thus lower percentage tolerance capacitors help to reduce
this error source. Figure 26 illustrates a difference of 0.57ms
between two DLY_X outputs ramping to DLY_X threshold
voltage, these 5% capacitors were from a common source.
In applications where two or more GATEs or LOGIC outputs
must have concurrent transitions, it is recommended that a
common GATE drive be used to eliminate this timing error.
FIGURE 22. ±VOLTAGE SEQUENCING
-Vout
-Vin
R1
ISL612X GATE
D1
Additional 2 components
necessary for -V control
and sequencing.
D1 necessary to prevent premature turn-on. R1 is used to hold
FET Vgs = 0V until D1 Vz is overcome. R1 value can be changed to
adjust -V ramp rates. Choose a R1 value between 4MΩ and 10MΩ
initially and fine tune resistor value for the particular need.
FIGURE 23. -VOLTAGE FET DRIVE CIRCUIT
FIGURE 26. CAPACITOR TIMING MISMATCH
19
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
DLY_X Threshold Voltage and Charging Current
Mismatch
The two other error sources come from the IC itself and are
the differences in the DLY_X threshold voltage, (DLY_Vth)
when the GATE charging latch is set and the DLY_X
charging current, (DLY_ichg) across the four individual I/Os.
Both of these parameters are bounded by specification and
Figure 27 illustrates that with a common capacitor the typical
error contributed by these factors is insignificant as both
DLY_X traces overlay each other.
FIGURE 27. DLY_VTH AND DLY_ICHG TIMING MISMATCH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN9005.8
February 5, 2007
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Package Outline Drawing
L24.4x4
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X 2.5
4.00
A
20X 0.50
B
PIN 1
INDEX AREA
PIN #1 CORNER
(C 0 . 25)
24
19
1
4.00
18
2 . 10 ± 0 . 15
13
0.15
(4X)
12
7
0.10 M C A B
0 . 07
24X 0 . 23 +- 0
. 05 4
24X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0 . 1
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 10 )
( 20X 0 . 5 )
C
0 . 2 REF
5
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
21
FN9005.8
February 5, 2007