LINER LTC1861 Mpower, 12-bit, 250ksps 1- and 2-channel adcs in msop Datasheet

LTC1860/LTC1861
µPower, 12-Bit, 250ksps
1- and 2-Channel ADCs in MSOP
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FEATURES
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DESCRIPTIO
12-Bit 250ksps ADCs in MSOP Package
Single 5V Supply
Low Supply Current: 850µA (Typ)
Auto Shutdown Reduces Supply Current
to 2µA at 1ksps
True Differential Inputs
1-Channel (LTC1860) or 2-Channel (LTC1861)
Versions
SPI/MICROWIRETM Compatible Serial I/O
High Speed Upgrade to LTC1286/LTC1298
Pin Compatible with 16-Bit LTC1864/LTC1865
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APPLICATIO S
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High Speed Data Acquisition
Portable or Compact Instrumentation
Low Power Battery-Operated Instrumentation
Isolated and/or Remote Data Acquisition
The LTC®1860/LTC1861 are 12-bit A/D converters that are
offered in MSOP and SO-8 packages and operate on a
single 5V supply. At 250ksps, the supply current is only
850µA. The supply current drops at lower speeds because
the LTC1860/LTC1861 automatically power down to a
typical supply current of 1nA between conversions. These
12-bit switched capacitor successive approximation ADCs
include sample-and-holds. The LTC1860 has a differential
analog input with an adjustable reference pin. The LTC1861
offers a software-selectable 2-channel MUX and an adjustable reference pin on the MSOP version.
The 3-wire, serial I/O, MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
These ADCs can be used in ratiometric applications or with
external references. The high impedance analog inputs
and the ability to operate with reduced spans down to 1V
full scale, allow direct connection to signal sources in
many applications, eliminating the need for external gain
stages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATIO
Supply Current vs Sampling Frequency
Single 5V Supply, 250ksps, 12-Bit Sampling ADC
1000
1µF
LTC1860
1
ANALOG INPUT
0V TO 5V
VREF
VCC
2
IN +
SCK
3
IN –
SDO
GND
CONV
4
8
7
6
5
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
SUPPLY CURRENT (µA)
100
5V
10
1
0.1
1860 TA01
0.01
0.01
0.1
10
100
1
SAMPLING FREQUENCY (kHz)
1000
1860 TA02
18601f
1
LTC1860/LTC1861
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ABSOLUTE
RATI GS
(Notes 1, 2)
Supply Voltage (VCC) ................................................. 7V
Ground Voltage Difference
AGND, DGND LTC1861 MSOP Package ........... ±0.3V
Analog Input .................... (GND – 0.3V) to (VCC + 0.3V)
Digital Input ..................................... (GND – 0.3V) to 7V
Digital Output .................. (GND – 0.3V) to (VCC + 0.3V)
Power Dissipation .............................................. 400mW
Operating Temperature Range
LTC1860C/LTC1861C ............................. 0°C to 70°C
LTC1860I/LTC1861I .......................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
VREF
IN +
IN¯
GND
1
2
3
4
8
7
6
5
VCC
SCK
SDO
CONV
MS8 PART MARKING
TJMAX = 150°C, θJA = 210°C/W
LTWR
LTWS
ORDER PART
NUMBER
TOP VIEW
VREF 1
8 VCC
IN + 2
7 SCK
–
6 SDO
IN
3
GND 4
CONV
CH0
CH1
AGND
DGND
LTC1860CMS8
LTC1860IMS8
MS8 PACKAGE
8-LEAD PLASTIC MSOP
5 CONV
S8 PACKAGE
8-LEAD PLASTIC SO
10
9
8
7
6
1
2
3
4
5
VREF
VCC
SCK
SDO
SDI
LTC1861CMS
LTC1861IMS
MS PART MARKING
MS PACKAGE
10-LEAD PLASTIC MSOP
LTWT
LTWU
ORDER PART
NUMBER
TJMAX = 150°C, θJA = 210°C/W
TOP VIEW
CONV 1
8 VCC
LTC1860CS8
LTC1860IS8
CH0 2
7 SCK
CH1 3
6 SDO
S8 PART MARKING
GND 4
5 SDI
1860
1860I
TJMAX = 150°C, θJA = 175°C/W
ORDER PART
NUMBER
TOP VIEW
LTC1861CS8
LTC1861IS8
S8 PART MARKING
1861
1861I
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 175°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER A D
ULTIPLEXER CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
PARAMETER
CONDITIONS
Resolution
No Missing Codes Resolution
INL
(Note 3)
MIN
●
12
●
12
TYP
MAX
Bits
Bits
±1
●
Transition Noise
0.07
Gain Error
●
Offset Error
LTC1860 SO-8 and MSOP, LTC1861 MSOP
LTC1861 SO-8
●
●
Input Differential Voltage Range
VIN = IN + – IN –
●
Absolute Input Range
IN+ Input
IN– Input
VREF Input Range
LTC1860 S0-8 and MSOP, LTC1861 MSOP
Analog Input Leakage Current
(Note 4)
CIN Input Capacitance
In Sample Mode
During Conversion
UNITS
±2
±3
LSB
LSBRMS
±20
mV
±5
±7
mV
mV
0
VREF
V
– 0.05
– 0.05
VCC + 0.05
VCC /2
V
V
1
VCC
V
±1
µA
●
12
5
pF
pF
18601f
2
LTC1860/LTC1861
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DY A IC ACCURACY
TA = 25°C. VCC = 5V, fSAMPLE = 250kHz, unless otherwise specified.
SYMBOL PARAMETER
SNR
S/(N + D) Signal-to-Noise Plus Distortion Ratio
THD
CONDITIONS
MIN
Signal-to-Noise Ratio
100kHz Input Signal
TYP
MAX
UNITS
72
dB
71
dB
Total Hamonic Distortion Up to 5th Harmonic 100kHz Input Signal
77
dB
Full Power Bandwidth
20
MHz
125
kHz
Full Linear Bandwidth
S/(N + D) ≥ 68dB
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DIGITAL A D DC ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VCC = 5.25V
●
VIL
Low Level Input Voltage
VCC = 4.75V
●
0.8
V
IIH
High Level Input Current
VIN = VCC
●
2.5
µA
IIL
Low Level Input Current
VIN = 0V
●
– 2.5
µA
VOH
High Level Output Voltage
VCC = 4.75V, IO = 10µA
VCC = 4.75V, IO = 360µA
●
●
VOL
Low Level Output Voltage
VCC = 4.75V, IO = 1.6mA
●
0.4
V
IOZ
Hi-Z Output Leakage
CONV = VCC
●
±3
µA
ISOURCE
Output Source Current
VOUT = 0V
– 25
mA
ISINK
Output Sink Current
VOUT = VCC
20
mA
IREF
Reference Current (LTC1860 SO-8, MSOP and CONV = VCC
LTC1861 MSOP)
fSMPL = fSMPL(MAX)
●
●
0.001
0.05
3
0.1
µA
mA
ICC
Supply Current
CONV = VCC After Conversion
fSMPL = fSMPL(MAX)
●
●
0.001
0.85
3
1.3
µA
mA
PD
Power Dissipation
fSMPL = fSMPL(MAX)
TYP
MAX
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E DED OPERATI G CO DITIO S
UNITS
2.4
4.5
2.4
V
4.74
4.72
V
V
4.25
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RECO
MIN
mW
The ● denotes specifications which apply over the
full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
VCC
Supply Voltage
fSCK
Clock Frequency
tCYC
Total Cycle Time
tSMPL
Analog Input Sampling Time
tsuCONV
Setup Time CONV↓ Before First SCK↑,
(See Figure 1)
thDI
Holdtime SDI After SCK↑
tsuDI
Setup Time SDI Stable Before SCK↑
tWHCLK
SCK High Time
fSCK = fSCK(MAX)
tWLCLK
SCK Low Time
fSCK = fSCK(MAX)
tWHCONV
CONV High Time Between Data
Transfer Cycles
tWLCONV
CONV Low Time During Data Transfer
12
SCK
thCONV
Hold Time CONV Low After Last SCK↑
13
ns
●
4.75
5.25
DC
20
UNITS
12 • SCK + tCONV
LTC1860
LTC1861
V
MHz
µs
12
10
SCK
SCK
30
ns
LTC1861
15
ns
LTC1861
15
ns
40%
1/fSCK
40%
1/fSCK
tCONV
µs
18601f
3
LTC1860/LTC1861
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating
Conditions, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tCONV
Conversion Time (See Figure 1)
MIN
●
fSMPL(MAX) Maximum Sampling Frequency
tdDO
MAX
UNITS
2.75
3.2
µs
15
20
25
ns
ns
30
60
ns
30
60
ns
250
●
Delay Time, SCK↓ to SDO Data Valid
TYP
CLOAD = 20pF
kHz
●
tdis
Delay Time, CONV↑ to SDO Hi-Z
ten
Delay Time, CONV↓ to SDO Enabled
CLOAD = 20pF
●
thDO
Time Output Data Remains
Valid After SCK↓
CLOAD = 20pF
●
tr
SDO Rise Time
tf
SDO Fall Time
●
10
ns
CLOAD = 20pF
8
ns
CLOAD = 20pF
4
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
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Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample
mode.
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Sampling
Frequency
CONV LOW = 800ns
TA = 25°C
VCC = 5V
800
1
600
400
CONV HIGH = 3.2µS
fSMPL = 250kHz
VCC = 5V
VREF = 5V
200
0.1
0.1
10
100
1.0
SAMPLING FREQUENCY (kHz)
1000
1860/61 G01
0
–50
CONV = VCC = 5V
800
SLEEP CURRENT (nA)
10
0.01
0.01
1000
900
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
100
Sleep Current vs Temperature
Supply Current vs Temperature
1000
1000
–25
50
0
75
25
TEMPERATURE (°C)
100
125
1860/61 G02
700
600
500
400
300
200
100
0
–50
–25
50
0
75
25
TEMPERATURE (°C)
100
125
1860/61 G03
18601f
4
LTC1860/LTC1861
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TYPICAL PERFOR A CE CHARACTERISTICS
Reference Current vs
Sample Rate
40
30
20
fS = 250kHz
TA = 25°C
50 VCC = 5V
fS = 250kHz
54 VCC = 5V
= 5V
V
53 REF
REFERENCE CURRENT (µA)
REFERENCE CURRENT (µA)
50
60
55
CONV IS LOW FOR 800ns
TA = 25°C
VCC = 5V
VREF = 5V
52
40
51
IREF (µA)
60
Reference Current vs
Reference Voltage
Reference Current vs
Temperature
50
49
20
48
47
10
30
10
46
0
0
50
100
150
200
SAMPLE RATE (kHz)
45
–50 –25
250
0
50
25
0
75
TEMPERATURE (°C)
1860/61 G04
–0.5
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
100
TA = 25°C
VCC = 5V
VREF = 5V
0.5
0
–0.5
–1.0
1
0
–1
–2
0
–0.2
–0.4
–0.8
–1.0
–50
1860/61 G10
50
75
100
125
VCC = 5V
4 TA = 25°C
0.2
–5
5
25
5
0.4
–4
3
4
2
REFERENCE VOLTAGE (V)
0
Change in Gain Error vs
Reference Voltage
0.6
–0.6
1
25
1860/61 G09
VCC = 5V
–3
0
50
TEMPERATURE (°C)
CHANGE IN GAIN ERROR (LSB)
0.8
CHANGE IN OFFSET (LSB)
CHANGE IN OFFSET ERROR (LSB)
1.0
TA = 25°C
VCC = 5V
2
5
4
75
Change in Offset vs Temperature
3
3
VREF (V)
1860/61 G07
Change in Offset Error vs
Reference Voltage
4
2
VCC = 5V
VREF = 5V
CONV = 0V
0
–50 –25
512 1024 1536 2048 2560 3072 3584 4096
CODE
0
1860/61 G07
5
1
Analog Input Leakage vs
Temperature
ANALOG INPUT LEAKAGE (nA)
DNL EOC ERROR (LSBs)
INL COC ERROR (LSBs)
1.0
TA = 25°C
VCC = 5V
VREF = 5V
0
0
1860/61 G06
Typical DNL Curve
0.5
–1.0
125
1860/61 G05
Typical INL Curve
1.0
100
3
2
1
0
–1
–2
–3
–4
–25
50
0
75
25
TEMPERATURE (°C)
100
125
1860/61 G11
–5
0
1
4
2
3
REFERENCE VOLTAGE(V)
5
1860/61 G12
18601f
5
LTC1860/LTC1861
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TYPICAL PERFOR A CE CHARACTERISTICS
Signal-to-(Noise + Distortion)
vs Input Level
Change in Gain Error vs
Temperature
SIGNAL-TO-(NOISE + DISTORTION) (dB)
VCC = 5V
VREF = 5V
0.8
CHANGE IN GAIN ERROR (LSB)
80
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–50
50
0
75
25
TEMPERATURE (°C)
–25
100
fIN = 10kHz
TA = 25°C
VCC = 5V
70
60
50
40
30
0
–40 –35 –30 –25 –20 –15 –10
INPUT LEVEL (dB)
SINAD
30
20
10
0
10
100
fIN (kHz)
1000
–120
10000
0
10 20 30 40 50 60 70 80 90 100
f (kHz)
1860/61 G15
Spurious Free Dynamic Range
vs fIN
100
TA = 25°C
VCC = 5V
VIN = 0dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
90
80
70
60
50
40
30
20
10
100
1000
TA = 25°C
VCC = 5V
VIN = 0dB
10
0
1
1
10
100
1000
fIN (kHz)
fIN (kHz)
1860/61 G16
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0
SPURIOUS FREE DYNAMIC RANGE (dB)
50
TOTAL HARMONIC DISTORTION (dB)
SIGNAL-TO-(NOISE + DISTORTION) (dB)
60
1
–5
Total Harmonic Distortion
vs fIN
SNR
40
–80
1195 G20
0
70
–60
–100
10
125
TA = 25°C
VCC = 5V
VIN = 0dB
80
–40
20
Signal-to-(Noise + Distortion)
vs fIN
90
fS = 204.1kHz
fIN = 99.5kHz
TA = 25°C
VCC = 5V
–20
1860/61 G13
100
4096 Point FFT
0
AMPLITUDE (dB)
1.0
1860/61 G17
1860/61 G18
LTC1860
VREF (Pin 1): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
IN +, IN– (Pins 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
SCK (Pin 7): Shift Clock Input. This clock synchronizes the
serial data transfer.
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
18601f
6
LTC1860/LTC1861
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PI FU CTIO S
LTC1861 (MSOP Package)
LTC1861 (SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
AGND (Pin 4): Analog Ground. AGND should be tied
directly to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied
directly to an analog ground plane.
SDI (Pin 5): Digital Data Input. The A/D configuration
word is shifted into this input.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 7): Shift Clock Input. This clock synchronizes the
serial data transfer.
SCK (Pin 8): Shift Clock Input. This clock synchronizes the
serial data transfer.
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. VREF is tied internally to this pin.
VCC (Pin 9): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free
of noise with respect to AGND.
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FUNCTIONAL BLOCK DIAGRA
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CONV (SDI) SCK
VCC
PIN NAMES IN
PARENTHESES
REFER TO LTC1861
CONVERT
CLK
SDO
SERIAL
PORT
BIAS AND
SHUTDOWN
DATA IN
12-BITS
IN +
(CH0)
+
IN –
(CH1)
–
12-BIT
SAMPLING
ADC
DATA OUT
1860/61 BD
GND
VREF
18601f
7
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LTC1860/LTC1861
TEST CIRCUITS
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
Load Circuit for tdDO, tr, tf, tdis and ten
TEST POINT
VOH
SDO
VOL
VCC tdis WAVEFORM 2, ten
3k
SDO
tdis WAVEFORM 1
20pF
tr
tf
1860 TC04
1860 TC01
Voltage Waveforms for ten
Voltage Waveforms for tdis
CONV
SDO
1860 TC03
ten
Voltage Waveforms for SDO Delay Times, tdDO and thDO
SDO
WAVEFORM 1
(SEE NOTE 1)
VIL
tdDO
thDO
VOH
90%
tdis
SDO
WAVEFORM 2
(SEE NOTE 2)
SCK
VIH
CONV
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1860 TC05
SDO
VOL
1860 TC02
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APPLICATIO S I FOR ATIO
LTC1860 OPERATION
Analog Inputs
Operating Sequence
The LTC1860 has a unipolar differential analog input. The
converter will measure the voltage between the “IN + ” and
“IN – ” inputs. A zero code will occur when IN+ minus IN –
equals zero. Full scale occurs when IN+ minus IN – equals
VREF minus 1LSB. See Figure 2. Both the “IN+ ” and
“IN – ” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN – ”
is grounded and VREF is tied to VCC, a rail-to-rail input span
will result on “IN+ ” as shown in Figure 3.
The LTC1860 conversion cycle begins with the rising edge
of CONV. After a period equal to t CONV, the conversion is
finished. If CONV is left high after this time, the LTC1860
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1860 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
Reference Input
The voltage on the reference input of the LTC1860 (and the
LTC1861 MSOP package) defines the full-scale range of
the A/D converter. These ADCs can operate with reference
voltages from VCC to 1V.
18601f
8
LTC1860/LTC1861
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APPLICATIO S I FOR ATIO
CONV
t SMPL
SLEEP MODE
tCONV
1
2
3
4
5
6
7
8
9 10 11 12
SCK
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
SDO
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC
WILL OUTPUT ZEROS INDEFINITELY
1860 F01
Figure 1. LTC1860 Operating Sequence
1µF
111111111111
VCC
111111111110
•
•
•
LTC1860
1
000000000001
000000000000
VIN*
VREF
VREF – 1LSB
VREF – 2LSB
1LSB
0V
*VIN = IN + – IN –
VIN = 0V TO VCC
VREF
VCC
2
IN +
SCK
3
IN –
SDO
GND
CONV
4
8
7
6
5
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
1860 F03
1860 F02
Figure 2. LTC1860 Transfer Curve
LTC1861 OPERATION
Operating Sequence
The LTC1861 conversion cycle begins with the rising edge
of CONV. After a period equal to t CONV, the conversion is
finished. If CONV is left high after this time, the LTC1861
goes into sleep mode. The LTC1861’s 2-bit data word is
clocked into the SDI input on the rising edge of SCK after
CONV goes low. Additional inputs on the SDI pin are then
ignored until the next CONV cycle. The shift clock (SCK)
synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising
SCK edge in both transmitting and receiving systems. The
data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK
clocks are applied with CONV low, SDO will output zeros
indefinitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
Figure 3. LTC1860 with Rail-to-Rail Input Span
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table.
In single-ended mode, all input channels are measured
with respect to GND (or AGND). A zero code will occur
when the “+” input minus the “–” input equals zero. Full
scale occurs when the “+” input minus the “–” input
equals VREF minus 1LSB. See Figure 5. Both the “+” and
“–” inputs are sampled at the same time so common
mode noise is rejected. The input span in the SO-8
package is fixed at VREF = VCC. If the “–” input in
differential mode is grounded, a rail-to-rail input span
will result on the “+” input.
Reference Input
The reference input of the LTC1861 SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference input
of the LTC1861 MSOP package defines the span of the A/
D converter. The LTC1861 MSOP package can operate
with reference voltages from 1V to VCC.
18601f
9
LTC1860/LTC1861
U
W
U U
APPLICATIO S I FOR ATIO
CONV
SDI
t SMPL
SLEEP MODE
tCONV
S/D O/S
DON’T CARE
1
2
DON’T CARE
3
4
5
6
7
8
9 10 11 12
SCK
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
SDO
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1860 F04
Figure 4. LTC1861 Operating Sequence
111111111111
Table 1. Multiplexer Channel Selection
111111111110
•
•
•
VIN*
000000000001
000000000000
VCC
VCC – 1LSB
VCC – 2LSB
1LSB
0V
*VIN = (SELECTED “+” CHANNEL) –
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
1860 F05
MUX ADDRESS
SGL/DIFF ODD/SIGN
0
1
1
1
0
0
1
0
CHANNEL #
0
1
+
+
+
–
–
+
GND
–
–
186465 TBL1
Figure 5. LTC1861 Transfer Curve
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1860/LTC1861 should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluate the device. To achieve the optimum performance,
use a printed circuit board. The ground pins (AGND and
DGND for the LTC1861 MSOP package and GND for the
LTC1860 and LTC1861 SO-8 package) should be tied
directly to the analog ground plane with minimum lead
length.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with a
minimum of 1µF tantalum. Keep the bypass capacitor
leads as short as possible.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1860/
LTC1861 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem if source resistances are less than 200Ω or high
speed op amps are used (e.g., the LT®1211, LT1469,
LT1807, LT1810, LT1630, LT1226 or LT1215). But if large
source resistances are used, or if slow settling op amps
drive the inputs, take care to ensure the transients caused
by the current spikes settle completely before the conversion begins.
18601f
10
LTC1860/LTC1861
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.42 ± 0.04
(.0165 ± .0015)
TYP
0.254
(.010)
8
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.1
(.192 ± .004)
DETAIL “A”
0.52
(.206)
REF
7 6 5
0° – 6° TYP
GAUGE PLANE
0.65
(.0256)
BSC
1
0.53 ± 0.015
(.021 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
4
2 3
1.10
(.043)
MAX
DETAIL “A”
0.86
(.034)
REF
0.18
(.077)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.22 – 0.38
(.009 – .015)
0.13 ± 0.05
(.005 ± .002)
0.65
(.0256)
BCS
MSOP (MS8) 1001
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.254
(.010)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.497 ± 0.076
(.0196 ± .003)
REF
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.10
(.192 ± .004)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.01
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
0.13 ± 0.05
(.005 ± .002)
0.50
(.0197)
TYP
MSOP (MS) 1001
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 1298
1
2
3
4
18601f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1860/LTC1861
U
TYPICAL APPLICATIO
Sample Two Channels Simultaneously with a Single Input ADC
5V
0.1µF
f1
(0V TO 0.66V)
+
4.096V
REF
5k
4.096V
REF
100Ω
1/2
LT1492
–
100pF
0.1µF
1µF
0.1µF
1µF
20k
8
VCC
28.7k
5pF
10k
10k
2
1µF
3
0.1µF
f2
(0V TO 2V)
IN–
5V
5k
8
+
0.1µF
1/2
LT1492
–
IN+
4
1
REF
7
SCK
6
LTC1860
SDO
5
CONV
GND
4
100Ω
100pF
1860 TA03
RELATED PARTS
PART NUMBER
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
12-Bit Serial I/O ADCs
LTC1286/LTC1298
12.5ksps/11.1ksps
1.3mW/1.7mW
1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V
LTC1400
400ksps
75mW
1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V
LTC1401
200ksps
15mW
SO-8 with Internal Reference, 3V
LTC1402
2.2Msps
90mW
Serial I/O, Bipolar or Unipolar, Internal Reference
LTC1404
600ksps
25mW
SO-8 with Internal Reference, Bipolar or Unipolar, 5V
LTC1417
400ksps
20mW
16-Pin SSOP, Unipolar or Bipolar, Reference, 5V
LTC1418
200ksps
15mW
Serial/Parallel I/O, Internal Reference, 5V
14-Bit Serial I/O ADCs
16-Bit Serial I/O ADCs
LTC1609
200ksps
65mW
LTC1864/LTC1865
250ksps
4.25mW
Configurable Bipolar or Unipolar Input Ranges, 5V
SO-8, MS8, 1-Channel, 5V/SO-8, MS10, 2-Channel, 5V
References
LT1460
Micropower Precision Series Reference
Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23
LT1790
Micropower Low Dropout Reference
60µA Supply Current, 10ppm/°C, SOT-23
18601f
12
Linear Technology Corporation
LT/TP 0502 2K • PRINTED IN USA
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●
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 LINEAR TECHNOLOGY CORPORATION 2001