TriQuint AGR21180EF 180 w, 2.110 ghz-2.170 ghz, n-channel e-mode, lateral mosfet Datasheet

AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Introduction
The AGR21180EF is a high-voltage, gold-metalized,
laterally diffused metal oxide semiconductor
(LDMOS) RF power transistor suitable for wideband
code division multiple access (W-CDMA), single and
multicarrier class AB wireless base station power
amplifier applications.
375D–03, STYLE 1
Figure 1. AGR21180EF (flanged) Package
Features
Typical performance for two carrier 3GPP
W-CDMA systems. F1 = 2135 MHz and
F2 = 2145 MHz with 3.84 MHz channel bandwidth
(BW), adjacent channel BW = 3.84 MHz at
F1 – 5 MHz and F2 + 5 MHz. Third-order distortion
is measured over 3.84 MHz BW at F1 – 10 MHz
and F2 + 10 MHz. Typical peak-to-average (P/A)
ratio of 8.5 dB at 0.01% (probability) CCDF:
— Output power: 38 W.
— Power gain: 14 dB.
— Efficiency: 26%.
— IM3: –36 dBc.
— ACPR: –39 dBc.
— Return loss: –12 dB.
High-reliability, gold-metalization process.
Hot carrier injection (HCI) induced bias drift of <5%
over 20 years.
Internally matched.
High gain, efficiency, and linearity.
Integrated ESD protection.
Device can withstand a 10:1 voltage standing wave
ratio (VSWR) at 28 Vdc, 2140 MHz, 180 W output
power pulsed 4 µs at 10% duty.
Large signal impedance parameters available.
Table 1. Thermal Characteristics
Parameter
Thermal Resistance,
Junction to Case
Sym
Value
Unit
Rı JC
0.35
°C/W
Table 2. Absolute Maximum Ratings*
Parameter
Drain-source Voltage
Gate-source Voltage
Total Dissipation at TC = 25 °C
Derate Above 25 ˇC
Operating Junction Temperature
Storage Temperature Range
Sym Value
65
VDSS
VGS –0.5, 15
PD
500
—
2.86
TJ
200
Unit
Vdc
Vdc
W
W/°C
°C
TSTG –65, 150
°C
* Stresses in excess of the absolute maximum ratings can cause
permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at
these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute
maximum ratings for extended periods can adversely affect
device reliability.
Table 3. ESD Rating*
AGR21180EF
HBM
MM
CDM
Minimum (V)
500
50
1000
Class
1B
A
4
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
during all handling, assembly, and test operations. PEAK
Agere Devices
employs a human-body model (HBM), a machine model (MM),
and a charged-device model (CDM) qualification requirement in
order to determine ESD-susceptibility limits and protection
design evaluation. ESD voltage thresholds are dependent on the
circuit parameters used in each of the models, as defined by
JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and
JESD22-C101A (CDM) standards.
Caution: MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be
observed.
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Electrical Characteristics
Recommended operating conditions apply unless otherwise specified: T C = 30 °C.
Table 4. dc Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
V(BR)DSS
IGSS
IDSS
65
—
—
—
—
—
—
6
200
18
Vdc
µAdc
µAdc
GFS
—
2.8
3.0
—
12
3.4
3.7
0.08
—
4.0
4.6
—
S
Vdc
Vdc
Vdc
Off Characteristics
300 µA)
Drain-source Breakdown Voltage (VGS = 0, ID = 400
Gate-source Leakage Current (VGS = 5 V, VDS = 0 V)
Zero Gate Voltage Drain Leakage Current (VDS = 28 V, VGS = 0 V)
On Characteristics
Forward Transconductance (VDS = 10 V, ID = 1 A)
Gate Threshold Voltage (VDS = 10 V, ID = 600 µA)
Gate Quiescent Voltage (VDS = 28 V, ID = 2 x 800 mA)
Drain-source On-voltage (VGS = 10 V, ID = 1 A)
VGS(TH)
VGS(Q)
VDS(ON)
Table 5. RF Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
CRSS
—
4.0
—
pF
14
—
dB
—
–36
–33
dBc
ACPR
—
–39
–36
dBc
IRL
—
–13
–10
dB
Dynamic Characteristics
Reverse Transfer Capacitance
(VDS = 28 V, VGS = 0, f = 1.0 MHz)
(This part is internally matched on both the input and output.)
Test Fixture)
Functional Tests (in Supplied
Agere Systems
Supplied Test Fixture)
Common-source Amplifier Power Gain*
Drain Efficiency*
Third-order Intermodulation Distortion*
(IM3 distortion measured over 3.84 MHz BW @ f1 – 10 MHz
and f2 + 10 MHz)
Adjacent Channel Power Ratio*
(ACPR measured over BW of 3.84 MHz @ f1 – 5 MHz
and f2 + 5 MHz)
Input Return Loss*
Power Output, 1 dB Compression Point, pulsed 4 µs at 10% duty.
(VDD = 28 V, fC = 2140.0 MHz)
Output Mismatch Stress
(VDD = 28 V, POUT = 180 W (pulsed 4 µs at 10% duty),
IDQ = 2 x 800 mA, fC = 2140.0 MHz VSWR = 10:1; [all phase angles])
GPS
η
IM3
P1dB
ψ
* 3GPP W-CDMA, typical P/A ratio of 8.5 dB at 0.01% CCDF, f1 = 2135.0 MHz, and f2 = 2145 MHz.
VDD = 28 Vdc, IDQ = 2 x 800 mA, and POUT = 38 W average.
Nominal operating voltage 28 Vdc. Qualified for a maximum operating voltage of 32 Vdc ±0.5 V.
13
23
160
26
200
—
—
No degradation in output
power.
%
W
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Test Circuit Illustrations
L1
VGG
R5
R3
+
C9
C11
Z1
C5
C1
Z13
Z9
Z5
Z7
1A
2A
Z2
Z4
R6
R4
C2
L2
Z6
Z11
C13
C15
C17
Z15 C3 Z17
Z19
Z12
Z10
Z14
VDD
+
C6
C10
OUT
Z16 C4 Z18
+
C12
Z20
1B
Z8
R2
C7
3 DUT
2B
VGG
+
+
Z3
IN
VDD
R1
C8
C14
C16
PINS:
1A. DRAIN
1B. DRAIN
2A. GATE
2B. GATE
3. SOURCE
C18
A. Schematic
C11
R3
C9
R5
L1 R1
C5
C15
C7
C13
C1
IN
C3
OUT
C4
C2
C8
L2 R2
R6
C17
C14
C6
C18
C16
C10
R4
C12
Parts List:
■ Microstrip line: Z1, Z20: 1.079 in. x 0.065 in.; Z2, Z19: 0.914 in. x 0.112 in.; Z3: 0.100 in. x 0.065 in.; Z4: 1.814 in. x 0.065 in.;
Z5, Z6: 0.340 in. x 0.065 in.; Z7, Z8: 0.455 in. x 0.600 in.; Z9, Z10: 0.835 in. x 0.035 in.; Z11, Z12: 0.510 in. x 0.645 in.;
Z13, Z14: 0.585 in. x 0.050 in.; Z15, Z16: 0.089 in. x 0.166 in.; Z17: 2.006 in. x 0.065 in.; Z18: 0.292 in. x 0.065 in.
®
■ ATC chip capacitor: C1, C2, C3, C4: 20 pF 100B200JW500X; C5, C6, C7, C8: 5.6 pF 100B5R6BW500X (side mounted);
C13, C14: 1000 pF 100B102JCA500X.
■ Murata® capacitor: C9, C10: 2.2 µF, 50 V GRM43ER71H225KA01L C15, C16: 4.7 µF, 50 V GRM55ER7H475KA01
®
■ Sprague tantalum surface-mount chip capacitor: C11, C12, C17, C18: 15 µF, 35 V.
■ 1206 size chip resistor: R1, R2: 4.7 Ω; R3, R4: 560 kΩ; R5, R6 470 kΩ.
®
■ Fair-Rite ferrite bead: L1, L2 2743019447.
®
■ Taconic ORCER RF-35: board material, 1 oz. copper, 30 mil thickness, εr = 3.5.
B. Component Layout
Figure 2. Test Circuit
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
U CT
8
0.6
90
IN D
0.
10
0.1
0.4
20
50
20
10
5.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.2
0.2
20
0.4
0.1
)
/ Yo
(-jB
CE
1.
0
5
0.12
0.37
0.1
-70
40
-1
0.
5
0.
07
30
-1
43
0.
8
0.0
2
0.4
9
0.0
.41
0
0.4
0.39
F
0.38
0.11
-100
0.
0
IV
CT
DU
IN
2.
1.8
1.6
1.2
1.0
0.9
0
-90
0.13
-75
R
0.7
0.14
-80
0.36
-110
(-j
06
Z
X/
1.4
0.15
0.35
0
-4
-4
4
-70
-5
6
0.8
5
-3
0.1
0.3
0
-12
5
3
-60
-5
0.3
7
-60
0.1
VE
0.6
32
CA P
AC
I TI
T
5
,O
o)
0.2
-30
CE
CO
M
-65
18
0.
RE
AC
TA
N
EN
4
0
-5
-25
0.
PO
N
4
0.
0.4
0.0
0.6
0
3.
-20
31
0.
19
0.
ZS
0.3
5
0.4
0.8
-85
AN
PT
CE
US
ES
0
1.
4.0
0.2
f1
0
f3
-4
4
0.
f1
-15
ZL
0.2
8
f3
0.2
2
0.3
0.2
9
0.2
1
-30
6
0.4
4
0.0
0
-15 -80
8
0.
5.0
0.2
-10
0.48
10
0.6
-20
D L OA D <
OW A R
7
HST
0.4
N GT
-170
EL E
V
WA
<Ð
-90
-160
Ð
RESISTANCE COMPONENT (R/Zo), OR CONDUCTANCE COMPONENT (G/Yo)
50
0.49
0.25
0.2
6
0.24
0.27
0.23
0.25
0.24
0.26
0.23
0.27
REFL ECTI ON COEFFI CI EN T I N D EG
REES
L E OF
ANG
I SSI ON COEFFI CI EN T I N
TRA N SM
D EGR
EES
L E OF
ANG
Z0 = 10 Ω
0.0 Ð > W A V EL E
N GTH
S TOW
A RD
0.0
0.49
0.48
± 180
170
Typical Performance Characteristics
(Optimally tuned for 28 Vds, 2 x 800 mA IDQ, POUT = 2 W-CDMA 38 W average operation.)
MHz (f)
2110 (f1)
2140 (f2)
2170 (f3)
ZL Ω
ZS Ω
(Complex Source Impedance) (Complex Optimum Load Impedance)
4.02 – j7.92
3.92 – j6.59
3.98 – j7.73
3.79 – j6.32
3.80 – j7.63
3.67 – j6.12
ZS = Test circuit impedance as measured from gate to gate, balanced configuration.
ZL = Test circuit impedance as measured from drain to drain, balanced configuration.
+
2A
1A
+
PINS:
1A. DRAIN
1B. DRAIN
2A. GATE
2B. GATE
3. SOURCE
3 DUT
–
ZS
2B
–
1B
ZL
Figure 3. Series Equivalent Balanced Input and Output Impedances
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Typical Performance Characteristics (continued)
0
40
-10
 (%), GPS (dB)
35
-20
30
-30
25
20
IM3
GPS
15
ACPR
-40
-50
10
5
0
-60

1
ACPR (dBc), IM3 (dBc)
45
-70
100
10
POUT (W, average)
Test Conditions:
28 VDS, IDQ = 1600 mA.
Two W-CDMA carriers, F1 = 2135 MHz and F2 = 2145 MHz each carrier has 8.98 dB P/A ratio @ 0.01% CCDF, 3.84 MHz channel BW (CBW).
30
 (%), GPS (dB)
25
20
15
10
0

-7
-14
IRL
-21
GPS
IM3
5
0
2040
ACPR
2070
2100
2130
2160
2190
2220
-28
-35
-42
2250
ACPR (dBc), IM3 (dBc), IRL (dB)
Figure 4. Power Gain, Drain Efficiency, ACPR, and IM3 vs. Output Power (2 W-CDMA carrier data)
FTEST (MHz)
Test Conditions:
28 VDS, IDQ = 1600 mA, POUT = 38 W (average).
Two W-CDMA carriers, each carrier has 8.98 dB P/A @ 0.01% probability (CCDF), F1 = FTEST - 5 MHz and F2 = FTEST + 5 MHz , 3.84 MHz
CBW.
Figure 5. Power Gain, Drain Efficiency, ACPR, IM3, and IRL vs. Frequency (2 W-CDMA signal data)
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
15
60
14
50
GPS
13
40
12
30
11
20

10
9
 (%)
GPS (dB)
Typical Performance Characteristics (continued)
10
1
10
100
0
1000
POUT (W)
Test Conditions:
28 VDS, IDQ = 1600 mA, 2140 MHz.
0
50
-10
45
-20
40
-30
35
-40
30
IM3
-50
25
-60
20
-70
IM5
-80
15
IM7

10
-90
-100
5
1
10
100
POUT (W, PEP)
Test Conditions:
28 VDS, IDQ = 1600 mA.
F1 = 2135 MHz and F2 = 2145 MHz.
Figure 7. IM3, IM5, and IM7 vs. Output Power (2 CW signal data)
0
1000
 (%)
IM3, IM5, AND IM7 (dBc)Z
Figure 6. Power Gain and Drain Efficiency vs. Output Power (CW signal data)
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Typical Performance Characteristics (continued)
0
-10
IM3 (dBc)
-20
-30
-40
1200 mA
-50
1400 mA
-60
-70
1600 mA
1800 mA
1
2000 mA
10
100
1000
POUT (W, PEP)
Test Conditions:
28 VDS, IDQ = 1200 mA to 2000 mA in 200 mA steps.
F1 = 2135 MHz and F2 = 2145 MHz.
Figure 8. IM3 vs. Output Power at 1200 mA to 2000 mA, 200 mA Steps (2 CW signal data)
15
2000 mA
GAIN (dB)
14.5
14
1800 mA
13.5
1600 mA
13
1400 mA
12.5
1200 mA
12
11.5
1
10
100
1000
Test Conditions:
28 VDS, IDQ = 1200 mA to 2000 mA in 200 mA steps.
F1 = 2135 MHz and F2 = 2145 MHz.
Figure 9. Power Gain vs. Output Power at 1200 mA to 2000 mA, 200 mA Steps (2 CW signal data)
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Typical Performance Characteristics (continued)
43
-21
41
-23
42
-22
-24
39
-25
38
-26
IM3

37
-27
36
-28
35
-29
34
33
IM3 (dBc)
 (%)
40
-30
23
24
25
26
27
28
29
30
31
-31
VDS (V)
Test Conditions:
IDQ = 1600 mA, POUT = 170 W peak envelope power (PEP).
F1 = 2135 MHz and F2 = 2145 MHz.
Figure 10. IM3 and Drain Efficiency vs. VDS (2 CW signal data)
0
IMD (dBc)
-10
-20
-30
-40
-50
-60
0.01
IM3
IM5
IM7
0.1
1
10
TONE SEPARATION (F, MHz)
Test Conditions:
28 VDS, IDQ = 1600 mA, POUT = 170 W (PEP).
FCENTER = 2140 MHz, F1 = FCENTER - ∆F/2 MHz, F2 = FCENTER - ∆F/2 MHz.
Figure 11. Intermodulation Products vs. Tone Separation (2 CW signal data)
100
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Typical Performance Characteristics (continued)
20
10
F1
0
F2
-10
-20
-30
IMD3
IMD3
-40
-50
-60
-70
-80
ACPR
ACPR
2 CARRIER W-CDMA 3GPP, P/A = 8.5 dB @ 0.01% CCDF
10 MHz SPACING, 3.84 MHz CBW, POUT = 38 W,
VDD = 28 V, IDQ = 1600 mA
Carrier 2.1625 GHz
5 MHz
Figure 12. Spectral Plot
Span 50 MHz
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Package Dimensions
All dimensions are in inches. Tolerances are ±0.005 in. unless specified.
1A
1B
PEAK DEVICES
AGR19K180U
AGR21180XF
XXXXX
YYWWLL XXXXX
ZZZZZZZ
ZZZZZZZ
2A
PINS:
1A. DRAIN
1B. DRAIN
2A. GATE
2B. GATE
3. SOURCE
3
2B
Label Notes:
■ M before the part number denotes model program. X before the part number denotes engineering prototype.
■
■
■
■
The last two letters of the part number denote wafer technology and package type.
YYWWLL is the date code including place of manufacture: year year work week (YYWW), LL = location (AL = Allentown, PA; BK = Bangkok,
Thailand). XXXXX = five-digit wafer lot number.
ZZZZZZZ = seven-digit assembly lot number on production parts.
ZZZZZZZZZZZZ = 12-digit (five-digit lot, two-digit wafer, and five-digit serial number) on models and engineering prototypes.