LTC1860L/LTC1861L µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 12-Bit 150ksps ADCs in MSOP Package Single 3V Supply Low Supply Current: 450µA (Typ) Auto Shutdown Reduces Supply Current to 10µA at 1ksps True Differential Inputs 1-Channel (LTC1860L) or 2-Channel (LTC1861L) Versions SPI/MICROWIRETM Compatible Serial I/O High Speed Upgrade to LTC1285/LTC1288 Pin Compatible with 16-Bit LTC1864L/LTC1865L No Minimum Data Transfer Rate U APPLICATIO S ■ ■ ■ ■ High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition The LTC®1860L/LTC1861L are 12-bit A/D converters that are offered in MSOP and SO-8 packages and operate on a single 3V supply. At 150ksps, the supply current is only 450µA. The supply current drops at lower speeds because the LTC1860L/LTC1861L automatically power down between conversions. These 12-bit switched capacitor successive approximation ADCs include sample-and-holds. The LTC1860L has a differential analog input with an external reference pin. The LTC1861L offers a softwareselectable 2-channel MUX and an external reference pin on the MSOP version. The 3-wire, serial I/O, MSOP or SO-8 package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale allow direct connection to signal sources in many applications, eliminating the need for external gain stages. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. U TYPICAL APPLICATIO Supply Current vs Sampling Frequency Single 3V Supply, 150ksps, 12-Bit Sampling ADC 1000 3V LTC1860L 1 ANALOG INPUT 0V TO 3V VREF VCC 2 IN + SCK 3 IN – SDO 4 GND CONV 8 7 6 5 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS SUPPLY CURRENT (µA) 1µF CONV LOW = 1.5µs TA = 25°C VCC = 2.7V 100 10 1 1860L TA01 0.1 0.01 1 10 0.1 100 SAMPLING FREQUENCY (kHz) 1000 1860L/61L TA02 18601Lf 1 LTC1860L/LTC1861L W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) Supply Voltage (VCC) ................................................. 7V Ground Voltage Difference AGND, DGND LTC1861L MSOP Package ......... ±0.3V Analog Input .................... (GND – 0.3V) to (VCC + 0.3V) Digital Input ..................................... (GND – 0.3V) to 7V Digital Output .................. (GND – 0.3V) to (VCC + 0.3V) Power Dissipation .............................................. 400mW Operating Temperature Range LTC1860LC/LTC1861LC ......................... 0°C to 70°C LTC1860LI/LTC1861LI ...................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U U W PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW VREF IN + IN¯ GND 1 2 3 4 8 7 6 5 VCC SCK SDO CONV MS8 PART MARKING TJMAX = 150°C, θJA = 210°C/W LTD2 LTD3 ORDER PART NUMBER TOP VIEW VREF 1 8 VCC IN + 7 SCK IN – 2 3 GND 4 CONV CH0 CH1 AGND DGND LTC1860LCMS8 LTC1860LIMS8 MS8 PACKAGE 8-LEAD PLASTIC MSOP 6 SDO 5 CONV S8 PACKAGE 8-LEAD PLASTIC SO 10 9 8 7 6 1 2 3 4 5 VREF VCC SCK SDO SDI LTC1861LCMS LTC1861LIMS MS PART MARKING MS PACKAGE 10-LEAD PLASTIC MSOP LTD4 LTD5 ORDER PART NUMBER TJMAX = 150°C, θJA = 210°C/W TOP VIEW CONV 1 8 VCC LTC1860LCS8 LTC1860LIS8 CH0 2 7 SCK CH1 3 6 SDO S8 PART MARKING GND 4 5 SDI 1860L 1860LI TJMAX = 150°C, θJA = 175°C/W ORDER PART NUMBER TOP VIEW LTC1861LCS8 LTC1861LIS8 S8 PART MARKING 1861L 1861LI S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. W U U CO VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. PARAMETER CONDITIONS Resolution No Missing Codes Resolution INL (Note 3) MIN ● 12 ● 12 TYP MAX Bits Bits ±1 ● Transition Noise 0.13 Gain Error ● Offset Error ● = IN + – IN – Input Differential Voltage Range VIN Absolute Input Range IN+ Input IN– Input VREF Input Range LTC1860L S0-8 and MSOP, LTC1861L MSOP Analog Input Leakage Current (Note 4) CIN Input Capacitance In Sample Mode During Conversion ● UNITS ±2 LSB LSBRMS ±20 mV ±5 mV 0 VREF V – 0.05 – 0.05 VCC + 0.05 VCC /2 V V 1 VCC V ±1 µA ● 12 5 pF pF 18601Lf 2 LTC1860L/LTC1861L W U DY A IC ACCURACY TA = 25°C. VCC = 3V, VREF = 3V, fSAMPLE = 150kHz, unless otherwise specified. SYMBOL PARAMETER SNR S/(N + D) Signal-to-Noise Plus Distortion Ratio THD CONDITIONS MIN Signal-to-Noise Ratio 1kHz Input Signal TYP MAX UNITS 72 dB 72 dB Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal 86 dB Full Power Bandwidth 10 MHz 30 kHz Full Linear Bandwidth S/(N + D) ≥ 68dB U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 3.3V ● VIL Low Level Input Voltage VCC = 2.7V ● 0.45 V IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● – 2.5 µA VOH High Level Output Voltage VCC = 2.7V, IO = 10µA VCC = 2.7V, IO = 360µA ● ● VOL Low Level Output Voltage VCC = 2.7V, IO = 400µA ● 0.3 V IOZ Hi-Z Output Leakage CONV = VCC ● ±3 µA ISOURCE Output Source Current VOUT = 0V – 6.5 mA ISINK Output Sink Current VOUT = VCC 6.5 mA IREF Reference Current (LTC1860L SO-8, MSOP and LTC1861L MSOP) CONV = VCC fSMPL = fSMPL(MAX) ● ● 0.001 0.01 3 0.1 µA mA ICC Supply Current CONV = VCC After Conversion fSMPL = fSMPL(MAX) ● ● 0.5 0.45 10 1.0 µA mA PD Power Dissipation fSMPL = fSMPL(MAX) TYP MAX U U U WW E DED OPERATI G CO DITIO S UNITS 1.9 2.3 2.1 V 2.6 2.45 V V 1.22 U RECO MIN mW The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX VCC Supply Voltage fSCK Clock Frequency tCYC Total Cycle Time tSMPL Analog Input Sampling Time (Note 5) tsuCONV Setup Time CONV↓ Before First SCK↑, (See Figure 1) thDI Holdtime SDI After SCK↑ tsuDI Setup Time SDI Stable Before SCK↑ tWHCLK SCK High Time fSCK = fSCK(MAX) tWLCLK SCK Low Time fSCK = fSCK(MAX) tWHCONV CONV High Time Between Data Transfer Cycles tWLCONV CONV Low Time During Data Transfer 12 SCK thCONV Hold Time CONV Low After Last SCK↑ 26 ns ● 2.7 3.6 DC 8 UNITS 12 • SCK + tCONV LTC1860L LTC1861L V MHz µs 12 10 SCK SCK 60 ns LTC1861L 30 ns LTC1861L 30 ns 45% 1/fSCK 45% 1/fSCK tCONV µs 18601Lf 3 LTC1860L/LTC1861L WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL PARAMETER CONDITIONS tCONV Conversion Time (See Figure 1) MIN ● fSMPL(MAX) Maximum Sampling Frequency tdDO MAX UNITS 3.7 4.66 µs 45 55 60 ns ns 55 120 ns 35 120 ns 150 ● Delay Time, SCK↓ to SDO Data Valid TYP kHz CLOAD = 20pF ● tdis Delay Time, CONV↑ to SDO Hi-Z ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF ● thDO Time Output Data Remains Valid After SCK↓ CLOAD = 20pF ● tr SDO Rise Time tf SDO Fall Time ● 15 ns CLOAD = 20pF 25 ns CLOAD = 20pF 12 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 5 Note 4: Channel leakage current is measured while the part is in sample mode. Note 5: Assumes fSCK = fSCK(MAX). In the case of the LTC1860L SCK does not have to be clocked during this time if the SDO data word is not desired. In the case of the LTC1861L a minimum of 2 clocks are required on the SCK input after CONV falls to configure the MUX during this time. U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Sampling Frequency 600 500 100 10 1 20 fS = 150kHz VCC = 2.7V VREF = 2.5V SHUTDOWN CURRENT (µA) CONV LOW = 1.5µs TA = 25°C VCC = 2.7V SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 1000 Sleep Current vs Temperature Supply Current vs Temperature 400 300 200 fS = 150kHz VCC = 2.7V VREF = 2.5V 15 10 5 100 0.1 0.01 1 10 0.1 100 SAMPLING FREQUENCY (kHz) 1000 1860L/61L G01 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1860L/61L G02 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1860L/61L G03 18601Lf 4 LTC1860L/LTC1861L U W TYPICAL PERFOR A CE CHARACTERISTICS Reference Current vs Sampling Rate 25 25 8 REFERENCE CURRENT (µA) CONV LOW = 1.5µs TA = 25°C VCC = 2.7V VREF = 2.5V 9 7 6 5 4 3 2 fS = 150kHz VCC = 2.7V VREF = 2.5V 20 REFERENCE CURRENT (µA) 10 REFERENCE CURRENT (µA) Reference Current vs Reference Voltage Reference Current vs Temperature 15 10 5 fS = 150kHz TA = 25°C VCC = 3.6V 20 15 10 5 1 0 –50 –25 0 0 25 75 100 125 50 SAMPLING FREQUENCY (kHz) 150 0 50 25 75 0 TEMPERATURE (°C) Typical INL Curve 1.0 1.5 2.0 2.5 3.0 REFERENCE VOLTAGE (V) 100 ANALOG INPUT LEAKAGE (nA) DNL ERROR (LSBs) –0.5 0 –0.5 –1.0 512 1024 1536 2048 2560 3072 3584 4096 CODE 0 75 50 25 50 25 75 0 TEMPERATURE (°C) 1860L/61L G08 Change in Offset vs Reference Voltage 1 0 –1 0.6 2 fS = 150kHz VCC = 2.7V VREF = 2.5V GHANGE IN GAIN ERROR (LSB) CHANGE IN OFFSET (LSB) 0.8 125 Change in Gain Error vs Reference Voltage 1.0 fS = 150kHz TA = 25°C VCC = 3.6V 100 1860L/61L G09 Change in Offset vs Temperature 2 4.0 CONV = 0V VCC = 2.7V VREF = 2.5V 0 –50 –25 512 1024 1536 2048 2560 3072 3584 4096 CODE 1860L/61L G07 3.5 Analog Input Leakage vs Temperature fS = 150kHz TA = 25°C VCC = 2.7V VREF = 2.5V 0.5 0 0 0.5 1860L/61L G06 1.0 fS = 150kHz TA = 25°C VCC = 2.7V VREF = 2.5V 0.5 INL ERROR (LSBs) 0 Typical DNL Curve 1.0 CHANGE IN OFFSET (LSB) 125 1860L/61L G05 1860L/61L G04 –1.0 100 0.4 0.2 0 –0.2 –0.4 –0.6 fS = 150kHz TA = 25°C VCC = 3.6V 1 0 –1 –0.8 –2 –1.0 0 2 3 1 REFERENCE VOLTAGE (V) 4 1860L/61L G10 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1860L/61L G11 –2 0 2 3 1 REFERENCE VOLTAGE (V) 4 1860L/61L G12 18601Lf 5 LTC1860L/LTC1861L U W TYPICAL PERFOR A CE CHARACTERISTICS Change in Gain Error vs Temperature 4096 Point FFT Non Averaged 1.0 fS = 150kHz VCC = 2.7V VREF = 2.5V 0.6 fIN = 1kHz fS = 150kHz TA = 25°C VCC = 3V VREF = 3V –10 –20 –30 0.2 0 –0.2 –0.4 –40 60 –50 –60 –70 50 40 30 –80 fS = 150kHz TA = 25°C VCC = 3V VIN = 0dB VREF = 3V 20 –90 –0.6 –100 –0.8 10 –110 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 –120 0 80 0 70 –10 100 –30 30 fS = 150kHz TA = 25°C VCC = 3V VIN = 0dB VREF = 3V 10 0 1 10 fIN (kHz) 100 80 70 –40 –50 –60 60 50 40 –70 30 –80 20 –90 10 –100 0 1 1860L/61L G16 U U U PI FU CTIO S 90 SFDR (dB) THD (dB) 50 Spurious Free Dynamic Range vs fIN fS = 150kHz TA = 25°C VCC = 3V VIN = 0dB VREF = 3V –20 60 100 1860L/61L G15 Total Harmonic Distortion vs fIN 40 10 fIN (kHz) 1860L/61L G14 Signal-to-(Noise + Distortion) vs fIN 20 1 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 fIN (kHz) 1860L/61L G13 SINAD (dB) 70 SNR (dB) 0.4 AMPLITUDE (dB) CHANGE IN GAIN ERROR (LSB) 0.8 –1.0 SNR vs fIN 80 0 10 fIN (kHz) 100 1860L/61L G17 fS = 150kHz TA = 25°C VCC = 3V VIN = 0dB VREF = 3V 1 10 fIN (kHz) 100 1860L/61L G18 LTC1860L VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. IN +, IN– (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. CONV (Pin 5): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. 18601Lf 6 LTC1860L/LTC1861L U U U PI FU CTIO S LTC1861L (MSOP Package) LTC1861L (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. W FUNCTIONAL BLOCK DIAGRA U CONV (SDI) SCK VCC CONVERT CLK SDO SERIAL PORT BIAS AND SHUTDOWN DATA IN 12-BITS IN + (CH0) + IN – (CH1) – 12-BIT SAMPLING ADC DATA OUT PIN NAMES IN PARENTHESES REFER TO LTC1861L 1860L/61L BD GND VREF 18601Lf 7 U LTC1860L/LTC1861L TEST CIRCUITS Voltage Waveforms for SDO Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, tf, tdis and ten TEST POINT VOH SDO VOL VCC tdis WAVEFORM 2, ten 3k SDO tdis WAVEFORM 1 20pF tr tf 1860 TC04 1860 TC01 Voltage Waveforms for ten Voltage Waveforms for tdis CONV SDO 1860 TC03 ten Voltage Waveforms for SDO Delay Times, tdDO and thDO SDO WAVEFORM 1 (SEE NOTE 1) VIL tdDO thDO VOH 90% tdis SDO WAVEFORM 2 (SEE NOTE 2) SCK VIH CONV 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL 1860 TC05 SDO VOL 1860 TC02 U W U U APPLICATIO S I FOR ATIO LTC1860L OPERATION Analog Inputs Operating Sequence The LTC1860L has a unipolar differential analog input. The converter will measure the voltage between the “IN + ” and “IN – ” inputs. A zero code will occur when IN+ minus IN – equals zero. Full scale occurs when IN+ minus IN – equals VREF minus 1LSB. See Figure 2. Both the “IN+ ” and “IN – ” inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If “IN – ” is grounded and VREF is tied to VCC, a rail-to-rail input span will result on “IN+ ” as shown in Figure 3. The LTC1860L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1860L goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1860L goes into sample mode and SDO is enabled. SCK synchronizes the data transfer with each bit being transmitted from SDO on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1. Reference Input The voltage on the reference input of the LTC1860L (and the LTC1861L MSOP package) defines the full-scale range of the A/D converter. These ADCs can operate with reference voltages from VCC to 1V. 18601Lf 8 LTC1860L/LTC1861L U W U U APPLICATIO S I FOR ATIO CONV t SMPL SLEEP MODE tCONV 1 SCK 2 3 4 5 6 7 8 9 10 11 12 DON'T CARE B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* SDO Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F01 Figure 1. LTC1860L Operating Sequence 1µF 111111111111 VCC 111111111110 • • • LTC1860L 1 000000000001 000000000000 VIN* VREF VREF – 1LSB VREF – 2LSB 1LSB 0V *VIN = IN + – IN – VIN = 0V TO VCC VREF VCC 2 IN + SCK 3 IN – SDO GND CONV 4 8 7 6 5 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS 1860 F03 1860 F02 Figure 2. LTC1860L Transfer Curve LTC1861L OPERATION Operating Sequence The LTC1861L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1861L goes into sleep mode. The LTC1861L’s 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. Analog Inputs The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a Figure 3. LTC1860L with Rail-to-Rail Input Span given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of Table 1. In single-ended mode, all input channels are measured with respect to GND (or AGND). A zero code will occur when the “+” input minus the “–” input equals zero. Full scale occurs when the “+” input minus the “–” input equals VREF minus 1LSB. See Figure 5. Both the “+” and “–” inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the “–” input in differential mode is grounded, a rail-to-rail input span will result on the “+” input. Reference Input The reference input of the LTC1861L SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1861L MSOP package defines the span of the A/D converter. The LTC1861L MSOP package can operate with reference voltages from 1V to VCC. 18601Lf 9 LTC1860L/LTC1861L U W U U APPLICATIO S I FOR ATIO CONV SDI t SMPL SLEEP MODE tCONV S/D O/S DON’T CARE 1 SCK 2 DON’T CARE 3 4 5 6 7 8 9 10 11 12 DON'T CARE B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* SDO Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F04 Figure 4. LTC1861L Operating Sequence 111111111111 Table 1. Multiplexer Channel Selection 111111111110 • • • VIN* 000000000001 000000000000 VCC VCC – 1LSB VCC – 2LSB 1LSB 0V *VIN = (SELECTED “+” CHANNEL) – (SELECTED “–” CHANNEL) REFER TO TABLE 1 SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE 1860 F05 MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 CHANNEL # 0 1 + + + – – + GND – – 186465 TBL1 Figure 5. LTC1861L Transfer Curve GENERAL ANALOG CONSIDERATIONS Grounding The LTC1860L/LTC1861L should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTC1861L MSOP package and GND for the LTC1860L and LTC1861L SO-8 package) should be tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1µF tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1860L/ LTC1861L have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200Ω or high speed op amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins. 18601Lf 10 LTC1860L/LTC1861L U PACKAGE DESCRIPTIO MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 0.254 (.010) 8 0.52 (.206) REF 7 6 5 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.90 ± 0.15 (1.93 ± .006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.42 ± 0.04 (.0165 ± .0015) TYP 0.65 (.0256) BSC 1 0.53 ± 0.015 (.021 ± .006) DETAIL “A” RECOMMENDED SOLDER PAD LAYOUT 0.18 (.077) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 2 3 4 1.10 (.043) MAX SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.86 (.034) REF 0.13 ± 0.076 (.005 ± .003) 0.65 (.0256) BSC MSOP (MS8) 0802 MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 10 9 8 7 6 3.2 – 3.45 (.126 – .136) 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.90 ± 0.15 (1.93 ± .006) DETAIL “A” 0.497 ± 0.076 (.0196 ± .003) REF 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.53 ± 0.01 (.021 ± .006) 0.18 (.007) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 1.10 (.043) MAX DETAIL “A” SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.13 ± 0.076 (.005 ± .003) 0.50 (.0197) BSC MSOP (MS) 0802 S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC .245 MIN .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) .053 – .069 (1.346 – 1.752) 0°– 8° TYP 8 7 6 5 .004 – .010 (0.101 – 0.254) .160 ±.005 .016 – .050 (0.406 – 1.270) .030 ±.005 TYP RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .050 (1.270) BSC .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) 1 2 3 4 SO8 0303 18601Lf Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC1860L/LTC1861L U TYPICAL APPLICATIO Tiny 2-Chip Data-Acquistion System 1µF 3V 3V 0.1µF 8 + 3 VIN 4 LTC6910-1 – 2 7 6 VREF 1 499Ω 5 270pF IN+ SCK LTC1860L IN – SDO GND AGND 1µF VCC CONV ADC CONTROL GAIN CONTROL LTC6910-1 (IN TSOT-23 PACKAGE) COMPACTLY ADDS 40dB OF INPUT GAIN RANGE TO THE LTC1860L (IN MSOP 8-PIN PACKAGE). SINGLE 3V SUPPLY 1860L/61L TA03 RELATED PARTS PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION 12-Bit Serial I/O ADCs LTC1286/LTC1298 12.5ksps/11.1ksps 1.3mW/1.7mW 1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V LTC1400 400ksps 75mW 1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V LTC1401 200ksps 15mW SO-8 with Internal Reference, 3V LTC1402 2.2Msps 90mW Serial I/O, Bipolar or Unipolar, Internal Reference LTC1404 600ksps 25mW SO-8 with Internal Reference, Bipolar or Unipolar, 5V LTC1860/LTC1861 250ksps 4.25mW SO-8, MS8, 1-Channel, 5V/SO-8, MS, 2-Channel, 5V LTC1417 400ksps 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V LTC1418 200ksps 15mW Serial/Parallel I/O, Internal Reference, 5V LTC1609 200ksps 65mW Configurable Bipolar or Unipolar Input Ranges, 5V LTC1864/LTC1865 250ksps 4.25mW SO-8, MS8, 1-Channel, 5V/SO-8, MS, 2-Channel, 5V LTC1864L/LTC1865L 150ksps 1.22mW SO-8, MS8, 1-Channel, 3V/SO-8, MS, 2-Channel, 3V 14-Bit Serial I/O ADCs 16-Bit Serial I/O ADCs References LT1460 Micropower Precision Series Reference Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23 LT1790 Micropower Low Dropout Reference 60µA Supply Current, 10ppm/°C, SOT-23 18601Lf 12 Linear Technology Corporation LT/TP 0303 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001