AKM AK8825VG Hd/sd multi format video encoder with 3ch dac Datasheet

[AK8825]
AK8825
HD/SD Multi Format Video Encoder with 3ch DAC
General Description
The AK8825 is a HD/SD TV Video Encoder with onchip 3-channel 10bit DAC.
As input data, in SDTV encoder mode, SMTE-125M / ITUR-R.BT601, 656 compatible Y/Cb/Cr 4:2:2 formats (8bit) are
accepted and in HDTV encoder mode, SMPTE-274M (1080i), SMPTE296M (720p) compatible Y/Cb/Cr 4:2:2 formats (8bit x 2)
are accepted.
As input data capture method, either a Synchronous mode to be made by detecting encoded EAV signal or a mode to
synchronize with externally-fed H/V SYNC signal is selectable.
Outputs of CVBS / SDY / SDC and HDY / HDPB / HDPR and R / G / B analog signal can be output exclusively.
VBI signal and Macrovision signal can be also superimposed on output in addition to Video signals by register setting.
AK8825 supports I2C compatible interface as Micro-Processor interface.
Features
Component Video Encoder
- Compatible Input Data
SMPTE125M-1995 / ITU-R BT601 (525i/625i)
SMPTE293M-1996 / ITU-R BT1358 (525p/625p)
SMPTE274M-1998 (1080i)
SMPTE296M-2001 (720p)
- Input Signal Format (525i / 625i, 525p / 625p, 1080i, 720P)
Y/Cb/Cr 4:2:2 (8bit x 1: 525i/625i)
Y/Cb/Cr 4:2:2 (8bit x 2: 525p/625p/1080i/720p)
RGB 6:6:6
RGB 5:6:5
- Input Clock
27MHz (525i / 625i / 525p / 625p) / 74.25MHz (1080i/720p)
- Output Signals
Y/Pb/Pr Interlace
Y/Pb/Pr Progressive
(EIA 770.2, EAI 770.3)
- Input Signal Synchronization
ITU-R.BT 656 I/F (EAV Decode)
Slave operation by HSYNC / VSYNC
(525i: ITU-R. BT601 Compatible 625i / 525p / 625p / 1080i / 720p; CEA-861-D Compatible)
- VBID (CGMS-A), CC/XDS, WSS, CEA-805-B (Type A/B)
- Macrovision 525i / 625i Rev.7.1.1L, 525p/625p Macrovision Progressive 1.2
- Internal Color bar Generator
- Internal Black Burst Generator
- Adjustable Y / Pb / Pr Delay Function
NTSC / PAL Composite Video Encoder
- NTSC-M, PAL-B, D, G, H, I. M, N Encoding
- Composite Video Output / S-Video Output
- Compatible Input Data
SMPTE125M-1995 / ITU-R BT601(525i/625i) Y/Cb/Cr 4:2:2 (8bit x 1)
RGB 6:6:6
RGB 5:6:5
- Input Signal Synchronization
ITU-R.BT 656 I/F (EAV Decode)
Slave operation by HSYNC / VSYNC
( 525i / 625i: ITU-R. BT601 Compatible)
- Input Clock
27MHz
- VBID(CGMS-A), CC/XDS, WSS
- Macrovision Rev. 7.1.L
Rev-E-00
1
2008/03
[AK8825]
RGB Video DAC
- RGB output
- Input Data Format
RGB 6:6:6
RGB 5:6:5
- Input Clock
54MHz (max)
Common Specification
- 10bit DAC x 3ch (max operating speed 150MHz)
- I2C BUS I/F (400kHz) compatible
- Power Down mode
- Internal VREF Circuit
- 3.0V / 1.8V VCC
- Package
- 57pin FBGA (5mm x 5mm)
- 48pin QFN (7.2mm x 7.2mm)
* This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectual rights. The use
of Macrovision’s copy protection technology in the device must be authorized by Macrovision and is intended for home and
other limited pay-per -view use only, unless otherwise authorized in written by Macrovision. Reverse engineering or
disassembly is prohibited.
Rev-E-00
2
2008/03
[AK8825]
1. Block Diagram
CLKIN
27MHz or 74.25MHz
Clock Gen
PLL
74.25MHz-> 148.5MHz
6.75/13.5/27/54/148.5MHz
27MHz -> 54MHz
PDN SDA SCL SELA
TMO
u-P I/F
TEST
TEST1
Y
Y
Cb
YCbCr
18-bit
NTSC/PAL
C
Composite Video
CVBS
Encoder
YCbCr to RGB
RGB
Cb/B
Cr/R
Component
Encoder
Cb/B
Cr/R
G
G
B
B
Delay
Selector
RGB to YCbCr
DAC1
HDY/SDY/G
DAC2
HDPb/SDC/B
DAC3
HDPr/CVBS/R
Y/G
Y/G
Selector
VDI
Selector
HDI
Sync Generator
(EAV Decode or HD/VD Sync)
DATA[17:0]
Cr
TEST0
R
R
Delay
Buffer
HDO
Delay
Buffer
VDO
VREF
PVDD1
PVDD2
DVDD DVSS
AVDD AVSS
VREF
IREF BYPASS FLT
Fig. 1 Block Diagram
Rev-E-00
3
2008/03
[AK8825]
With Register setting, AK8825 works as
- Multi-Format Component Video Encoder (Component Video Encoder)
- NTSC/PAL Composite Video Encoder (Composite Video Encoder)
- High Speed Video DAC
1-1. Component Video Encoder Block
From
Timing
Generator
HD-Timing
Generator
CLK Rate C
CGMS-A
WSS
Y[7:0
sin(x)/x
x2
x2
Compensation
LPF-D
LPF-G*
SYNC
Generator
Y[9:0]
to DAC
CLK Rate B
*CLK Rate D
Cb[7:0]
Cr[7:0]
4:2:2
to
4:4:4
x2 Interpolation
CLK Rate A
From
Clock Gen
LPF-E
x2
x2
LPF-F
LPF-H*
Pb[9:0]
to DAC
Pr[9:0]
to DAC
CLK Rate B
6.75MHz/13.5/27/54/74.25/148.5MHz
Fig. 2 Component Video Encoder Block
This Block described as Component Video Encoder Block in this datasheet.
CLK Rate D is only a case of D1(525i/625i) mode.
Clock Rate
CLK Rate A
CLK Rate B
CLK Rate C
CLK Rate D
Rev-E-00
D1( 525i /625i )
6.75MHz
13.5MHz
27MHz
54MHz
D2( 525P / 625P )
13.5MHz
27MHz
54MHz
-
4
D3/D4(1080i/720P)
37.125MHz
74.25MHz
148.5MHz
-
2008/03
[AK8825]
1-2. NTSC/PAL Composite Video Encoder Block
From
Timing
Generator
SD-Timing
Generator
CGMS-A
WSS
Y[7:0
SYNC
Generator
x2
LPF-A
sin(x)/x
Y[9:0]
to DAC
sin(x)/x
CVBS[9:0]
to DAC
sin(x)/x
C[9:0]
to DAC
13.5MHz
U
Cb[7:0]
C
Interpolation
Cr[7:0]
4:2:2 to 4:4:4
LPF-B
cos
6.75MHz
From
Clock Gen
27MHz
x2
LPF-C
V
13.5MHz
sin
DFS
27MHz
Fig. 3 Composite Video Encoder Block
This Block described as Composite Video Encoder Block in this datasheet.
1-3 High Speed Video DAC mode
AK8825 can be used as High Speed Video DAC. This mode is described as Video DAC mode in this datasheet.
From
CLKIN
DATA[5:0] / DATA[4:0]
DATA[17:0]
Data
Distributor
DATA[11:6] / DATA[10:5]
DAC1
Level
Delay
Shifter
(unit CLK)
DATA[17:12] / DATA[15:11]
DAC2
DAC3
HDI
Delay
HDO
VDI
Delay
VDO
Fig. 4 High Speed Video ADC Block
Rev-E-00
5
2008/03
[AK8825]
1-4. CLK Gen Block
CLKIN
x2 PLL
74.25→148.5MHz
x4 PLL
27→108MHz
x2 CLK
1/2 DIV
Fig. 5
1/2 DIV
x1 CLK
1/4 DIV
x1/2 CLK
1/8 DIV
x1/4 CLK
CLK Gen Block
Clock Rate
x1/4 CLK
x1/2 CLK
x1 CLK
x2 CLK
Rev-E-00
D1( 525i /625i )
6.75MHz
13.5MHz
27MHz
54MHz
D2( 525P / 625P )
13.5MHz
27MHz
54MHz
6
D3/D4(1080i/720P)
37.125MHz
74.25MHz
148.5MHz
2008/03
[AK8825]
Notice Information
In this document, relations of the word are shown as following table
Number of Lines in Frame
525 Interlace
625 Interlace
525 Progressive
625 Progressive
1125 Interlace
750 Progressive
Rev-E-00
Description in this datasheet
525i or 480i or D1
625i or 576i or D1
525p or 480p or D2
625p or 576p or D2
1125i or 1080i or D3
750p or 720p or D4
7
2008/03
[AK8825]
2. Ordering Guide
AK8825VG 57 pin FBGA
AK8825VN 48 pin QFN
Rev-E-00
8
2008/03
[AK8825]
3. Pin Assignment
3.1 AK8825VG
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
Fig. 6 Ball Layout (Bottom View)
A
B
C
D
E
F
G
H
J
9
TEST1
VDO
HDO
CLKIN
VDI
PVDD2
DVSS
DVDD
TMO
8
FLT
NC
NC
HDI
DATA17
DATA16
DATA15
NC
DATA14
7
NC
NC
6
DACO3
DACO2
5
DACO1
NC
4
AVDD
AVSS
3
BYPASS
VREF
NC
DATA12
DATA13
DATA11
DVSS
DATA10
PVDD2
DATA8
DATA9
DATA6
DATA7
2
IREF
BVSS
SDA
SELA
DATA0
DVSS
DATA1
DATA5
DATA4
1
TEST0
PDN
SCL
PVDD1
NC
DVDD
DATA2
DATA3
DVSS
Fig. 7-1 Pin Assignment (Bottom View)
Rev-E-00
9
2008/03
[AK8825]
3.2 AK8825VN
DATA14
DATA15
DVDD
DVSS
DATA16
PVDD2
DATA17
VDI
HDI
CLKIN
HDO
VDO
36 35 34 33 32 31 30 29 28 27 26 25
TEST1
FLT
DACO3
DACO2
DACO1
AVSS
AVDD
VREF
BYPASS
BVSS
IREF
TEST0
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
TMO
DATA13
DATA12
DATA11
DVSS
PVDD2
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
1 2 3 4 5 6 7 8 9 10 11 12
DATA4
DATA3
DATA2
DATA1
DVDD
DVSS
DATA0
SELA
PVDD1
SDA
SCL
PDN
Fig. 7-2 Pin Layout (TopView)
Rev-E-00
10
2008/03
[AK8825]
4. Function of Pins
4-1 AK8825VG
Pin#
Pin Name
Power
I/O
D9
CLKIN
P2
I
E2
DATA0
P2
I
G2
DATA1
P2
I
G1
DATA2
P2
I
H1
DATA3
P2
I
J2
DATA4
P2
I
H2
DATA5
P2
I
H3
DATA6
P2
I
J3
DATA7
P2
I
H4
DATA8
P2
I/O
J4
DATA9
P2
I/O
H5
DATA10
P2
I/O
H6
DATA11
P2
I/O
H7
DATA12
P2
I/O
J7
DATA13
P2
I/O
J8
DATA14
P2
I/O
G8
DATA15
P2
I/O
F8
DATA16
P2
I/O
E8
DATA17
P2
I/O
D8
HDI
P2
I/O
E9
VDI
P2
I/O
Rev-E-00
Function
Clock Input Pin
Composite Video Encoder Mode: Input 27MHz Clock.
Component Video Encoder Mode: Either 27MHz or 74.25MHz clock is input.
(Depending on Input Video Format)
High Speed Video DAC Mode: Max input clock is 54MHz.
Prohibited Hi-z States
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin =Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
In case of slave Synchronization operation mode, Horizontal Sync timing should be
input.
In case of PDN pin = Low, Hi-z states is possible.
In case of slave Synchronization operation mode, Vertical Sync timing should be
input.
In case of PDN pin = Low, Hi-z states is possible.
11
2008/03
[AK8825]
B1
PDN
P1
I
C2
SDA
P1
I/O
C1
SCL
P1
I
D2
SELA
P1
I
C9
HDO
P2
O
B9
VDO
P2
O
A5
DACO1
A
O
B6
DACO2
A
O
A6
DACO3
A
O
B3
VREF
A
I
A2
IREF
A
O
A3
BYPASS
A
O
FLT
AVDD
AVSS
DVDD
A
A
A
D
O
P
G
P
Control Pin for Power Down and Reset.
AK8825 is initialized with PDN = Low.
AK8825 becomes Power down states during PDN=Low
Normal operation mode, PDN pin should be High.
This pin is Prohibited to be Hi-z States
I2C Bus Data Input Pin.
Pulled up externally.
I2C BUS clock input pin.
Pulled up externally.
I2C BUS Address select pin.
Fixed to PVSS1 or PVDD1.
Horizontal Sync Timing signal output pin.
In case of PDN pin = Low, this pin outputs Low.
Vertical Sync Timing signal output pin.
In case of PDN Pin = Low, this pin outputs Low.
DAC1 output pin. Output signal is set by register
Composite Video Encoder mode:
Y or CVBS
Component Video Encoder mode:
Y or G
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
DAC2 output pin. Output signal is set by register
Composite Video Encoder mode:
Pb or B
Component Video Encoder mode:
C
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
DAC3 output pin. Output signal is set by register
Composite Video Encoder mode:
Pr or R
Component Video Encoder mode:
CVBS
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
to be connected to AVDD via a 0.1 uF capacitor
Reference Current Output pin for DAC
Should be connected to AVSS via a 3.3 K ohm ( +/- 1 % ) resistor.
Output pin to output On-Chip VREF voltage.
Should be connected to AVSS via a larger-than 0.1 uF capacitor.
Filter Pin for PLL
Power supply pin for Analog.
Ground pin for Analog
Power supply pins for Digital.
DVSS
D
G
Ground pins for Digital.
PVDD1
PVDD2
P1
P2
P
P
B2
BVSS
A
G
A1
TEST0
I
P1
A9
TEST1
I
P2
J9
TMO
I/O
P2
Power supply pin for I/O(PDN, SDA, SCL, SELA)
Power supply pins for I/O(CLKIN, DATA[17:0], HDI, VDI)
Ground pin for Substrate.
Connect to AVSS.
TEST pin.
Connect to DVSS.
(Internally Pull-down with approx. 100k-ohm)
TEST pin.
Connect to DVSS.
(Internally Pull-down with approx. 100k-ohm)
TEST pin.
Leave open.
(Internally Pull-down with approx. 100k-ohm)
A8
A4
B4
F1,H9
F2,G9,
J1,J6
D1
J5, F9
A7, B5,
B7, B8,
C3, C8,
E1, H8
Rev-E-00
NC
NCpins.
Leave open.
12
2008/03
[AK8825]
4-2 AK8825VN
pin#
Pin Name
power
I/O
1
PDN
P1
I
2
SCL
P1
I
3
SDA
P1
I/O
4
PVDD1
P1
P
5
SELA
P1
I
6
DATA0
P2
I
7
8
DVSS
DVDD
D
D
G
P
9
DATA1
P2
I
10
DATA2
P2
I
11
DATA3
P2
I
12
DATA4
P2
I
13
DATA5
P2
I
14
DATA6
P2
I
15
DATA7
P2
I
16
DATA8
P2
I/O
17
DATA9
P2
I/O
18
DATA10
P2
I/O
19
20
PVDD2
DVSS
P2
D
P
G
21
DATA11
P2
I/O
22
DATA12
P2
I/O
23
DATA13
P2
I/O
24
TMO
I/O
P2
25
DATA14
P2
I/O
26
DATA15
P2
I/O
27
DVDD
D
P
Rev-E-00
Function
Control Pin for Power Down and Reset.
AK8825 is initialized with PDN = Low.
AK8825 becomes Power down states during PDN=Low
Normal operation mode, PDN pin should be High.
This pin is Prohibited to be Hi-z States
I2C BUS clock input pin.
Pulled up externally.
I2C Bus Data Input Pin.
Pulled up externally.
Power supply pin for I/O(PDN, SDA, SCL, SELA)
I2C BUS Address select pin.
Fixed to PVSS1 or PVDD1.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Ground pins for Digital.
Power supply pins for Digital.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.能になります。
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Power supply pins for I/O(CLKIN, DATA[17:0], HDI, VDI)
Ground pins for Digital.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
TEST pin.
Leave open.
(Internally Pull-down with approx. 100k-ohm)
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Power supply pins for Digital.
13
2008/03
[AK8825]
28
DVSS
D
G
29
DATA16
P2
I/O
30
PVDD2
P2
P
31
DATA17
P2
I/O
32
VDI
P2
I/O
33
HDI
P2
I/O
34
CLKIN
P2
I
35
HDO
P2
O
36
VDO
P2
O
37
TEST1
I
P2
38
FLT
A
O
39
DACO3
A
O
40
DACO2
A
O
41
DACO1
A
O
42
43
44
AVSS
AVDD
VREF
A
A
A
G
P
I
45
BYPASS
A
O
46
BVSS
A
G
47
IREF
A
O
48
TEST0
I
P1
Ground pins for Digital.
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
Power supply pins for I/O(CLKIN, DATA[17:0], HDI, VDI)
Data Input pin
Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
In case of slave Synchronization operation mode, Vertical Sync timing should be
input.
In case of PDN pin = Low, Hi-z states is possible.
In case of slave Synchronization operation mode, Horizontal Sync timing should be
input.
In case of PDN pin = Low, Hi-z states is possible.
Clock Input Pin
Composite Video Encoder Mode: Input 27MHz Clock.
Component Video Encoder Mode: Either 27MHz or 74.25MHz clock is input.
(Depending on Input Video Format)
High Speed Video DAC Mode: Max input clock is 54MHz.
Prohibited Hi-z States
Horizontal Sync Timing signal output pin.
In case of PDN pin = Low, this pin outputs Low.
Vertical Sync Timing signal output pin.
In case of PDN Pin = Low, this pin outputs Low.
TEST pin.
Connect to DVSS.
(Internally Pull-down with approx. 100k-ohm)
Filter Pin for PLL
DAC3 output pin. Output signal is set by register
Composite Video Encoder mode:
Pr or R
Component Video Encoder mode:
CVBS
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
DAC2 output pin. Output signal is set by register
Composite Video Encoder mode:
Pb or B
Component Video Encoder mode:
C
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
DAC1 output pin. Output signal is set by register
Composite Video Encoder mode:
Y or CVBS
Component Video Encoder mode:
Y or G
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
Ground pin for Analog
Power supply pin for Analog.
to be connected to AVDD via a 0.1 uF capacitor
Output pin to output On-Chip VREF voltage.
Should be connected to AVSS via a larger-than 0.1 uF capacitor.
Ground pin for Substrate.
Connect to AVSS.
Reference Current Output pin for DAC
Should be connected to AVSS via a 3.3 K ohm ( +/- 1 % ) resistor.
TEST pin.
Connect to DVSS.
(Internally Pull-down with approx. 100k-ohm)
Power A: AVDD D: DVDD P1: PVDD1 P2: PVDD2
I/O: Input/Output pin I: Input pin O: Output pin G: Ground pin P: Power Supply pin
Pull Up / Down Pins
Rev-E-00
14
2008/03
[AK8825]
Pin Name
TEST0
TEST1
TMO
Rev-E-00
Pull-up/Down
Pull Down
Pull Down
Pull Down
Pull-Up/Down Resistor
Approx. 100k-ohm
Approx. 100k-ohm
Approx. 100k-ohm
15
2008/03
[AK8825]
5.
■
Electrical Characteristics
Absolute Maximum Ratings (* Power supply voltages are values where each ground pin(DVSS=AVSS) is at 0V)
Parameter
Min.
Max.
Unit
Power Supply (VDD)
AVDD (DAC,PLL,VREF)
4.2
DVDD (Digital Core)
-0.3
2.2
V
PDVD1(Digital I/O)
4.2
PVDD2 (Digital I/O)
4.2
Input Voltage (VIN)
PVDD1 + 0.3
-0.3
V
PVDD2 + 0.3
Input Current (IIN)
+/- 10
mA
Storage temperature
-40
125
°C
* All power supply ground pins (DVSS, AVSS) should be at the same potential.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal Operating Specifications are not guaranteed at these extremes.
■
■
Recommended Operating Conditions
Parameter
Min.
Power Supply (VDD)
AVDD
2.7
DVDD
1.65
PVDD1
DVDD
PVDD2
DVDD
Operating Temperature (TA)
-40
Typ.
Max.
3.0
1.8
1.8
1.8
3.6
2.0
3.6
3.6
85
Unit
V
°C
Analog Characteristics and Power Dissipation
(operating voltage AVDD3.0V, DVDD 1.8V Temperature 25°C)
Parameter
Min
Typ.
Max.
Unit
Condition
DAC Resolution
10
bit
Integral Non-Linearity Error INL
+/- 0.6
+/- 2.0
LSB
Note 1)
Differential Non-Linearity Error DNL
+/- 0.4
+/- 1.0
LSB
Note 1)
Output Full Scale Voltage
1.15
1.28
1.41
V
Load Resistor 300Ω
DAC SNR
54
dB
Note 2)
Output Bandwidth
+/- 1
dB
Note 3)
Unbalances between DACs
1.5
3
%
Note 4)
Internal Reference Voltage
1.43
V
Internal Reference Drift
60
ppm/°C
Current Consumption of Analog part
30
40
mA
Note 5)
Current Consumption of Digital part
Component Encoder mode
35
70
mA
Note 6)
Composite Encoder mode
8
16
DAC mode
8
16
Current Consumption of Sleep mode
1
mA
Current Consumption of Power down
10
300
uA
PDN=Low
Note 1. DAC:148MHz Operation
Note 2. 2MHz Sin-wave input. (Noise Band-Width 0 – 30MHz)
Note 3. Output Bandwidth 30MHz: at 148MHz Operation DAC1 (Load Resistor 300ohm) Channel Only External Load
Capacitor 10 pF (SubAddress[0x0A] HDAFLT[1:0]=11)
Note 4. Variation when a 700 mV equivalent code is input on DACs.
Note 5. DAC 3ch ON fs=74MHz / Component mode (Y: 30MHz Sin wave, CbCr: 15MHz Sin wave)
Note 6: Clock-rate and Input data is
Composite Video Encoder mode: 515i (27MHz) Internal Color Bar
Component Video Encoder mode: 1080i (74Mhz) Y: 30MHz Sin wave, CbCr: 15MHz Sin wave)
High Speed DAC mode: 54MHz Clock 20MHz SIn wave Data input.
Rev-E-00
16
2008/03
[AK8825]
■
Digital Input / Output DC Characteristics
(AVDD=2.7-3.6V, DVDD=1.65-2.0V, PVDD1= 1.65-3.6V, PVDD2 = 1.65-3.6V Ta= -40-85°C)
Parameter
Symbol
MIN
TYP
MAX
unit
Condition
High Level Input Voltage 1
VIH1
0.70 PVDD1
V
Note. 1
High Level Input Voltage 2
VIH2
0.70 PVDD2
V
Note. 2
Low Level Input Voltage 1
VIL1
0.30 PVDD1
V
Note. 1
Low Level Input Voltage 2
VIL2
0.30 PVDD2
V
Note. 2
High Level Output Voltage
VOH
0.80 PVDD2
V
Note. 3 IOH = -600 uA
Low Level Output Voltage
VOL
0.20 PVDD2
V
Note. 3 IOL = 1.4 mA
Input pin Leakage Current
ILIKG
±10
uA
Note. 4
Note. 5
I2C High Level Input
VIHC
0.77PVDD1
V
Voltage
Note. 5
I2C Low Level Input
VILC
0.21PVDD1
V
Voltage
Note. 6
I2C Low Level Output
VOL2
0.4
V
IOLC=3mA
Voltage
Note. 1.
Note. 2.
Note. 3.
Note. 4.
Note. 5.
Note. 6.
Rev-E-00
PDN pin.
CLKIN, DATA[17:0], HDI, VDI pins
HDO, VDO pins
CLKIN, DATA[17:0], HDI, VDI, PDN, SELA, SDA, SCL pins
SELA, SDA, SCL pins
SDA pin
17
2008/03
[AK8825]
■
AC Timing
( AVDD=2.7-3.6V, DVDD=1.65-2.0V, PVDD1 = DVDD-3.6V, PVDD2 = DVDD-3.6V Ta: -40 -85°C)
(1) CLKIN
(1-1) Component Video Encoder / Composite Video Encoder mode
fCLK
tCLKL
VIH,VIL の 1/2 レベル
tCLKH
VIH
CLKIN
VIL
Fig. 8
parameter
CLKIN
Symbol
min
tCLKH
CLKIN Pulse Width L
tCLKL
max
74.25
27
fCLK
CLKIN Pulse Width H
Typ
unit
MHz
4.04
15.0
4.04
15.0
nsec
nsec
Note
74.25 / 74.175MHz
27MHz(*)
74.25/74.175MHz
27MHz
74.25 / 74.175MHz
27MHz
(*) Accuracy of frequency may affect to color display.
(1-2) Video DAC mode
parameter
CLKIN
CLKIN Pulse Width H
CLKIN Pulse WIdth L
Rev-E-00
Symbol
min
fCLK
tCLKH
tCLKL
6
7.4
7.4
18
typ
max
unit
54
MHz
nsec
nsec
Note
2008/03
[AK8825]
(2) Pixel Data Input Timing
VIH
VIL
CLKIN
tDH
tDS
DATA17-DATA0
HDI
VDI
Fig. 9
parameter
Symbol
min
typ
max
unit
Data Setup Time
tDS_HD
3.3
nsec
Data Hold Time
tDH_HD
3.3
nsec
Note) DATA17:DATA0, HDI, VDI can be captured inverted clock edge by resister setting
(3) HSYNC Pulse Width
pHSW
HDI
Fig. 10
parameter
HSYNC Pulse Width
Symbol
pHSW
min
typ
15
128
15
64
15
272
max
unit
Note
D1 Video 27MHz
CLKs
D2 Video 27MHz
D3, D4 Video 74.25MHz
(4) PDN Pulse Width
tPDN
PDN
Fig. 11
Parameter
PDN Pulse Width
Rev-E-00
Synbol
min
tPDN
100
19
typ
max
unit
備考
ns
2008/03
[AK8825]
(5) Power Up sequence
There are no order restriction to make power up, AVDD, DVDD, PVDD1, PVDD2.
Clock input is not necessary to write register.
(5-1) The sequence for power down mode after power-up.
Clock input to the CLKIN pin is necessary to guarantee “Current Consumption of Power down”
(r) : Register-bit
Power
Supply
AVDD:2.7V
DVDD:1.65V
PVDD:1.65V
t >100ns(Note.1)
PDN
CLKIN
DTRSTN (r)
PLLPDN (r)
CONVMOD[1:0] (r)
t >100clk
Low
0x00 (Composite Video Encoder mode)
Fig. 12 Power-Up sequence (To make Power down state after power-up)
Note.1) Please wait 100ns for make PDN pin low after the Voltage of Power Supply becomes stable enough,
Rev-E-00
20
2008/03
[AK8825]
(5-2) Setting to Composite Video Encoder mode after power-up
After initializing with PDN-pin = Low, AK8825 is Composite Video Encoder mode.
(r) : Register-bit
Power
Supply
AVDD:2.7V
DVDD:1.65V
PVDD:1.65V
t >100ns (1)
PDN
27MHz
CLKIN
PLLPDN (r)
CONVMOD[1:0] (r)
0x00
Register set (r)
DTRSTN (r)
t > 100clk (2)
t > 30ms
(3)
DACnEN (r)
DATA
Fig. 13 Power-Up sequence (To set Composite Video Encoder mode after power-up)
(1) PDN-pin should be Low states more than 100ns after power-up.
(2) To initialize in Composite Video Encoder Block. Clock input is ncessary to CLKIN-pin.
DTRSTN-bit should be 0 more than 100clock count.
(3) BT656 Interface mode operation, it is more than 1-Frame periode to synchronize with input
data. To avoid displaying noise etc, DAC should be ON after synchronization.
Rev-E-00
21
2008/03
[AK8825]
(5-3) Setting to Component Video Encoder mode after power-up
After initializing with PDN-pin = Low, AK8825 is Composite Video Encoder mode.
Set to Component Video Encoder mode by register setting. (Set CONVMOD[1:0]-bit =[01])
(r) Shows Register-bit
Power
Supply
AVDD:2.7V
DVDD:1.65V
PVDD:1.65V
t >100ns (1)
PDN
27MHz or 74.25MHz
CLKIN
t>100clk
PLLPDN (r)
CONVMOD[1:0] (r)
DTRSTN (r)
(2)
(3)
0x00
0x01
(4)
Register set (r)
31 ms
(5)
DACnEN (r)
t>30 ms
(6)
DATA
Fig. 14 Power-Up sequence (To set Component Video Encoder mode after power-up)
(1)
(2)
(3)
(4)
(5)(6)
Rev-E-00
PDN-pin should be Low states more than 100ns after power-up.
Set to Component Video Encoder mode after 100clock count with Clock Input to CLKIN-pin.
PLLPDN-bit should be set to High after setting Component Video Encoder mode.
DTRSTN-bit shoud be set to High after setting component Video Encoder mode.
After setting PLLPDN -bit = High, wait more than 31ms, then set DAC ON.
22
2008/03
[AK8825]
(5-4) Setting to High Speed Video DAC mode after power-up
After initializing with PDN-pin = Low, AK8825 is Composite Video Encoder mode.
Set to Component Video Encoder mode by register setting. (Set CONVMOD[1:0]-bit =[10])
(r) shows Register-bit
Power
Supply
t >100ns
AVDD:2.7V
DVDD:1.65V
PVDD:1.65V
(1)
PDN
54MHz (max)
CLKIN
t >100clk
PLLPDN (r)
CONVMOD[1:0] (r)
DTRSTN (r)
(2)
Low
0x00
0x10
(3)
Register set (r)
DACnEN (r)
DATA
Fig. 15 Power-Up sequence (To set High Speed Video DAC mode after power-up)
(1) PDN-pin should be Low states more than 100ns after power-up.
(2) Set to High Speed DAC mode after 100clock count with Clock Input to CLKIN-pin.
(3) Set to DTRSTN-bit should be High after setting High Speed Video DAC mode
Rev-E-00
23
2008/03
[AK8825]
(6) Power-Down Sequence and reset sequence after power-down release
Before setting to PDN=LOW, DTRSTN(r) should be Low to initialize.
After power-down release (PDN =LOW -> High), wait for 10ms for Analog Reference Voltage / Current becomes stable.
During PDN=Low (Power down States), either with clock-in or clock-not in is
During PDN = Low, AVDD / DVDD can be power-off.
Power down sequence is shown as Fig. 16. (r) means Register-bit.
PDN = Low makes AK8825 initialize condition, so that after power-down release, make sure register setting.
(6-1) Power-Down and power-down release Sequence from Composite Video Encoder mode
C LK IN
(27M H z)
F ix to Low or H igh
D A C nE N (r)
C O N V M O D [1:0](r)
D TR S TN (r)
0x00
R egister is initialized, it is
necessary to set regsiter again
t > 100clk
PDN
10m s
VREF
Fig. 16 Power-Down and power-down release Sequence from Composite Video Encoder mode
Rev-E-00
24
2008/03
[AK8825]
(6-2) Power-Down and power-down release Sequence from Component Video Encoder mode
C LK IN
27 or 74.25M H z
F ix to Low or H igh
D A C nE N (r)
P LLP D N (r)
C O N V M O D [1:0](r)
0x01
0x00
R egister is initialized, it is
necessary to set regsiter again
t > 100clk
D TR S TN (r)
PDN
10m s
VREF
Fig. 17 Power-Down and power-down release Sequence from Component Video Encoder mode
(6-3) Power-Down and power-down release Sequence from High Speed Video DAC mode
C LK IN
54M H z (m ax)
F ix to Low or H igh
D A C nE N (r)
C O N V M O D [1:0](r)
D TR S TN (r)
0x10
0x00
t >100clk
PDN
10m s
VREF
Fig. 18 Power-Down and power-down release Sequence from Component Video Encoder mode
Rev-E-00
25
2008/03
[AK8825]
2
(7) I C Timing
(7-1) Timing 1
tBUF
tHD:STA
tR
tSU:STO
tF
SDA
tF
tR
SCL
tSU:STA
tLOW
Fig. 19 I2C Timing 1
parameter
symbol
min
tBUF
1.3
usec
tHD:STA
0.6
usec
Clock Pulse Low Time
tLOW
1.3
usec
Input Signal Rise Time
tR
300
nsec
Input Signal Fall Time
tF
300
nsec
Bus Free Time
Hold Time (Start Condition)
max
unit
Setup Time(Start Condition)
tSU:STA
0.6
usec
Setup Time(Stop Condition)
tSU:STO
0.6
usec
The above I2C Bus related timings are I2C Bus specifications, and they are not the device limits.
For details, refer to I2C Bus Specifications.
(7-2) Timing 2
tHD:DAT
SDA
tHIGH
SCL
tSU:DAT
Fig. 20 I2C Timing 2
parameter
symbol
min
Data Setup Time
tSU:DAT
100 (note1)
Data Hold Time
tHD:DAT
0.0
tHIGH
0.6
Clock Pulse High Time
max
unit
nsec
0.9 (note2)
usec
usec
note 1 : when to use in I2C Bus Standard mode, tSU : DAT > = 250 nsec must be satisfied.
note 2 : when the AK8825 is used on not-extended tLOW Bus (used at tLOW = minimum specification),
this condition must be satisfied.
R/W operation to the register is possible without Clock input to CLKIN-pin.
Rev-E-00
26
2008/03
[AK8825]
6. Common Function Specification
This section describes common function specifications among Composite Video Encoder, Component Video Encoder, High
Speed Video DAC function Block.
■ Device Control Interface
The AK8825 is controlled via I2C Bus Control Interface.
[ I2C Bus Slave Address ]
I2C Slave Address is selectable to be either 0x40 or 0x42 by SELA pin setting.
SELA -pin
Low
(PVSS1)
High
(PVDD1)
A6
0
A5
1
SLAVE Address
0x40
0x42
A4
0
A3
0
A2
0
A1
0
A0
SELA
R/W
[ I2C Control Sequence ]
( 1 ) Write Sequence
When the Slave Address of the AK8825 Write mode is received at the first byte, Sub-Address at the second byte and Data at
the third & succeeding bytes are received.
There are 2 operations in Write sequence—
A sequence to write at every single byte, and a sequential write operation to write multiple bytes successively.
(a) Single byte Write sequence
Slave
Address
S
w
A
Sub
Address
1-
8-bits
1-
8-bits
bit
Data
A
bit
A
Stp
1-
8-bits
bit
(b) Multiple Byte ( m-bytes ) Write Sequence ( Sequential Write Operation )
Slave
Address
8-bits
S
w
A
1
Sub
Address(n)
8-bits
A
Data(n)
A
Data(n+1)
A
1
8-bits
1
8-bits
1
･･･
Data(n+m)
A
8-bits
1
stp
(2) Read Sequence
When the Slave Address of the AK8825 Read Mode is received at the first byte, data at the second and succeeding bytes are
transmitted from the AK8825.
S
Slave
Address
8-bits
w
A
Sub
Address(n)
A
1
8-bits
1
rS
Slave
Address
8-bits
R
A
Data1
A
Data2
A
Data3
A
1
8-bits
1
8-bits
1
8-bits
1
･･･
Data n
Ā
8-bits
1
stp
Abbreviated Terms listed above mean :
S, rS
A
Ā
Stp
R/W
: Start Condition
: Acknowledge ( SDA low )
: Not Acknowledged ( SDA high )
: Stop Condition
: 1 : Read, 0 : Write
: to be controlled by the Master Device. To be output by micro-computer normally.
: to be controlled by the Slave Device. To be output by the AK8825.
Note: At the MutipleByte Read/Write Sequence, read or write register operation cannot done at one-time.
Add[0x00] - Add[0x35] operation is done, then Add[0x36] - Add[0x3F] should be done.
To read or to write Test Register, 1 Byte Read/Write sequence should be done.
Rev-E-00
27
2008/03
[AK8825]
■
Mode Select
AK8825 has 3-function block as Composite Video Encoder, Component Video Encoder and High Speed Video DAC.These
functions are selected by CONVMOD[1:0]-bit of I/O Data Format Register (R/W) [Sub Address 0x0B].
At mode change timing, CONVMOD[1:0]-bit and DACnEN-bit of DAC Control Register(R/W) [Sub Address 0x0D] and
PLLPDN-bit of Powerdown Mode Register (R/W) [Sub Address 0x06] should be taken care.
I/O Data Format Register
Sub Address 0x0B
bit 7
bit 6
HDSDMASE
YC2RGB
bit 5
Reserved
CONVMOD[1:0]-bit
bit 4
DTFMT
bit 3
CONVMOD1
Mode
00
Composite Video Encoder mode
01
Component Video Encoder mode
10
High Speed Video DAC mode
11
Reserved
DAC Control Register
Sub Address 0x0D
bit 7
bit 6
Reserved
Reserved
bit 5
OLVL
bit 2
CONVMOD0
default Value 0x00
bit 1
bit 0
INPFMT1
INPFMT0
Note
Component Video Encoder Block becomes power
down state automatically.
PLL Block is still working, PLLPDN-bit can make
PLL block to power down state.
Composite Video Encoder Block becomes Power
down states automatically.
PLLPDN-bit should be set to “1” for this mode.
Composite/Component Video Encoder Block
become power down state automatically.
PLLPDN-bit should be set to “0” .
Reserve set
bit 4
DTRSTN
bit 3
CVBSSEL
bit 2
DAC3EN
default Value 0x00
bit 1
bit 0
DAC2EN
DAC1EN
Output signal from DAC1/2/3 with setting DACnEN-bit =1 (n=1,2,3)
CONVMOD[1:0]-bit
condition
00
01
CVBSSEL=0
CVBSSEL=1
DAC1 output
Y
CVBS
Y
DAC1EN=1
DAC2 output
C
Pb
In CVBSSEL=1 case, DAC2EN-bit
and DAC3EN-bit
should be set 0. (Output signal from DAC2, DAC3 is 0 )
DAC3 output
CVBS
Pr
Powerdown Mode Register
Sub Address 0x06
< HD Block >
bit 7
bit 6
bit 5
Reserved
Reserved
Reserved
bit 4
Reserved
bit 3
Reserved
bit 2
PLLPDN
Default Value 0x00
bit 1
bit 0
SLPEN1
SLPEN0
When setting to Component mode, PLLPDN-bit should be set to “1” since x2 PLL is necessary to work for Component Video
Encoder mode.
PLLPDN-bit
0
1
Rev-E-00
Operation
PLL is power down states
PLL is working.
Component Video Encoder mode, this bit should be set 1.
28
2008/03
[AK8825]
Mode switching sequence
(1) Component Video Encoder mode to Composite Video Encoder mode
Component Video Encoder mode
CONVMOD[1:0]-bit (r)
Composite Video Encoder mode
0x00
0x01
(6)
(7)
Register Setting (r)
(9)
DTRSTN-bit (r)
(2)
DACnEN-bit (r)
(4)
PLLPDN-bit (r)
HDBBG-bit (r)
(10)
PLL is Power Down State
(3)
(1)
t >30ms
Data Input
Low or High
Input
(5)
(8)
t >100clk
Input
Low or High
CLKIN
Fig. 21 Mode Switching sequence (Component Video Encoder mode to Composite Video Encoder mode)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
To avoid making noise, Black Burst Generator is On, then stop inputting data.
Turn Off DACs.
Black Burst Generator OFF.
Set PLLPDN-bit = 0 (PLL Block becomes Power Down States)
Stop Clock Input to CLKIN pin.
Mode Change from Componet VIdeo Encoder mode to Composite Video Encoder mode.
Set Sync-mode, Output Signal etc.
Chang clock, if necessary.
It is allows that changing clock without stopping clock input, however Process(6), (7) should
be done before clock change.
(9) Set DTRSTN=1 after DTRSTN-bit =0.
DTRSTN-bit =0 periode should be more than 100-clk counts with clock input.
(10) Turn On DACs after more than 30ms later
Rev-E-00
29
2008/03
[AK8825]
(2) Composite Video Encoder mode to Component Video Encoder mode
Composite Video Encoder mode
CONVMOD[1:0]-bit (r)
Component Video Encoder mode
0x01
0x00
(5)
(6)
Register Setting (r)
(2)
DACnEN-bit (r)
(10)
(8)
PLLPDN-bit (r)
SDBB-bit (r)
t > 1 ms
(1)
(3)
Low or High
Data Input
Input
(7)
(9)
t >30ms
Input
Low or High
(4)
CLKIN
Fig. 22 Mode Switching sequence (Composite Video Encoder mode to Component Video Encoder mode)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
To avoid making noise, Black Burst Generator is On, then stop inputting data.
Turns OFF DACs.
Black Burst Generator OFF.
Stop Clock Input to CLKIN pin.
Mode Change from Composite Video Encoder mode to Component Video Encoder mode.
Set Sync-mode, Output Signal etc.
Chang clock, if necessary.
It is allows that changing clock without stopping clock input, however Process (6), (7) should
Be done before clock change.
(8) After Input Clock becomes stable, Internal PLL makes power-up. (PLLPDN-bit =1)
(9) After PLL becomes stable, starting input video data.
(10) Turn ON DACs after more than 30ms later
Rev-E-00
30
2008/03
[AK8825]
(3) Clock rate change in Component Video Encoder mode
Fig.23 shows the sequence of Clock rate is changed from 27MHz to 74.25MHz or 74.25MHz to 27MHz.
27MHz / 74.25MHz mode
74.25MHz / 27MHz mode
(5)
HDMOD[1:0]-bit (r)
D1 or D2 / D3 or D4
D3 or D4 / D1 or D2
(2)
DACnEN-bit (r)
(9)
(4)
PLLPDN-bit (r)
(1)
(7)
(3)
t>1Frm
HDBB-bit (r)
t > 1ms
Data input
Low or High
Input
(8)
CLKIN
27MHz / 74.25MHz
Fig. 23
Low or High
(6)
Input
74.25MHz / 27MHz
Clock rate change in Component Video Encoder mode
(1)
(2)
(3)
(4)
(5)
(6)
To avoid making noise, Black Burst Generator is On, then stop inputting data.
Turns Off DACs
Black Burst Generator OFF.
Set PLLPDN-bit = 0 (PLL Block becomes Power Down States)
Mode Change, for example, from D1 to D3.
Chang clock
It is allows that changing clock without stopping clock input, however, PLLPDN-bit should be 0.
(7) Turning on PLL (Set PLLPDN-bit = 1)
(8) After PLL becomes stable, starting input video data.
(9) Turn ON DACs after more than 30ms later
Rev-E-00
31
2008/03
[AK8825]
■ Clock
Input Clock is determined by output signal. The relation between input Clock and the output signal is defined as following table.
Input Clock
NTSC/PAL
Component Video Encoder
Composite Video Encoder
mode
High Speed Video DAC mode
mode
D1, D2
D3, D4
Input Clock to CLKIN pin
27MHz
27MHz
74.25MHz
54MHz (max)
DAC operation clock rate
27MHz
54MHz
148.5MHz
Clock to CLKIN pin
Internal PLL status
OFF
ON
ON
OFF
D1 = 480i/576i(525i/625i), D2 = 480p/576p (525p/625p), D3 = 1080i (1125i), D4 = 720p (750p)
In case of switching clock, PLLPDN-bit of Powerdown Mode Register (R/W) [Sub Address 0x06] should be “0”.
■
Internal PLL
AK8825 has x2 PLL.
In case of Component Video Encoder mode, PLL should be on.
In time to switch clock rate, PLLPDN-bit should be “0”.
Powerdown Mode Register
Sub Address 0x06
< HD Block >
bit 7
bit 6
bit 5
Reserved
Reserved
Reserved
PLLPDN
0
1
bit 4
Reserved
bit 3
Reserved
bit 2
PLLPDN
Default Value 0x00
bit 1
bit 0
SLPEN1
SLPEN0
Function
PLL is Power Down
PLL is working.
Set PLLPDN=1, in case of Component Video Encoder mode.
■ Reset
(1) Component Video Encoder Block and High Speed DAC Block, and Serial Interface Block are reset with making
PDN-pin = Low. It is not necessary to input clock to CLKIN pin.
(2) Composite Video Encoder Block.
Composite Video Encoder Block is reset under the condition of DTRSTN-bit =”0” of DAC Control Register(R/W) [Sub
Address 0x0D] with clock input to CLKIN-pin. It should be keep DTSTN-bit = “0” at least 100 clock count.
DAC Control Register
Sub Address 0x0D
bit 7
bit 6
Reserved
Reserved
bit 5
OLVL
bit 3
CVBSSEL
bit 4
DTRSTN
bit 2
DAC3EN
default Value 0x00
bit 1
bit 0
DAC2EN
DAC1EN
After Reset all register values become default value, and Video DAC output pins become Hi-z.
Rev-E-00
32
2008/03
[AK8825]
■
Power Down
It is possible to make AK8825 power down states with PDN-pin = Low. Power down sequence is defined section (6)
Power-Down Sequence and reset sequence after power-down release of AC Timing definition.
After releasing PDN-Pin =Low, all register values become default values, It is necessary to set the register again.
During PDN pin =Low, AVDD and DVDD can be power-off with PVDD1and PVDD2=ON.
■
Sleep Mode
To set SLPEN[1:0]-bit of Powerdown Mode Register (R/W) [Sub Address 0x06] =[11], AK8825 becomes sleep mode. In
this mode, all blocks except serial I/F block become power down mode. To save power consumption much less, use the
PDN-pin.
Sub Address 0x06
< HD Block >
bit 7
bit 6
bit 5
Reserved
Reserved
Reserved
Rev-E-00
bit 4
Reserved
bit 3
Reserved
33
bit 2
PLLPDN
Default Value 0x00
bit 1
bit 0
SLPEN1
SLPEN0
2008/03
[AK8825]
■
Data Input Format
AK8825 supports 4 kinds of Data Input Format such as 8-bit YCbCr / 16-bit YCbCr / 18bit RGB / 16-bit RGB formats.
Data Input Format can be defined by INPFMT[1:0]-bit and DTFMT-bit of I/O Data Format Register (R/W).
I/O Data Format Register
Sub Address 0x0B
bit 7
bit 6
HDSDMASE
YC2RGB
bit 5
Reserved
bit 4
DTFMT
bit 3
CONVMOD1
bit 2
CONVMOD0
default Value 0x00
bit 1
bit 0
INPFMT1
INPFMT0
INPFMT[1:0] -bits defines bit width. Detailed setting is shown in following table
INPFMT[1:0]-bit
Input Data Format (width)
Note
00
8-bit Data input
01
16-bit Data Input
10
18-bit Data Input
High Speed DAC mode only
11
Reserve
DTFMT -bit defines Data format.
DTFMT -bit
Input Data Format
0
YCbCr Data format
RGB Data Format
1
In case of CONVMOD[1:0]=[00] or [01], internal RGB to YCbCr convertor
works*
* In case of RGB Input mode, AK8825 doesn’t support Rec.656 I/F mode.
* 525i/625i/525P/625P composite, component encode only.
CONVMOD[1:0] -bits define encoder mode show as following table.
CONVMOD[1:0] -bit
mode
00
Composite Video Encoder mode
01
Component Video Encoder mode
10
High Speed DAC mode
11
Prohibited to set
INPFMT[1:0] -bit
DTFMT-bit
CONVMOD[1:0] -bit
YCbCr
DATA
DATA
Formatter
MUX
RGB
to
YCbCr
Composite
Video Encoder
Y
MUX
Cb/Cr
Decimation
Filter
Cb/Cr
Composite
Video Encoder
Video DAC
Mode
RGB
Fig. 24 Data Interface block outline
Rev-E-00
34
2008/03
[AK8825]
(1) YCbCr 8bit Data Input Format
In case of 525i / 625i Data Input, this forma is used. Data clock is 27MHz.
DATA7-DATA0 pins are used as Data Input pins. The order of YCbCr data should be fed Cb[7:0] / Y[7:0] / Cr[7:0] / Y[7:0].
Yn / Cbn / Crn means Y[n] / Cb[n] / Cr[n] in following table.
D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0
Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0
D17 - D0 corresponds to DATA17 - DATA0 pins
The Register setting is defined as following table.
[I/O Data Fromat Register] Setting
INPFMT[1:0]-bit
DTFMT-bit
00
0
Note
8bit YCbCr Data Input
Output signal is set CONVMOD[1:0]-bit of I/O Data Format Register (R/W) [Sub Address 0x0B] and HD Mode Register
(R/W) [Sub Address 0x00] or SD Block Control Register (R/W) [Sub Address 0x11]
CLKIN
(27MHz)
DATA[7:0]
Cb
Y
･･･ ･･･ Cbn Y2n
Crn Y2n+1 Cbn+1 Y2n+2 Crn+1 Y2n+3 Cbn+2 Y2n+4 Crn+2 ･･･ ･･･
Fig. 25
Rev-E-00
35
2008/03
[AK8825]
(2) YCbCr 16bit Data Input Format
In case of 525i / 625i / 525P / 625P / 1080i / 720P Data input, this format is used.
The relation between input data format and Input clock rate to CLKIN pin are relation as follows,
525i / 625i / 525p / 625p : 27MHz
1080i / 720p / : 74.25MHz
DATA15-DATA0 pins are used as Data Input pins.
Yn / Cbn / Crn means Y[n] / Cb[n] / Cr[n] in following table.
D17 D16 D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
Cb7
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
Y7
Y6
Y5
Cr7
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
D17 - D0 corresponds to DATA17 - DATA0 pins
The Register setting is defined as following table.
[I/O Data Fromat Register] Setting
INPFMT[1:0]-bit
DTFMT-bit
01
0
D4
D3
D2
D1
D0
Y4
Y3
Y2
Y1
Y0
Note
16bit YCbCr Data Input
Output signal is set CONVMOD[1:0]-bit of I/O Data Format Register (R/W) [Sub Address 0x0B] and HD Mode Register
(R/W) [Sub Address 0x00] or SD Block Control Register (R/W) [Sub Address 0x11]
(2-1) 525i / 625i Data input
CLKIN
(27MHz)
Data[7:0]
Y0
Y1
Y2
Y3
･･･
Y2n
Y2n+1
Data[15:8]
Cb0
Cr0
Cb1
Cr1
･･･
Cbn
Crn
Y2n+2
Cbn+1
･･･
･･･
Fig. 26
(2-2) 525P / 625P / 1080i / 720P Data input
CLKIN
(27 or 74.25MHz)
Data[7:0]
Y0
Y1
Y2
Y3
･･･ ･･･ ･･･ ･･･
Data[15:8]
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Y2n Y2n+1 Y2n+2 Y2n+3 Y2n+4 Y2n+5 ･･･ ･･･ ･･･
･･･ ･･･ Cbn
Crn Cbn+1 Crn+1 Cbn+2 Crn+2 ･･･
･･･ ･･･
Fig. 27
Rev-E-00
36
2008/03
[AK8825]
(3) RGB 8bit Data Input Format (RGB5:6:5)
In case of to encode NTSC/PAL composite Video signal or YPbPr component Video signal from RGB data, this mode is used.
Clock rate to CLKIN pin is 27MHz.
DATA7-DATA0 pins are used as Data Input pins. Input data format is RG[7:0] / GB[7:0] shown as following table.
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
-
-
-
-
-
-
-
-
-
-
D7
R4
G2
D6
R3
G1
D5
R2
G0
D4
R1
B4
D3
R0
B3
D2
G5
B2
D1
G4
B1
D0
G3
B0
D17 - D0 corresponds to DATA17 - DATA0 pins
RG Data = [ R4, R3, R2, R1, R0, G5, G4, G3 ]
GB Data = [ G2, G1, G0, B4, B3, B2, B1, B0 ]
The Register setting is defined as following table.
[I/O Data Fromat Register] Setting
INPFMT[1:0]-bit
DTFMT-bit
00
1
Note
8bit RGB Data Input
Output signal is set CONVMOD[1:0]-bit of I/O Data Format Register (R/W) [Sub Address 0x0B] and HD Mode Register
(R/W) [Sub Address 0x00] or SD Block Control Register (R/W) [Sub Address 0x11]
CLKIN
(27MHz)
DATA[7:0]
RG0 GB0 RG1 GB1
…
…
RGn GBn RGn+1 GBn+1 ･･･
･･･ ･･･ ･･･ ･･･ ･･･ ･･･
Fig. 28
Rev-E-00
37
2008/03
[AK8825]
(4) RGB 16bit Data Input Format (RGB 5:6:5)
In case of encoding NTSC/PAL / 525i/625i , 525p/625p component signal, Clock rate to CLKIN pin 27MHz..
Using as High Speed DAC mode, the maximum conversion rate is 54MHz.
DATA15 - DATA0 pins are used as Data Input pins.
D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
The Register setting is defined as following table.
[I/O Data Fromat Register] Setting
INPFMT[1:0]-bit
DTFMT-bit
01
1
D1
B1
D0
B0
Note
16bit RGB Input
Output signal is set CONVMOD[1:0]-bit of I/O Data Format Register (R/W) [Sub Address 0x0B] and HD Mode Register
(R/W) [Sub Address 0x00] or SD Block Control Register (R/W) [Sub Address 0x11]
(4-1) 525i / 625i data input case
CLKIN
(27MHz)
Data[4:0]
B0
B0
B1
B1
B2
B2
･･･ ･･･
Bn
Bn
Bn+1 Bn+1 Bn+2 Bn+2 ･･･ ･･･ ･･･
Data[10:5]
G0
G0
G1
G1
G2
G2
･･･ ･･･
Gn
Gn
Gn+1 Gn+1 Gn+2 Gn+2 ･･･
･･･ ･･･
Data[15:11]
R0
R0
R1
R1
R2
R2
･･･ ･･･
Rn
Rn
Rn+1 Rn+1 Rn+2 Rn+2 ･･･
･･･ ･･･
Fig. 29
(4-2) 525P / 625P data input case
CLKIN
(27MHz)
Data[4:0]
B0
B1
B2
B3
･･･ ･･･ ･･･ ･･･
Bn
Bn+1 Bn+2 Bn+3 Bn+4 Bn+5 ･･･ ･･･ ･･･
Data[10:5]
G0
G1
G2
G3
･･･ ･･･ ･･･ ･･･
Gn
Gn+1 Gn+2 Gn+3 Gn+4 Gn+5 ･･･
Data[15:11]
R0
R0
R1
R1
･･･ ･･･ ･･･ ･･･
Rn
Rn+1 Rn+2 Rn+3 Rn+4 Rn+5
･･･ ･･･
･･･ ･･･ ･･･
Fig. 30
Rev-E-00
38
2008/03
[AK8825]
(5) RGB 18bit Data Input Format (RGB 6:6:6）
In case of encoding NTSC/PAL / 525i/625i , 525p/625p component signal, Clock rate to CLKIN pin 27MHz..
Using as High Speed DAC mode, the maximum conversion rate is 54MHz.
DATA17 - DATA0 pins are used as Data Input pins.
D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
The Register setting is defined as following table.
[I/O Data Fromat Register] Setting
INPFMT[1:0]-bit
DTFMT-bit
10
1
D1
B1
D0
B0
Note
18bit RGB Input
Output signal is set CONVMOD[1:0]-bit of I/O Data Format Register (R/W) [Sub Address 0x0B] and HD Mode Register
(R/W) [Sub Address 0x00] or SD Block Control Register (R/W) [Sub Address 0x11]
(5-1) 525i / 625i data input case
CLKIN
(27MHz)
Data[5:0]
B0
B0
B1
B1
B2
B2
･･･ ･･･
Bn
Bn
Bn+1 Bn+1 Bn+2 Bn+2 ･･･ ･･･ ･･･
Data[11:6]
G0
G0
G1
G1
G2
G2
･･･ ･･･
Gn
Gn
Gn+1 Gn+1 Gn+2 Gn+2 ･･･
Data[17:12]
R0
R0
R1
R1
R2
R2
･･･ ･･･
Rn
Rn
Rn+1 Rn+1 Rn+2 Rn+2
･･･ ･･･
･･･ ･･･ ･･･
Fig. 31
(5-2) 525P / 625P data input case
CLKIN
(27MHz)
Data[5:0]
B0
B1
B2
B3
･･･ ･･･ ･･･ ･･･
Bn
Bn+1 Bn+2 Bn+3 Bn+4 Bn+5 ･･･ ･･･ ･･･
Data[11:6]
G0
G1
G2
G3
G4
G5
･･･ ･･･
Gn
Gn+1 Gn+2 Gn+3 Gn+4 Gn+5 ･･･
Data[17:12]
R0
R1
R2
R3
R4
R5
･･･ ･･･
Rn
Rn+1 Rn+2 Rn+3 Rn+4 Rn+5
･･･ ･･･
･･･ ･･･ ･･･
Fig. 32
Rev-E-00
39
2008/03
[AK8825]
■
On chip out-put limiter
Limiter function is performed on signals which exceed Pedestal Level.
Limiter Levels are set at “no limiter”, “- 1.5IRE”, “- 7IRE”.
The limit level is set with HDCLPLVL[1:0]-bit of HD VBI & Clip Level Control Register (R/W) [Sub Address 0x01] in
Component Video Encoder mode and SDCLPLVL[1:0]-bit of SD Block Delay Register (R/W) [Sub Address 0x13] in Composite
Video Encoder mode.
HD VBI & Clip Level Control Register
Sub Address 0x01
bit 5
bit 7
bit 6
Reserved
HDCLPLVL1 HDCLPLVL0
SD Block Delay Register
Sub Address 0x13
bit 7
bit 6
SDCLPLVL1 SDCLPLVL0
bit 5
SYD2
bit 4
Reserved
bit 3
Reserved
bit 2
HDVUNMSK
bit 4
SYD1
bit 3
SYD0
bit 2
Reserved
bit 1
HDVL1
default Value 0x04
bit 0
HDVL0
default Value 0x00
bit 1
bit 0
Reserved
Reserved
The Limit level defined as this table.
HDCLPLVL[1:0]-bit
Under-shoot Limit Level
SDCLPLVL[1:0]-bit
00
no Clipping
01
Clipped at -7.0 IRE Level
10
Clipped at -1.5 IRE Level
11
Reserved
■
Black Burst Signal Generation Function
The AK8825can output Black Burst Signal (Black Level Output).
When HDBBG-bit of HD Mode Register (R/W) [Sub Address 0x00] in Component Video Encoder mode, SDBBG-bit of
SD Block Control Register (R/W) [Sub Address 0x11] is set to “1”, same operation is processed as in the case when the
fixed-16 Luminance signal and the fixed-Cb/Cr signal outputs are input. In this case when setup-bit is “ON”, set-up process is
done and when it is “OFF”, no set-up process is made.
HD Mode Register
Sub Address 0x00
bit 7
bit 6
HDCBG
HDBBG
bit 5
HDSETUP
bit 4
HDEAVDEC
bit 3
HDCEA861
bit 2
HDMODE1
default Value 0x00
bit 1
bit 0
HDMODE0
HDRFRSH
SD Block Control Register
Sub Address 0x11
bit 6
bit 7
SDCBG
SDBBG
bit 5
SDSETUP
bit 4
SCR
bit 3
SDVM3
bit 2
SDVM2
Default Value 0x10
bit 1
bit 0
SDVM1
SDVM0
Rev-E-00
40
2008/03
[AK8825]
■
Color Bar Signal Generation Function
The AK8825 can output 100% Color Bar Signal. Color Bar Signal is output by setting HDCBG-bit of HD Mode Register (R/W)
[Sub Address 0x00] in Component Video Encoder mode and SDCBG-bit of SD Block Control Register (R/W) [Sub Address
0x11] in Composite Video Encoder mode to “1”.
HD Mode Register
Sub Address 0x00
bit 7
bit 6
HDCBG
HDBBG
bit 5
HDSETUP
bit 4
HDEAVDEC
bit 3
HDCEA861
bit 2
HDMODE1
default Value 0x00
bit 1
bit 0
HDMODE0
HDRFRSH
SD Block Control Register
Sub Address 0x11
bit 7
bit 6
SDBBG
SDCBG
bit 5
SDSETUP
bit 4
SCR
bit 3
SDVM3
bit 2
SDVM2
Default Value 0x10
bit 1
bit 0
SDVM1
SDVM0
■
Setup Process Function
In the AK8825, a 7.5% set-up can be added by Register.
In Component Video Encoder mode, HDSETUP-bit of HD Mode Register (R/W) [Sub Address 0x00] is the control bit of this
function and , in composite Video Encoder mode, SDSETUP-bit of SD Block Control Register (R/W) [Sub Address 0x11] is the
control bit of this function
This bit is enabled at Color-bar Generator mode and Black Burst Generator mode.
HD Mode Register
Sub Address 0x00
bit 7
bit 6
HDCBG
HDBBG
bit 5
HDSETUP
bit 4
HDEAVDEC
bit 3
HDCEA861
bit 2
HDMODE1
default Value 0x00
bit 1
bit 0
HDMODE0
HDRFRSH
SD Block Control Register
Sub Address 0x11
bit 7
bit 6
SDBBG
SDCBG
bit 5
SDSETUP
bit 4
SCR
bit 3
SDVM3
bit 2
SDVM2
Default Value 0x10
bit 1
bit 0
SDVM1
SDVM0
Rev-E-00
41
2008/03
[AK8825]
■
Closed Caption
The AK8825 has encoding function of the Closed Captioning and Extended Data.
ON/OFF control of these functions and its data are in accordance with SD/HD V-Blanking Control Register (R/W) [Sub
Address 0x12] setting. Data occupies a consecutive 2Byte Register area
Closed Caption Data 1 Register (R/W) [Sub Address 0x26]
Closed Caption Data 2 Register (R/W) [Sub Address 0x27]
for Closed Caption data and
CC Extended Data 1 Register (R/W) [Sub Address 0x28]
CC Extended Data 2 Register (R/W) [Sub Address 0x29]
for Extended data.
Data is written at 0x26/0x28(closed caption / extended data) first, then 0x27/0x29 in this order
Data is judged to be updated when data at 0x27 is written.
When data is updated, it is encoded on a coming thereafter, pre-scribed Line.
When no data updating is made, ASCII Null code is output.
Each data is assumed with ODD parity + 7 bit US ASCII code. Parity is processed at the Host side.
* Closed Caption Data is encoded on the following Lines.
D1/60 System (SMPTE)
Closed Caption
21 Line default
Extended Data
284 Line default
625/50 System (ITU-R)
22 Line default
335 Line default
RGB output mode doesn’t support closed caption encoding function.
240+/- 48nsec
10.5 +/- 0.25usec
12.91 usec
240+/- 48nsec
Two 7-bit + PARITY ASCII
Characters Data
D0-D6
PARITY
D0-D6
PARITY
START
50 +/- 2 IRE
40IRE
10.003 +/- 0.25usec
27.382 usec
33.764 usec
61 usec
Fig. 33
Rev-E-00
42
2008/03
[AK8825]
■
WSS
The AK8825 supports to encode WSS (ITU-R. Bt1119), IEC62375 which distinguish the Aspect Ratio etc. Turning “ON/OFF”
of this function is controlled by WSSEN-bit of SD/HD V-Blanking Control Register (R/W) [Sub Address 0x12] at Composite
Video Encoder mode, HDWSS-bit of HD Block Control Register (R/W)[Sub Address 0x07].
Setting data is set to SD WSS Data 1/2 Register(R/W) [Sub Address 0x18 / 0x19] at composite Video Encoder mode, and HD
WSS Data 1/2 Register (R/W) [Sub Address 0x08/0x09] at Component Video Encoder mode.
SD/HD V-Blanking Control Register
Sub Address 0x12
bit 7
bit 6
bit 5
Reserved
Reserved
Reserved
HD Block Control Register
Sub Address 0x07
bit 7
bit 6
HDWSS
HDCFLT1
bit 5
HDCFLT0
bit 4
Reserved
bit 3
SDWSS
bit 4
HDYFLT1
bit 3
HDYFLT0
bit 2
SDHDCC284
bit 2
Reserved
Default Value 0x00
bit 1
bit 0
SDHDCC21
SDVBID
bit 1
COLSNCEN
default Value 0x00
bit 0
HDVRATIO
WSS Data Up-date Timing
VSYNC
Set Control Register
2
I C SDA
DATA
WSS Data1
WSS Data2
OLD DATA
NEW DATA
Fig. 34
WSS Data1: Composite Video Encoder mode SubAddress 0x18 / Component Video Encoder mode 0x08
WSS Data2: Composite Video Encoder mode SubAddress 0x19 / Component Video Encoder mode 0x09
Rev-E-00
43
2008/03
[AK8825]
WSS Waveform
500mV +/- 5%
0H
d [us]
a [us]
b [us]
c [us]
e [us]
44.5 [us] (defined only 625i)
Fig. 35
Encode
Line
625i /50Hz
(ITU-R.Bt.1119)
625p /50Hz
(IEC 62375)
23
43
Encode
Clock
5MHz
(Ts=200ns)
10MHz +/- 1kHz
(Ts = 100ns)
c
d
e
11.0 +/- 0.25
27.4
38.4
5.5 +/- 0.125
13.7
19.2
Encode Line: 625i/50 23-Line / 625p/50 43-Line
The input video data is not encoded on the WSS encoded line.
Coding: bi-phase modulation coding
Run-in
Start code
29 elements
24 elements
Group 1
Aspect ratio
24 elements
Bit numbering
0
1
2
Group 2
Enhanced Services
24 elements
Bit numbering
3
4
LSB
MSB
0 : 000111
1 : 111000
0x1F1C71C7
Rev-E-00
5
6
7
LSB
MSB
0 : 000111
1 : 111000
Group 3
Subtitles
18 elements
Bit numbering
8
9
10
LSB
MSB
0 : 000111
1 : 111000
Group4
Others
18 elements
Bit numbering
11
12
13
LSB
MSB
0 : 000111
1 : 111000
0x1E3C1F
44
2008/03
[AK8825]
■ Video DAC
The AK8825 has 10-bit resolution, discrete 3 channel current DACs which run at 150MHz.
These DACs are designed to output 1.28Vo-p Full Scale with load resistors of 300-ohm(+/-1.0%) when a
3.9k-ohm(+/-1.0%)resistor is connected between IREF pin and AVSS.
VREF pin should be connected to AVDD via 0.1uF ore more capacitor, and BYPASS pin should be connected to AVSS via
0.1uF or more capacitor. ( Refer to System Connection example. )
Each DAC’s “ON/OFF” can be individually controlled by DACnEN-bit (n=1,2,3) of DAC Control Register [SubAddress0x0D].
At the time of DAC-OFF state, the output DAC is Hi-z.
DAC Control Register
Sub Address 0x0D
bit 7
bit 6
Reserved
Reserved
bit 5
OLVL
bit 4
DTRSTN
bit 3
CVBSSEL
bit 2
DAC3EN
default Value 0x00
bit 1
bit 0
DAC2EN
DAC1EN
The relation between DACnEN-bit (n=1,2,3) and DAC output are shown in following table.
DAC1EN -bit
DAC2EN -bit
DAC3EN -bit
0
1
0
1
0
1
DAC1=OFF
DAC1=ON
DAC2=OFF
DAC2=ON
DAC3=OFF
DAC3=ON
■
DAC Setting
CVBSSEL-bit of DAC Control Register(R/W) [Sub Address 0x0D] sets the output signal from DAC1 and DAC3. Following
table shows the output signal and CVBSEL-bit.
DAC Control Register
Sub Address 0x0D
bit 7
bit 6
Reserved
Reserved
bit 5
OLVL
bit 4
DTRSTN
bit 3
CVBSSEL
bit 2
DAC3EN
SD-YC output
SD-CVBS output
HD output
CONVMOD[1:0]=00
CONVMOD[1:0]=00
CONVMOD[1:0]=01
CVBSSEL-bit
0
1
0
DAC1
Y
CVBS
Y
DAC2
C
0-code output
Pb
DAC3
CVBS
0-code output
Pr
HD output: Output signal from Component Video Encoder Block
SD-YC output and SD-CVBS output: Output signal from Composite Video Encoder Block
The operation clock of DACs is
Composite Video Encoder mode:
Component Video Encoder mode:
High Speed Video DAC mode:
Rev-E-00
default Value 0x00
bit 1
bit 0
DAC2EN
DAC1EN
Video DAC mode
CONVMOD[1:0]=10
G
B
R
Same clock-rate as the clock fed into CLKIN-pin.
x2 clock rate of the clock fed into CLKIN-pin
Same clock-rate as the clock fed into CLKIN-pin.
45
2008/03
[AK8825]
7.
■
Multi-Fomat Compnent Video Encoder Block
Block Diagram
From
Timing
Generator
HD-Timing
Generator
CLK Rate C
CGMS-A
WSS
Y[7:0
sin(x)/x
x2
x2
Compensation
LPF-D
LPF-G*
SYNC
Generator
Y[9:0]
to DAC
CLK Rate B
*CLK Rate D
Cb[7:0]
Cr[7:0]
4:2:2
to
4:4:4
x2 Interpolation
CLK Rate A
From
Clock Gen
LPF-E
x2
x2
LPF-F
LPF-H*
Pb[9:0]
to DAC
Pr[9:0]
to DAC
CLK Rate B
6.75MHz/13.5/27/54/74.25/148.5MHz
Fig. 36 Component Video Encoder Block
Rev-E-00
46
2008/03
[AK8825]
■
Signal Process (Data Path)
The output signal can be set with HDRFRSH-bit, HDMODE[1:0]-bit of HD Mode Register [Sub Address 0x00].
Sub Address 0x00
bit 7
bit 6
HDCBG
HDBBG
bit 5
HDSETUP
bit 4
HDEAVDEC
The output signals are defined as following table.
Output signal
HDMODE[1:0] -bit
HDRFRSH -bit
525i
00
0
625i
00
1
525p
01
0
625p
01
1
1080i / 60
10
0
1080i / 50
10
1
720p / 60
11
0
720p / 50
11
1
Rev-E-00
bit 3
HDCEA861
bit 2
HDMODE1
default Value 0x00
bit 1
bit 0
HDMODE0
HDRFRSH
Note
D1/60
D1/50
D2/60
D2/50
D3/60
D3/50
D4/60
D4/50
47
2008/03
[AK8825]
(1) Case of 525i /625i Data Input
Y/Cb/Cr multiplexed data synchronized to 27MHz clock fed into CLKIN-pin are input.
When EAV-Decoding mode, the timing signal is extracted from data stream. After extracting sync-timing, the Y/Cb/Cr data are
proceeded into Y-process block and Cb/Cr -process block. In case of H/V Slave operation mode, it is same way as EAV sync
mode.
As shown in the block diagram,
Y data proceeded by x4 over-sampling filter is added the Sync-timing signal after pass through the delay adjustment block.
Cb/Cr data proceeded by x8 over-sampling filter are processed by delay adjustment block. These data are passed to the DAC
with 54MHz Clock rate.
Synchronization Timing
SYNC Form
YData[9:0]
8-bit or 16-bit
Cb/Y/Cr
EAV
Decoder
DEMUX
Level
Conversion
MUX
x2
Interpolation
LPF-D
x2
Interpolation
LPF-G
x2
Interpolation
LPF-F
x2
Interpolation
LPF-H
Delay
CBData[9:0]
4:2:2
to
4:4:4
CRData[9:0]
Interpolation
LPF-E
DAC
Delay
DAC
Delay
DAC
27MHz
13.5MHz
Input Formatter
27MHz
54MHz
Synchronization Mode
Fig. 37 525i/625i mode Block Diagram
x4 Over-sampling Filter for Y-data (Luminance Data)
10
0
0.0
2.0
4.0
6.0
8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0
0.200
0.000
-20
0.00 0.75 1.50 2.25 3.00 3.75 4.50 5.25 6.00 6.75
-0.200
-30
Gain[dB}
Gain[dB]
-10
-0.400
-40
-0.600
-50
-0.800
-60
-1.000
Frequency[MHz]
Fig. 38
Frequncy[MHz]
Fig. 39
x8 Over-Sampling Filter for Cb/Cr-Data (Color Data)
10
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0 11.0 12.0 13.0
-10
Gain[dB]
-20
-30
-40
-50
-60
Frequency[MHz]
Fig. 40
Rev-E-00
48
2008/03
[AK8825]
(2) Case of 525P/625P Data Input
Y/Cb/Cr data should be input with 16-bit width at 27MHz clock-rate.
x2 Over-sampling filter for Y-data and x4 Over-sampling filter for Cb/Cr data is equipped.
The block diagram is shown as follows,
Synchronization Timing
SYNC Form
Y
8-bit
EAV
Decoder
Y
MUX
8-bit
sin(x)/x
Compensation
x2
Interpolation
LPF-D
4:2:2
to
4:4:4
Interpolation
LPF-E
x2
Interpolation
LPF-F
Y [9:0]
Cb/Cr
Y
DEMUX
Level
Conversion
Cb/Cr
CB [9:0]
CR [9:0]
Cb/Cr
27MHz
Input Formatter
13.5MHz
27MHz
Delay
DAC
Delay
DAC
Delay
DAC
54MHz
Synchronization Mode
Fig. 41 525P/625P mode Block Diagram
Rev-E-00
49
2008/03
[AK8825]
Over-sampling filter with aperture-effect compensation for Luminance (525P/625P)
AK8825 equips the aperture-effect compensation filter for Luminance Signal.
This filter can be set with HDAFT[1:0]-bit of HD Block Miscellaneous Control Register [Sub Address 0x0A].
Compensation degree can be set with this register-bit. “Mode 0” is less compensation and “Mode 3” is more compensation.
HD Block Miscellaneous Control Register
Sub Address 0x0A
bit 7
bit 6
bit 5
Reserved
Reserved
STD770_2C
0
0
HDAFLT[1:0]-bit
00
01
10
11
0
Filter mode
MODE0
MODE1
MODE2
MODE3
bit 4
bit 3
HDCEA805B CCWSSSUE
Default Value
0
0
default Value 0x00
bit 1
bit 0
HDAFLT1
HDAFLT0
bit 2
Reserved
0
0
0
Note
less
more
x2 Over-sampling Filter for Y-data
10
3
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
2
1
-20
Gain[dB]
Gain[dB]
-10
Aperteu Filter
-30
-40
0
-1 0
5
10
MODE3
-2
MODE2
-3
-50
-4
-60
-5
MODE1
MODE0
Frequency[MHz]
Frequency[MHz]
Fig. 42 Aperture Filter
Fig. 43 x2 Over-sampling filter for 525p/625p
x4 Over-sampling Filter for Cb/Cr
10
0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
G ain[dB]
-10
-20
-30
-40
-50
-60
Frequency[MHz]
Fig. 44 x4 Over-sampling filter for 525p/625p
Rev-E-00
50
2008/03
[AK8825]
(3) Case of 1125i (1080i) 750P(720P) data input
Y/Cb/Cr data should be input with 16-bit width at 74.25MHz clock-rate.
x2 Over-sampling filter for Y-data and x4 Over-sampling filter for Cb/Cr data is equipped.
The block diagram is shown as follows,
Synchronization Timing
SYNC Form
Y
8-bit
EAV
Decoder
Y
MUX
8-bit
sin(x)/x
x2
Compensation
Interpolation
4:2:2
to
4:4:4
Interpolation
LPF-E
x2
Interpolation
LPF-F
Y [9:0]
Cb/Cr
Y
DEMUX
Level
Conversion
Cb/Cr
CB [9:0]
CR [9:0]
Cb/Cr
74.25MHz
Input Formatter
37.125MHz
74.25MHz
Delay
DAC
Delay
DAC
Delay
DAC
148.5MHz
Synchronization Mode
Fig. 45 1080i/720P mode Block Diagram
Rev-E-00
51
2008/03
[AK8825]
Over-sampling filter with aperture-effect compensation for Luminance (1080i/720P)
AK8825 equips the aperture-effect compensation filter for Luminance Signal.
This filter can be set with HDAFT[1:0]-bit of HD Block Miscellaneous Control Register [Sub Address 0x0A].
Compensation degree can be set with this register-bit. “Mode 0” is less compensation and “Mode 3” is more compensation.
HD Block Miscellaneous Control Register
Sub Address 0x0A
bit 7
bit 6
bit 5
Reserved
Reserved
STD770_2C
0
0
HDAFLT[1:0]-bit
00
01
10
11
bit 4
bit 3
HDCEA805B CCWSSSUE
Default Value
0
0
0
Filter Mode
MODE0
MODE1
MODE2
MODE3
bit 2
Reserved
default Value 0x00
bit 1
bit 0
HDAFLT1
HDAFLT0
0
0
0
Note
X2 Over-sampling Filter for Y-data
10
0
5
Aperteu Filter
3
10 15 20 25 30 35 40 45 50 55 60 65 70
2
1
-20
Gain[dB]
Gain[dB]
-10
0
-30
-40
0
-1 0
10
20
-2
MODE1
-4
-60
40
MODE2
-3
-50
30
MODE3
MODE0
-5
Frequency[MHz]
Frequency[MHz]
Fig. 46 Aperture Filter
Fig. 47 x2 Over-sampling filter for 1080i/720p
x4 Over-sampling Filter for Cb/Cr
10
0
Gain[dB]
-10
0
5
10
15
21
26
31
36
-20
-30
-40
-50
-60
Frequency[MHz]
Fig. 48 x4 Over-sampling filter for 1080i/720p
Rev-E-00
52
2008/03
[AK8825]
■
Luminance, Chrominance Band-Width Limitation Filter
AK8825 equips Band-Width Limit Filter for Luminance and Chrominance.
For Luminance, Filter is set by HDYFLT[1:0]-bit of HD Block Control Register (R/W) [SubAddress 0x07].
For Chrominance, Filter is set by HDCFLT[1:0]-bit of HD Block Control Register (R/W) [Sub Address 0x07].
HD Block Control Register
Sub Address 0x07
bit 7
bit 6
HDWSS
HDCFLT1
HDYFLT[1:0]
00
01
10
11
HDCFLT[1:0]
00
01
10
11
Rev-E-00
Filter
Normal
Mid
Soft
Reserve
Filter
Normal
Mid
Soft
Reserve
bit 5
HDCFLT0
bit 4
HDYFLT1
bit 3
HDYFLT0
bit 2
Reserved
bit 1
COLSNCEN
default Value 0x00
bit 0
HDVRATIO
Note
Default (no limit)
YFLT1 on Next Page
YFLT2 on Next Page
Note
Default (no limit)
CFLT1 on Next Page
CFLT2 on Next Page
53
2008/03
[AK8825]
Frequency response of Band-Width Limitation Filter
The default frequency response (HDYFLT [1:0]= 00 / HDCFLT[1:0]=00) is shown in the previous section.
10
10
0
0
2
4
-20
6
8 10 12 14 16 18 20 22 24 26
YFLT1
-30
-10
Gain[dB]
Gain[dB]
-10 0
YFLT2
0
1
2
-20
3
4
-40
-50
-50
-60
-60
CFLT1
Fig. 50 525i / 625i Luminance Band-Width Limitation Filter
10
0
0
20
YFLT2
-20
-30
-10 0
25
Gain[dB]
Gain[dB]
15
YFLT1
-50
-50
-60
-60
1
2
3
4
7
8
9 10 11 12 13
YFLT1
CFLT1
Fig. 52 525P/ 625P Chrominance Band-Width Limitation Filter
10
10
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
-10
YFLT2
Gain[dB]
Gain[dB]
6
Frequency[MHz]
Fig. 51 525P / 625P Luminance Band-Width Limitation Filter
YFLT1
-30
-40
-50
-50
-60
0
5
10
15
20
25
30
35
CFLT2
-20
-40
CFLT1
-60
Frequency[MHz]
Frequency[MHz]
Fig. 54 1080i/720P Luminance Band-Width Limitation Filter
Rev-E-00
5
CFLT2
YFLT2
Frequency[MHz]
-30
10 11 12 13
CFLT2
-30
-40
-20
9
-20
-40
-10 0
8
Fig. 49 525i / 625i Chrominance Band-Width Limitation Filter
10
10
7
Frequency[MHz]
Frequency[MHz]
5
6
-30
-40
-10 0
5
54
Fig. 53 1080i/720P Chrominance Band-Width Limitation Filter
2008/03
[AK8825]
■
Video Interface Timing
AK8825 has 2 types of Video Interface, EAV Decode mode and Slave SYNC mode.
Interface Mode is set by the HDEAVDEC-bit of HD Mode Register [Sub Address 0x00].
HD Mode Register
Sub Address 0x00
bit 7
bit 6
HDCBG
HDBBG
HDEAVDEC-bit
0
1
Rev-E-00
bit 5
HDSETUP
Interface mode
HD/VD Slave mode
EAV Decode mode
bit 4
HDEAVDEC
bit 3
HDCEA861
bit 2
HDMODE1
default Value 0x00
bit 1
bit 0
HDMODE0
HDRFRSH
Note
Set HDCEA861-bit = 0
55
2008/03
[AK8825]
(1) EAV Decode mode
(1 -1 ) EAV Decode
EAV code which is encoded on input data stream is decoded, and the device makes synchronization with its timing. At the time
of 16-bit width data input case, synchronization is made with EAV of the Y7-Y0 data, and it is not reference to the EAV/SAV
which are contained in CbCr7-0 data.
In case of RGB data input mode, AK8825 doesn’t support this interface mode.
EAV/SAV Code
Those codes succeeding 0xFF - 0x00 - 0x00 which are fed as input data become EAV/SAV codes.
EAV/SAV codes have following meanings, started with MSB.
Bit Number
MSB
WORD
VALUE
7
6
5
4
0
0xFF
1
1
1
1
1
0x00
0
0
0
0
2
0x00
0
0
0
0
3
0xxx
1
F
V
H
3
1
0
0
P3
2
1
0
0
P2
LSB
0
1
0
0
P0
1
1
0
0
P1
F
= 0 : Field 1
= 1 : Field 2
(F-bit is always 0 in case of Progressive data)
V
= 0 : Field Blanking (V-Blanking) 以外
= 1: Field Blanking (V-Blanking)
H
= 0: SAV
= 1: EAV
P3, P2, P1, P0: Protection Bit
Following is a relation between Protection bit and F/V/H-bit.
F
V
H
P3
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
Reference standards
Input Data
525i
625i
525p
625p
1080i
720p
Rev-E-00
P2
0
1
0
1
1
0
1
0
P1
0
0
1
1
1
1
0
0
P0
0
1
1
0
1
0
0
1
Reference
ITU-R.BT656
ITU-R.BT656
SMPTE 293M
ITU-R. BT1358
SMPTE 274M
SMPTE 296M
56
2008/03
[AK8825]
(1-2) Synchronization for Horizontal direction (EAV-Sync mode)
AK8825 synchronizes with input data horizontally using EAV code
EAV code and horizontal position is shown as following table.
525i (480i) case
Cb
Y
Cr
359
718 359
Y
719
Cb
360
Y
Cr
720
360
EAV
Y
721
・・・
Cb
428
Y
Cr
856 428
SAV
Y
857
Cb
0
Y
0
Cr
0
Y
1
625i (576i) case
Cb
Y
Cr
359
718 359
Y
719
Cb
360
Y
Cr
720
360
EAV
Y
721
・・・
Cb
431
Y
Cr
862 431
SAV
Y
863
Cb
0
Y
0
Cr
0
Y
1
525P (480P) case
Y
718
TRS
719
720
721
722
EAV
723
854
855 856
SAV
857
0
1
2
625P (576P) case
Y
718
TRS
719
720
721
722
EAV
723
860
861 862
SAV
863
0
1
2
1125i (1080i) / 60Hz case
1918 1919
Y
TRS
1920
1921
1923
2196
2197
2199
0
1
2
1125i (1080i) / 50Hz case
1918 1919
Y
TRS
1920
2639
0
1
2
750P (720P) / 60Hz case
1278 1279
Y
TRS
1280
1649
0
1
2
750P (720P) / 50Hz case
1278 1279
Y
TRS
1280
1979
0
1
2
Rev-E-00
1922
EAV
1921
1922
1923
EAV
1281
1282
1283
EAV
1281
1282
EAV
1283
・・・
・・・
・・・
・・・
・・・
・・・
57
2198
SAV
2636
2637
2638
SAV
1646
1647
1648
SAV
1976
1977
1978
SAV
2008/03
[AK8825]
(1-3) Synchronization for Vertical direction (EAV-Sync mode)
The AK8825 makes Vertical Synchronization (Line Synchronization) with either F-bit or V-bit of EAV.
Interlaced signal: using F-bit
Progressive signal: using V-bit
(1-2-1) F-bit
Relation between F-bit and Line-Number
F-bit
525i
625i
0
Line4 - Line265
Line1 - Line312
Line266 - Line525
1
Line313 - Line625
Line1 - Line3
525P/625P
1080i
Line1 - Line563
All Lines
F=0
Line564 - Line1125
720P
All Lines
F=0
(1-2-2) V-bit
Relation between V-bit and Line-Number
- 525i (480i), 625i (576i), 1080i case
Field
V-bit
525i
625i
Start (V=1)
Line1 - Line19
Line624 - Line22
Field 1
End (V=0)
Line20 - Line263
Line23 - Line310
Start (V=1)
Line264 - Line282
Line311 - Line335
Field 2
End (V=0)
Line283 - Line525
Line336 - Line623
Note: AK8825 don’t care V-bit in case of 525i / 625i / 1080i mode
- 525P, 625P, 750P case
V-bit
525P
Start (V=1)
Line1 - Line42
End (V=0)
Line43 - Line525
Rev-E-00
625P
Line621 - Line44
Line45 - Line625
58
1080i (60/50Hz)
Line1124 - Line1125 - Line20
Line21 - Line560
Line561 - Line583
Line584 - Line1123
720P
Line746 - Line750 - Line25
Line26 - Line745
2008/03
[AK8825]
(1-4) Interlace data and Progressive data synchronization
(1-4-1) Interlace data (525i / 625i / 1080i)
When in the Interlaced input data cases (525i / 625i / 1080i), Line Synchronization with input data is made with F-bit of EAV.
Digital
Line-No.
1
2
3
4
5
6
7
8
9
264
265
266
267
268
269
270
271
F-bit
Digital
Line-No.
263
272
F-bit
Fig. 55 525i mode
Digital
Line-No.
623
624
625
1
2
3
4
5
6
311
312
313
314
315
316
317
318
F-bit
Digital
Line-No.
310
319
F-bit
Fig. 56 625i mode
1124
1125
1
2
3
4
5
6
561
562
563
564
565
566
567
568
Digital
Line-No.
F-bit
Digital
Line-No.
F-bit
Fig. 57 1080i mode
Rev-E-00
59
2008/03
[AK8825]
(1-3-2) Progressive Data (525p / 625p / 720p)
When in the Progressive data input cases, Line Synchronization with input data is made with V-bit of EAV.
524 525
Digital
Line-No.
1
2
6
7
8
9
10
11
12
13
5
6
7
14
...
40
41
42
V-bit
Fig. 58 525p case
620 621
Digital
Line-No.
622 623 624 625
1
2
3
4
8
...
42
43
44
45
V-bit
Fig. 59 625p case
Digital
Line-No.
745
746
749
750
1
2
3
4
5
6
7
25
26
V-bit
Fig. 60 720 case
Rev-E-00
60
2008/03
[AK8825]
(1-2) EAV/SAV and Data
(1-2-1) 525i (T: 13.5MHz)
Y
Cb
Cr
718
719
E AV
720
721
359
722
360
723
734
・・・
361
735
736
367
S AV
856
857
737
・・・
368
16T
0
428
1
0
122T
138T
0H
50%
50%
Fig. 61
Clock count between EAV to 0th data is 138T.
(1-2-2) 625i (T: 13.5MHz)
Y
Cb
Cr
718
719
359
E AV
720
721
360
722
723
361
730
・・・
731
732
365
S AV
862
863
733
366
12T
・・・
431
0
1
0
132T
144T
0H
50%
50%
Fig. 62
Clock count between EAV to 0th data is 144T.
Rev-E-00
61
2008/03
[AK8825]
(1-2-3) 525P (T: 27MHz)
Y
718
719
720
EAV
721 722
723
・・・
734
735
736
737
・・・
16T
854
SAV
855 856
857
0
1
2
SAV
861 862
863
0
1
2
122T
138T
0H
50%
50%
Fig. 63
Clock count between EAV to 0th data is 138T.
(1-2-4) 625P (T: 27MHz)
Y
718
719
720
EAV
721 722
723
・・・
730
731
732
12T
733
・・・
860
132T
144T
0H
50%
50%
Fig. 64
Clock count between EAV to 0th data is 144T.
Rev-E-00
62
2008/03
[AK8825]
(1-2-5) 1080i / 60Hz (T: 74.25MHz)
Y
1920
EAV
1921 1922
1923
0H
2008
1924
・・ ・
88T
2196
188T
SAV
2197 2198
2199
0
1
2
2639
0
1
2
4T
192T
280T
50%
50%
Fig. 65
Clock count between EAV to 0th data is 280T.
(1-2-6) 1080i / 50Hz (T: 74.25MHz)
Y
1920
EAV
1921 1922
1923
0H
2448
1924
・・ ・
528T
2636
188T
SAV
2637 2638
4T
192T
720T
50%
50%
Fig. 66
Clock count between EAV to 0th data is 720T.
Rev-E-00
63
2008/03
[AK8825]
(1-2-7) 720P / 50Hz ( T: 74.25MHz)
Y
1280
EAV
1281 1282
1283
0H
1390
1284
・・・
110T
1646
SAV
1647 1648
256T
1649
0
1
2
4T
260T
370T
50%
50%
Fig. 67
Clock count between EAV to 0th data is 370T.
(1-2-8) 750P(720P) / 50Hz (T: 74.25MHz)
Y
1280
EAV
1281 1282
1283
0H
1720
1284
440T
・・・
1976
256T
SAV
1977 1978
1979
0
1
2
4T
260T
700T
50%
50%
Fig. 68
Clock count between EAV to 0th data is 700T.
Rev-E-00
64
2008/03
[AK8825]
(1-3) Timing for Data Capture
(1-3-1) 525i / 625i 8-bit input mode
CLKIN
(27MHz)
Data
Cb
Y
･･･ ･･･ Cbn Y2n
Crn Y2n+1 Cbn+1 Y2n+2 Crn+1 Y2n+3 Cbn+2 Y2n+4 Crn+2 ･･･ ･･･
Fig. 69
Synchronization code is embedded as follows.
CLKIN
(27MHz)
Data
0xXX 0xXX ･･･
･･･ 0xZZ 0xZZ 0xFF 0x00 0x00 0xYY Cb
Y
Cr
Y
･･･
EAV/SAV
Fig. 70
Rev-E-00
65
2008/03
[AK8825]
(1-3-2) 525P / 625P / 1080i / 720P 16-bit data input mode
CLKIN
Y0
Y1
Y2
Y3
･･･ ･･･ ･･･ ･･･
Cb0
Cr0
Cb1
Cr1
Cb2
Y2n Y2n+1 Y2n+2 Y2n+3 Y2n+4 Y2n+5 ･･･ ･･･ ･･･
Data
Cr2
･･･ ･･･ Cbn
Crn Cbn+1 Crn+1 Cbn+2 Crn+2 ･･･
･･･ ･･･
Fig. 71
Synchronization code is embedded in Ydata as follows.
CLKIN
Y_Data
0xXX 0xXX ･･･
･･･ 0xZY 0xFF 0x00 0x00 0xYY
Y
Y
Y
Y
Y
･･･
･･･
EAV/SAV
Fig. 72
Rev-E-00
66
2008/03
[AK8825]
(2) Slave Synchronization mode
AK8825 can make synchronization using HSYNC/VSYNC timing.
The coming HSYNC is used for synchronization for horizontally, and VSYNC is used for Line-Sync.
The falling edge of the each timing signal is used for Synchronization.
Synchronization timing is AK8825 original timing and the timing defined in CEA861-D standard.
Timing is set by the register (HDCEA861-bit of HD mode Register [Sub Address 0x00].
HD Mode Register
Sub Address 0x00
bit 7
bit 6
HDCBG
HDBBG
HDCEA861-bit
HDCEA861D
0
1
bit 5
HDSETUP
bit 4
HDEAVDEC
Sync-timing
AK8825 Sync timing
CEA-861-D Sync-timing
bit 3
HDCEA861
bit 2
HDMODE1
default Value 0x00
bit 1
bit 0
HDMODE0
HDRFRSH
Note
The AK8825 recognizes 1st/2nd Field to watch the relation between HSYNC and VSYNC falling edge.
Rev-E-00
67
2008/03
[AK8825]
(2-1) 525i 8-bit x 1ch (Based on ITU-R .BT.601 standard)
(2-1-1) HDCEA861-bit = 0
244T (-2T/+1T)
27MHz
Data
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
HDI
Fig. 73 525i HSYNC and data (8-bit x 1ch)
Digital
Line-No.
3
4
5
6
7
8
9
10
11
HDI
VDI
Fig. 74 525i Relation between HSYNC and VSYNC (1)
Digital
Line-No.
266
267
268
269
270
271
272
273
274
HDI
VDI
Fig. 75 525i Relation between HSYNC and VSYNC (2)
1/2 H
1/2 H
HDI
Start of 1st Field
1/4 H 1/4 H
VDI
Start of 2nd Field
1/4 H 1/4 H
VDI
Fig. 76 Recognition of Field
Rev-E-00
68
2008/03
[AK8825]
(2-1-2) CEA861D-bit = 1
CEA 861-D : 525i(480i) / 60Hz (HDTV)
720(1440)[email protected]/60Hz(Formats 6 & 7)
HDI, VDI Input Timing
LINE
1716 Total Horizontal Clocks per line
Data Enable
1440 Clocks for Active Video
238
124
Outside of Data Enable period
Y: 10H, CbCr: 80H
114 clocks
38
HDI
Fig. 77
Field 1
Field 1: 22 Vertical Blanking Lines
240 Active Vertical Lines per field
Data
Enable
38
1716clocks
238
HDI
524 525 1
2
3
4
5
6
7
8
9
10 11
21 22
261 262 263
VDI
Fig. 78
Field 2
Field 2: 23 Vertical Blanking Lines
240 Active Vertical Lines per field
Data
Enable
38
1716clocks
858
238
HDI
261 262 263 264 265 266 267 268 269 270271 272 273
284 285
524 525 1
VDI
Fig. 79
Rev-E-00
69
2008/03
[AK8825]
(2-2) 625i 8-bit x 1ch (Based on ITU-R .BT.601)
(2-2-1) HDCEA861-bit = 0
264T (-2T/+1T)
27MHz
Data
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
HDI
Fig. 80 625i HSYNC and data (8-bit x 1ch)
Digital
Line-No.
622
623
624
625
1
2
3
4
5
6
7
8
319
320
HD
VD
Fig. 81
Digital
Line-No.
310
311
625i Relation between HSYNC and VSYNC (1)
312
313
314
315
316
317
318
HD
VD
Fig. 82
525i Relation between HSYNC and VSYNC (2)
1/2 H
1/2 H
HDI
Start of 1st Field
1/4 H 1/4 H
VDI
Start of 2nd Field
1/4 H 1/4 H
VDI
Fig. 83 Recognition of Field
Rev-E-00
70
2008/03
[AK8825]
(2-2-2) HDCEA861-bit = 1
CEA 861-D : 625i(576i) / 60Hz (HDTV)
720(1440)x576i@50Hz(Formats 21 & 22)
HDI and VDI timing
LINE
1728 Total Horizontal Clocks per line
Outside of Data Enable period
Y: 10H, CbCr: 80H
Data Enable
1440 Clocks for Active Video
264
126
24
138 clocks
HDI
Fig. 84
Field 1
Field 1: 24 Vertical Blanking Lines
288 Active Vertical Lines per field
Data
Enable
24
1728clocks
264
HDI
623 624 625 1
2
3
4
5
6
7
8
9
10
22 23
310 311 312
VDI
Fig. 85
Field 2
Field 2: 25 Vertical Blanking Lines
288 Active Vertical Lines per field
Data
Enable
24
1728clocks
264
864
HDI
310 311 312 313 314 315 316 317 318 319320 321 322
335 336
623 624 625
VDI
Fig. 86
Rev-E-00
71
2008/03
[AK8825]
( 2-3 ) 525P 8-bit x 2ch (Based on SMPTE 293M)
(2-3-1) HDCEA861-bit = 0
HDI and VDI timing
122T (-2T/+1T)
27MHz
Data (Y)
Y0
Y1
Y2
Y3
---
Y2n
Y2n+1
Data (Cb/Cr)
Cb0
Cr0
Cb1
Cr1
---
Cbn
Crn
HDI
Fig. 87 525p HSYNC and data (8-bit x 2ch)
Digital
Line-No.
1
2
6
7
8
9
10
11
12
13
14
15
16
17
18
525
HDI
VDI
Fig. 88 525p Relation between HSYNC and VSYNC
HDI
1/2 H
1/2 H
VDI
Fig. 89 Relation between HSYNC and VSYNC
Rev-E-00
72
2008/03
[AK8825]
(2-3-2) HDCEA861-bit = 1
CEA 861-D : 525p(480p) / 60Hz : HDTV
[email protected]/60Hz(Formats 2 & 3)
HDI and VDI timing
LINE
Outside of Data Enable period
Y: 10H, CbCr: 80H
858 Total Horizontal Clocks per line
Data Enable
122
62
60 clocks
720 Clocks for Active Video
16
HDI
Fig. 90
Field
Progressive Frame: 45 Vertical Blanking Lines
480 Active Vertical Lines
（Data
Enable)
16
858clocks
122
HDI
522 523 524 525 1
7
8
9
10 11 12 13
42 43
522 523 524 525
VDI
Fig. 91
Rev-E-00
73
2008/03
[AK8825]
( 2-4 ) 625P 8-bit x 2ch
(2-4-1) HDCEA861-bit = 0
HDI and VDI timing
132T
27MHz
Y[7:0]
Y0
Y1
Y2
Y3
---
Y2n
Y2n+1
CBCR[7:0]
Cb0
Cr0
Cb1
Cr1
---
Cbn
Crn
HDI
Fig. 92 625p HSYNC and data (8-bit x 2ch)
Clock count between falling edge of HDI to 0th data is 132T.
Rev-E-00
74
2008/03
[AK8825]
(2-4-2) HDCEA861-bit = 1
CEA 861-D : 625p(576p) / 50Hz : HDTV
720(1440)x576p@50Hz(Formats 17 & 18)
HDI and VDI timing
LINE
Outside of Data Enable period
Y: 10H, CbCr: 80H
864 Total Horizontal Clocks per line
Data Enable
720 Clocks for Active Video
132
64
68 clocks
12
HDI
Fig. 93
Field
Progressive Frame: 49 Vertical Blanking Lines
576 Active Vertical Lines
(Data
Enable)
12
864clocks
132
HDI
620 621 622
624 625 1
2
3
4
5
6
7
44 45
620 621 622 623
VDI
Fig. 94
Rev-E-00
75
2008/03
[AK8825]
( 2-5) 1080i / 60Hz (8-bit x 2ch)
(2-5-1) HDCEA861-bit = 0
HDI and VDi timing
236T (-2T/+1T)
74.25MHz
or
74.25/1.001
Data (Y)
Y0
Y1
Y2
Y3
---
Y 2n
Y 2n+ 1
Data (Cb/Cr)
Cb 0
Cr 0
Cb 1
Cr 1
---
C bn
Cr n
HDI
Fig. 95 1080i HSYNC and data (8-bit x 2ch)
1124
1125
1
2
3
4
5
6
7
568
569
Digital
Line-No.
HDI
VDI
Fig. 96
561
562
563
1080i Relation between HSYNC and VSYNC (1)
564
565
566
567
Digital
Line-No.
HDI
VDI
Fig. 97
1080i Relation between HSYNC and VSYNC (2)
1/2 H
1/2 H
HDI
Start of 1st Filed
1/2 H
VDI
Start of 2nd Field
1/2 H
VDI
Fig. 98 Recognition of Field
Rev-E-00
76
2008/03
[AK8825]
(2-5-2) HDCEA861-bit = 1
CEA 861-D : 1080i / 60Hz : HDTV
[email protected]/60Hz(Formats 5)
HDI and VDI timing
LINE
2200 Total Horizontal Clocks per line
Outside of Data Enable periode
Y:10H, CbCr:80H
Data Enable
1920 Clocks for Active Video
192
44
148 clocks
88
HDI
Fig. 99
Field 1
Field 1: 22 Vertical Blanking Lines
540 Active Vertical Lines per field
(Data
Enable)
88
2200clocks
192
HDI
1123 1124 1125
1
2
3
4
5
6
7
8
9
19
20
21
560 561 562
VDI
Fig. 100
Field 2
Field 2: 23 Vertical Blanking Lines
540 Active Vertical Lines per field
(Data
Enable)
88
2200clocks
1100
192
HDI
560 561 562 563 564 565 566 567 568 569 570 571
582 583 584
1123 1124 1125
VDI
Fig. 101
Rev-E-00
77
2008/03
[AK8825]
( 2-6) 1080i / 50Hz (8-bit x 2ch)
(2-6-1) HDCEA861-bit = 0
HDI and VDI timing
236T
74.25MHz
or
74.25/1.001
DATA[7:0]
Y0
Y1
Y2
Y3
---
Y 2n
Y 2n+ 1
DATA[15:8]
Cb 0
Cr 0
Cb 1
Cr 1
---
Cb n
Cr n
HDI
Fig. 102
1124
1125
1125i(1080i) HSYNC and data (8-bit x 2ch)
1
2
3
4
5
6
7
Digital
Line-No.
HDI
VDI
Fig. 103
561
562
1125i (1080i) Relation between HSYNC and VSYNC(1)
563
564
565
566
567
568
569
Digital
Line-No.
HDI
VDI
Fig. 104
1125i (1080i) Relation between HSYNC and VSYNC(2)
1/2H
1/2H
HDI
start of 1st field
1/2H
VDI
Start of 2nd Field
1/2H
VDI
Fig. 105
Rev-E-00
Field Recognition
78
2008/03
[AK8825]
(2-6-2) HDCEA861-bit = 1
EIA/CEA 861-B : 1080i / 50Hz : HDTV
1920x1080i@50Hz(Formats 20)
LINE
2640 Total Horizontal Clocks per line
Data Enable
1920 Clocks for Active Video
192
44
Outside of Data Enable periode
Y:10H, CbCr:80H
148 clocks
528
HDI
Fig. 106
Field 1
Field 1: 22 Vertical Blanking Lines
540 Active Vertical Lines per field
(Data
Enable)
528
2640clocks
192
HDI
112 112 112
1
2
3
4
5
6
7
8
9
1
2
21
560 561 562
VDI
Fig. 107
Field 2
Field 2: 23 Vertical Blanking Lines
540 Active Vertical Lines per field
(Data
Enable)
528
2640clocks
1320
192
HDI
560 561 562 563 564 565 566 567 568 569 570 571
582 583 584
1123 1124 1125
VDI
Fig. 108
Rev-E-00
79
2008/03
[AK8825]
( 2-7 ) 720P / 60Hz 8-bit x 2ch
(2-7-1) HDCEA861-bit = 0
300T (-2T/+1T)
74.25MHz
or
74.25/1.001
Data (Y)
Y0
Y1
Y2
Y3
---
Y 2n
Y2n+1
Data (Cb/Cr)
Cb 0
Cr0
Cb 1
Cr1
---
Cb n
Crn
HDI
Fig. 109 720P HSYNC and Data (8-bit x 2ch）
749
750
1
2
3
4
5
6
7
Digital
Line-No.
HDI
VDI
Fig. 110
720P
Relatio between HSYNC and VSYNC
HDI
1/2 H
1/2 H
VDI
Fig. 111 HSYNC and VSYNC
Rev-E-00
80
2008/03
[AK8825]
(2-7-1) HDCEA861-bit = 1
CEA 861-B : 720p / 60Hz : HDTV
[email protected]/60Hz(Formats 4)
LINE
1650 Total Horizontal Clocks per line
Outside of Data Enable periode
Y:10H, CbCr:80H
Data Enable
260
40
1280 Clocks for Active Video
220 clocks
110
HDI
Fig. 112
Field
Progressive Frame: 30 Vertical Blanking Lines
720 Active Vertical Lines
(Data
Enable)
110
1650clocks
260
HDI
745 746 747 748 749 750
1
2
3
4
5
6
24
25
26
745 746
750
VDI
Fig. 113
Rev-E-00
81
2008/03
[AK8825]
( 2-8 ) 720P / 50Hz 8-bit x 2ch
(2-8-1) HDCEA861-bit = 0
300T
74.25MHz
DATA[7:0]
Y0
Y1
Y2
Y3
---
Y 2n
Y2n+1
DATA[15:8]
Cb 0
Cr0
Cb 1
Cr1
---
Cb n
Crn
HDI
Fig. 114 720P HD and Data (8-bit x1ch)
749
750
1
2
3
4
5
6
7
Digital
Line-No.
HDI
VDI
Fig. 115 720P Relation between HDI and VDI
HDI
1/2 H
1/2 H
VDI
Fig. 116
Rev-E-00
HDI VDI Input Timing
82
2008/03
[AK8825]
(2-8-1) HDCEA861-bit = 1
CEA 861-B : 720p / 50Hz : HDTV
1280x720p@50Hz(Formats 19)
LINE
Outside of Data Enable periode
Y:10H, CbCr:80H
1980 Total Horizontal Clocks per line
Data Enable
260
1280 Clocks for Active Video
40
220 clocks
440
HDI
Fig. 117
Progressive Frame: 30 Vertical Blanking Lines
720 Active Vertical Lines
Field
(Data
Enable)
440
1980clocks
260
HDI
745 746 747 748 749 750
1
2
3
4
5
6
24
25
26
745 746
750
VDI
Fig. 118
Rev-E-00
83
2008/03
[AK8825]
■
Output Synchronization waveform
AK8825 output synchronization waveform on Ysignal at default, however, COLSNCEN-bit of HD Block Control Register
[SubAddress 0x27] can add Synchronization waveform on not only Y-signal but also on PB and Pr signal.
The synchronization waveform on Pb and Pr is same as synchronization waveform on Y-signal.
HD Block Control Register
Sub Address 0x07
bit 7
bit 6
HDWSS
HDCFLT1
COLSNCEN-bit
0
1
bit 5
HDCFLT0
bit 4
HDYFLT1
bit 3
HDYFLT0
bit 2
Reserved
bit 1
COLSNCEN
default Value 0x00
bit 0
HDVRATIO
Function
Sync on Y-signal
Sync on Y, Pb, Pr signal
Y
Y
Pb
No sync-waveform
Pb
Pr
No sync-waveform
Pr
COLSNCEN-bit = 0
COLSNCEN-bit = 1
Fig. 119 525i / 625i / 525p / 625p case
Y
Pb
Pr
Y
Pb
no sync waveform
Pr
no sync waveform
COLSNCEN-bit = 0
COLSNCEN-bit = 1
Fig. 120 1080i / 720p case
Rev-E-00
84
2008/03
[AK8825]
(1) 525i waveform (EIA-770.2-C)
[Sync waveform level]
Only 525i output mode, AK8825 can output both of 286mV sync-waveform and 300mV sync-waveform with setting
HDVRATIO-bit of HD Block Control Register [SubAddress0x07]
HD Block Control Register
Sub Address 0x07
bit 7
bit 6
HDWSS
HDCFLT1
bit 5
HDCFLT0
HDVRATIO-bit
0
1
bit 4
HDYFLT1
bit 3
HDYFLT0
bit 2
Reserved
bit 1
COLSNCEN
default Value 0x00
bit 0
HDVRATIO
Sync waveform Level
300mV (EIA770.2-A)
286mV (EIA770.1-A)
(1-1) 525i Sync waveform
H o r iz o n ta l B la n k in g r is e t im e
90%
50%
S y n c r is e t im e
10%
90%
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
300m V*
10%
H b la n k in g s ta r t
to H -re fe re n c e
S ync
H r e f e r e n c e to B la n k in g E n d
Fig. 121
measurement
point
Total line period(derived)
Sync rise time
Horizontal Sync
10% - 90%
50%
value
Recommended
tolerance
63.556
140
4.7
+/- 20
+/- 0.1
units
usec
nsec
usec
Design Spec (T=1/13.5MHz)
H-Blanking start to H-reference
H reference to H-blanking end
Measurement Point
50%
50%
Reference Clock
16T
122T
* 286mV sync waveform can be output by register setting.
Rev-E-00
85
2008/03
[AK8825]
(1-2) 525i Frame Configuration: Vertical SYNC signal wave form timing
3H
B
A
1
3H
E
0 .5 H
2
3H
F
D
3
4
5
C
6
7
8
9
19
1 9 + 1 /- 2 L in e
(s e t b y re g is te r)
3H
3H
3H
0 .5 H
263
264
265
266
267
268
269
270
271
272
273
283
Fig. 122
Symbol
A
B
C
D
E
F
Duration
429T
858T
31T
429T
858T
63T
Measurement point
Reference
50%
13.5MHz Clock
G
I
H
I
I
Equalizing Pulse
I
300mV
or
286mV
Serration Pulse
Fig. 123 Equalizing Pulse と Serration Pulse
Symbol
Measurement
point
Value
Field Period (derived)
16.6833
Frame period (derived)
33.3667
Vertical blanking start before first
50%
1.5
equalizing pulse
Vertical blanking
19* lines + 1.5
(63.556usec x 20lines + 1.5usec)
usec
Pre-equalizing duration
3
G
Pre-equalizing pulse width
50%
2.3
Vertical sync duration
3
H
Vertical serration pulse width
50%
4.7
Post-equalizing duration
3
G
Post-equalizing pulse width
50%
2.3
I
Sync rise time
140
* There is a case of V-Blank of 20 lines. This value is pre-settable by register.
Rev-E-00
86
Recommended
tolerance
units
msec
msec
+/- 0.1
usec
0
+/- 0.1
lines
usec
lines
usec
lines
usec
lines
usec
nsec
+/- 0.1
+/- 0.1
+/- 0.1
+/- 20
2008/03
[AK8825]
(2) 625i Sync-Signal
(2-1) 625i Horizontal SYNC waveform
H o r iz o n ta l B la n k in g r is e t im e
90%
50%
700m V
S y n c r is e t im e
10%
90%
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
300m V
10%
H b la n k in g s ta r t
to H -re fe re n c e
S ync
H r e f e r e n c e to B la n k in g E n d
Fig. 124
measurement
point
Total line period(derived)
Sync rise time
Horizontal Sync
Design Spec.
Recommended
tolerance
64.0
0.2
4.7
+/- 0.1
+/- 0.2
units
usec
usec
usec
(T=1/13.5MHz)
H-Blanking start to H-reference
H reference to H-blanking end
Rev-E-00
10% - 90%
50%
value
Measurement Point
50%
50%
Reference Clock
12T
132T
87
2008/03
[AK8825]
(2-2) 625i Frame Configuration and signal waveform
0.5H
623
624
625
1
2
3
4
5
6
0.5H
310
311
312
313
314
315
316
317
318
319
320
Fig. 125
G
I
H
I
I
Equalizing Pulse
I
300mV
Serration Pulse
Fig. 126 Equalizing Pulse と Serration Pulse
Symbol
Measurement
point
50%
50%
50%
Value
G
Pre-equalizing pulse width
2.35
H
Vertical serration pulse width
4.7
G
Post-equalizing pulse width
2.35
I
Sync rise time
200
* There is case where tolerance of Sync rise time is added to Pulse width tolerance.
Rev-E-00
88
Recommended
tolerance
+/- 0.1
+/- 0.2
+/- 0.1
MAX300
units
usec
usec
usec
nsec
2008/03
[AK8825]
(3) 525p waveform ( EIA-770.2-C )
(3-1) 525p Horizontal Sync waveform
H o r iz o n ta l B la n k in g r is e t im e
90%
50%
S y n c r is e t im e
10%
90%
H o r iz o n ta l
r e f e r e n c e p o in t
50%
300m V
50%
10%
H b la n k in g s ta r t
to H -re fe re n c e
S ync
H r e f e r e n c e to B la n k in g E n d
Fig. 127
measurement
point
Total line period(derived)
Sync rise time
Horizontal Sync
Rev-E-00
10% - 90%
50%
value
31.776
70
2.33
89
Recommended
tolerance
+/- 10
+/- 0.05
units
usec
nsec
usec
2008/03
[AK8825]
(3-2) 525p Vertical Sync waveform and Timing
AK8825 supports both of CEA-770.2-A and CEA770.2-C
HD Block Miscellaneous Control Register
Sub Address 0x0A
bit 7
bit 6
bit 5
Reserved
Reserved
STD770_2C
STD770_2C -bit
0
1
bit 4
HDCEA805B
bit 3
CCWSSSUE
Standard
CEA 770.2-A
CEA 770.2-C
bit 2
Reserved
default Value 0x00
bit 1
bit 0
HDAFLT1
HDAFLT0
Remark
(3-2-2) CEA 770.2-A (STD770_2C-bit =0)
63
858
6H
6H
6H
63
795
795
525
1
858
2
6
7
8
12
13
42
14
43
42
Fig. 128
Measurement
point
Frame period (derived)
Vertical blanking
(31.776usec x 42lines + 0.59usec)
Vertical sync duration
Vertical serration pulse width
Recommended
tolerance
value
16.6833
6
2.33
50%
msec
lines
usec
lines
usec
0
+/- 0.05
42 lines + 0.59usec
units
+/- 0.05
(3-2-3) CEA 770.2-C (STD770_2C-bit =1)
63
858
6H
9H
6H
63
795
795
525
1
2
858
9
10
11
15
16
17
45
46
45
Fig. 129
Measurement
point
Frame period (derived)
Vertical blanking
(31.776usec x 42lines + 0.59usec)
Vertical sync duration
Vertical serration pulse width
Rev-E-00
value
Recommended
tolerance
16.6833
45 lines + 0.59usec
6
2.33
50%
90
0
+/- 0.05
+/- 0.05
units
msec
lines
usec
lines
usec
2008/03
[AK8825]
(4) 625p Syncronization Waveform (ITU-R. BT1368)
(4-1) 625p Horizontal Sync waveform
e
90%
a
50%
700m V
f
10%
90%
50%
H orizontal
reference point
50%
300m V
10%
C
d
b
Fig. 130
Symbol
H
a
d
f
Rev-E-00
Characteristics
Nominal line period (us)
Horizontal blanking interval(us)
Synchronizing pulse (us)
Build-up time (10 to 90%) of the edges of the horizontal synchronizing pulses (us)
91
625/50/1:1
32
6.0±1.5
2.35±0.1
0.1±0.05
2008/03
[AK8825]
(4-2) 625p Vertical Sync waveform and timing
α
β
χ
A
δ
B
C
D
Fig. 131
r
p
s
Fig. 132
Symbol
V
D
-
Characteristics
Nominal frame period (ms)
Vertical blanking interval
Build-up time (10 to 90%) of the edges of vertical blanking pulse (us)
Interval between front edges of vertical blanking interval and front edges of first vertical
A
synchronizing pulse
Interval between back edges of last vertical synchronizing pulse and back edge of vertical
C
blanking interval
B
Duration of sequence of vertical synchronizing pulses
p
Duration of vertical synchronizing pulse (us)
r
Interval between vertical synchronizing pulse (us)
s
Build-up time (10 to 90%) og the vertical synchronizing pulses (us)
* For H and a, see Table 1 (ITU-R BT.1358)
625/50/1:1
20
49H+α*
0.15±0.05
5H*
39H*
5H*
29.65±0.1
2.35±0.1
0.1±0.05
Line number
α
621
Rev-E-00
β
1
χ
6
92
δ
44
2008/03
[AK8825]
(5) 1080i Synchronization waveform (EIA-770.3-C )
(5-1-1) 1080i Horizontal Sync waveform (60Hz)
2200T
0H
b
e (1 9 2 T )
50%
f
V /2
50%
f
V /2
Sp
f
50%
Sm
45T
1920T
a (4 4 T )
4T
c (4 4 T )
272T
4T
EAV
V ID E O D ATA
SAV
EAV
A N C IL L A R Y D ATA o r
B L A N K IN G C O D E W O R D S
1920T
90%
300m V
B L A N K IN G
300m V
BPSRT
10%
BPSTP
H LFP
f
t1
BRO AD PU LSE
t2
Fig. 133
1080i 60Hz
Symbol
a
b
c
e
f
t2 – t1
Sm
Sp
V
BPSRT
BPSTP
HLFP
Rev-E-00
Parameter
Negative line sync width
End of active video
positive line sync width
Start of active video
Rise/fall time
Symmetry of rising edge
Amplitude of negative pulse
Amplitude of positive pulse
Amplitude of video signal
Total Lines
Active Lines
Broad pulse start pos
Broad pulse stop pos
H/2 pos
Nominal value
0.593 [usec]
1.120 [usec]
0.593 [usec]
2.589 [usec]
0.054 [usec]
300 [mV]
300 [mV]
700 [mV]
Reference
clock Interval
44
89
44
192
4
2200
1920
132
1012
1100
93
Tolerance
CLK
+/- 3
+/- 3
-0 / + 6
+/- 1.5
Tolerance
+/- 0.040 [usec]
+0.080 [usec]
+/- 0.040 [usec]
+0.080 [usec]
+/- 0.020 [usec]
+/- 0.002 [usec]
+/- 6mV
+/- 6mV
-12, +0
-3 ~ +3
-3 ~ +3
-3 ~ +3
2008/03
[AK8825]
(5-1-2) 1080i Vertical Sync waveform and timing (60Hz)
Frame Configuration
22H
20H
5H
1123
1124
1125
1
2
3
4
5
6
7
8....
20
21
First Field
23H
20.5H
5H
560
561
562
563
564
565
5H
566
567
568
569
570...
583
584
SecondField
Fig. 134
Vertical Sync waveform (Refer to ITU-R.BT709)
300mV
300mV
δ
η
γ
0H
1H
Fig. 135
δ
γ
η
Rev-E-00
Duration
132 T
1100 T
1012 T
Tolerance
+/- 3
+/- 3
+/- 3
94
2008/03
[AK8825]
(5-2-1) 1080i Horizontal Sync waveform (50Hz)
2640T
0H
b
e (1 9 2 T )
50%
f
V /2
50%
f
V /2
Sp
f
50%
Sm
485T
1920T
a (4 4 T )
4T
c (4 4 T )
712T
4T
EAV
V ID E O D ATA
SAV
EAV
A N C IL L A R Y D ATA o r
B L A N K IN G C O D E W O R D S
1920T
90%
300m V
B L A N K IN G
300m V
BPSRT
10%
BPSTP
H LFP
f
t1
BRO AD PU LSE
t2
Fig. 136
1080i 60Hz
Symbol
a
b
c
e
f
t2 – t1
Sm
Sp
V
BPSRT
BPSTP
HLFP
Rev-E-00
parameter
Negative line sync width
End of active video
positive line sync width
Start of active video
Rise/fall time
Symmetry of rising edge
Amplitude of negative pulse
Amplitude of positive pulse
Amplitude of video signal
Total Lines
Active Lines
Broad pulse start pos
Broad pulse stop pos
H/2 pos
Nominal value
0.593 [usec]
7.120 [usec]
0.593 [usec]
2.589 [usec]
0.054 [usec]
300 [mV]
300 [mV]
700 [mV]
Reference
clock Interval
44
529
44
192
4
2640
1920
132
1012
1100
95
Tolerance
CLK
+/- 3
+/- 3
-0 / + 6
+/- 1.5
Tolerance
+/- 0.040 [usec]
+0.080 [usec]
+/- 0.040 [usec]
+0.080 [usec]
+/- 0.020 [usec]
+/- 0.002 [usec]
+/- 6mV
+/- 6mV
-12, +0
-3 ~ +3
-3 ~ +3
-3 ~ +3
2008/03
[AK8825]
(5-2-2) 1080i Vertical Sync waveform(50Hz)
22H
20H
5H
1123
1124
1125
1
2
3
4
5
6
7
8....
20
21
First Field
23H
20.5H
5H
560
561
562
563
564
5H
565
566
567
568
569
570...
583
584
SecondField
Fig. 137
Vertical Sync Waveform (Refer to ITU-R.BT709 standard)
300mV
300mV
δ
η
γ
0H
1H
Fig. 138
δ
γ
η
Rev-E-00
Duration
132 T
1100 T
1012 T
Tolerance
+/- 3
+/- 3
+/- 3
96
2008/03
[AK8825]
(6) 720p Synchronization waveform and timing (EIA-770.3-C )
(6-1-1) 720p Horizontal Sync waveform (60Hz)
1650T
0H
b
e (2 6 0 T )
50%
f
V /2
50%
f
V /2
Sp
f
50%
Sm
70T
1280T
c (4 0 T )
a (4 0 T )
4T
362T
4T
EAV
V ID E O D ATA
SAV
EAV
A N C IL L A R Y D ATA o r
B L A N K IN G C O D E W O R D S
1280T
90%
300m V
B L A N K IN G
300m V
10%
BR O AD PU LSE
f
t1
t2
BPSRT
BPSTP
Fig. 139
Symbol
a
b
c
e
f
t2 – t1
Sm
Sp
V
BPSRT
BPSTP
Rev-E-00
parameter
Negative line sync width
End of active video
positive line sync width
Start of active video
Rise/fall time
Symmetry of rising edge
Amplitude of negative pulse
Amplitude of positive pulse
Amplitude of video signal
Total Lines
Active Lines
Broad Pulse Start pos
Broad Pulse stop pos
Nominal value
0.539 [usec]
1.495 [usec]
0.539 [usec]
3.502 [usec]
0.054 [usec]
300 [mV]
300 [mV]
700 [mV]
Reference
clock Interval
40
111
40
260
4
1650
1280
260
1540
97
Tolerance
CLK
+/- 3
+/- 3
-0 / + 6
+/- 1.5
-12, +0
0 ~ +6
-6 ~ 0
Tolerance
+/- 0.040 [usec]
+0.080 [usec]
+/- 0.040 [usec]
+0.080 [usec]
+/- 0.020 [usec]
+/- 0.002 [usec]
+/- 6mV
+/- 6mV
+0.080 [usec]
- 0.080 [usec]
2008/03
[AK8825]
(6-1-2) 720p Vertical Sync waveform (60Hz) (Refer to EIA-770.3-C)
30H
25H
5H
745
746...
750
1
2
3
4
5
6
7
8....
25
26
Fig. 140
300mV
300mV
δ
γ
0H
1H
Fig. 141
δ
γ
Rev-E-00
Duration
260 T
1540T
Tolerance
-0 / +6
-6 / +0
98
2008/03
[AK8825]
(6) 720p Synchronization waveform ( EIA-770.3-C )
(6-1-1) 720p Horizontal Sync waveform (50Hz) (based on SMPTE296M）
1650T
0H
b
e (2 6 0 T )
50%
f
V /2
50%
f
V /2
Sp
f
50%
Sm
70T
1280T
c (4 0 T )
a (4 0 T )
4T
362T
4T
EAV
V ID E O D ATA
SAV
EAV
A N C IL L A R Y D ATA o r
B L A N K IN G C O D E W O R D S
1280T
90%
300m V
B L A N K IN G
300m V
10%
BR O AD PU LSE
f
t1
t2
BPSRT
BPSTP
Fig. 142
Symbol
a
b
c
e
f
t2 – t1
Sm
Sp
V
BPSRT
BPSTP
Rev-E-00
parameter
Negative line sync width
End of active video
positive line sync width
Start of active video
Rise/fall time
Symmetry of rising edge
Amplitude of negative pulse
Amplitude of positive pulse
Amplitude of video signal
Total Lines
Active Lines
Broad Pulse Start pos
Broad Pulse stop pos
Nominal value
0.539 [usec]
5.926 [usec]
0.539 [usec]
3.502 [usec]
0.054 [usec]
300 [mV]
300 [mV]
700 [mV]
Reference
clock Interval
40
440
40
260
4
1980
1280
260
1540
99
Tolerance
CLK
+/- 3
+/- 0.040 [usec]
+/- 3
-0 / +6
+/- 1.5
+/- 0.040 [usec]
+0.080 [usec]
+/- 0.020 [usec]
0 ~ +6
-6 ~ 0
+0.080 [usec]
- 0.080 [usec]
Tolerance
2008/03
[AK8825]
■
V-Blank Interval
The AK8825 has functions to set V-Blank Interval and to control Output Mode during the V-Blank Interval.
V-Blank Interval is set by HDVL[1:0]0bit of HD VBI & Chip Level Control Register [SubAddress 0x01] .
The output mode during V-Blank Interval set by VUNMASK-bit.
HD VBI & Clip Level Control Register
Sub Address 0x01
bit 7
bit 6
bit 5
HDCLPLVL1 HDCLPLVL0
Reserved
bit 4
Reserved
bit 3
Reserved
bit 2
HDVUNMSK
default Value 0x04
bit 1
bit 0
HDVL1
HDVL0
V-Blank Interval Setting
10
Line1 – Line18
Line264 – Line281
Line623 – Line20
Line311 – Line333
Line1 – Line40
Line621 – Line42
Line1124 – Line1125
Line1 – Line18
Line561 – Line581
Line746 – Line750
Line1 – Line23
525i
625i
525p
625p
1080i
720p
HDVL[1:0]-bit
11
00
Line1 – Line19
Line1 – Line20
Line264 – Line282
Line264 – Line283
Line623 – Line21
Line623 – Line22
Line311 – Line334
Line311 – Line335
Line1 – Line41
Line1 – Line42
Line621 – Line43
Line621 – Line44
Line1124 – Line1125
Line1124 – Line1125
Line1 – Line19
Line1 – Line20
Line561 – Line582
Line561 – Line583
Line746 – Line750
Line746 – Line750
Line1 – Line24
Line1 – Line25
The relation between B-Blank Interval and HDVUNMASK-bit are shown as following table
mode
525i/625i mode
525p/625p mode
1080i mode
HDVUNMSK
Blank Level output
Blank Level output
Blank Level output
0
during V-Blank Interval during V-Blank Interval during V-Blank Interval
1
Rev-E-00
Input data is output
even during V-Blank
Interval
(525i : Line1-9 &
Line264-272
625i : Line623-7 &
Line311-318
are excluded)
Input data is output
even during V-Blank
Interval
( 525p : Line1-12
625p : Line641-5
are excluded )
100
Input data is output
even during V-Blank
Interval
(Line1124-1125-6 &
Line561-568
are
excluded)
01
Line1 – Line21
Line264 – Line284
Line623 – Line23
Line311 – Line336
Line1 – Line43
Line621 – Line45
Line1124 – Line1125
Line1 – Line21
Line561 – Line584
Line746 – Line750
Line1 – Line26
720p mode
Blank Level output
during V-Blank Interval
Input data is output
even during V-Blank
Interval
(Line746-750-5
excluded )
are
2008/03
[AK8825]
■
Adjustable Timing Function Between SYNC signal and HDY Signal, Between HDPB Signal and HDPr signal
SYNC Timing and Y signal output relation is adjustable in the AK8825. Setting of adjustable amount is made by
HDYDELAY[2:0]-bit of HDYPBPR Delay Control Register [SubAddress 0x02].
Adjustable range between SYNC signal and Y signal is +/- 3clocks.
Adjustable unit in 525i / p mode is based on 27MHz clock and in 1080i/720p modes it is based on 74.25MHz clock.
By this bit manipulation, Pb/Pr are shifted similarly as in the case of Y.
Pb / Pr signals with Y signal relation are adjusted by PBPRDELAY[2:0]-bit of HDYPBPR Delay COntrol Register
[SubAddress0x02].
Adjustable range is +/- 3clocks. Adjustable unit in 525i / p modes is based on 27MHz clock, and in 080i/720p modes, it is based
on 74.25MHz.
244T @ 27MHz
Y
Y
(default)
247T @ 27MHz
241T @ 27MHz
Y
Pb/Pr
27MHz-clock
3clk 3clk
Y signal and PbPr signal relation
SYNC signal and Y signal relation
Fig. 143
Y
525i/p, 625i/p mode
Y
188T @ 74.25MHz
(default)
Pb/Pr
Y
74.25MHz-clock
185T @ 74.25MHz
3clk 3clk
191T @ 74.25MHz
Y signal and PbPr signal relation
SYNC signal and Y signal relation
Fig. 144 1080i mode
Rev-E-00
101
2008/03
[AK8825]
Y
Y
256T @ 74.25MHz
(default)
Pb/Pr
Y
74.25MHz-clock
253T @ 74.25MHz
3clk 3clk
259T @ 74.25MHz
Y signal and PbPr signal relation
SYNC signal and Y signal relation
Fig. 145 720p mode
Rev-E-00
102
2008/03
[AK8825]
■ Analog RGB Signal Output
RGB conversion ( 601 Color Space and always Sync-On-Green(SOG) ) is possible only with 525i / 625i or SDTV input.
Conversion Factors
R=Y
+ 1.372 * ( Cr + 128 )
G = Y + 0.336 * ( Cb + 128 ) + 0.698 * ( Cr + 128 )
B = Y + 1.732 * ( Cb + 128 )
RGB signals are output at the same timing as in YPbPr conversion and their levels are RGB Matrix results.
A similar SYNC signal is carried out on G signal.
The AK8825 outputs RGB signal by setting YC2RGB-bit of I/O Data Format Register.
I/O Data Format Register
Sub Address 0x0B
bit 7
bit 6
HDSDMASE
YC2RGB
bit 5
Reserved
bit 4
DTFMT
bit 3
CONVMOD1
bit 2
CONVMOD0
default Value 0x00
bit 1
bit 0
INPFMT1
INPFMT0
Input Data
analog RGB Output
YC2RGB-bit
YCbCr Data
1
RGB Data*
0
* AK8825 doesn’t support EAV decode Interface mode in case of RGB Data in.
Input Data
Rev-E-00
103
2008/03
[AK8825]
■
Video ID (CEA-805-A / CEA-805-B)
The AK8825 has a function to super impose a Copy Protect Information CGMS-A on output signal.
The AK8825 supports both of CEA-805-A and CEA-805-B standards.
(1) CEA-805-A
700mV
H : White Peak (70+/- 10)%
Ref
70%
bit1
bit2
bit3
bit20
L : 0 (+10 / - 5) %
0H
0
b
a
-300mV
c
Fig. 146
a
b
c
Line
11.2 +/- 0.3usec
Line 20
2.235 +/- 50nsec
49.1 +/- 0.44usec
(time from 0H)
Line 283
6T (5.8 +/- 0.15usec)
22T
T : 1/(fH x 33)
T +/- 30nsec
Line 41
(time from 0H)
(21.2 +/- 0.22usec)
= 963nsec
Line 19
4T
22T
T : 1/(fH x 2200/77)
1080i
T +/- 30nsec
= 1.038usec
Line 582
( 4.15 +/- 0.16usec)
( 22.84 +/- 0.21usec)
4T
22T
T : 1/(fH x 1650/58)
Line 24
720P
T +/- 30nsec
= 0.782usec
(3.13 +/- 0.09usec)
(17.20+/- 0.16usec)
* SYNC signal waveform of 525i/p signals differ from the above, but timing is defined based on 0H point as starting point (time
from 0H).
525i*
(480i)
525P*
(480P)
bit
Data
1
2
WORD 0
2bits
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
CRCC
6bits
WORD 2
8bits
WORD 1
4bits
15
20 bit data is configured with WROD 0: 2bits / WROD 1: 4 bits / WORD 2: 8 bits / CRCC: 6 bits, as shown above.
When to set CGMS-A data, set HDVBIDEN-bit of HD VBID Data 1 Register [SubAddress 0x03] to “1”, and write a setting
value to HD VBID Data 1/2 Register[SubAddress 0x03/0x04].
HD VBID Data 1 Register
Address 0x03
bit 7
bit 6
HDVBIDEN
Reserved
bit 5
HDVBID1
bit 4
HDVBID2
bit 3
HDVBID3
bit 2
HDVBID4
Default Value 0x00
bit 1
bit 0
HDVBID5
HDVBID6
HD VBID Data 2 Register
Address 0x04
bit 7
bit 6
HDVBID7
HDVBID8
bit 5
HDVBID9
bit 4
HDVBID10
bit 3
HDVBID11
bit 2
HDVBID12
Default Value 0x00
bit 1
bit 0
HDVBID13
HDVBID14
Rev-E-00
104
2008/03
[AK8825]
CGMS-A data should be finished being written 1-line before of the target lines.
CGMS-A data Out
2
I C Write
525i: Line20 / Line283
525p: Line41
1080i: Line19 / Line582
720p: Line24
Data(n)
Fig. 147
CRCC is automatically calculated and added in the AK8825.
Default value of “CRCC Polynomial expressed X6+X+1” are all ones (see diagram bellow)
SW1
D
D
D
D
D
D
b
Input
SW2
Output
a
Fig. 148
CRCC generation is made as follows Set default values to all ones and closed SW1.
Set SW2 to “a” position and first 14bit data is input, then at the 15th bit open SW1 and set SW2 to “b” position, and CRCC is
output.
When CGMS-A output and other signal waveforms coincide, CGMS-A precedes.
Rev-E-00
105
2008/03
[AK8825]
(2) CEA-805-B
This standard is adopted to 480p / 1080i / 720p output mode. CEA805-B Type-A standard is same as CEA-805-A standard.
700mV
S SB : Star Symbol
70%
•
•
p127
p126
p8
p7
p6
p5
p4
p3
p2
p1
p0
h5
h4
h3
h2
h1
h0
0H
H : White Peak (70+/- 10)%
•
0
b
a
-300mV
b
L : 0 (+10 / - 5) %
b
b
Fig. 149
1
480P*
a
156T
(Time from 0H)
b
Tolerance form 0H
4T
+/- 18.5ns
Line
T : 1/27MHz
Line 43
Line 18
Line 581
720P
232T*2
8T
+/- 18.5ns
T : 1/74.25MHz
Line 23
*1 SYNC signal waveform of 480p differ from the above, but timing is defined based on 0H point as starting points.
*2 position of 232T is the position before starting active video area.
1080i
308T
10T
+/- 18.5ns
T : 1/74.25MHz
When to set CEA-805-B TypeB Data, set HDCEA805B-bit of HD Block Miscellaneous Control Register[SubAddress 0x0A]
to “1”, and write a setting value to VBID-B Header Data Register/VBID Version Number Register/VBID Payload Packet
Length Register/VBID-B Data1/2/3/4/5/6/7/8/9/10/11/12/13 Register {SubAddress 0x40 - 0x50}
CRCC is automatically calculated and added in the AK8825.
Default values of “CRCC Polynomial expression X6+X+1” are all ones (see diagram bellows)
SW1
D
D
D
D
D
D
b
Input
SW2
Output
a
Fig. 150
Rev-E-00
106
2008/03
[AK8825]
■
Closed Caption
The description about “Closed Caption” is written in [6. Common Function Specification].
Closed Caption function is valid at 525i mode.
■
WSS
The description about “WSS” is written in [6. Common Function Specification].
WSS function is valid at 625i /625p mode.
■
RGB Output
The AK8825 can output Analog RGB signal with digital RGB Data in.
YC2RGB-bit of I/O Data Format Register [SubAddress 0x0B] is a control bit for RGB output function.
I/O Data Format Register
Sub Address 0x0B
bit 7
bit 6
HDSDMASE
YC2RGB
YC2RGB-bit
0
1
■
bit 5
Reserved
Output signal
YUV Output
RGB Output
bit 4
DTFMT
bit 3
CONVMOD1
bit 2
CONVMOD0
default Value 0x00
bit 1
bit 0
INPFMT1
INPFMT0
Note
DAC operating clock
The AK8825 has x2 PLL, DAC works with this x2 clock in Component Video Encoder mode. Following table shows DAC
operation clock of each mode.
Input Data
DAC Operation Clock
Rev-E-00
525i/625i
54MHz
525p/625p
54MHz
1080i
148.5MHz
107
720p
148.5MHz
2008/03
[AK8825]
8. Composite Video Encoder Block
■
Block Diagram
From
Timing
Generator
SD-Timing
Generator
CGMS-A
WSS
Y[7:0
SYNC
Generator
sin(x)/x
Y[9:0]
to DAC
sin(x)/x
CVBS[9:0]
to DAC
sin(x)/x
C[9:0]
to DAC
x2
LPF-A
13.5MHz
U
Cb[7:0]
C
Cr[7:0]
4:2:2 to 4:4:4
LPF-B
cos
6.75MHz
From
Clock Gen
27MHz
x2
LPF-C
V
13.5MHz
sin
DFS
27MHz
Fig. 151 Composite Video Encoder Block Diagram
Rev-E-00
108
2008/03
[AK8825]
■
Setting of Output Signal
SDVM[3:0]-bit of SD Block Control Register [SubAddress0x11] defines the output signal from the AK8825.
SD Block Control Register
Sub Address 0x11
bit 7
bit 6
SDBBG
SDCBG
bit 5
SDSETUP
bit 4
SCR
bit 3
SDVM3
Table of the relation between output signal and SDVM[3:0]-bit
SDVM0 SDVM1 SDVM2 SDVM3
SCR
NTSC
0
0
0
0
1
NTSC-4.43
1
1
0
0
0
PAL
1
1
1
1
1
PAL-M
1
0
1
0
1
PAL-60
1
1
1
0
0
PAL-Nc
0
1
1
1
1
Rev-E-00
109
bit 2
SDVM2
Default Value 0x10
bit 1
bit 0
SDVM1
SDVM0
Note
Setup-bit should be set, if it is necessary
2008/03
[AK8825]
■
Video Signal Filter
(1) Luminance Filter
Luminance Filter of Composite Video Encoder can be selectable by register setting. Register-bit for filter setting is SD Block
FLT Register(R/W) SDYLFT[1:0]-bit.
SD Block FLT Register
Sub Address 0x14
bit 7
bit 6
Reserved
Reserved
bit 5
Reserved
SDYFLT [1:0] -bit
00
01
10
bit 4
SDYFLT1
bit 3
SDYFLT0
Selected Filter
YFLT0
YFLT1
YFLT2
bit 2
Reserved
default Value 0x00
bit 1
bit 0
Reserved
Reserved
Note
Default
Characteristics of each filter are shown as Fig. 152.
10
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0 11.0 12.0 13.0
Gain[dB]
-10
-20
YFLT1
-30
YFLT2
YFLT0
-40
-50
-60
Frequency[MHz]
Fig. 152 LPF-A
Rev-E-00
110
2008/03
[AK8825]
(2) Chrominance Filter
(2-1) Over-Sampling Filter(6.75Mhz -> 13.5MHz) for Cb/Cr Data in Composite Video Encoder Block. (LPF-B)
Frequency Response of this Filter is shown as Fig. 153
10
0
Gain[dB]
-10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
-20
-30
-40
-50
-60
Frequency[MHz]
Fig. 153
LPF-B Frequency Response
(2-2) Over-Sampling Filter(6.75Mhz -> 13.5MHz) for C Data in Composite Video Encoder Block. (LPF-C)
Frequency Response of this Filter is shown as Fig. 154
10
0
0.0 1.0
2.0 3.0 4.0
5.0 6.0 7.0
8.0 9.0 10.0 11.0 12.0 13.0
Gain[dB]
-10
-20
-30
-40
-50
-60
Frequency[MHz]
Fig. 154
Rev-E-00
LPF-C Frequency Response
111
2008/03
[AK8825]
■
Color Burst Signal (SDTV)
Color burst signal is generated by 32bits-length Digital Frequency Synthesizer. Subcarrier Frequency of Color-Burst is set by
SDVM0-SDVM1 -bits of SD Block Control Register (R/W) [Sub Address 0x11].
SD Block Control Register
Sub Address 0x11
bit 7
bit 6
SDBBG
SDCBG
bit 5
SDSETUP
bit 4
SCR
bit 3
SDVM3
bit 2
SDVM2
Standard
Subcarrier Freq
(MHz)
Video Process 1
[SDVM1,SDVM0]
NTSC-M
3.57954545
[0,0]
PAL-M
3.57561188
[0,1]
PAL-B,D,G,H,I
4.43361875
[1,1]
PAL-N(Arg)
3.5820558
[1,0]
PAL-N(non-Arg)
4.43361875
[1,1]
PAL60
4.43361875
[1,1]
4.43361875
[1,1]
NTSC-4.43
Default Value 0x10
bit 1
bit 0
SDVM1
SDVM0
Burst Table
Sub-carrier frequency 3.57561188MHz is allowed when PAL-M mode is selected.
Sub Carrier Frequency and Sub Carrier Phase are set by Sub Carrier Frequency Control Register (R/W) [Sub Address
0x16] Sub Carrier Phase Control Register (R/W) [Sub Address 0x17].
The burst frequency and initial phase resolution are as follows.
Frequency resolution
SCH Phase resolution
Rev-E-00
0.8046Hz
360°/256
112
2008/03
[AK8825]
■
Video Interface Timing (Composite Video Encoder Block)
To synchronize with input data, AK8825 supports two kinds of interface mode.
(1) ITU-R BT.656 interface mode
(2) Slave operation with HD/VD Interface mode
This interface mode is set by REC656-bit of
SD Blanking Set Register
Sub Address 0x10
bit 7
bit 6
SDBLN4
SDBLN3
REC656-bit
0
1
SD Blanking Set Register (R/W) [Sub Address 0x10].
bit 5
SDBLN2
bit 4
SDBLN1
Interface mode
Slave operation with HD/VD
ITU-R.BT656 I/F mode
bit 3
SDBLN0
bit 2
Reserved
Default Value 0xA1
bit 1
bit 0
Reserved
REC656
Note
(1) ITU-R BT.656 I/F mode
When AK8825 receives ITU-R BT. 656 signal, AK8825 decodes [EAV] code in the data for synchronization then outputs the
HSYNC. AK8825 outputs HSYNC at the rising edge of SYSCLK in the timing of the 32nd/24th (NTSC/PAL) data slot, which is
counted from the [EAV] starting point as below.
REC656-bit=1 of SD Blanking Set Register (R/W) [Sub Address 0x10] should be “0” for setting to this mode.
Y/Cb/Cr
Data#
525 system
Data#
625 system
Cb
EAV
Y Cr
Y
Cb
Y
Cr
Y
Cb
Y
Cr
Y
Cb
SAV
Y Cr
Y
Cb
Y
Cr
Y
Cb
360 720 360 721 361 722 361 723
368 736 368
855 428 856 428 857
0
0
0
1
1
360 720 360 721 361 722 361 723
366 732 366
861 431 862 431 863
0
0
0
1
1
CLKIN
33/ 25T(525/ 625)
243/ 263T(525/ 625)
276/ 288T(525 / 625)
HDI
Analog Out
Fig. 155
Rev-E-00
113
2008/03
[AK8825]
(2) Slave mode
On slave mode operation, HSYNC and VSYNC are input to AK8825.
AK8825 monitors the transition of HSYNC at the timing of the rising edge of SYSCLK. After AK8825 recognizes HSYNC is
Low-logic, AK8825 sets the slot number to the 32nd/24th (NTSC/PAL), internally, then AK8825 starts to sample the data as Cb
on 276th/288th (NTSC/PAL) slot.
Video field is recognized the transition timing between VSYNC and HSYNC. As in the figure, there is a tolerance of ±1/4H.
This interface mode is set by REC656-bit =0 of SD Blanking Set Register (R/W) [Sub Address 0x10].
244T / 264T (525/625)
27MHz
Data
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
HDI
Fig. 156 Relation between HSYNC and Data
Field Detection with HSYNC and VSYNC
1/2 H
1/2 H
HDI
1st Field
1/4 H 1/4 H
VDI
2nd Field
1/4 H 1/4 H
VDI
Fig. 157 HD/VD timing
Rev-E-00
114
2008/03
[AK8825]
Relation between Line# and VD is shown as Fig.158
525-Line System
Digital
Line-No.
525
1
2
3
4
5
6
7
8
9
10
11
HDI
VDI
Fig. 158 1st Field
Digital
Line-No.
262
263
264
265
266
267
268
269
270
271
272
273
274
HDI
VDI
Fig. 159 2nd Field
625 Line System
Digital
Line-No.
622
623
624
625
1
2
3
4
5
6
7
8
319
320
HDI
VDI
Fig. 160 1st Field
Digital
Line-No.
310
311
312
313
314
315
316
317
318
HDI
VDI
Fig. 161 2nd Field
Rev-E-00
115
2008/03
[AK8825]
■
SYNC Signal Waveform, Burst Waveform (SD)
(1-1) NTSC / NTSC-4.43 / PAL-M(SD Block Control Register [SDVM3:SDVM2]-bit = 00 / 01 の場合)（SMPTE-170M ）
H o r iz o n ta l B la n k in g r is e t im e
90%
50%
50%
B u r s t E n v e lo p e
r is e t im e
90%
S y n c r is e t im e
10%
10%
B u r s t H e ig h t
90%
B u rs t
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
S ync Le vel
10%
S ync
H . r e f . t o B u r s t S ta r t
H b la n k in g s ta r t
to H -re fe re n c e
H r e f e r e n c e to B la n k in g E n d
Fig. 162
measurement
point
Total line period(derived)
Sync Level
Horizontal Blanking rise time
Sync rise time
Burst envelope rise time
H-Blanking start to H-reference
Horizontal Sync
Horizontal reference point to
burst start
H reference to H-blanking end
Burst *
Burst Height **
value
Recommended
tolerance
units
10% - 90%
10% - 90%
10% - 90%
50%
50%
63.556
40
140
140
300
1.5
4.7
+/- 1
+/- 20
+/- 20
+200 -100
+/- 0.1
+/- 0.1
usec
IRE
nsec
nsec
nsec
usec
usec
50%
19
defined by SC/H
cycles
50%
50%
9.2
9
40
+ 0.2 - 0.1
+/- 1
+/- 1
usec
cycles
IRE
* measurement of Burst Timing Length is made between the Burst Start Point which is defined as the zero-cross point,
preceding the first-half cycle of the sub-carrier where Burst Amplitude becomes higher than 50 % level and the Burst End Point,
defined in the same manner.
Burst Time Length ( period ) is 10 cycles in NTSC-4.43 mode.
** Burst Height of PAL-M mode is 306 mV.
19 cycles +/-10°
9 cycles
50%
Fig. 163 NTSC Color Burst
Rev-E-00
116
2008/03
[AK8825]
(1-2-1) Vertical SYNC Signal Timing (NTSC/NTSC4.43)
3H
B
A
1
3H
E
0 .5 H
2
3H
F
D
3
4
5
C
6
7
8
9
19
1 9 + 1 /- 2 L in e
(レ ジ ス タ に て 設 定 )
3H
3H
3H
0 .5 H
263
264
265
266
267
268
269
270
271
272
273
283
Fig. 164
Symbol
A
B
C
D
E
F
Duration
429T
858T
31T
429T
858T
63T
Measurement point
Reference
50%
13.5MHz Clock
G
I
H
I
I
Equalizing Pulse
I
286mV
Serration Pulse
Fig. 165 Equalizing Pulse and Serration Pulse
Symbol
Measurement
point
Value
Field Period (derived)
16.6833
Frame period (derived)
33.3667
Vertical blanking start before first
50%
1.5
equalizing pulse
Vertical blanking
19* lines + 1.5
(63.556usec x 20lines + 1.5usec)
usec
Pre-equalizing duration
3
G
Pre-equalizing pulse width
50%
2.3
Vertical sync duration
3
H
Vertical serration pulse width
50%
4.7
Post-equalizing duration
3
G
Post-equalizing pulse width
50%
2.3
I
Sync rise time
140
* There is a case with V-Blank of 20 Lines. This value is pre-settable by register.
Rev-E-00
117
Recommended
tolerance
units
msec
msec
+/- 0.1
usec
0
+/- 0.1
lines
usec
lines
usec
lines
usec
lines
usec
nsec
+/- 0.1
+/- 0.1
+/- 0.1
+/- 20
2008/03
[AK8825]
(1-2-2) Vertical SYNC Signal Timing and Burst Phase (PAL-M)
A
519
257
520
258
521
259
522
523
260
524
261
525
262
1
263
2
264
3
265
4
266
5
267
6
268
7
269
8
9
A
B
270
271
A
519
257
520
258
521
259
522
260
523
524
261
525
262
263
1
2
264
3
265
4
266
5
267
6
268
269
10
272
B
7
8
A
B
270
B
9
271
10
272
Fig. 166
A: Phase of Burst: nominal Value + 135°
B: Phase of Burst : nominal Value - 135°
Rev-E-00
118
2008/03
[AK8825]
(2-1) PAL-B,D,G,H,I,N / PAL-60 (SD Block Control Register[SDVM3:SDVM2]-bit = 11)
H o r iz o n ta l B la n k in g r is e t im e
90%
50%
50%
B u r s t E n v e lo p e
r is e t im e
90%
S y n c r is e t im e
10%
10%
B u r s t H e ig h t
90%
B u rs t
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
S ync Le vel
10%
H o r iz o n ta l S y n c
H . r e f . t o B u r s t S ta r t
H b la n k in g s ta r t
to H -re fe re n c e
H r e f e r e n c e to B la n k in g E n d
Fig. 167
measurement
point
Total line period(derived)
Sync Level
Horizontal Blanking rise time
Sync rise time
Burst envelope rise time
H-Blanking start to H-reference
Horizontal Sync
Horizontal reference point to
burst start
H reference to H-blanking end
Burst *
Burst Height **
Rev-E-00
value
Recommended
tolerance
units
64.0
300
0.3
0.2
+/- 0.1
+/- 0.1
1.5
4.7
+/- 0.3
+/- 0.2
usec
mV
usec
usec
nsec
usec
usec
50%
19
defined by SC/H
cycles
50%
50%
10.5
10
300
+/- 1
usec
cycles
mV
10% - 90%
10% - 90%
10% - 90%
50%
50%
119
2008/03
[AK8825]
(2-2) Vertical SYNC Signal Timing and Burst Phase
PAL-B,D,G,H,I,N / PAL-60 (SD Block Control Register [SDVM3:SDVM2]-bit = 11)
A
308
620
308
620
309
621
309
621
310
622
311
623
310
622
312
624
311
623
625
312
624
313
314
1
313
625
315
2
314
1
316
3
315
2
317
4
316
3
318
5
317
4
5
319
320
A
B
6
7
A
B
318
319
A
B
6
B
322
321
322
8
320
7
321
8
Fig. 168
A: Phase of Burst: nominal Value + 135°
B: Phase of Burst: nominal Value - 135°
Rev-E-00
120
2008/03
[AK8825]
■
Video ID
The AK8825 supports to encode the Video ID (EIAJ CPR-1204) which distinguishes the Aspect Ratio etc...
This is also used as CGMS (Copy Generation Management System).
Turning “ON / OFF “of this function is controlled by SDVBID-bit of SD/HD V-Blanking Control Register (R/W) [Sub Address 0x12]
and setting data is set by SD VBID-A Data1/Data2 Register ( 0x2A, 0x2B ).
Video ID information has the highest order of priority among VBI information (when simultaneous output with Macrovision
signaling occurs, only the VBI information is super-imposed on this line).
As for the Video ID setting for component Video Encoder mode is described in another section.
VBID Data Up-date Timing
VSYNC
S et C ontro l R egister
u-P D a ta
N EW D AT A
DATA
O LD D A T A
N EW D AT A
Fig. 169
VBID Data Code Assignment
20 bit data is configured with Word0 = 2 bits, Word1 = 4 bits, Word2 = 8 bits, CRC = 6 bits.
CRC is automatically calculated and added in the AK8825.
Default values of “CRC Polynomial Expression X6 + X + 1” are all ones.
bit1
bit20
DATA
WORD0
2bit
WORD1
4bit
WORD2
8bit
CRC
6bit
VBID Waveform
Ref.
bit1 bit2 bit3
•••
bit20
70IRE +/- 10IRE
0IRE + 10 IRE
− 5 IRE
2.235usec +/- 50nsec
11.2usec +/- 0.3usec
49.1usec +/- 0.44usec
1H
Fig. 170
525/60 System
70IRE
20/283
amplitude
encode line
Rev-E-00
121
2008/03
[AK8825]
■
Closed Caption
The description about “Closed Caption” is written in [6. Common Function Specification].
■
WSS
The description about “WSS” is written in [6. Common Function Specification].
Rev-E-00
122
2008/03
[AK8825]
9. High Speed Video DAC mode
■
Block Diagram
Data
HDI
Level
Converter
DAC
Delay
(+/-3clk)
HDO
VDO
VDI
Fig. 171 High Speed Video DAC mode
■
Input Data Format
Input Data
RGB565
RGB666
■
Output
Analog RGB
Analog RGB
Operation
Digital RGB Data is converted to Analog RGB signal by DAC
Digital RGB Data is converted to Analog RGB signal by DAC
Full-Scale Code and Level Conversion
Input data is expanded to 10-bit, then it is converted to analog signal with DAC.
Full-Scale code is shown as following table.
RGB565
RGB666
R=0x3F0
R=0x3E0
G=0x3F0
Full-Scale Code
G=0x3F0
B=0x3F0
B=0x3E0
The DAC output Level at Full-Scale Code can be set with OLVL-bit of DAC Control Register [SubAddress 0x0D].
DAC Control Register
Sub Address 0x0D
bit 7
bit 6
Reserved
Reserved
OLVL-ibit
0
1
Rev-E-00
bit 5
OLVL
bit 4
DTRSTN
bit 3
CVBSSEL
bit 2
DAC3EN
default Value 0x00
bit 1
bit 0
DAC2EN
DAC1EN
Output Level [V]
1.28V (typ)
0.7V (typ)
123
2008/03
[AK8825]
■
Delay Function for Input Timing Signal
Input Timing Signal can be delayed by setting Register. Amount of adjustment is +/- 3-clock.
Delay adjustment is controled by Video DAC Delay Control Register [SubAddress0x51].
Video DAC Delay Control Register
Sub Address 0x51
bit 7
bit 6
bit 5
Reserved
Reserved
Reserved
bit 4
Reserved
bit 3
Resrved
bit 2
HDLY2
default Value 0x00
bit 1
bit 0
HDLY1
HDLY0
Amount of Delay is set wit 2’s Compriment.
HDLY[2:0]-bit
Delay
000
Delay 0
001
1CLK Delay
010
2CLK Delay
011
3CLK Delay
111
1CLK Advanced
110
2CLK Advanced
101
3CLK Advanced
Rev-E-00
124
2008/03
[AK8825]
10. AK8825 Register Definition
■
Register Map
SubRegister
Address
0x00
HD Mode Register
0x01
HD VBI & Clip Level Control Register
0x02
HDYPBPR Delay Control Register
0x03
HD VBID Data 1 Register
0x04
HD VBID Data 2 Register
Default
R/W
0x00
0x04
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
Function
Component Video Encoder Setting
Setting for VBI Intervale & Clip
Delay Adjustment for Component Video Block
VBID Data Setting Reigster
0x05
Reserved Register
0x00
R/W
0x06
0x07
Powerdown Mode Register
HD Block Control Register
0x00
0x00
R/W
R/W
0x08
0x09
0x0A
0x0B
0x0C
HD WSS Data 1 Register
HD WSS Data 2 Register
HD Block Miscellaneous Control Register
I/O Data Format Register
I/O Pin Control Register
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
0x0D
DAC Control Register
0x00
R/W
Control DAC
0x10
0x11
0x12
0x13
SD Blanking Set Register
SD Block Control Register
SD/HD V-Blanking Control Register
SD Block Delay Register
0xA1
0x10
0x00
0x00
R/W
R/W
R/W
R/W
Setting VBI Interval for Composite Video Encoder
Control Regsiter for Composite VIdeo Encoder mode
Setting VBI Interval signal
Delay Control Register for Composite Video Encoder
0x14
0x15
0x16
0x17
0x18
0x19
SD Block FLT Register
Reserve Register
Sub Carrier Frequency Control Register
Sub Carrier Phase Control Register
SD WSS Data 1 Register
SD WSS Data 2 Register
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
Setting Luminance Filter
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
Macrovision 1 Register
Macrovision 2 Register
Macrovision 3 Register
Macrovision 4 Register
Macrovision 5 Register
Macrovision 6 Register
Macrovision 7 Register
Macrovision 8 Register
Macrovision 9 Register
Macrovision 10 Register
Macrovision 11 Register
0x0F
0xFC
0x20
0xD0
0x6F
0x0F
0x00
0x00
0x0C
0xF3
0x09
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Macrovision Register
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
Closed Caption Data 1 Register
Closed Caption Data 2 Register
CC Extended Data 1 Register
CC Extended Data 2 Register
SD VBID-A Data1 Register
SD VBID-A Data2 Register
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
Closed Caption Data Set-Register for Composite
Video Encoder Block
Closed Caption Extended Data Set-Register for
Composite Video Encoder block
VBID Data Set-Register for Composite Video
Encoder Block
Macrovision 12 Register
Macrovision 13 Register
Macrovision 14 Register
Macrovision 15 Register
Macrovision 16 Register
Macrovision 17 Register
Macrovision 18 Register
0xE3
0xBD
0x66
0xB5
0x90
0xB2
0x7D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Macrovision Register
0x34
0x35
Status Register
Device ID & Revision ID Register
0x00
0x25
R
R
Rev-E-00
125
Setting for Power Down
WSS Data Register for Component Video Encoder
Control Register for Component Video Encoder
Setting I/O Data format
Setting I/O Pin configration
Adjust Subcarrier Frequency
Adjust Subcarrier Phase.
WSS Data Register for WSS
Status Register
Device ID and Revision ID Register
2008/03
[AK8825]
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
TEST Register 1
TEST Regster 2
TEST Regster 3
TEST Regster 4
TEST Regster 5
TEST Regster 6
TEST Regster 7
TEST Regster 8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Test Register
Test Register
Test Register
Test Register
Test Register
Test Register
Test Register
Test Register
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
VBID-B Header Data Register
VBID-B Version Number Register
VBID-B Payload Packet Length Register
VBID-B Payload Data1 Register
VBID-B Payload Data2 Register
VBID-B Payload Data3 Register
VBID-B Payload Data4 Register
VBID-B Payload Data5 Register
VBID-B Payload Data6 Register
VBID-B Payload Data7 Register
VBID-B Payload Data8 Register
VBID-B Payload Data9 Register
VBID-B Payload Data10 Register
VBID-B Payload Data11 Register
VBID-B Payload Data12 Register
VBID-B Payload Data13 Register
VBID-B Payload Data14 Register
0x08
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Setting VBID Header
SettingVBID Version Number
Setting VBID Packet Length
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
Setting VIBD Payload Data
0x51
Video DAC Delay Control Register
0x00
R/W
Delay control Regsiter for High Speed DAC mode
* Write default values (0x00) to TEST Register(TEST Register 1 to TEST Register 8), if it is necessary to access these registers.
Rev-E-00
126
2008/03
[AK8825]
Rev-E-00
127
2008/03
[AK8825]
HD Mode Register (R/W) [Sub Address 0x00]
[Component Video Encoder]
Register to set the AK8825 mode at Component Video Encoder mode
Sub Address 0x00
bit 7
bit 6
HDCBG
HDBBG
0
0
bit 5
HDSETUP
0
HD Mode Register (R/W) [Sub Address 0x00]
BIT Register Name
bit 4
bit 3
HDEAVDEC
HDCEA861
Default Value
0
0
R/W
bit 0
HDRFRSH
Refresh Rate bit
R/W
bit1
~
bit2
HDMODE0
~
HDMODE1
Mode Set bit
R/W
bit3
HDCEA861
H/V timing std bit
R/W
bit 4
HDEAVDEC
EAV Decode bit
R/W
bit 5
HDSETUP
HD Setup-bit
R/W
bit 6
HDBBG
HD Black Burst bit
R/W
bit 7
Rev-E-00
HDCBG
HD Color Bar bit
R/W
bit 2
HDMODE1
default Value 0x00
bit 1
bit 0
HDMODE0
HDRFRSH
0
0
0
Definition
to select refresh rate
0 : 60Hz
1 : 50Hz
to select input / output signals
[HDMODE1:HDMODE0]
00 : 525i/625i
01 : 525p/625p
10 : 1080i
11 : 720p
to appoint relation when to synchronize with HSYNC / VSYNC
0: Data capture is done by the AK8825 timing.
1: it is done by the compatible timing specified in CEA 861B.
When EAVDEC: 1, this bit is ignored.
to select the AK8825 Sync mode
0 : to be synchronized with HSYNC / VSYNC signals
1 : to be synchronized with EAV
to set on / off of 7.5 % set-up
0: no set-up process is done.
1: set-up process is done.
to output Black Burst Signal ( SYNC Signal Output only )
0 : normal output
1: Black Burst Signal Output is enabled.
to output Color Bar Signal
0 : normal output
1: Color Bar Signal is output.
When HDBB bit is set, HDBB is prioritized.
128
2008/03
[AK8825]
HD VBI & Clip Level Control Register (R/W) [Sub Address 0x01]
[Component Video Encoder]
VBI, Clipping level of output is set.
Sub Address 0x01
bit 7
bit 6
HDCLPLVL1 HDCLPLVL0
0
0
bit 5
Reserved
0
bit 4
bit 3
Reserved
Reserved
Default Value
0
0
bit 2
HDVUNMSK
bit 1
HDVL1
1
0
default Value 0x04
bit 0
HDVL0
0
HD VBI & Clip Level Control Register (R/W) [Sub Address 0x01]
BIT Register Name
R/W
Definition
Adjust VBI blanking lines.
Final lines of the blanking period are adjusted. Values are relative
number of the default line (line 20).
HDVL0
bit 0
~
HD VB Setting
R/W [HDVL1:HDVL0]-bit
~
01:increased by 1 line
HDVL1
bit 1
00: default
11: decreased by 1 line.
10: decreased by 2 lines.
Sets the masking action during V-Blanking periods.
0 : during V-Blanking outputs are masked.（Black is outputs）
1: normal operation. (Input data is output during V-Blanking
periods.)
Following lines are in the interest.
bit 2
HDVUNMSK
V-Blank Unmask bit
R/W
525i : 10 - 20(+/-VL[1:0]) and
273- 283(+/-VL[1:0]) Line
525P : 13 - 42(+/-VL[1:0]) Line
1080i : 7 - 20(+/-VL[1:0]) line and
569 - 583(+/-VL[1:0]) line
720P : 6 - 24(+/-VL[1:0]) lien
bit 3
~
bit 5
bit 6
~
bit 7
Rev-E-00
Reserved
HDCLPLVL0
~
HDCLPLVL1
Reserved bit
HD Clamp Level bit
R/W
Reserved, write 0x00
R/W
Define clipping level of the over sampling filter.
[HDCLPLVL1:HDCLPLVL0] =
00:no clipping
01: clips at about -7.0 IRE below pedestal level.
10: clips at about -1.5 IRE below pedestal level.
11:Reserved
129
2008/03
[AK8825]
HDYPBPR Delay Control Register (R/W) [Sub Address 0x02]
[Component Video Encoder]
Delay amounts of Y signal and Pb / Pr signals are set.
Sub Address 0x02
bit 7
bit 6
Reserved
PBPRDLY2
0
0
bit 5
PBPRDLY1
0
bit 4
bit 3
PBPRDLY0
Reserved
Default Value
0
0
bit 2
HDYDELAY2
0
Default Value 0x00
bit 1
bit 0
HDYDEALY1 HDYDELAY0
0
0
HDYPBPR Delay Control Register (R/W) [Sub Address 0x02]
BIT Register Name
R/W
Definition
Luminance signal delay amount is set. It is a delay from SYNC
signal.
Delay amount is set based on 27 MHz clock in 480i / p modes,
and 74.25 MHz in 1080i / 720p modes.
[ HDYDELAY2 : YDELAY1 ] - bit
000 : delay amount 0
HDYDELAY0
bit 0
001: 1 CLK time is delayed.
~
HDY Delay Set bits
R/W 010: 2 CLK time is delayed.
~
HDYDELAY2
bit 2
011: 3 CLK time is delayed.
bit 3
Reserved
Reserved bit
R/W
bit 4
~
bit 6
PBPRDLY0
~
PBPRDLY2
C Delay Set bits
R/W
bit 7
Rev-E-00
Reserved
Reserved bit
R/W
111: advance 1 CLK time to output.
110: advance 2 CLK time to output.
101: advance 3 CLK time to output.
100 : reserved
Reserved, write “0 “.
Chroma signal delay amount is set. It is a delay from Luminance
signal.
Delay amount is set, based on 27 MHz clock in 480i/p modes, and
74.25 MHz in 1080i / 720p modes.
Both Pb / Pr are delayed by same amount by Delay Amount
setting.
[ PBPRDLY2 : PBPRDLY0 ] – bit
000: delay amount 0
001: 1 CLK time is delayed.
010: 2 CLK time is delayed.
011: 3 CLK time is delayed.
111: advance 1 CLK time to output.
110: advance 2 CLK time to output.
101: advance 3 CLK time to output.
100: reserved
Reserved, write “0 “.
130
2008/03
[AK8825]
HD VBID Data 1 Register (R/W) [Address 0x03]
HD VBID Data 2 Register (R/W) [Address 0x04]
[Component Video Encoder]
Registers to set CGMS-A Data
CGMS-A Data is set. CRCC Data is automatically generated and added.
Address 0x03
bit 7
HDVBIDEN
bit 6
Reserved
bit 5
HDVBID1
0
0
bit 6
HDVBID8
bit 5
HDVBID9
0
0
0
Address 0x04
bit 7
HDVBID7
0
HD VBID Data 1 Register (R/W) [Address 0x03]
BIT Register Name
bit 0
HDVBID6
~
~
VBID DATA bit
bit 5
HDVBID1
bit 6
Reserved
Reserved bit
bit 7
HDVBIDEN
VBID Enable bit
HD VBID Data 2 Register (R/W) [Address 0x04
BIT
Register Name
HDVBID14
bit 0
~
VBID Data bit
~
HDVBID7
bit 7
bit 4
bit 3
HDVBID2
HDVBID3
Default Value
0
0
bit 2
HDVBID4
bit 4
bit 3
HDVBID10
HDVBID11
Default Value
0
0
bit 2
HDVBID12
R/W
R/W
R/W
R/W
R/W
R/W
0
0
Default Value 0x00
bit 1
bit 0
HDVBID5
HDVBID6
0
0
Default Value 0x00
bit 1
bit 0
HDVBID13
HDVBID14
0
0
Definition
VBID (CGMS-A) Data is set.
Data to be set are CGMS1 ~ CGMS6.
CGMS7 ~ CGMS14 should be set at CGMS Data 2 Register.
Reserve, write “0 “.
This bit is set when VBID (CGMS-A) signal is to be
super-imposed.
Target Line to be super-imposed with, is automatically decided by
setting [ HDMODE1 : HDMODE0 ]-bits for HDMODE Register.
0: CGMS-A function is “OFF “.
1: CGMS-A signal is super-imposed.
Definition
VBID (CGMS-A) Data is set.
Data to be set are CGMS7 ~ CGMS14.
CGMS1 ~ CGMS6 should be set at CGMS Data 1 Register.
- About Outputting CGMS Data
Write Operation of CGMS Data via I2C interface must be completed by the time when the preceding 2 Lines are completed,
from a target output Line.
Each Line starts at EAV.
Rev-E-00
131
2008/03
[AK8825]
Reserved Register (R/W) [Sub Address 0x05]
Reserve Register
Sub Address 0x05
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
Reserved
0
Reserved Register (R/W) [Sub Address 0x05]
BIT Register Name
bit 0
~
Reserved
Reserved bit
bit 7
Rev-E-00
bit 4
bit 3
Reserved
Reserved
Default Value
0
0
R/W
R/W
bit 2
Reserved
0
Default Value 0x00
bit 1
bit 0
Reserved
Reserved
0
0
Definition
Reserve, write “0x00 “.
132
2008/03
[AK8825]
Powerdown Mode Register (R/W) [Sub Address 0x06]
[Common Register for all Function block]
to set Power-Down and Operation modes of the AK8825.
Sub Address 0x06
bit 7
bit 6
Reserved
Reserved
0
bit 5
Reserved
0
0
bit 4
bit 3
Reserved
Reserved
Default Value
0
0
BIT
Register Name
bit 0
~
bit 1
SLPEN0
~
SLPEN1
Sleep Enable bit
R/W
bit 2
PLLPDN
PLL Power Down bit
R/W
bit 3
~
bit 6
Reserved
Reserved bit
R/W
Rev-E-00
R/W
bit 2
PLLPDN
0
Default Value 0x00
bit 1
bit 0
SLPEN1
SLPEN0
0
0
Definition
to control operation of SD / HD blocks ( digital portion )
[ SLPEN1 : SLPEN0 ]-bit
00: both SD /HD blocks are enabled.
01: HD block only is enabled.
10: SD block only is enabled.
11: entire device is put into Power-Down mode.
to control Power-Down of PLL
0 : Power Down
1 : release from Power-Down
Reserved, write “0 “.
133
2008/03
[AK8825]
HD Block Control Register (R/W) [Sub Address 0x07]
[Component Video Encoder]
to set miscellaneous function to register
Sub Address 0x07
bit 7
bit 6
HDWSS
HDCFLT1
0
bit 5
HDCFLT0
0
0
HD Block Control Register
BIT Register Name
bit 4
bit 3
HDYFLT1
HDYFLT0
Default Value
0
0
R/W
bit 0
HDVRATIO
Video ratio bit
R/W
bit 1
COLSNCEN
Color SYNC Enable bit
R/W
bit 2
Reserved
Reserved-bit
R/W
HDY Filter select
R/W
bit3
~
bit4
HDYFLT0
~
HDYFLT1
bit5
~
bit6
HDCFLT0
~
HDCFLT1
HDPBPR
Filter select
R/W
bit 7
HDWSS
WSS set bit
R/W
Rev-E-00
bit 2
Reserved
bit 1
COLSNCEN
0
0
default Value 0x00
bit 0
HDVRATIO
0
Definition
286 / 714 Ratio Video Signal is output at D1 / 60Hz operation.
0 : 300 / 700 Ratio Video Signal is output (770.2-A)
1 : 286 / 714 Ratio Video Signal is output (770.1-A)
to add sync signal on Pb/Pr signal.
0: No sync on Pb/Pr signal
1: Sync on Pb/Pr signal
Reserved, write “0 “.
to select HDY Video Signal Band Limit Filter
[HDYFLT 1: HDYFLT 0] =
00 : Normal
01 : Mild
10 : Soft
11 : Normal
to select HDPB / HDPR Video Signal Band Limit Filter
[HDCFLT 1: HDCFLT 0] =
00 : Normal
01 : Mild
10 : Soft
11 : Normal
to encode WSS signal
It is turned on only when D1/50Hz is Output
0 : WSS off
1 : WSS on
134
2008/03
[AK8825]
HD WSS Data 1 Register (R/W) [Sub Address 0x08]
HD WSS Data 2 Register (R/W) [Sub Address 0x09]
[Component Video Encoder]
Register to set WSS Data
Sub Address 0x08
bit 7
bit 6
HDG2-7
HDG2-6
0
0
Sub Address 0x09
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
HDG2-5
0
bit 5
HDG4-13
0
bit 4
bit 3
HDG2-4
HDG1-3
Default Value
0
0
bit 2
HDG1-2
bit 4
bit 3
HDG4-12
HDG4-11
Default Value
0
0
bit 2
HDG3-10
0
0
default Value 0x00
bit 1
bit 0
HDG1-1
HDG1-0
0
0
default Value 0x00
bit 1
bit 0
HDG3-9
HDG3-8
0
0
Note) WSS Data is written in order of 0x08 and then 0x09.
When the second byte (0x09) of WSS Data is written, the AK8825 interprets that data has been up-dated and it encodes the
WSS signal on the next Video Line (LIne23).
Data is retained till it is up-dated with a new one.
Rev-E-00
135
2008/03
[AK8825]
HD Block Miscellaneous Control Register (R/W) [Sub Address 0x0A]
[Component Video Encoder]
to set miscellaneous function to register
Sub Address 0x0A
bit 7
bit 6
Reserved
Reserved
0
bit 5
STD770_2C
0
0
bit 4
bit 3
HDCEA805B CCWSSSUE
Default Value
0
0
Register Name
bit 0
~
bit 1
HDAFLT0
~
HDAFLT1
HD Aperture Filter Set
bit
R/W
bit 2
Reserved
Reserved
R/W
bit 3
CCWSSSUE
CC,
WSS,
Enable bit
bit 4
HDCEA805B
CEA 805B Encode bit
R/W
bit 5
STD770_2C
CEA 770.2-C bit
R/W
to adapt CEA770.2-C standard
0: to adapt CEA770.2.A standard
1: to adapt CEA770.2.C standard
bit 6
~
bit 7
Reserved
Reserved
R/W
Reserved, write “0 “.
Setup
R/W
default Value 0x00
bit 1
bit 0
HDAFLT1
HDAFLT0
0
BIT
Rev-E-00
R/W
bit 2
Reserved
0
0
Definition
to set aperture compensation filter
[AFLT1:AFLT0]
00: Mode0 : Less compensation (default)
01: Mode1
10: Mode2
11: Mode3 : much compensation
Reserved, write “0 “.
to set the Set-up on the CC/WSS line.
0: no Set-up on CC/WSS line.
1: 7.5% Set-up is added on CC/WSS line
to Encode CEA805B TypeB data
0: no encoding TypeB data
1: encoding TypeB data
136
2008/03
[AK8825]
I/O Data Format Register (R/W) [Sub Address 0x0B]
[Common Register for all Function block]
to set input / output configuration
Sub Address 0x0B
bit 7
bit 6
HDSDMASE
YC2RGB
0
bit 5
Reserved
0
BIT
Register Name
bit 0
~
bit 1
INPFMT0
~
INPFMT1
bit 2
~
bit 3
CONVMOD0
~
CONVMOD1
bit 4
DTFMT
bit 5
0
bit 4
bit 3
DTFMT
CONVMOD1
Default Value
0
0
R/W
Input Data Format bit
R/W
Convert Module Select
bit
R/W
Data Format bit
R/W
Reserved
Reserved bit
R/W
bit 6
YC2RGB
YCbCr to RGB bit
R/W
bit 7
HDSDMASE
HD/SD Master mode
Enable bit
R/W
Rev-E-00
bit 2
CONVMOD0
0
default Value 0x00
bit 1
bit 0
INPFMT1
INPFMT0
0
0
Definition
to set input data bit width format
[INPFMT1: INPFMT0]
00: 8bit data input
01: 16bit data input
10: 18bit data input
11: prohibited to set
to select encoding block
CONVMOD[1:0]=
00: to select Composite Video Encoder Block
Component Video Encoder Block becomes sleep mode
automatically.
01: to select Component Video Encoder Block
Composite Video Encoder Block becomes sleep mode
automatically.
10: to select High Speed DAC Block
Composite Video Encoder Block and Component Video
Encoder Block becomes sleep mode automatically.
11: Prohibited to set
to set Input data format
0: YCbCr data
1: RGB data
Reserved, write “0 “.
to set YCbCr to RGB data conversion
This mode only work at CONVMOD[1:0]=01.
0: no conversion
1: YCbCr to RGB conversion is worked
to set self-sync mode* in case of HDBBG-bit / HDCBG-bit /
SDBBG-bit / SDCBG-bit is set.
self-sync mode: working without HD/VD and EAV timing signal
0: no self-sync mode.
1: self-sync mode
137
2008/03
[AK8825]
I/O Pin Control Register (R/W) [Sub Address 0x0C]
[Common Register for all Function block]
to set the attribute of I/O pins.
Sub Address 0x0C
bit 7
bit 6
VDOEN
HDOEN
0
bit 5
VDI_INV
0
0
bit 4
bit 3
HDI_INV
Reserved
Default Value
0
0
BIT
Register Name
bit 0
CLKINV
Clock Invert -bit
R/W
bit 1
HDOPOL
HDO Polarity bit
R/W
bit 2
VDOPOL
VDO Polarity bit
R/W
bit 3
Reserved
Reserved
R/W
bit 4
HDI_INV
HD polarity select
R/W
bit 5
VDI_INV
VD polarity select
R/W
bit 6
HDOEN
HDO Output Enable bit
R/W
bit 7
VDOEN
VDO
bit
Rev-E-00
R/W
Output Enable
R/W
bit 2
VDOPOL
0
Default Value 0x00
bit 1
bit 0
HDOPOL
CLKINV
0
0
Definition
to set polarity of Clock for CLKIN pin
0: Capturing the data at the rising edge of clock
1: Capturing the data at the falling edge of clock
to set polarity of HDO
0: Same polarity as Input data.
1: Inverted polarity as Input data
to set polarity of VDO
0: Same polarity as Input data.
1: Inverted polarity as Input data
Reserved, write “0 “.
to set polarity of HDI
0 : Active Lo
1 : Active High
to set polarity of VDI
0 : Active Lo
1 : Active High
to control HDO
0: Disable to output the timing signal from HDO
1: Enable to output the timing signal from HDO
to control VDO
0: Disable to output the timing signal from VDO
1: Enable to output the timing signal from VDO
138
2008/03
[AK8825]
DAC Control Register(R/W) [Sub Address 0x0D]
[Common Register for all Function block]
to set on / off of DACs
Sub Address 0x0D
bit 7
bit 6
Reserved
Reserved
0
bit 5
OLVL
0
0
bit 4
bit 3
DTRSTN
CVBSSEL
Default Value
0
0
BIT
Register Name
bit 0
DAC1EN
DAC1 Enable bit
R/W
bit 1
DAC2EN
DAC2 Enable bit
R/W
bit 2
DAC3EN
DAC3 Enable bit
R/W
bit 3
CVBSSEL
CVBS Select bit
R/W
bit 4
DTRSTN
Data Clear bit
R/W
bit 5
OLVL
Output Level bit
R/W
bit 6
~
bit 7
Reserved
Reserved bit
R/W
Rev-E-00
R/W
bit 2
DAC3EN
default Value 0x00
bit 1
bit 0
DAC2EN
DAC1EN
0
0
0
Definition
to control DAC1 ON/OFF
0: OFF (Output pin is Hi-z States)
1: ON
to control DAC2 ON/OFF
0: OFF (Output pin is Hi-z States)
1: ON
to control DAC3 ON/OFF
0: OFF (Output pin is Hi-z States)
1: ON
to select the DAC for CVBS output
0: DAC3 outputs CVBS
1: DAC1 outputs CVBS
to Reset all block
0: Initialize the circuit
1: to release initialized states
to control DAC output Level
This bit is valid at High Speed DAC mode.
0: to output about 1.28V at 0xFF code.
1: to output about 0.7V at 0xFF code.
Reserved, write “0 “.
139
2008/03
[AK8825]
SD Blanking Set Register (R/W) [Sub Address 0x10]
[Composite Video Encoder Block]
to set AK8825 Interface mode and V-Blanking Length at composite Video Encoder mode.
Sub Address 0x10
bit 7
bit 6
SDBLN4
SDBLN3
1
bit 5
SDBLN2
0
1
bit 4
bit 3
SDBLN1
SDBLN0
Default Value
0
0
BIT
Register Name
bit 0
REC656
REC 656 bit
R/W
Reserved
Reserved bit
R/W
SDBLN0
~
SDBLN4
SD Blanking Line No.
R/W
bit 1
~
bit 2
bit 3
~
bit 7
Rev-E-00
R/W
bit 2
Reserved
0
Default Value 0xA1
bit 1
bit 0
Reserved
REC656
0
1
Definition
set this bit when to synchronize with ITU-R. BT.656
( compatible ) EAV.
0 : EVA is not decoded
( in case of synchronization with HSYNC / VSYNC )
1: EVA is decoded and the timing is synchronized with it.
Reserved, write “0 “.
to set Line Blanking output.
140
2008/03
[AK8825]
SD Block Control Register (R/W) [Sub Address 0x11]
[Composite Video Encoder Block]
to set Output signals
Sub Address 0x11
bit 7
bit 6
SDBBG
SDCBG
0
bit 5
SDSETUP
0
BIT
Register Name
bit 0
~
bit 3
SDVM0
~
SDVM3
bit 4
SCR
bit 5
SDSETUP
bit 6
bit 7
0
bit 4
bit 3
SCR
SDVM3
Default Value
1
0
R/W
Video Mode 0 Register
~
Video Mode 3 Register
R/W
Sub Carrier Reset bit
R/W
SD Setup-bit
R/W
SDCBG
SD
Color
Bar
Generator Control bit
R/W
SDBBG
SD
Black
Burst
Generator Control bit
R/W
bit 2
SDVM2
0
Default Value 0x10
bit 1
bit 0
SDVM1
SDVM0
0
0
Definition
[ SDVM1 : SDVM0 ] – bit
00 : 3.57954545 MHz
01 : 3.57561188 MHz
10 : 3.5820558 MHz
11 : 4.43361875 MHz
[ SDVM3 : SDVM2 ] – bit
00 : 525 / 60
01: 525 / 60 PAL (PAL-M etc...)
10 : reserved
11 : 625 / 50 PAL ( PAL-B, D, G, H, I, N )
to set enable / disable reset of Sub-carrier for each color sequence
0: no sub-carrier reset is done.
1: sub-carrier reset is enabled.
NTSC: reset at every 2 Frames.
PAL: reset at every 4 Frames.
to set the Set-Up
0 : no set-up
1: 7.5 % set-up is added.
Even when the set-up is turned on, set-up (Pedestal) is not added
while Blanking Line is being output.
setting bit of On-Chip Color Bar
0: input data is encoded.
1: On-Chip Color Bar is output.
When SDBBG bit is set, SDBBG is prioritized.
Black Burst Generator bit
to output Black Burst signal
0: input data is encoded.
1: Black Burst signal is output.
Even when SDCBG bit is set, SDBBG is prioritized.
SDVM3 – SDVM0 settings for each Standard are as follows.
NTSC
PAL-B,D,G,H,I
PAL-M
PAL-60
NTSC-4.43
Rev-E-00
SDVM3:SDVM0
0000
1111
0101
0111
0011
141
2008/03
[AK8825]
SD/HD V-Blanking Control Register (R/W) [Sub Address 0x12]
[Composite Video Encoder / Component Video Encoder Block]
to set V-Blanking Interval output Data
Sub Address 0x12
bit 7
bit 6
Reserved
Reserved
0
bit 5
Reserved
0
0
bit 4
bit 3
Reserved
SDWSS
Default Value
0
0
BIT
Register Name
bit 0
SDVBID
SD Video ID bit
R/W
bit 1
SDHDCC21
Closed Caption bit
R/W
bit 2
SDHDCC284
R/W
0
Default Value 0x00
bit 1
bit 0
SDHDCC21
SDVBID
0
0
Definition
to set VBID data for Composite Video Encoder mode/
0: VBID OFF
1: VBID ON
to make Closed Caption signal enable for Composite Video
Encoder and Component Video Encoder mode.
0: OFF
1: ON
to make Closed Caption Extended signal enable for Composite
Video Encoder and Component Video Encoder mode.
Closed
Caption
Extended Data bit
R/W
0: OFF
1: ON
to make WSS enable for Composite Video Encoder.
bit 3
SDWSS
WSS set bit
R/W
bit 4
~
bit 7
Reserved
Reserved bit
R/W
Rev-E-00
bit 2
SDHDCC284
0: OFF
1: ON
Reserved, write “0 “.
142
2008/03
[AK8825]
SD Block Delay Register (R/W) [Sub Address 0x13]
[Composite Video Encoder Block]
to adjust YC Delay amount of output signal
Sub Address 0x13
bit 7
bit 6
SDCLPLVL1 SDCLPLVL0
0
BIT
bit 0
~
bit 2
bit 5
SYD2
0
0
Register Name
Reserved
bit 3
~
bit 5
SYD0
~
SYD2
bit 6
~
bit 7
SDCLPLVL0
~
SDCLPLVL1
Rev-E-00
bit 4
bit 3
SYD1
SYD0
Default Value
0
0
R/W
Reserved bit
R/W
S-video Y Delay bit
R/W
SD Clip Level Set bit
R/W
bit 2
Reserved
0
default Value 0x00
bit 1
bit 0
Reserved
Reserved
0
0
Definition
Reserved, write “0 “.
[[ SYD2 : SYD0 ] – bit
101: Y component output advances 3 clock times to C component.
110: Y component output advances 2 clock times to C component.
111: Y component output advances 1 clock time to C component.
000 : no delay between Y component and C component
001 : Y component output is delayed by 1 clock time to C
component.
010 : Y component output is delayed by 2 clock time to C
component.
011 : Y component output is delayed by 3 clock time to C
component.
to clip the under-shoot of the Over-Sampling Filter Outputs to a
pre-set value.
[ SDCLPLVL1:SDCLPLVL1 ]
00: no clipping
01: to be clipped at approximately - 7.0IRE
10: to be clipped at approximately -1.5IRE
11: reserved
143
2008/03
[AK8825]
SD Block FLT Register (R/W) [Sub Address 0x14]
[Composite Video Encoder Block]
to set Band Limit Filter.
Sub Address 0x14
bit 7
bit 6
Reserved
Reserved
0
BIT
bit 0
~
bit 2
bit 5
Reserved
0
0
Register Name
Reserved
bit 4
bit 3
SDYFLT1
SDYFLT0
Default Value
0
0
R/W
Reserved bit
bit 2
Reserved
default Value 0x00
bit 1
bit 0
Reserved
Reserved
0
0
Definition
R/W
Reserved, write “0 “.
bit 3
~
bit 4
SDYFLT0
~
SDYFLT1
SDY Filter Select bit
R/W
to set SDY Video Signal Band Limit Filter
[SDYFLT1:SDYFLT0]=
00: Normal
01: Mild
10: soft
11: Inhibited
bit 5
~
bit 7
Reserved
Reserved
R/W
Reserved, write “0 “.
Rev-E-00
0
144
2008/03
[AK8825]
Reserve Register (R/W) [Sub Address 0x15]
[Composite Video Encoder]
Reserved Register
Sub Address 0x15
bit 7
bit 6
Reserved
Reserved
0
BIT
bit 0
~
bit 7
bit 5
Reserved
0
0
Register Name
Rev-E-00
Reserved
bit 4
bit 3
Reserved
Reserved
Default Value
0
0
R/W
Reserved bit
R/W
bit 2
Reserved
0
default Value 0x00
bit 1
bit 0
Reserved
Reserved
0
0
Definition
Reserved, write “0 “.
145
2008/03
[AK8825]
Sub Carrier Frequency Control Register (R/W) [Sub Address 0x16]
[Composite Video Encoder]
to set subcarrier Frequency
Sub Address 0x16
bit 7
bit 6
SUBF7
SUBF6
0
0
BIT
Register Name
bit 0
~
bit 7
SUBF0
~
SUBF7
Rev-E-00
bit 5
SUBF5
0
Sub Carrier Frequency
control bit
bit 4
bit 3
SUBF4
SUBF3
Default Value
0
0
bit 2
SUBF2
bit 1
SUBF1
0
0
default Value 0x00
bit 0
SUBF0
0
R/W
Definition
R/W
to fine-tune the sub-carrier
Frequency adjustment can be done, ranging from + 127 to _ 128
and adjustable step is in 0.8 Hz / step.
146
2008/03
[AK8825]
Sub Carrier Phase Control Register (R/W) [Sub Address 0x17]
[Composite Video Encoder]
to set subcarrier Phase
Sub Address 0x17
bit 7
bit 6
SUBP7
SUBP6
0
0
BIT
Register Name
bit 0
~
bit 7
SUBP0
~
SUBP7
Rev-E-00
bit 5
SUBP5
0
bit 4
bit 3
SUBP4
SUBP3
Default Value
0
0
R/W
Sub Carrier Phase
control bit
R/W
bit 2
SUBP2
bit 1
SUBP1
0
0
default Value 0x00
bit 0
SUBP0
0
Definition
bit 0 ~ bit 7 Sub-Carrier Phase Control bits
to set default value of sub-carrier phase
Adjustable step: 360 / 255 [deg.]
Sub-Carrier Phase is set at _ 180 degrees at default condition.
Phase rotates counter-clockwise to the set value.
147
2008/03
[AK8825]
SD WSS Data 1 Register (R/W) [Sub Address 0x18]
SD WSS Data 2 Register (R/W) [Sub Address 0x19]
[Composite Video Encoder]
to set WSS Data for Composite Video Encoder mode
Sub Address 0x18
bit 7
bit 6
SDG2-7
SDG2-6
0
0
Sub Address 0x19
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
SDG2-5
0
bit 5
SDG4-13
0
bit 4
bit 3
SDG2-4
SDG1-3
Default Value
0
0
bit 2
SDG1-2
bit 4
bit 3
SDG4-12
SDG4-11
Default Value
0
0
bit 2
SDG3-10
0
0
default Value 0x00
bit 1
bit 0
SDG1-1
SDG1-0
0
0
default Value 0x00
bit 1
bit 0
SDG3-9
SDG3-8
0
0
Note) WSS Data is written in order of 0x18 and then 0x19.
When the second byte (0x19) of WSS Data is written, the AK8825 interprets that Data has been up-dated and it encodes the
Data on the next Video Line (Line 23).
Data is retained till it is up-dated with a new one.
Rev-E-00
148
2008/03
[AK8825]
Closed Caption Data 1 Register (R/W) [Sub Address 0x26]
Closed Caption Data 2 Register (R/W) [Sub Address 0x27]
[Component Video Encoder/ Composite Video Encoder Block]
to set Closed Caption Data
Sub Address 0x26
bit 7
bit 6
CC7
CC6
0
0
Sub Address 0x27
bit 7
bit 6
CC15
CC14
0
0
bit 5
CC5
0
bit 5
CC13
0
bit 4
bit 3
CC4
CC3
Default Value
0
0
bit 2
CC2
bit 1
CC1
0
0
bit 4
bit 3
CC12
CC11
Default Value
0
0
bit 2
CC10
bit 1
CC9
0
0
default Value 0x00
bit 0
CC0
0
default Value 0x00
bit 0
CC8
0
Note) Closed Caption Data is written in order of 0x26 and then 0x27.
When the second byte (0x27) of Closed Caption Data is written, the AK8825 interprets that Data has been up-dated and it
encodes the Data on the next Video Line.
Null Codes are automatically output on those, not-data-updated lines.
It is assumed that Parity bit of each Byte Data is added by the Host side.
Rev-E-00
149
2008/03
[AK8825]
CC Extended Data 1 Register (R/W) [Sub Address 0x28]
CC Extended Data 2 Register (R/W) [Sub Address 0x29]
[Component Video Encoder/ Composite Video Encoder Block]
to set Closed Caption Extended Data
Sub Address 0x28
bit 7
bit 6
EXT7
EXT6
0
0
Sub Address 0x29
bit 7
bit 6
EXT15
EXT14
0
0
bit 5
EXT5
0
bit 5
EXT13
0
bit 4
bit 3
EXT4
EXT3
Default Value
0
0
bit 2
EXT2
bit 1
EXT1
0
0
bit 4
bit 3
EXT12
EXT11
Default Value
0
0
bit 2
EXT10
bit 1
EXT9
0
0
default Value 0x00
bit 0
EXT0
0
default Value 0x00
bit 0
EXT8
0
Note) Closed Caption Extended Data is written in order of 0x28 and then 0x29.
When the second byte (0x29) of Closed Caption Extended Data is written, the AK8825 interprets that Data has been up-dated
and it encodes the Data on the next Video Line.
Null Codes are automatically output on those, not-data-updated lines.
It is assumed that Parity bit of each Byte Data is added by the Host side.
Rev-E-00
150
2008/03
[AK8825]
SD VBID-A Data1 Register (R/W) [Sub Address 0x2A]
SD VBID-A Data2 Register (R/W) [Sub Address 0x2B]
[Composite Video Encoder Block]
to set VBID-A Data
Sub Address 0x2A
bit 7
bit 6
Reserved
Reserved
0
0
Sub Address 0x2B
bit 7
bit 6
SDVBID7
SDVBID8
0
0
bit 5
SDVBID1
0
bit 5
SDVBID9
0
bit 4
bit 3
SDVBID2
SDVBID3
Default Value
0
0
bit 2
SDVBID4
bit 4
bit 3
SDVBID10
SDVBID11
Default Value
0
0
bit 2
SDVBID12
0
0
default Value 0x00
bit 1
bit 0
SDVBID5
SDVBID6
0
0
default Value 0x00
bit 1
bit 0
SDVBID13
SDVBID14
0
0
Note) write “0 “to reserved bits.
VBID1 ~ VBID14 correspond to bit 1 ~ bit 14 which are described at {VBID Data Code Assignment} diagram
at item { Video ID }.
A 6 Bit CRC Code from bit 15 ~ bit 20 is automatically added by the AK8825.
Data is retained till it is up-dated with a new one.
Rev-E-00
151
2008/03
[AK8825]
Status Register (R) [Sub Address 0x34]
to show Status of the AK8825
Sub Address 0x34
bit 7
bit 6
Reserved
Reserved
bit 5
Reserved
bit 4
Reserved
BIT
Register Name
bit 0
EN21
Encode 21 bit
R
bit 1
EN284
Encode 284 bit
R
bit 2
~
bit 7
Reserved
Reserved bit
R
Rev-E-00
R/W
bit 3
Reserved
bit 2
Reserved
bit 1
EN284
bit 0
EN21
Definition
to indicate up-date timing of the Closed-Caption Data
When EN21 bit is “1 “, the AK8825 waits for data input coming.
This bit becomes “0 “after data is written at the second byte (0x27).
to indicate up-date timing of the Closed-Caption Extended Data
When EN284 bit is “1 “, the AK8822 waits for data input coming.
This bit becomes “0 “after data is written at the second byte (0x29).
Reserved bit write “0 “.
152
2008/03
[AK8825]
Device ID & Revision ID Register (R) [Sub Address 0x35]
to indicate the AK8825 Device ID and Revision ID
Sub Address 0x35
bit 7
bit 6
REV1
REV0
0
0
BIT
bit 0
~
bit 5
Register Name
DEV0
~
DEV5
bit 6
~
bit 7
REV0
~
REV1
Rev-E-00
bit 5
DEV5
1
bit 4
DEV4
0
bit 3
DEV3
0
R/W
Device ID bit
Revision ID
bit 2
DEV2
1
bit 1
DEV1
0
default Value 0x25
bit 0
DEV0
1
Definition
R
to indicate Device ID
0x25 is assigned to the AK8825
R
to indicate Revision ID
Revision ID is up-dated when a possible software modification is
made.
It starts at 0x00.
153
2008/03
[AK8825]
VBID-B Header Data Register (R/W) [Sub Address 0x40]
[Component Video Encoder Block]
to set Video ID Type-B Header data
Sub Address 0x40
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
h5
0
bit 4
bit 3
h4
h3
Default Value
0
1
bit 2
h2
bit 1
h1
0
0
bit 2
p2
bit 1
p1
0
0
bit 2
p10
bit 1
p9
0
0
default Value 0x08
bit 0
h0
0
VBID-B Version Number Register (R/W) [Sub Address 0x41]
[Component Video Encoder Block]
to set Video ID Type-B Payload Data
Sub Address 0x41
bit 7
p7
0
bit 6
p6
bit 5
p5
0
0
bit 4
bit 3
p4
p3
Default Value
0
0
default Value 0x00
bit 0
p0
0
VBID-B Payload Packet Length Register (R/W) [Sub Address 0x42]
[Component Video Encoder Block]
to set Video ID Type-B Payload data
Sub Address 0x42
bit 7
p15
0
Rev-E-00
bit 6
p14
bit 5
p13
0
0
bit 4
bit 3
p12
p11
Default Value
0
0
154
default Value 0x00
bit 0
p8
0
2008/03
[AK8825]
VBID-B Data1 Register (R/W) [Sub Address 0x43] - VBID-B Data13 Register (R/W) [Sub Address 0x2B]
[Component Video Encoder Block]
to set Video ID data.
CRC code is automatically appended by AK8825.
The data is hold till new data is up-dated.
VBID-B Payload Data1 Register (R/W) [Sub Address 0x43]
Sub Address 0x43
bit 7
bit 6
bit 5
bit 4
bit 3
p23
p22
p21
p20
p19
Default Value
0
0
0
0
0
bit 2
p18
bit 1
p17
0
0
VBID-B Payload Data2 Register (R/W) [Sub Address 0x44]
Sub Address 0x44
bit 7
bit 6
bit 5
bit 4
bit 3
p31
p30
p29
p28
p27
Default Value
0
0
0
0
0
bit 2
p26
bit 1
p25
0
0
VBID-B Payload Data3 Register (R/W) [Sub Address 0x45]
Sub Address 0x45
bit 7
bit 6
bit 5
bit 4
bit 3
p39
p38
p37
p36
p35
Default Value
0
0
0
0
0
bit 2
p34
bit 1
p33
0
0
VBID-B Payload Data4 Register (R/W) [Sub Address 0x46]
Sub Address 0x46
bit 7
bit 6
bit 5
bit 4
bit 3
p47
p46
p45
p44
p43
Default Value
0
0
0
0
0
bit 2
p42
bit 1
p41
0
0
VBID-B Payload Data5 Register (R/W) [Sub Address 0x47]
Sub Address 0x47
bit 7
bit 6
bit 5
bit 4
bit 3
p55
p54
p53
p52
p51
Default Value
0
0
0
0
0
bit 2
p50
bit 1
p49
0
0
VBID-B Payload Data6 Register (R/W) [Sub Address 0x48]
Sub Address 0x48
bit 7
bit 6
bit 5
bit 4
bit 3
p63
p62
p61
p60
p59
Default Value
0
0
0
0
0
bit 2
p58
bit 1
p57
0
0
Rev-E-00
155
default Value 0x00
bit 0
p16
0
default Value 0x00
bit 0
p24
0
default Value 0x00
bit 0
p32
0
default Value 0x00
bit 0
p40
0
default Value 0x00
bit 0
p48
0
default Value 0x00
bit 0
p56
0
2008/03
[AK8825]
VBID-B Payload Data7 Register (R/W) [Sub Address 0x49]
Sub Address 0x49
bit 7
bit 6
bit 5
bit 4
bit 3
p71
p70
p69
p68
p67
Default Value
0
0
0
0
0
bit 2
p66
bit 1
p65
0
0
VBID-B Payload Data8 Register (R/W) [Sub Address 0x4A]
Sub Address 0x4A
bit 7
bit 6
bit 5
bit 4
bit 3
p79
p78
p77
p76
p75
Default Value
0
0
0
0
0
bit 2
p74
bit 1
p73
0
0
VBID-B Payload Data9 Register (R/W) [Sub Address 0x4B]
Sub Address 0x4B
bit 7
bit 6
bit 5
bit 4
bit 3
p87
p86
p85
p84
p83
Default Value
0
0
0
0
0
bit 2
p82
bit 1
p81
0
0
VBID-B Payload Data10 Register (R/W) [Sub Address 0x4C]
Sub Address 0x4C
bit 7
bit 6
bit 5
bit 4
bit 3
p95
p94
p93
p92
p91
Default Value
0
0
0
0
0
bit 2
p90
bit 1
p89
0
0
VBID-B Payload Data11 Register (R/W) [Sub Address 0x4D]
Sub Address 0x4D
bit 7
bit 6
bit 5
bit 4
bit 3
p103
p102
p101
p100
p99
Default Value
0
0
0
0
0
bit 2
p98
bit 1
p97
0
0
VBID-B Payload Data12 Register (R/W) [Sub Address 0x4E]
Sub Address 0x4E
bit 7
bit 6
bit 5
bit 4
bit 3
p111
p110
p109
p108
p107
Default Value
0
0
0
0
0
bit 2
p106
bit 1
p105
0
0
VBID-B Payload Data13 Register (R/W) [Sub Address 0x4F]
Sub Address 0x4F
bit 7
bit 6
bit 5
bit 4
bit 3
p119
p118
p117
p116
p115
Default Value
0
0
0
0
0
bit 2
p114
bit 1
p113
0
0
bit 2
Reserved
bit 1
p121
0
0
VBID-B Payload Data14 Register (R/W) [Sub Address 0x50]
Sub Address 0x50
bit 7
bit 6
bit 5
bit 4
bit 3
Reserved
Reserved
Reserved
Reserved
Reserved
Default Value
0
0
0
0
0
Rev-E-00
156
default Value 0x00
bit 0
p64
0
default Value 0x00
bit 0
p72
0
default Value 0x00
bit 0
p80
0
default Value 0x00
bit 0
p88
0
default Value 0x00
bit 0
p96
0
default Value 0x00
bit 0
p104
0
default Value 0x00
bit 0
p112
0
default Value 0x00
bit 0
p120
0
2008/03
[AK8825]
Video DAC Delay Control Register(R/W) [Sub Address 0x51]
[High Speed Video DAC mode]
to set Video DAC delay
Sub Address 0x51
bit 7
bit 6
Reserved
Reserved
0
BIT
bit 5
Reserved
0
0
Register Name
bit 0
~
bit 2
HDLY0
~
HDLY2
bit 3
~
bit 7
Reserved
Rev-E-00
bit 4
bit 3
Reserved
Reserved
Default Value
0
0
bit 2
HDLY2
bit 1
HDLY1
0
0
R/W
default Value 0x00
bit 0
HDLY0
0
Definition
HD Delay bit
R/W
to adjust HDI timing delay
000 : 3CLK delay
001 : 2CLK delay
010 : 1CLK delay
011 : no delay
111 : 1CLK advanced
110 : 2CLK advanced
101 : 3CLK advanced
100 : inhibited to set
Reserved
R/W
Reserved, write “0”
157
2008/03
[AK8825]
11. SYSTEM CONNECTION EXAMPLE
8 or 16
MPEG
DATA[15:0]
CLKIN
HDI
VDI
Decoder
DAC1
-
DAC2
-
DAC3
-
Amp + LPF
300-ohm
75-ohm
x 3ch
AK8825
SELA
AVDD
AVDD
PVDD2
0.1uF
VREF
4.7nF
820-ohm
FLT
u-P
SDA
SCL
2
I C Bus
BYPASS
0.1uF
IREF
PDN
GPIO
3.9k-ohm
Data I/O Power
PVDD1
TMO
u-P I/O Power
TEST0
TEST1
PVDD2
Digital 1.8V
0.1uF
DVDD
10uF
Fig. 172
Rev-E-00
DVSS
AVSS
AVDD
10uF
Analog 3.0V
0.1uF
System Connection example
158
2008/03
[AK8825]
12. Package
12-1 AK8825VG
5.0 ± 0.1
A
57 − Φ0.3 ± 0.05
Φ0.05 M S
9 8 7 6
5 4 3 2 1
B
F
G
H
J
4.0
5.0 ± 0.1
A
B
C
D
E
0.5
0.5
0.08 S
0.23 ± 0.05
0.89±0.10
S
Fig. 173-1 Package (BGA 5mm x 5mm)
Rev-E-00
159
2008/03
[AK8825]
12-2 AK8825VN
7.20±0.10
7.00±0.05
A
36
3-C0.2
25
37
36
25
24
24
37
7.20±0.10
7.00±0.05
B
45°
48
12
12
1
45°
13
13
48
C0.6
0.17±0.05
3-0.50+0.40
-0.15
0.22±0.05
0.35±0.12
0.05 M S AB
1
0.25 +0.40
-0.15
0.92±0.08
0.05 S
S
-0.015
0.02 +0.02
0.17±0.05
0.50
Fig. 173-2 Package (QFN48 7.2mm x 7.2mm)
Rev-E-00
160
2008/03
[AK8825]
13. Marking
13-1 AK8825VG
8825
XXXX
●
Fig. 174-1
Marking (AK8825VG)
a. Pin Type
b. Pin count
c. Product Number
d. Control Code
13-2
: BGA
: 57pin (Including Index pin)
: 8825
: XXXX (4 digits)
AK8825VN
AKM
AK8825VN
XXXXXXX
1
Fig. 175-2
Marking (AK8825VG)
a. Pin Type
b. Pin count
c. Product Number
d. Control Code
Rev-E-00
: QFN
: 48pin
: 8825VN
: XXXXXXX (7 digits)
161
2008/03
[AK8825]
IMPORTANT NOTICE
z
z
z
z
z
Rev-E-00
These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of
Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the
application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety,
life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for
such use, except for the use approved with the express written consent by Representative Director of
AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the
device or system containing it, and which must therefore meet very high standards of
performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields,
in which its failure to function or perform may reasonably be expected to result in loss of life or in
significant injury or damage to person or property.
It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above
content and conditions, and the buyer or distributor agrees to assume any and all responsibility and
liability for and hold AKEMD harmless from any and all claims arising from the use of said product in
the absence of such notification.
162
2008/03