INNOVASIC L64250JC20 Histogram/hough transform processor Datasheet

IA64250
Histogram/Hough Transform Processor
Data Sheet
August 19, 2008
IA64250
Histogram/Hough Transform Processor
Data Sheet
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Histogram/Hough Transform Processor
Copyright
Data Sheet
August 19, 2008
2008 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
fido®, fido1100®, and SPIDER are trademarks of Innovasic Semiconductor, Inc.
I2C™ Bus is a trademark of Philips Electronics N.V.
Motorola is a registered trademark of Motorola, Inc.
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IA64250
Histogram/Hough Transform Processor
Data Sheet
August 19, 2008
TABLE OF CONTENTS
Features ........................................................................................................................................... 4
Block Diagram ................................................................................................................................ 6
Description ...................................................................................................................................... 7
I/O Signal Description ................................................................................................................ 8
Initialization Mode .......................................................................................................................... 9
Memory Configurations ................................................................................................................ 11
ACC RAM Find Pixel Mode .................................................................................................... 12
Computation Mode ....................................................................................................................... 13
I/O Mode ................................................................................................................................... 15
I/O Sequences ............................................................................................................................... 16
Writing LUT RAM ............................................................................................................... 18
Pixel Processing ........................................................................................................................ 19
AC/DC Parameters........................................................................................................................ 20
DC Characteristics ........................................................................................................................ 20
AC Characteristics ........................................................................................................................ 21
Pixel Processing Operation ....................................................................................................... 21
I/O Timing ................................................................................................................................ 21
Control Memory Timing – Writing Mode Data ....................................................................... 21
Control Memory Timing – Reading and Writing Markers: Packaging Information .................... 22
Packaging Information .................................................................................................................. 23
Ordering Information .................................................................................................................... 24
Revision History ........................................................................................................................... 24
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IA64250
Histogram/Hough Transform Processor
Data Sheet
August 19, 2008
Features
Histogram and Hough Transform Calculation
Four 512 X 9 Look-up Tables Provided to Perform User-defined Point-wise
Transformations
Real-time Histogram Equalization
High Data Rates
512 X 24 Accumulation RAM
Pixel Location Function
The IA64250 is a "plug-and-play" drop-in replacement for the original LSI L64250. This replacement IC
has been developed using innovASIC’s MILESTM, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while ensuring
they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even
as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA64250 including functional and I/O descriptions, electrical characteristics, and applicable timing.
Package Pinout for 68 PLCC PACKAGE:
9
8
7
6
5
4
3
2
1
68
67
66
65 64 63
62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27
28 29
30
31 32 33
34 35
36
37
38 39 40
41
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Histogram/Hough Transform Processor
Data Sheet
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PIN DESIGNATOR:
PIN
NAME
GND
CI.5
CI.4
CI.3
CI.2
CI.1
CI.0
WE
REGADR.5
VDD
REGADR.4
REGADR.3
REGADR.2
REGADR.1
REGADR.0
VDO.8
VDO.7
GRID #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PIN
NAME
GND
VDD
VDO.6
VDO.5
VDO.4
VDO.3
VDO.2
VDO.1
VDO.0
VDD
RESET FP
GND
RY
CY
RX
CX
CLK1
GRID #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
PIN
NAME
GRID #
GND
35
STARTIO
36
VDD
37
CLK2
38
PO
39
IODV
40
DV
41
AT
42
GND
43
VDD
44
DO.0
45
DO.1
46
DO.2
47
DO.3
48
DO.4
49
VDD
50
GND
51
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PIN
NAME
DO.5
DO.6
DO.7
DO.8
DI.0
DI.1
DI.2
DI.3
DI.4
VDD
DI.5
DI.6
DI.7
DI.8
CI.8
CI.7
CI.6
GRID #
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
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Histogram/Hough Transform Processor
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Block Diagram
Figure 1
MOD_RAMDATA
SYNC
24
AT
RAMADDR 9
REGADR
24
ACC RAM
512 X 24
RAMDATA 24
ADDER
6
SYNC
9
SHIFT
24
24
CLOCK
STARTIO_N
HCLR
2
DV
DO
SAT
RESETFP
SEL
DI
9
4
CONTROLLER
9
LUT
2
CLOCK
LUTADDR
IODV
LUTDATA
OUT_SEL
CLOCK
10
LUTOUT
LUT RAM
4 X 512 X 9
9
ADDER
9
VDO
SHIFT
9
9
CI
9
OUT_SEL
CY
CLOCK
RESET
FP
2
RY
Y
COUNTER
Y
9
9
CX
CLOCK
FP
COUNTER
CLOCK
RX
X
COUNTER
X
9
CI
AT
MARKER
MEMORY
MODE
REGADR
WE_N
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Histogram/Hough Transform Processor
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Description
The IA64250 performs three separate tasks, histogram generation, modified Hough transforms, and
pixel location. There are three modes of operation for the IA64250: computation, I/O, and
initialization.
The controller block in the block diagram decodes the instructions and contains the mode registers.
After decoding the mode, the controller generates all of the control signals to the rest of the part.
These control signals include the addresses and input data for the LUT and ACC RAMs, the select
lines for both the output mux and the shifter, and the reset for the FP counter. This block also
controls the clearing of the ACC RAM.
The ACC RAM stores the video data that is to be output during the I/O mode. This data can be
modified, depending on mode, by several methods prior to being output. These methods are
described in the computation mode section.
The LUT RAM can store up to four different data modifying functions. These functions are used to
modify the video data coming in and access the appropriate data in the ACC RAM through the ACC
RAM address. This data is then sent out on the DO output.
During the initialization mode, the functions to be performed are defined. This is accomplished by
setting the values in the mode registers contained in the controller block.
During the computation mode, the histogram, Hough transform, or pixel location data is computed.
Data equalization also occurs during this mode if desired. The controller block controls the adders
and shifters during this mode to ensure correct data manipulation. This is accomplished through the
data stored in the mode registers as well as the DV input. The controller block also generates the
addresses to both the RAMs.
The I/O mode allows data to be transferred to the Accumulation RAM (ACC RAM) and/or to and
from the Look Up Table RAM (LUT RAM). The user can also update the marker memory during
the I/O mode. The marker memory is used to quickly find points of interest on the histogram,
Hough transform, or accumulated histogram curves. Up to seven points of interest can be specified
on the grey level axis or parameter axis. The corresponding value on the accumulation axis will then
be available. The reverse is also true, where the user can specify accumulation values of interest and
obtain the corresponding grey values. The memory map located in the I/O mode description shows
the configuration of the data stored in the memory. The transfer of data from an external source to
either of the RAMs is done through either the CI or DI input bus. The controller block takes in the
data and passes it along to the appropriate RAM. The controller block also supplies the RAM with
the address and control signals needed to write the data. During a data transfer from one RAM to
the other, the controller block performs a similar task, overseeing the transfer and supplying the
necessary control signals and address.
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I/O Signal Description
The diagram below describes the I/O characteristics for each signal on the IC. The signal
names correspond to the signal names on the pinout diagrams provide.
I/O Characteristics:
IODV
VDO.0 - VDO.8
CIO.0 - CIO.8
WE
REGADR.0 - REGADR.5
O
O
I
I
I
AT
I
When HIGH, ACC RAM or LUT RAM data on the DO bus is valid.
LUT RAM data output (uses CLK1).
Control register and LUT input data bus.
Used to strobe data into mode latches when LOW.
Selects mode latch, marker or maximum registers.
Selects marker and maximum registers when HIGH or mode latches when LOW.
AT must be LOW to access the LUT or ACC RAMs via the DO bus.
CLK1
I
Pixel clock active at rising edge.
CLK2
I
User I/O clock (may be connected to CLK1)
STARTIO
CX,CY
RX,RY
RESET FP
I
I
I
I
Initiates RAM I/O at HIGH to LOW transition.
Used to increment X or Y counters when HIGH.
Resets X or Y counters(overrides CX, CY) when HIGH.
Resets FP counter when HIGH.
PO
O
Test pin should be left unconnected.
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Initialization Mode
Initialization defines the operation of the IA64250. The mode and marker memories store
66 nine-bit words that define the operation of the part and contain marker information. The
REGADR input is used to select the proper register. Data is written over the CI bus and
read on the DO bus. The AT pin controls whether data is a mode word or a marker. When
AT is low, the data written is mode information, which is stored in the mode registers
contained in the controller block. When AT is high, the data is a marker, and is stored in the
marker memory. To prevent erroneous operation STARTIOn should be high, and IODV
and DV should be low during initialization.
Mode Register Table:
A
T
0
0
REGA
DR
0
1
R/
W
W
R
W
W
BIT LOCATION
ci0
do0
sel0
fn0
ci1
do1
sel1
fn1
ci2
do2
sel2
Eq
ci3
do3
sel3
io0
ci4
do4
lut0
io1
ci5
do5
lut1
hclr0
ci6
do6
sh1
hclr1
ci7
do7
sat
func
ci8
do8
TESTn
pdwn
Marker Memory Table:
AT
1
1
1
1
REGADR
0
1
2
3
R/W
R
R
R
R
CONTENTS
GREY LEVEL OF MAXIMUM ACC COUNT BITS 0-8
MAXIMUM ACC COUNT BITS 0-8
MAXIMUM ACC COUNT BITS 9-17
MAXIMUM ACC COUNT BITS 18-23*
1
1
1
1
16
17
18
19
W
W
W
W
TEST MODE, DO NOT ACCESS
TEST MODE, DO NOT ACCESS
TEST MODE, DO NOT ACCESS
TEST MODE, DO NOT ACCESS
1
1
1
1
32
33
34
35
R/W
R/W
R/W
R/W
R/W MARKER 0 GREY LEVEL BITS 0-8
R/W MARKER 0 ACC COUNT BITS 0-8
R/W MARKER 0 ACC COUNT BITS 9-17
R/W MARKER 0 ACC COUNT BITS 18-23*
1
1
1
1
36
37
38
39
R/W
R/W
R/W
R/W
1
1
1
1
56
57
58
59
R/W
R/W
R/W
R/W
R/W MARKER 1 GREY LEVEL BITS 0-8
R/W MARKER 1 ACC COUNT BITS 0-8
R/W MARKER 1 ACC COUNT BITS 9-17
R/W MARKER 1 ACC COUNT BITS 18-23*
.
.
.
R/W MARKER 6 GREY LEVEL BITS 0-8
R/W MARKER 6 ACC COUNT BITS 0-8
R/W MARKER 6 ACC COUNT BITS 9-17
R/W MARKER 6 ACC COUNT BITS 18-23*
*ACC COUNT BIT 18-23 APPEARS ON BIT LOCATION 0-5 RESPECTIVELY
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Mode Definition:
The controller block decodes the instructions brought in to the IA64250 on the CI bus, with
the REGADR input determining which instructions are being read in. The Mode Memory
table shows the configuration of the CI bus encoded instruction depending on the state of
REGADR. A brief description of the instruction bits follows:
sel(3:0) selects the nine bits of the ACC RAM to be transferred to the DO output or to the LUT
RAM.
sel0
0
1
0
1
0
…
1
sel1
0
0
1
1
0
sel2
0
0
0
0
1
sel3
0
0
0
0
0
Sel
0
1
2
3
4
window
select bits 0-8
select bits 1-9
select bits 2-10
select bits 3-11
select bits 4-12
1
1
1
15
select bits 15-23
lut(1:0) defines one of the four 512 X 9 LUTs as active.
sh1
When low, the least significant nine bits of the 10 bit LUT and Y count sum will address the
ACC RAM. When high, the nine most significant bits of the sum will be used.
sat
When high, the nine bits selected from the 24 bit ACC RAM output will be forced to 511
(111111111) if the 24 bit ACC RAM output contains a 1 in the range of bits from the sel + 9
to 23. Otherwise the nine bits selected from the ACC RAM output will be unchanged.
test
Used for testing when low. Should be high for normal operation.
fn(1:0) Determines the operation performed during the computational mode.
fn0
0
0
1
1
eq
fn1
0
1
0
1
FUNCTION
modified Hough transform computation
undefined
histogram computation
pixel location
When high, causes the output of the ACC RAM to be accumulated as it is read. This is
commonly used to compute the histogram equalization transfer function. When low, the
ACC RAM output is not modified.
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io(1:0) Control the operations of the ACC and LUT RAMs during I/O mode (when the
STARTIOn signal has been asserted).
io0
0
0
1
1
io1
0
1
0
1
FUNCTION
transfer data from the ACC RAM to the LUT RAM
read the ACC RAM
read the LUT RAM
write the LUT RAM
hclr(1:0) Control the clearing of the ACC RAM during I/O mode
hclr0
0
hclr1
0
0
1
1
1
0
1
func
FUNCTION
ACC RAM cleared when either the ACC RAM or LUT RAM is
accessed
Undefined
ACC RAM cleared only when the ACC RAM is accessed
ACC RAM not cleared during an i/o operation
Determines the function performed by the marker processor. When high, each marker
circuit within the processor will locate an accumulated count from the ACC RAM
corresponding to the previously given grey value. When low, each marker will locate the
grey value corresponding to a previously given accumulation count from the ACC RAM.
pdwn When high, the ACC and LUT RAMs are placed in an inactive mode. Should be low for
normal operation.
Memory Configurations
The following memory maps specify the configuration of the ACC RAM and the LUT RAM in the
various computational modes.
ACC RAM Histogram Mode:
Grey Level
0
1
.
.
.
.
511
Memory Contents
Count for Grey Value 0
Count for Grey Value 1
.
.
.
.
Count for Grey Value 511
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ACC RAM Modified Hough Transform Mode:
Hough Transform
Parameter Axis
0
1
.
.
.
.
Memory Contents
511
Projection Along r = 511
Projection Along r = 0
Projection Along r = 1
.
.
.
.
ACC RAM Find Pixel Mode
Address
0
1
.
.
.
.
N
N+1
.
.
.
.
511
Memory Contents
0-8
9-17
18-23
X0
Y0
FLAG
X1
Y1
FLAG
XN
0
YN
0
FLAG
0
0
0
0
LUT RAM Histogram Computation:
Histogram Transfer Function
0
1
.
.
.
.
511
Memory Contents
f(0)
f(1)
.
.
.
.
f(511)
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LUT RAM Hough Transform Mode
(45 <
90):
Address
0
1
.
.
.
.
511
Memory Contents
0*cot
1*cot
.
.
.
.
511*cot
LUT RAM Find Pixel Mode:
Address
0
1
.
.
.
.
511
Memory Contents
0-5
Flag for Grey Value
0
Flag for Grey Value
1
.
.
.
.
Flag for Grey Value
511
6-7
t0
8
Not Used
t1
Tag
Bit
t511
Computation Mode
Histogram Computation:
During histogram computation, the ACC RAM and LUT RAM form the active elements of
the data path. The ACC RAM is addressed by the controller block. The ACC RAM address
is the DI input signal. The data addressed by the DI signal is incremented if the DV input
signal is high, otherwise the data is left unchanged. The LUT is not used in the computation
of the histogram and can concurrently modify the image by a user-defined transfer function.
The DI signal addresses the LUT and the LUT data appears on the VDO output pins two
clock cycles later.
Histogram equalization can be performed in real time. The histogram is stored in the ACC
RAM. The equalization transfer function must be computed and transferred into the LUT
RAM. Then during the next frame as a new histogram is being computed, data will also be
equalized in real time and passed to the VDO output pins.
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Hough Transform Computation:
During Hough Transform computation, the ACC RAM stores the projection image, and the LUT
RAM is loaded with the function listed in the Modified Hough Transform Parameterization Table.
Case
1a
1b
1c
1d
r(X,Y, )
X tan + Y
Y cot + X
(YMAX - Y) cot (180 (XMAX - X) tan (180 -
)+X
)+Y
LUT[i]
itan
icot
(YMAX - I) cot (180 (XMAX - I) tan (180 -
)
)
CX,RX
Controls
X
Y
Y
X
During initialization, the LUT is loaded with the appropriate transfer function to compute
either f(x) or f(y). Once the LUT is loaded, the X and Y counters are used to generate the
proper memory addresses. The X counter is incremented at each valid pixel and reset at the
beginning of each line. The Y counter is incremented at the beginning of each line and reset
at the beginning of each frame. The control signals for these two counters are generated in
the controller block. As each pixel location along a line is addressed, the grey value at that
point is added to the partial sum in the memory location.
Intensity Averaging:
Another computational mode is possible by generating ACC RAM addresses differently. An
example of this is to compute the average intensity of an image as a function of position.
Consider a 512 X 512 pixel image divided into 256 blocks (16 X 16) of 32 X 32 pixels each.
To compute the average intensity, the Y counter would be incremented every 32 pixels and
reset at the beginning of each line. The X counter would be incremented every 32 lines and
reset at the beginning of a frame. The proper addresses will be generated by multiplying the
X counter output by 16 (this is done via the LUT). After processing, the first 256 locations
of the ACC RAM will hold the accumulated intensity in each 32 X 32 region. Setting sel(3:0)
= 10 will give the average intensity in each region.
Pixel Location:
Pixel location is used to determine the X and Y coordinates of up to 64 specific pixels or
group of pixels in an image. When performing pixel location, the user first loads one of the
LUTs with a table indicating which pixels are of interest. Each pixel in the table is assigned a
6 bit flag that allows the user to distinguish groups of pixels.
Each time an interesting pixel (as specified in the LUT) is found, the X, Y, and flag values
are stored in the ACC RAM at the address given by the FP counter. The FP counter is then
incremented. Note that only 512 values can be stored at any instance. In the event that
more values are stored, the first RAM locations will be overwritten.
Pixel location uses the LUT and the X and Y counters to store a six-bit code and location
information about pixels of interest. The X and Y counters hold the coordinates of the grey
value on the DI pins and are controlled in the same manner described in the Hough
transform section. DI addresses the LUT producing a one-bit tag and a six bit flag
associated with the grey value. If the tag bit is high and DV is high the six bit flag and X, Y
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CY,RY
Controls
Y
X
X
Y
IA64250
Histogram/Hough Transform Processor
Data Sheet
August 19, 2008
coordinates are stored in the ACC RAM. Storage space is assigned sequentially as defined by
the FP counter.
I/O Mode
Once a computation has taken place, the user reads data from the LUT or the ACC RAM.
These operations typically take place during a vertical retrace or some other period when the
processor is not busy and AT is low. This mode is also to load the LUT with the desired
transfer function. Generally, these operations are controlled by CLK2 so that data may be
read or written at a different rate than the pixel clock. If the ACC RAM is accessed, the
marker values will be updated.
The internal signals hclr(1:0) control whether or not the ACC RAM is cleared during I/O
operations. These values are stored in the mode registers of the controller block during the
initialization mode. If both hclr0 and hclr1 are high then the ACC RAM will not be cleared
during any I/O operation. If hclr0 is high and hclr1 is low, then each ACC RAM location
will be cleared after it is read. If both hclr0 and hclr1 are low then each ACC RAM location
is cleared when either the ACC RAM location or the corresponding LUT RAM location is
accessed.
Read/Transfer ACC RAM:
Once the histogram has been computed and stored in the ACC RAM, the user asserts
STARTIOn low to initiate reading of the data. One data value is read out of the ACC RAM
during each clock cycle of CLK2 starting with address 0. The address counter for the ACC
RAM is contained in the controller block. If STARTIO remains low, all 512 data values will
be read in sequential address order and the processor will return to pixel processing mode
after 512 clock cycles. If STARTIOn is returned high, the I/O mode halts and the user can
return to pixel processing operations. When the output flag IODV is high, the processor
has placed valid data from the LUT or ACC RAMs onto the I/O bus.
The user controls the destination of the ACC RAM data via the io(1:0) bits in the mode
registers located in the control memory. Code 01 signifies that histogram data will be placed
on the DO output bus, while code 00 will transfer data from the ACC RAM to the LUT
RAM.
In both cases the user can modify the histogram data. By setting the internal EQ control bit
high, an accumulated histogram will be output. The shifter allows the user to determine
which nine bits of the 24 bit ACC RAM output will be directed to the DO bus and LUT
RAM. The shifter control data is stored in the mode registers. The control signals for the
shifter are generated in the controller block. Additional control over the output format can
be obtained via the SAT pin in the control memory. When SAT is high, the resultant nine
bit shifted output will be forced to 511 (111111111) if overflow occurs in the shifter.
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Marker Circuitry:
When ACC RAM is accessed, the marker circuitry in the marker memory is updated. The
user can specify up to seven values of grey level and the associated count will be stored in
the mode memory. Setting func = 1 in the control memory register will accomplish this. By
setting func = 0, the user can specify a particular count and the marker memory will be
updated with the last grey value whose count is equal to (or just exceeds) the count of
interest.
The maximum count, and the grey value which it occurred at, are also updated during each
I/O cycle and stored in mode memory locations 0-3.
If the accumulated histogram is being computed, i.e. the EQ bit in the mode register is set,
then the maximum count register will be equal to the number of pixels scanned, and the grey
value will be the maximum grey level occurring in the image.
Reading and Writing the LUT:
Data input to and output from the LUT RAM is also controlled by CLK2 and STARTIOn.
On the falling edge of STARTIOn, the I/O cycle is initiated with the LUT RAM addresses
being read or written sequentially with each cycle of CLK2. This process is controlled by the
address counter in the controller block.
LUT read/write operations are defined by the io0-1 bits in the control memory. Code 10 is
used to read the LUT RAM. Data will be read sequentially and output on the DO bus. To
write the LUT RAM, code 11 is used in the control memory. Input from the CI bus is
stored in successive addresses with each cycle of CLK2.
The LUT RAM can also be addressed from the DI bus. A typical application would be
histogram equalization. The LUT would contain the equalized transfer function generated
by transferring ACC RAM data to the LUT with EQ high. Setting the FN0-FN1 bits for
histogram computation configures data from the DI bus to address both the ACC RAM and
the LUT. Equalized data is then output on the VDO bus. Histogram computation is taking
place concurrently. In this case CLK2 should be connected to CLK1 to achieve an
equalization rate equal to the pixel rate.
I/O Sequences
Read ACC, Read LUT, Transfer ACC to LUT
I/O operations can be divided into two groups: those that end before all 512 elements of
the ACC or LUT RAM have been accessed (short cycle) and those that end after all 512
elements have been accessed (long cycle). All I/O cycles are initiated by a high to low
transition on the STARTIOn input signal. AT must be low in each case.
The short cycle is terminated when STARTIOn is returned high before all elements of the
RAM have been read. The first data value appears on the DO pins three CLK2 cycles after
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STARTIOn goes low. The IODV flag also goes high after three cycles, indicating that the
data is valid. After the desired number of memory elements have been read, the user returns
STARTIOn high. The I/O mode completes three cycles later and IODV returns low to
indicate the end of the I/O operation. As soon as IODV returns low, the processor returns
to the pixel processing mode specified by the mode register.
The long cycle is terminated without user intervention after all elements of the ACC or LUT
RAMs have been accessed. Again, valid data appears on the DO pins three CLK2 cycles
after STARTIOn goes low. In this case, IODV is high for 512 CLK2 cycles and goes low
after the last RAM element has been read. After IODV returns low, STARTIOn can remain
low or be raised high at any time without affecting the operation of the IA64250.
READING ACC/LUT
RAM OR TRANSFERING
ACC TO LUT:
Short I/O Cycle:
CLK2
STARTIO
D0
XXXX
XXXX
XXXX
RAM0
RAM1
RAM2
XXXX
IODV
End of Long I/O Cycle:
CLK2
STARTIO
DO
RAM508
RAM509
RAM510
RAM511
XXXX
XXXX
XXXX
IODV
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WRITE LUT
The writing of data into the LUT RAM is similar to the operations described above, except
that the data to write into the RAM is placed on the CI bus when STARTIOn is low.
However, as described above, the processor will not return to the pixel processing mode
until IODV returns low.
The net result of this is that the IA64250 enters the I/O mode as soon as the STARTIOn
pin is pulled low and does not return to the pixel processing mode until IODV returns low.
The I/O mode will last N + 3 CLK2 cycles, where N is the number of RAM elements
written.
Writing LUT RAM
Short I/O Cycle
CLK2
STARTIO
CI[7:0]
RAM0
RAM1
RAM2
XXXX
XXXX
XXXX
RAM4
RAM5
XXXX
IODV
Start of Long I/O Cycle:
CLK2
STARTIO
CI
RAM0
RAM1
RAM2
RAM3
RAM6
IODV
End of Long I/O Cycle:
CLK2
STARTIO
CI
RAM508
RAM509
RAM510
RAM511
XXX
XXXX
XXXX
IODV
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Pixel Processing
(SMALL 2 x 2 IMAGE):
CLK1
RY
RX.CY
CX
DV
DI
VDO
I(0,0)
I(1,0)
I(0,1)
I(1,1)
XXXX
F(I(0,0))
F(I(1,0))
F(I(01))
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AC/DC Parameters
Military (TA = -55 to 125 C, VDD = 4.5 to 5.5V). All times in ns.
SYMBOL
tCYCLE
tPWH
tPWL
tDIS
tDIH
tOD
tWC
tPWW
tAS
tAH
tCS
tCH
tADO
tWD
PARAMETER
Minimum clock cycle time
Minimum clock pulse width HIGH
Minmum clock pulse width LOW
Input data setup time
Input data hold time
Output delay
Minimum WE cycle time
Minimum WE pulse width LOW
AT Address setup time
AT Address hold time
Coefficient setup time
Coefficient hold time
Output delay from address valid
Output Delay from WE
MIN
60
28
25
25
7
MAX
0.38
2.28
17.78
180
75
75
75
75
75
24.53
24.53
DC Characteristics
Specified at VDD = 5V over the specified temperature and voltage ranges1.
SYMBOL
PARAMETER
VIL
VIH
Low level input voltage
High level input voltage
Military temperature
range
Input current
High level output voltage
Low level output voltage
Output short circuit
current2
Quiescent supply current3
Operating supply current
Input capacitance
Output capacitance
IIN
VOH
VOL
IOS
IDDQ
IDD
CIN
COUT
CONDITION
MIN
TYP
MAX
0.8
2.25
VIN = VDD
IOH = -3.2 mA
IOL = 3.2 mA
VDD = Max, VO = VDD
VDD = Max, VO = 0V
VIN = VDD or VSS
tCYCLE = 50ns
Any input
Any output
-150
2.4
UNIT
V
V
200
4.5
0.2
15
-5
200
5
10
0.4
130
-100
15
uA
V
V
mA
mA
mA
mA
pF
pF
Notes:
1. Military temperature range is –55 to 125 C, +/- 10% power supply.
2. Not more than one output should be shorted at a time. Duration of short circuit test must not exceed
one second.
3. In power down mode.
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AC Characteristics
Pixel Processing Operation
tCYCLE
tPWH
tPWL
CLK1
tDIS
tDIH
DI_DV
tOD
VDO
I/O Timing
tWC
tPWH
tPWL
CLK2
tDIS
tDIH
CI/STARTIO
tOD
DO/IODV
Control Memory Timing – Writing Mode Data
tWC
WE
tAS
tPWW
tAH
ADDR
tCS
tCH
CI
tAS
AT
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Control Memory Timing – Reading
and Writing Markers:
tWC
WE
tAS
tPWW
tAH
ADDR
tCS
tCH
CI
tAS
AT
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Packaging Information
68 PLCC Package:
1.14X45°
.254X45°
SEE DETAIL A
PIN 1 IDENTIFIER
b
E1 E
e
A
D1
D
DETAIL A
A1
SEATING PLANE
c
68 PLCC, (17X17 pins):
Symbol
A
A1
b
c
D
D1
E
E1
e
MILLIMETER
MIN
NOM
MAX
4.02
5.08
2.29
3.3
0.331
0.53
0.2
25.02
25.27
24.13
24.33
25.02
25.27
24.13
24.33
1.27
BSC
IA211011114-01
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MIN
0.165
0.09
0.013
INCH
NOM
MAX
0.2
0.13
0.021
0.008
0.985
0.95
0.985
0.95
0.995
0.958
0.995
0.958
0.05
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Ordering Information
Part Number
IA64250-PLC68M
Temperature Grade
Military
Package Description
68 lead Plastic Leaded Chip Carrier
Cross Reference to Original Manufacturer Part Numbers:
innovASIC Part Number
IA64250-PLC68M
LSI Part Number


L64250JC15
L64250JC20
Revision History
The table below presents the sequence of revisions to document IA211011114.
Date
August 19, 2008
Revision
01
Description
Corrected control number and reformatted
some elements to meet publication
standards.
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