LF353-N www.ti.com SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 LF353-N Wide Bandwidth Dual JFET Input Operational Amplifier Check for Samples: LF353-N FEATURES DESCRIPTION • • • • • • • • • • • These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage (BI-FET II technology). They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF353-N is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and LM358 designs. 1 2 Internally Trimmed Offset Voltage: 10 mV Low Input Bias Current: 50pA Low Input Noise Voltage: 25 nV/√Hz Low Input Noise Current: 0.01 pA/√Hz Wide Gain Bandwidth: 4 MHz High Slew Rate: 13 V/μs Low Supply Current: 3.6 mA High Input Impedance: 1012Ω Low Total Harmonic Distortion : ≤0.02% Low 1/f Noise Corner: 50 Hz Fast Settling Time to 0.01%: 2 μs These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Typical Connection 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated LF353-N SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 www.ti.com Simplified Schematic Figure 1. 1/2 Dual Dual-In-Line Package Top View Figure 2. 8-Pin SOIC (See D Package) 8-Pin PDIP (See P Package) 2 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N LF353-N www.ti.com SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage ±18V See (3) Power Dissipation Operating Temperature Range 0°C to +70°C Tj(MAX) 150°C Differential Input Voltage ±30V Input Voltage Range (4) ±15V Output Short Circuit Duration Continuous Storage Temperature Range −65°C to +150°C Lead Temp. (Soldering, 10 sec.) 260°C Soldering Information: Dual-In-Line Package Soldering (10 sec.) 260°C Small Outline Package 215°C Vapor Phase (60 sec.) Infrared (15 sec.) 220°C ESD Tolerance (5) 1000V θJA D Package (1) (2) (3) (4) (5) TBD Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. For operating at elevated temperatures, the device must be derated based on a thermal resistance of 115°C/W typ junction to ambient for the P package, and 160°C/W typ junction to ambient for the D package. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Human body model, 1.5 kΩ in series with 100 pF. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N 3 LF353-N SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 www.ti.com DC Electrical Characteristics Symbol VOS Parameter Input Offset Voltage LF353-N Conditions MIn Typ Max RS=10kΩ, TA=25°C Over Temperature 5 10 13 ΔVOS/ΔT Average TC of Input Offset Voltage RS=10 kΩ 10 IOS Input Offset Current Tj=25°C (1) (2) 25 Tj≤70°C Tj=25°C (1) (2) IB Input Bias Current RIN Input Resistance Tj=25°C AVOL Large Signal Voltage Gain VS=±15V, TA=25°C 50 Tj≤70°C 25 Units mV mV μV/°C 100 pA 4 nA 200 pA 8 nA 1012 Ω 100 V/mV VO=±10V, RL=2 kΩ Over Temperature 15 VO Output Voltage Swing VS=±15V, RL=10kΩ ±12 ±13.5 V/mV V VCM Input Common-Mode Voltage VS=±15V ±11 +15 V −12 V CMRR Common-Mode Rejection Ratio RS≤ 10kΩ 70 100 dB PSRR Supply Voltage Rejection Ratio See (3) 70 100 dB IS Supply Current Range 3.6 6.5 mA These specifications apply for VS=±15V and 0°C≤TA≤+70°C. VOS, IBand IOS are measured at VCM=0. The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, Tj. Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj=TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = ±6V to ±15V. (1) (2) (3) AC Electrical Characteristics (1) Symbol Parameter LF353-N Conditions Min Amplifier to Amplifier Coupling TA=25°C, f=1 Hz−20 kHz (Input Referred) SR Slew Rate VS=±15V, TA=25°C 8.0 GBW Gain Bandwidth Product VS=±15V, TA=25°C 2.7 en Equivalent Input Noise Voltage TA=25°C, RS=100Ω, f=1000 Hz in Equivalent Input Noise Current THD Total Harmonic Distortion (1) 4 Typ Max Units −120 dB 13 V/μs 4 MHz 16 nV/√Hz Tj=25°C, f=1000 Hz 0.01 pA/√Hz AV=+10, RL=10k, VO=20Vp−p, BW=20 Hz-20 kHz <0.02 % These specifications apply for VS=±15V and 0°C≤TA≤+70°C. VOS, IBand IOS are measured at VCM=0. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N LF353-N www.ti.com SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 Typical Performance Characteristics Input Bias Current Input Bias Current Figure 3. Figure 4. Supply Current Positive Common-Mode Input Voltage Limit Figure 5. Figure 6. Negative Common-Mode Input Voltage Limit Positive Current Limit Figure 7. Figure 8. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N 5 LF353-N SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 6 Negative Current Limit Voltage Swing Figure 9. Figure 10. Output Voltage Swing Gain Bandwidth Figure 11. Figure 12. Bode Plot Slew Rate Figure 13. Figure 14. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N LF353-N www.ti.com SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Distortion vs. Frequency Undistorted Output Voltage Swing Figure 15. Figure 16. Open Loop Frequency Response Common-Mode Rejection Ratio Figure 17. Figure 18. Power Supply Rejection Ratio Equivalent Input Noise Voltage Figure 19. Figure 20. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N 7 LF353-N SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Open Loop Voltage Gain (V/V) Output Impedance Figure 21. Figure 22. Inverter Settling Time Figure 23. 8 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N LF353-N www.ti.com SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 Pulse Response Figure 24. Small Signaling Inverting Figure 25. Large Signal Inverting Figure 26. Small Signal Non-Inverting Figure 27. Large Signal Non-Inverting Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N 9 LF353-N SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 www.ti.com Figure 28. Current Limit (RL = 100Ω) 10 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N LF353-N www.ti.com SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 APPLICATION HINTS These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±6V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kΩ load resistance to ±10V over the full temperature range of 0°C to +70°C. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N 11 LF353-N SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 www.ti.com Detailed Schematic 12 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N LF353-N www.ti.com SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 Typical Applications Three-Band Active Tone Control (1) All controls flat. (2) Bass and treble boost, mid flat. (3) Bass and treble cut, mid flat. (4) Mid boost, bass and treble flat. (5) Mid cut, bass and treble flat. • All potentiometers are linear taper • Use the LF347 Quad for stereo applications Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N 13 LF353-N SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 www.ti.com Improved CMRR Instrumentation Amplifier (1) Fourth Order Low Pass Butterworth Filter (2) 14 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N LF353-N www.ti.com SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 Fourth Order High Pass Butterworth Filter (3) Ohms-to-Volts Converter (4) Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N 15 LF353-N SNOSBH3F – APRIL 1998 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LF353-N IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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