ASM3P622S01B/J May 2007 rev 0.4 Low Frequency Timing-Safe™ Peak EMI reduction IC General Features • eight-pin version and accepts one reference input and drives out one low-skew clock. • Low Frequency Clock distribution with TimingSafe™ Peak EMI Reduction Input frequency range: 4MHz - 20MHz. • Zero input - output propagation delay the REF pin. The PLL feedback is on-chip and is obtained • Low-skew outputs from the CLKOUT pad, internal to the device. • Output-output skew less than 250pS • Device-device skew less than 700pS All parts have on-chip PLLs that lock to an input clock on Multiple ASM3P622S01B/J devices can accept the same • Less than 200pS cycle-to-cycle jitter input clock and distribute it. In this case, the skew between • Available in 8pin, 150 mil SOIC, 4.4mm TSSOP the outputs of the two devices is guaranteed to be less than Package 700pS. • 3.3V Operation • Industrial temperature range The output has less than 200pS of cycle-to-cycle jitter. The • • Advanced CMOS technology The First True Drop-in Solution input and output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 250pS. Functional Description Refer “Spread Spectrum Control and Input-Output Skew ASM3P622S01B/J is a versatile, 3.3V Zero-delay buffer designed to distribute low frequency Timing-Safe™ clocks Table” for deviations and Input-Output Skew for ASM3P622S01B/J devices. with Peak EMI Reduction. The ASM3P622S01B/J is the Block Diagram VDD SSON SS% PLL Modulation XIN/CLKIN XOUT Crystal Oscillator Reference Divider Feedback Divider Phase Detector Loop Filter VCO Feedforward Divider GND PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. CLKOUT ASM3P622S01B/J May 2007 rev 0.4 Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves PCBs etc. These methods are expensive. Spread with a 50% duty cycle and as frequencies increase the spectrum clocking reduces the peak energy by reducing edge rates also get faster. Analysis shows that a square the Q factor of the clock. This is done by slowly wave is composed of fundamental frequency and modulating the clock frequency. The ASM3P622S01B/J harmonics. The fundamental frequency and harmonics uses the center modulation spread spectrum technique in generate the energy peaks that become the source of which the modulated output frequency varies above and EMI. Regulatory agencies test electronic equipment by below measuring the amount of peak energy radiated from the modulation rate. With center modulation, the average equipment. In fact, the peak level allowed decreases as frequency is the same as the unmodulated frequency and the frequency increases. The standard methods of there is no performance degradation. the reference frequency with a specified reducing EMI are to use shielding, filtering, multi-layer Timing-Safe™ technology Timing-Safe™ technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Pin Configuration CLKIN 1 CLKOUT1 2 8 CLKOUT3 7 VDD 3 6 CLKOUT2 GND 4 5 SSON 8 CLKOUT2 7 VDD 3 6 CLKOUT1 GND 4 5 SSON ASM3P622S01B SS% XIN / CLKIN 1 XOUT 2 ASM3P622S01J SS% Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 2 of 12 ASM3P622S01B/J May 2007 rev 0.4 Pin Description for ASM3P622S01B Pin # Pin Name 1 CLKIN 2 Description Input reference frequency, 5V-tolerant input 1 CLKOUT1 2 Buffered clock output 3 SS% Spread Spectrum Selection 4 GND Ground 5 SSON2 Spread Spectrum enable and disable option When SSON is HIGH, the spread spectrum is enabled and when LOW, it turns off the spread spectrum. 1 6 CLKOUT2 7 VDD 8 Buffered clock output 3.3V supply 1 CLKOUT3 Buffered clock output Notes: 1. Weak pull-down on all outputs. 2. Weak pull-up on these Inputs. 3. Buffered clock outputs are Timing-Safe™ Pin Description for ASM3P622S01J Pin # Pin Name 1 XIN/CLKIN 2 XOUT can be connected either to an external crystal or an external reference clock. Crystal connection. If using an external reference, this pin must be left unconnected. 3 SS%2 Spread Spectrum Selection 4 GND Ground 5 SSON2 6 CLKOUT 7 VDD 8 CLKOUT Description Crystal connection or external reference frequency input. This pin has dual functions. It Spread Spectrum enable and disable option When SSON is HIGH, the spread spectrum is enabled and when LOW, it turns off the spread spectrum. 1 Buffered clock output 3.3V supply 1 Buffered clock output Notes: 1. Weak pull-down on all outputs 2. Weak pull-up on these Inputs 3. Buffered clock outputs are Timing-Safe™ Spread Spectrum Control and Input-Output Skew Table Device Input Frequency ASM3P622S01B/J 12MHz SS % Deviation Input-Output Skew(±TSKEW) 0 ±0.25 % 0.063 1 ±0.50 % 0.125 Note: TSKEW is measured in units of the Clock Period Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 3 of 12 ASM3P622S01B/J May 2007 rev 0.4 Absolute Maximum Ratings Symbol Parameter Rating Unit VDD Voltage on any pin with respect to Ground -0.5 to +4.6 V TSTG Storage temperature -65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) 2 KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions for ASM3P622S01B/J Device Parameter Description Min Max Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) -40 +85 °C CL Load Capacitance 30 pF CIN Input Capacitance 7 pF Electrical Characteristics for ASM3P622S01B/J Parameter VIL Description Test Conditions Min Typ 1 Input LOW Voltage 1 Max Unit 0.8 V VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50 µA IIH Input HIGH Current VIN = VDD 100 µA IOL = 8mA 0.4 V VOL 2.0 Output LOW Voltage2 2 VOH Output HIGH Voltage IOH = -8mA IDD Supply Current Unloaded outputs Zo Output Impedance V 2.4 V 15 mA 23 Ω Note: 1. CLKIN input has a threshold voltage of VDD/2 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 4 of 12 ASM3P622S01B/J May 2007 rev 0.4 Switching Characteristics for ASM3P622S01B/J Parameter 1/t1 Description Test Conditions Output Frequency 2 Duty Cycle = (t2 / t1) * 100 t3 t4 t5 t6 1, 2 Output Rise Time 1, 2 Output Fall Time Output-to-output skew 2 Delay, CLKIN Rising Edge to CLKOUT Rising Edge 2 t7 Device-to-Device Skew 2 tJ Cycle-to-cycle jitter 2 tLOCK PLL Lock Time 2 Min Max Unit 20 MHz 60 % Measured between 0.8V and 2.0V 2.5 nS Measured between 2.0V and 0.8V 2.5 nS All outputs equally loaded 250 pS Measured at VDD /2 ±250 pS 700 pS 200 pS 1.0 mS 30pF load 4 Measured at VDD/2 40 Measured at VDD/2 on the CLKOUT pins of the device Loaded outputs Stable power supply, valid clock presented on CLKIN pin Typ 50 Note: 1. The parameters specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 5 of 12 ASM3P622S01B/J May 2007 rev 0.4 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time OUTPUT 2.0 V 0.8 V 2.0 V 0.8 V 3.3 V 0V t4 t3 Output - Output Skew 1.4 V O UTPUT 1.4 V O UTPUT t5 Input - Output Propagation Delay VDD /2 INPUT VDD /2 OUTPUT t6 Device - Device Skew CLKOUT, Device 1 VDD /2 VDD /2 CLKOUT, Device 2 t7 Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 6 of 12 ASM3P622S01B/J May 2007 rev 0.4 Input-Output Skew Test Circuit Input Timing-Safe™ Output +3.3V TSKEW - OUTPUTS TSKEW+ VDD CLKOUT CLOAD 0.1uF GND One clock cycle N=1 TSKEW represents input-output skew when spread spectrum is ON For example, TSKEW = ± 0.125 for an Input clock12MHz, translates in to (1/12MHz) * 0.125=10.41nS A Typical example of Timing-Safe™ waveform Input Input CLKOUT with SSOFF Timing-Safe™ CLKOUT Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 7 of 12 ASM3P622S01B/J May 2007 rev 0.4 Package Information 8-lead (150-mil) SOIC Package H E D A2 A C A1 D θ e L B Dimensions Symbol Inches Min Max Millimeters Min Max A1 0.004 0.010 0.10 0.25 A 0.053 0.069 1.35 1.75 A2 0.049 0.059 1.25 1.50 B 0.012 0.020 0.31 0.51 C 0.007 0.010 0.18 0.25 D 0.193 BSC 4.90 BSC E 0.154 BSC 3.91 BSC e 0.050 BSC 1.27 BSC H 0.236 BSC 6.00 BSC L 0.016 0.050 0.41 1.27 θ 0° 8° 0° 8° Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 8 of 12 ASM3P622S01B/J May 2007 rev 0.4 8-lead TSSOP (4.40-MM Body) H E D A2 A C θ e A1 L B Dimensions Symbol Inches Min Millimeters Max A Min Max 0.043 1.10 A1 0.002 0.006 0.05 0.15 A2 0.033 0.037 0.85 0.95 B 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 D 0.114 0.122 2.90 3.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.252 BSC 6.40 BSC L 0.020 0.028 0.50 0.70 θ 0° 8° 0° 8° Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 9 of 12 ASM3P622S01B/J May 2007 rev 0.4 Ordering Codes Ordering Code Marking Package Type Temperature ASM3P622S01BF-08-ST 3P622S01BF 8-pin 150-mil SOIC-TUBE, Pb Free Commercial ASM3I622S01BF-08-ST 3I622S01BF 8-pin 150-mil SOIC-TUBE, Pb Free Industrial ASM3P622S01BF-08-SR 3P622S01BF 8-pin 150-mil SOIC-TAPE & REEL, Pb Free Commercial ASM3I622S01BF-08-SR 3I622S01BF 8-pin 150-mil SOIC-TAPE & REEL, Pb Free Industrial ASM3P622S01BF-08-TT 3P622S01BF 8-pin 4.4-mm TSSOP - TUBE, Pb Free Commercial ASM3I622S01BF-08-TT 3I622S01BF 8-pin 4.4-mm TSSOP - TUBE, Pb Free Industrial ASM3P622S01BF-08-TR 3P622S01BF 8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free Commercial ASM3I622S01BF-08-TR 3I622S01BF 8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free Industrial ASM3P622S01BG-08-ST 3P622S01BG 8-pin 150-mil SOIC-TUBE, Green Commercial ASM3I622S01BG-08-ST 3I622S01BG 8-pin 150-mil SOIC-TUBE, Green Industrial ASM3P622S01BG-08-SR 3P622S01BG 8-pin 150-mil SOIC-TAPE & REEL, Green Commercial ASM3I622S01BG-08-SR 3I622S01BG 8-pin 150-mil SOIC-TAPE & REEL, Green Industrial ASM3P622S01BG-08-TT 3P622S01BG 8-pin 4.4-mm TSSOP - TUBE, Green Commercial ASM3I622S01BG-08-TT 3I622S01BG 8-pin 4.4-mm TSSOP - TUBE, Green Industrial ASM3P622S01BG-08-TR 3P622S01BG 8-pin 4.4-mm TSSOP - TAPE & REEL, Green Commercial ASM3I622S01BG-08-TR 3I622S01BG 8-pin 4.4-mm TSSOP - TAPE & REEL, Green Industrial ASM3P622S01JF-08-ST 3P622S01JF 8-pin 150-mil SOIC-TUBE, Pb Free Commercial ASM3I622S01JF-08-ST 3I622S01JF 8-pin 150-mil SOIC-TUBE, Pb Free Industrial ASM3P622S01JF-08-SR 3P622S01JF 8-pin 150-mil SOIC-TAPE & REEL, Pb Free Commercial ASM3I622S01JF-08-SR 3I622S01JF 8-pin 150-mil SOIC-TAPE & REEL, Pb Free Industrial ASM3P622S01JF-08-TT 3P622S01JF 8-pin 4.4-mm TSSOP - TUBE, Pb Free Commercial ASM3I622S01JF-08-TT 3I622S01JF 8-pin 4.4-mm TSSOP - TUBE, Pb Free Industrial ASM3P622S01JF-08-TR 3P622S01JF 8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free Commercial ASM3I622S01JF-08-TR 3I622S01JF 8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free Industrial ASM3P622S01JG-08-ST 3P622S01JG 8-pin 150-mil SOIC-TUBE, Green Commercial ASM3I622S01JG-08-ST 3I622S01JG 8-pin 150-mil SOIC-TUBE, Green Industrial ASM3P622S01JG-08-SR 3P622S01JG 8-pin 150-mil SOIC-TAPE & REEL, Green Commercial ASM3I622S01JG-08-SR 3I622S01JG 8-pin 150-mil SOIC-TAPE & REEL, Green Industrial ASM3P622S01JG-08-TT 3P622S01JG 8-pin 4.4-mm TSSOP - TUBE, Green Commercial ASM3I622S01JG-08-TT 3I622S01JG 8-pin 4.4-mm TSSOP - TUBE, Green Industrial ASM3P622S01JG-08-TR 3P622S01JG 8-pin 4.4-mm TSSOP - TAPE & REEL, Green Commercial ASM3I622S01JG-08-TR 3I622S01JG 8-pin 4.4-mm TSSOP - TAPE & REEL, Green Industrial Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 10 of 12 ASM3P622S01B/J May 2007 rev 0.4 Device Ordering Information A S M 3 P 6 2 2 S 0 1 B F - 0 8 - T R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 11 of 12 ASM3P622S01B/J May 2007 rev 0.4 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: ASM3P622S01B/J Document Version: 0.4 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Timing-Safe™ US Patent Pending. © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 12 of 12