ON NCP3233MNTXG High current synchronous buck converter Datasheet

NCP3233
High Current Synchronous
Buck Converter
The NCP3233 is a high current, high efficiency voltage−mode
synchronous buck controller which operates from 3.0 V to 21 V input
and generates output voltages down to 0.6 V at up to 20 A.
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Features
• Wide Input Voltage Range from 3.0 V to 21 V
• 0.6 V 1% Accurate Internal Reference Over Temperature
• Fixed Switching Frequency: 500 kHz (1 MHz and 300 kHz options
1
contact factory)
External Programmable Soft−Start
Lossless Low−side and High−side FET Current Sensing
Output Overvoltage Protection and Undervoltage Protection
Recoverable Overvoltage Protection
Hiccup Mode Operation for UVP, LS OCP and TSD
Pre−bias Start−up
Adjustable Output Voltage
Power Good Output
Internal Overtemperature Protection
Adjustable Input UVLO
This is a Pb−Free Device
1 40
A
WL
YY
WW
G
COMP
ISET
GND
VB
SS
FB
EN
VIN
VIN
VIN
1
4
3
5
2
6
9
8
10
VIN
11
VIN
12
VIN
13
VIN
14
VSW
15
36 PG
PGND
16
35 BST
PGND
17
PGND
18
PGND
19
32 VSW
PGND
20
31 VSW
40 VCC
VIN
EP42
39 XCP
GND
EP41
38 VINX
37 GND
34 VSW
27
28
29
PGND
PGND
VSW
30
26
PGND
VSW
25
PGND
23
PGND
24
22
33 VSW
PGND
21
PGND
VSW
EP43
PGND
Cellular Base Stations
ASIC, FPGA, DSP and CPU Core and I/O Supplies
Telecom and Network Equipment
Server and Storage System
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Typical Application
•
•
•
•
NCP3233
AWLYYWWG
QFN40 6x6, 0.5P
CASE 485AZ
7
•
•
•
•
•
•
•
•
•
•
•
MARKING
DIAGRAM
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP3233MNTXG
QFN40
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 4
1
Publication Order Number:
NCP3233/D
NCP3233
XCP
VINX
VB
Charge
Pump
VCC
VB
VB
VCC
BST
LDO
VB
OSC
VIN
COMP
VB
Control Logic
Ramp Generator
PWM Logic
VREF
E/A
FB
− and −
SS
UVLO
OVP, UVP
Power Good
HS and LS OCP, TSD
Protection
Soft Start
VCC
2 mA
EN
VSW
VB
VB
Enable
Logic
PGND
1.2V
POR
PG
GND
ISET
Figure 1. NCP3233 Block Diagram
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2
NCP3233
PIN DESCRIPTION
Pin No.
Symbol
1
ISET
Description
2
VB
The internal LDO output and input supply for the NCP3233. Connect a minimum of 4.7 mF ceramic
capacitor from this pin to PGND.
3
FB
Output voltage feedback.
4
COMP
5, 37
GND
6
SS
A capacitor from this pin to GND allows the user to adjust the soft−start ramp time.
7
EN
Logic control for enabling the switcher. An internal pull−up enables the device automatically. The EN pin
can also be driven high to turn on the device, or low to turn off the device. A comparator and precision
reference allow the user to implement this pin as an adjustable UVLO circuit.
8−14, EP42
VIN
The VIN pin is connected to the internal power MOSFETs. Connect input capacitor from VIN to PGND as
close as possible.
15, 29−34,
EP43
VSW
16−28
PGND
Ground reference and high−current return path for the low−side gate driver and low−side MOSFET.
35
BST
Top gate driver input supply, a bootstrap capacitor connection between the switch node and this pin.
36
PG
Power good indicator of the output voltage. Open−drain output. Connect PG to VCC with an external
resistor.
38
VINX
Input pin of internal charge pump, tie to VIN for 3.3 V input voltage application cases and tie to GND for
5 V or higher input voltage application cases.
39
XCP
Switching node of internal charge pump, leave it floating for 5 V or higher input voltage application cases
40
VCC
Input Supply for IC.
EP41
GND
Exposed Pad. Connect GND to a large copper plane at ground potential to improve thermal dissipation.
A resistor from this pin to ground sets the low−side overcurrent protection (OCP) threshold.
Output of the error amplifier.
Analog ground.
The VSW pin is connection of the drain and source of the internal power MOSFETs. Connect VSW to
one terminal of the inductor.
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3
NCP3233
VIN=3.3V
BST
VIN
VINX
Vout
VSW
XCP
ISET
NCP3233
VCC
FB
VB
COMP
VPG
EN
GND
PG
PGND
SS
Figure 2. Typical Application Circuit for VIN = 3.3 V
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4
NCP3233
VIN=3.3V
BST
VIN
VINx
Vout
VSW
XCP
ISET
NCP3233
VCC=5.0V
VCC
FB
VB
COMP
VB
EN
GND
PG
PGND
SS
Figure 3. Typical Application Circuit for Separate Rail in System VIN = 3.3 V and VCC = 5 V
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5
NCP3233
VIN>5.0V
BST
VIN
VINX
Vout
VSW
XCP
ISET
NCP3233
VCC
FB
VB
COMP
VB
EN
GND
PG
PGND
SS
Figure 4. Typical Application Circuit for VIN . 5.0 V
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NCP3233
VIN = 3.0 V − 21 V
BST
VIN
VINX
Vout
VSW
XCP
ISET
NCP3233
VCC = 5.0 V
VCC
FB
VB
COMP
VB
EN
GND
PG
PGND
SS
Figure 5. Typical Application Circuit for VIN = 3.0 V − 21 V and VCC = 5 V
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7
NCP3233
ABSOLUTE MAXIMUM RATINGS (measured vs. GND pads, unless otherwise noted)
Rating
Symbol
Value
Unit
VIN, VCC
(Note 1)
21
−0.3
V
VSW to GND
VSWH
23
−0.6 (DC)
28 V (t < 50 ns)
−5 V (t < 50 ns)
V
BST to GND
BST
28 (DC)
−0.6 (DC)
33 V (t < 50 ns)
V
6.0
−0.3
V
Power Supply to GND
All other pins
Operating Ambient Temperature Range
TA
−40 to +90
°C
Operating Junction Temperature Range (Note 1)
TJ
−40 to +125
°C
TJ(MAX)
+150
°C
Maximum Junction Temperature
Tstg
−55 to +150
°C
Electrostatic Discharge − Human Body Model
HBM
1.0
kV
Electrostatic Discharge − Charged Device Model
CDM
2.0
kV
HS FET Junction−to−Case Thermal Resistance (Note 2)
RqJC−HS
1.3
°C/W
LS FET Junction−to−Case Thermal Resistance (Note 2)
RqJC−LS
0.6
°C/W
RqJA
35
°C/W
Storage Temperature Range
Junction−to−Ambient Thermal Resistance
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. When VIN and VCC are connected together, VCC max value is 21 V.
2. RqJC thermal resistance is obtained by simulating a cold plate test on the exposed power pad. No specific JEDEC standard test exists, but
a close description can be found in the ANSI SEMI standard G30−88.
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8
NCP3233
ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VIN = VCC = 12 V, for min/max values unless otherwise noted, TJ =
+25°C for typical values)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
POWER SUPPLY
3.0
21
V
VINX Operation Voltage
VINX
VINX not connected to GND
3.0
5.5
V
VCC Operation Voltage
VCC
Vin > 5 V
5.0
21
V
VIN Operation Voltage
VIN
VB UVLO Threshold (Rising)
4.2
4.4
4.5
V
VB UVLO Threshold (Falling)
3.9
4.0
4.1
V
VINX UVLO Threshold (Rising)
2.7
2.9
3.05
V
VINX UVLO Threshold (Falling)
2.4
2.6
2.8
V
VINX UVLO Hysteresis
VB UVLO Falling Blanking Time
VB Output Voltage
VB
VB Dropout Voltage
VCC = 6 V, 0 < IB < 40 mA
VCC Quiescent Current
Shutdown Supply Current
V
2
ms
5.15
5.45
V
IB = 25 mA, VCC = 4.5 V
50
100
mV
VB Current Limit
4.9
0.275
VCC = 12 V
100
EN = H, COMP = H, no switching; PG open
4.5
7
mA
mA
mA
EN = 0; VCC = 16 V; PG open
110
130
EN = 0; VCC = 4.5 V; PG open
70
80
XCP Frequency
VINx = 3.3 V
250
kHz
XCP Drive Low Resistance
VINx = 3.3 V
3.3
W
XCP Drive High Resistance
VINx = 3.3 V
7.7
W
mA
FEEDBACK VOLTAGE
FB Input Voltage
Feedback Input Bias Current
VFB
TJ = 25°C, 4.5 V ≤ VCC ≤ 21 V
0.597
0.6
0.603
−40°C < TJ < 125°C; 4.5 V ≤ VCC ≤ 21 V
0.594
0.6
0.606
IFB
VFB = 0.6 V
75
V
nA
ERROR AMPLIFIER
Open Loop DC Gain (GBD)
Open Loop Unity Gain Bandwidth
60
F0dB,EA
Open Loop Phase Margin
Slew Rate
COMP pin to GND = 10 pF
COMP Clamp Voltage, High
3.1
COMP Clamp Voltage, Low
85
dB
24
MHz
60
°
2.5
V/m
3.4
3.6
0.5
V
V
Output Source Current
VFB = 0 V
18
mA
Output Sink Current
VFB = 1 V
20
mA
TJ = 25°C
See OCP section for more information
56.5
CURRENT LIMIT
Low−side RDSON over ISET
Current
RDSON/ISET
Low−side ISET Current Source
Temperature Coefficient
TC_LS_I−SET
Low−side OCP Switch−over
Threshold
Low−side Programmable OCP
Range
LS_OCPth
59.0
61.5
W/A
+0.23
%/°C
600
mV
Guaranteed by characterization
600
mV
High−side Fixed OCP
HS_OCP
30
A
HS OCP Min on time
HS_Tblnk
150
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP3233
ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VIN = VCC = 12 V, for min/max values unless otherwise noted, TJ =
+25°C for typical values)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
CURRENT LIMIT
LS OCP Blanking time
LS_Tblnk
150
ns
92
88
85
%
0
%
PWM
Maximum duty cycle
fsw = 500 kHz, VFB = 0 V, VIN = 5 V
fsw = 500 kHz, VFB = 0 V, VIN = 12 V
fsw = 500 kHz, VFB = 0 V, VIN = 21 V
Guaranteed by characterization
Minimum duty cycle
VCOMP < PWM Ramp Offset Voltage
88
86
67
Minimum GH on−time
Guaranteed by characterization
50
PWM Ramp Amplitude
Feedforward Ramp VINx = 0 V
VIN / 5.4
Feedforward Ramp VINx = 3.3 V
VIN / 1.4
PWM Ramp Offset
65
ns
V
0.63
V
OSCILLATOR
Oscillator Frequency Range
Hiccup Time Duration
fsw
fsw = 500 kHz, 3 V < VCC < 21 V
thiccup
fsw = 500 kHz, tSS > 1 ms
fsw = 500 kHz, tSS < 1 ms
450
500
550
4*tss
4
kHz
ms
ENABLE INPUT (EN)
EN Input Operating Range
5.5
Enable Threshold Voltage
V
VEN rising
1.13
1.2
1.27
V
VEN falling
Guaranteed by characterization
60
140
210
mV
Deep Disable Threshold
0.8
1.1
V
Enable Pull−up Current
2
Enable Hysteresis
mA
SOFTSTART INPUT (SS)
SS Start Delay
tSSD
SS End Threshold
SSEND
SS Source Current
ISS
2.3
2.6
3.0
ms
2.8
mA
0.6
2.15
2.5
V
VOLTAGE MONITOR
Power Good Sink Current
PG = 0.15 V
Output Overvoltage Rising
9
12
17
mA
725
750
775
mV
500
525
550
mV
Overvoltage Fault Blanking Time
ms
5
Output Under−Voltage Trip
Threshold
Under−voltage Protection Blanking
Time
20
ms
UVP Enable Delay
tSS
s
POWER STAGE
High−side on Resistance
RDSONH
−40°C < TJ < +125°C
2.8
4.8
6.7
mW
Low−side on Resistance
RDSONL
−40°C < TJ < +125°C
VGS = 5.2 V, ID = 20 A
0.9
2.0
3.9
mW
VFBOOT
IBOOT = 2 mA
0.2
V
Thermal Shutdown Threshold
150
°C
Thermal Shutdown Hysteresis
25
°C
THERMAL SHUTDOWN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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10
NCP3233
100
90
90
EFFICIENCY (%)
100
80
70
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
60
50
0
2
4
6
8
10
12
14
16
80
70
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
60
VIN = 3.3 V
FSW = 500 kHz
L = 0.33 mH
50
18
0
20
4
2
6
8
100
90
80
70
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
50
0
2
10
12
14
16
18
20
Figure 7. Efficiency vs. Load Current (VIN = 5.0 V),
Inductor: Wurth Electronics 7443320033
Figure 6. Efficiency vs. Load Current (VIN = 3.3 V),
Inductor: Wurth Electronics 7443320033
60
VIN = 5.0 V
FSW = 500 kHz
L = 0.33 mH
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY (%)
TYPICAL CHARACTERISTICS
4
6
8
VIN = 12.0 V
FSW = 500 kHz
L = 0.47 mH
10
12
14
16
18
20
LOAD CURRENT (A)
Figure 8. Efficiency vs. Load Current (VIN = 12.0 V),
Inductor: Wurth Electronics 7443320047
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11
NCP3233
TYPICAL CHARACTERISTICS
510
505
VIN = 12 V
500
VIN = 4.5 V
495
490
485
5
20
35
50
65
80 95 110 125
0.610
0.605
0.600
0.595
0.590
−40 −25 −10
5
20
35
50
65
80 95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Switching Frequency vs. Junction
Temperature
Figure 10. Feedback Reference Voltage vs.
Junction Temperature (VIN = 4.5 V and 12 V)
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
−40 −25 −10
5
20
35
50
65
80 95 110 125
ENABLE FALLING THRESHOLD VOLTAGE (V)
ENABLE RISING THRESHOLD VOLTAGE (V)
480
−40 −25 −10
VINX RISING THRESHOLD VOLTAGE (V)
FEEDBACK REFERENCE VOLTAGE (V)
515
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
1.02
1.00
−40 −25 −10
5
20
35
50
65
80 95 110125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Enable Rising Threshold Voltage vs.
Junction Temperature
Figure 12. Enable Falling Threshold Voltage
vs. Junction Temperature
3.00
2.95
2.90
2.85
2.80
−40 −25 −10
5
20
35
50
65
80
95 110 125
VINX FALLING THRESHOLD VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
520
2.70
2.68
2.66
2.64
2.62
2.60
−40 −25 −10
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. VINX Rising Threshold Voltage vs.
Junction Temperature
Figure 14. VINX Falling Threshold Voltage vs.
Junction Temperature
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NCP3233
VB FALLING THRESHOLD VOLTAGE (V)
4.40
4.38
4.36
4.34
4.32
4.30
−40 −25 −10
5
20
35
50
65
80
95 110 125
4.06
4.04
4.02
4.00
3.98
3.96
3.94
3.92
−40 −25 −10
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. VB Rising Threshold Voltage vs.
Junction Temperature
Figure 16. VB Falling Threshold Voltage vs.
Junction Temperature
16
90
14
89
12
10
8
6
4
2
0
−40 −25 −10
5
20
35
50
65
80
95 110 125
88
87
86
85
84
83
82
81
80
−40 −25 −10
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Quiescent Current vs. Junction
Temperature (VCC = 12 V, No Switching)
Figure 18. Shutdown Current vs. Junction
Temperature (VIN = 12 V)
SOFT−START SOURCE CURRENT (mA)
60
55
LS OCP ISET CURRENT (mA)
4.08
TJ, JUNCTION TEMPERATURE (°C)
SHUTDOWN CURRENT (mA)
QUIESCENT CURRENT (mA)
VB RISING THRESHOLD VOLTAGE (V)
TYPICAL CHARACTERISTICS
50
45
40
35
30
25
20
−40 −25 −10
5
20
35
50
65
80
95 110 125
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
−40 −25 −10
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. LS OCP ISET Current vs. Junction
Temperature
Figure 20. Soft−Source Current vs. Junction
Temperature
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NCP3233
OPERATION DESCRIPTION
Overview
OCP is the only fault that is active during a soft−start.
The NCP3233 is a 500 kHz fixed switching frequency,
high efficiency, and high current PWM synchronous buck
converter with a wide range of input voltage. It operates with
a single supply voltage from 3.0 V to 21 V and provides
output current as high as 20 A. NCP3233 utilizes voltage
mode control with input voltage feed−forward to provide for
easier compensation over the supply range of the converter.
For 3.3 V input voltage applications, with pin VINX
connected to pin VIN it enables an internal charge pump to
boost input voltage high enough to supply the internal LDO
and internal circuits. The internal charge pump’s operating
frequency is 250 kHz to reduce its power consumption. For
5.0 V or higher input voltage applications, with pin VINX
connected to GND, it disables the internal charge pump to
optimize the overall efficiency. The device also includes
pre−bias start−up capability to allow monotonic startup in
the event of a pre−biased output condition.
Protection features include over current protection (OCP),
output over and under voltage protection (OVP, UVP), and
internal thermal shut down (TSD) and power good indicator.
The enable function is highly programmable to allow for
adjustable startup voltages at higher input voltages. There is
also an SS pin for user to adjust the soft start time.
Adaptive Non−Overlap Gate Driver
In a synchronous buck converter, a certain dead time is
required between the low side drive signal and high side drive
signal to avoid shoot through. During the dead time, the
body diode of the low side FET freewheels the current. The
body diode has much higher voltage drop than that of the
MOSFET, which reduces the efficiency significantly. The
longer the body diode conducts, the lower the efficiency.
NCP3233 implements adaptive dead time control to
minimize the dead time, as well as preventing shoot through.
Pre−bias Startup
In some applications the controller will be required to start
switching when its output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converter’s output capacitors may have residue charge or the
converter’s output may be held up by a low current standby
power supply. NCP3233 supports pre−bias startup by
holding off switching until the output voltage rises above the
set regulated voltage. If the pre−bias voltage is higher than
the set regulated voltage, switching does not occur until the
output voltage drops back to the regulation point.
Reference Voltage
Precision Enable (EN)
The NCP3233 incorporates an internal reference that
allows output voltages as low as 0.6 V. The tolerance of the
internal reference is guaranteed over the entire operating
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error
amplifier offset and bias currents.
The ENABLE block allows the output to be toggled on
and off and is a precision analog input.
When the EN voltage exceeds V_EN, the controller will
initiate the soft−start sequence as long as the input voltage
and sub−regulated voltage have exceeded their UVLO
thresholds. V_EN_hyst helps to reject noise and allow the
pin to be resistively coupled to the input voltage or
sequenced with other rails.
If the EN voltage is held below 0.8 V, the NCP3233 enters
a deep shutdown state where the internal bias circuitry is off.
As the voltage at EN continues to rise, the Enable
comparator and reference are active and provide a more
accurate EN threshold. The drivers and charge pump are
held off until the rising voltage at EN crosses V_EN.
An internal 2 mA pullup automatically enables the device
when the EN pin is left floating.
Oscillator / Ramp
The ramp waveform is a saw tooth form at the PWM
frequency with a peak−to−peak amplitude of VCC/5.4 and
VCC/1.4, offset from GND by 0.7 V. The PWM duty cycle
is limited to a maximum of 92%, allowing the bootstrap
capacitors to charge during each cycle.
Error Amplifier
The error amplifier’s primary function is to regulate the
converter’s output voltage using a resistor divider connected
from the converter’s output to the FB pin of the controller,
as shown in the Applications Schematic. A type III
compensation network must be connected around the error
amplifier to stabilize the converter. It has a bandwidth of
greater than 24 MHz, with open loop gain of at least 60 dB.
INPUT SUPPLY / VCC
VDD
2 uA
Programmable Soft−Start
EN
An external capacitor connected from the SS pin to
ground sets up the soft−start period, which can limit the
start−up inrush current. The soft−start period can be
programmed based on the following equations:
t SS +
V ref
C SS
I SS
Enable
Logic
1.2 V
Figure 21.
(eq. 1)
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NCP3233
PROTECTION FEATURES
Under Voltage Protection (UVP)
high−side MOSFET drain to source voltage is compared
against a preset voltage reference. Once the overcurrent
protection is triggered, the protection scheme will do
cycle−by−cycle limitation to protect the device. It also
senses the freewheeling current in the low−side MOSFET
after a blanking time of 150 ns. The low−side MOSFET
drain to source voltage is compared against the voltage of an
internal temperature compensated current source and a
user−selected resistor RSET. The value of RSET for a given
OCP level is defined by the follow equation:
A UVP circuit monitors the VFB voltage to detect an
undervoltage event. If the VFB voltage is below this
threshold for more than 20 ms, a UVP fault is set and the
device will enter hiccup mode. (See below)
Over Voltage Protection (OVP)
Two−stage recoverable overvoltage protection scheme is
used in NCP3233. If FB pin voltage is higher than 690 mV,
the part enters stage I. In this stage, the control loop tends to
regulate the output voltage by turning off the HS MOSFET
and turning on the LS MOSFET to discharge the output
voltage. In stage I, the PG is still kept high. If FB pin voltage
is higher than 750 mV, the part enters stage II, and it keeps
LS MOSFET ON to discharge the output voltage and
protects the load, and the PG is pulled low. If the output
voltage returns to the nominal value, the loop is enabled
again and PG is pulled high. The control loop naturally takes
over to make sure that the part returns to normal operation.
RSET +
i LS
RDSON
i SET
5
(eq. 2)
In this equation, iLS is the inductor peak current value,
RDSON is the on resistance of low−side MOSFET, and iSET
is an internal current source used to compensate the
temperature effects of on resistance of low−side MOSFET.
NCP3233 can guarantee that RDSON/iSET is a constant
value. By doing this, OCP accuracy won’t be affected by the
variation of MOSFET RDSON. In case RSET is not
connected, the device switches the OCP threshold to a fixed
600 mV threshold.
After one OCP event is detected, the NCP3233 keeps the
high−side MOSFET off until the low−side MOSFET falls
below the trip point again and the high−side MOSFET turns
on in the next clock cycle. So the low−side overcurrent
protection shows pulse skipping behavior. An internal OCP
counter will count up to 3 consecutive OCP events. After the
third consecutive count, the device enters hiccup mode. The
LSOCP scheme is described in Figure 22.
Power Good Monitor (PG)
NCP3233 monitors the output voltage and signal when the
output is out of regulation or during a non−regulated
pre−bias condition, or fault condition. When the output
voltage is within the OVP and UVP thresholds, the power
good pin is a high impdence output. If the NCP3233 detects
an OCP, OVP, UVP, TSD or is in soft start, the PG pin it pulls
PG pin low. The PG pin is an open drain output and sink up
to 5 mA.
Over Current Protection (OCP)
The NCP3233 overcurrent scheme senses the high−side
MOSFET current for high side overcurrent protection. The
Power Good (PG) Operation
Power Good Pullup Voltage
LSOCP Trip Level
Inductor Current
Start
Reset/Start
Reset/Start
Backup Counter
Hiccup
Start
Hiccup Counter
1
2
3
tHiccup = 4xtSS
Skipped Pulses showing Skip Count
Figure 22. LSOCP Function with Counters and Power Good Shown (exaggerated for informational purposes)
www.onsemi.com
15
NCP3233
Hiccup Mode
the board such as input or output decoupling can add loop
inductance.
Ground Return for Power and Signals: Solid,
uninterrupted ground planes must be present and adjacent to
the high current path.
Copper Shapes on Component Layers: Large copper
planes on one or multiple layers with adequate vias will
increase thermal transfer, reduce copper conduction losses,
and minimize loop inductance. Greater than 20 A designs
require 2~3 layer shapes or more, increasing the number of
layers will only improvement performance.
Via Placement for Power and Ground: Place enough
vias to adequately connect outer layers to inner layers for
thermal transfer and to minimize added inductance in layer
transition. Multiple vias should be placed near important
components like input ceramics and output ceramic
capacitors.
Key Signal Routes: Do not route sensitive signals, such
as FB near or under noisy nets such as the switch node VSW
and BST node, to reduce noise coupling effects on the
sensitive lines.
Special layout guide: please pay attention to the special
requirement of layout guide.
To improve the Low−side OCP accuracy, users should use
single ground connection instead of separate analog ground
and power ground. Make sure that the inner layers (at least
2nd layer, 3rd layer and 4th layer) are dedicated for ground
plane. For thermal improvement, add vias as many as
possible to connect top layer to bottom layer and inner
layers. Keep copper pour of GND large, continuous and not
interrupted by other traces, which may affect the heat
transfer.
The NCP3233 utilizes hiccup mode for all of its fault
conditions. After the fault conditions have been met, the
NCP3233 turns off the high side and low side FET’s and PG
goes low. It waits for tHICCUP ms before reinitiating a
soft−start. OVP and OCP are the active fault detections
during the hiccup mode soft−start.
Thermal Shutdown (TSD)
The NCP3233 protects itself from overheating with an
internal thermal monitoring circuit. If the junction
temperature exceeds the thermal shutdown threshold both
the upper and lower MOSFETs will be shut OFF. Once the
temperature drops below the falling hysteresis threshold, the
voltage at the COMP pin will be pulled below the ramp
valley voltage and a hiccup will be initiated.
Application Note
When the input is 3.3 V or even at the minimum value
2.9 V and the load is heavy or is changing in step rapidly if
the impedance of input power supply is not optimized, it can
generate enough voltage drop to trigger input voltage
UVLO. In these applications, the input inductance should
be minimized, and input capacitance should be sufficient
for the biggest step load current.
Layout Guidelines
When laying out a power PCB for the NCP3233 there are
several general key points and special key points to consider.
General layout guide: these are the common techniques
for high frequency high power board layout design.
Base component placement: High current path
components should be placed to keep the current path as
tight as possible. Placement of components on the bottom of
www.onsemi.com
16
NCP3233
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
CASE 485AZ
ISSUE O
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
A B
D
PIN ONE
LOCATION
2X
0.15 C
L
L1
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
EXPOSED Cu
2X
TOP VIEW
0.15 C
(A3)
DETAIL B
0.10 C
DIM
A
A1
A3
b
D
D2
D3
E
E2
E3
e
G
K
L
L1
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
A
43X
0.08 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. POSITIONAL TOLERANCE APPLIES TO ALL
THREE EXPOSED PADS.
L
SIDE VIEW A1
C
NOTE 4
SEATING
PLANE
0.10 C A B
D3
D2
NOTE 5
G
DETAIL A
40X
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.18
0.30
6.00 BSC
2.30
2.50
1.40
1.60
6.00 BSC
4.30
4.50
1.90
2.10
0.50 BSC
2.20 BSC
0.20
−−−
0.30
0.50
−−−
0.15
L
SOLDERING FOOTPRINT
6.30
E3
4.56
E2
1.66
E3
1
1
G
40
K
40X
0.63
2.56
e
40X
e/2
G
BOTTOM VIEW
2.16
b
0.10 C A B
0.05 C
4.56
6.30
NOTE 3
2.16
PKG
OUTLINE
40X
0.50
PITCH
0.30
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
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NCP3233/D