Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 DLPA200 DLP® DMD Micromirror Driver 1 Features 2 Applications • • • 1 • • • • • • Designed for Use as a Part of a DLP Chipset Generates the Micromirror Clocking Pulses Required by the DLP Digital Micromirror Device (DMD) Generates Specialized Voltage Levels Required for Micromirror Clocking Pulse Generation Operates From a Single 12-V Power Supply Provides a VBIAS Voltage Level, Used by the DMD to Control the Array Border Mirrors Provides a VOFFSET Voltage Level, Used by the DMD as DMDVCC2 All Logic Inputs are LVTTL and CMOS Compatible Packaged in an Pb-Free Thermally-Enhanced Surface-Mount Package: 80-Pin, 0.5 mm-Pitch, Enlarged Terminal Pitch, Thin Profile Quad Flat Pack (HTQFP) Block Diagram MODE[1:0] • • Industrial: – Direct Imaging Lithography – Laser Marking and Repair Systems – Computer-to-Plate Printers – Rapid Prototyping Machines and 3D Printers – 3D Scanners for Machine Vision and Quality Control Medical: – Phototherapy Devices – Ophthalmology – Vascular Imaging – Hyperspectral Imaging – 3D Scanners for Limb and Skin Measurement – Confocal Microscopes Display: – 3D Imaging Microscopes – Intelligent and Adaptive Lighting – Augmented Reality and Information Overlay 2 SEL[1:0] 2 A[3:0] 4 STROBE Select, Latch, Output Logic and High-Voltage Output FET Switches 3 Description 16 OUT(00–15) OE The DLPA200 is a DMD micromirror driver that is one of multiple components in a DLP chipset. A dedicated DLP chipset provides developers easier access to the DMD as well as high speed micromirror control. P12V Device Information(1) Internal 5 V and Ref. Supplies V5REG VBIAS_RAIL VBIAS_LHI VBIAS Boost Converter VBIAS_SWL VBIAS VRESET_RAIL (SUBSTRATE) VRESET Buck-Boost Converter VRESET_SWL PART NUMBER DLPA200 PACKAGE HTQFP (80) BODY SIZE 14.00 mm × 14.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. VRESET VOFFSET_RAIL VOFFSET Regulator VOFFSET SCPEN SCPCK Serial Bus Interface SCPDI Power-Up Initialization Fault Logic IRQ SCPDO DEV_ID[1:0] 2 GND RESET 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Configurations........................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 1 1 1 2 4 4 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 Electrical Characteristics Control Logic .................... 8 5-V Linear Regulator................................................. 9 Bias Voltage Boost Converter................................... 9 Reset Voltage Buck-Boost Converter ..................... 10 VOFFSET/DMDVCC2 Regulator................................ 10 Switching Characteristics ...................................... 11 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 14 8.3 Feature Description................................................. 15 9 Application and Implementation ........................ 18 9.1 Application Information............................................ 18 10 Power Supply Recommendations ..................... 20 10.1 Power Supply Rail Guidelines............................... 20 11 Layout................................................................... 21 11.1 Layout Guidelines ................................................. 21 11.2 Thermal Considerations ........................................ 21 12 Device and Documentation Support ................. 22 12.1 12.2 12.3 12.4 12.5 12.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 23 23 13 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2013) to Revision D • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Revision B (August 2012) to Revision C Page • Added DLPR4101 to DLPR410 througout document............................................................................................................. 4 • Changed DAD2000 to DLPA200 in the Serial Communications Port (SCP) section........................................................... 17 • Changed text From: DLPA200PFC is functionally. equivalent.. To: DLPA200PFP ............................................................ 22 Changes from Revision A (June 2010) to Revision B Page • Added Applications ................................................................................................................................................................. 1 • Changed the Description, added Table 1............................................................................................................................... 1 • Added Device Configurations table ........................................................................................................................................ 4 • Changed I/O type of the signals ............................................................................................................................................. 5 • Corrected VRESET_SWL, VBIAS_RAIL and VOFFSET_RAIL signal notations ................................................................... 7 • Added VBIAS voltage to Electrical Characteristics ................................................................................................................... 9 • Added VRESET voltage values to Reset Voltage Buck-Boost Converter................................................................................ 10 • Added VOFFSET voltage to Electrical Characteristics ............................................................................................................. 10 • Added subsection Serial Communications Port (SCP) ........................................................................................................ 17 • Deleted Driver Output Logic Block section........................................................................................................................... 17 • Added Serial Communications Port Signal Definitions table................................................................................................ 17 • Changed Warning to Note .................................................................................................................................................... 20 • Changed Warning to Caution ............................................................................................................................................... 21 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 Changes from Original (April 2010) to Revision A • Page Changed device marking to include TI internal part number................................................................................................ 22 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 3 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com 5 Device Configurations DMD POWER AND MIRROR CLOCKING PULSE DRIVER DLP9500 (0.95 1080p Type A DMD) DIGITAL CONTROLLER DLPA200 (x2) DLP7000 (0.7 XGA Type A DMD) DLPA200 DLP5500 (0.55 XGA S450 DMD) DLPA200 DLPC410 DLPC200 Table 1. Supported DLP Chipset Configurations (1) 0.55 XGA Chipset 0.7 XGA CHIPSET QTY TI PART DESCRIPTION QTY TI PART 1 DLP5500 0.55 XGA S450 DMD(digital micromirror device) 1 DLP7000 DMD Controller for DLP5500 1 DLPC410 1 1 (1) QTY TI PART DESCRIPTION 0.7 XGA Type A DMD (digital micromirror device) 1 DLP9500 0.95 1080p Type A DMD(digital micromirror device) DLP Discovery 4100 DMD Controller 1 DLPC410 DLP Discovery 4100 DMD Controller 1 DLP Discovery 4100 DLPR410 Configuration PROM /DLPR410 1 1 DLPR410 / DLPR410 1 DLP Discovery 4100 Configuration PROM 1 DLPA200 2 DLPA200 DMD Micromirror Driver DLPC200 DLPA200 DMD Micromirror Driver 0.95 1080p CHIPSET DESCRIPTION DMD Micromirror Driver See Overview for more information. 6 Pin Configuration and Functions 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VBIAS_RAIL OUT15 VOFFSET_RAIL OUT14 VRESET_RAIL VRESET_RAIL OUT13 VOFFSET_RAIL OUT12 VBIAS_RAIL VBIAS_RAIL OUT11 VOFFSET_RAIL OUT10 VRESET_RAIL VRESET_RAIL OUT09 VOFFSET_RAIL OUT08 VBIAS_RAIL PFP Package 80-Pin HTQFP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND RESET SCPEN SCPDI SCPCK GND NC G NC NC P12V VOFFSET P12V V5REG GND DEV_ID1 DEV_ID0 IRQ SCPDO GND VBIAS_RAIL OUT00 VOFFSET_RAIL OUT01 VRESET_RAIL VRESET_RAIL OUT02 VOFFSET_RAIL OUT03 VBIAS_RAIL VBIAS_RAIL OUT04 VOFFSET_RAIL OUT05 VRESET_RAIL VRESET_RAIL OUT06 VOFFSET_RAIL OUT07 VBIAS_RAIL 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND MODE1 MODE0 SEL1 SEL0 OE GND VBIAS_SWL VBIAS VBIAS_LHI P12V VRESET_SWL VRESET GND STROBE A3 A2 A1 A0 GND 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 Pin Functions PIN NO. I/O (INPUT DEFAULT) OUT00 22 Output OUT01 24 Output OUT02 27 Output OUT03 29 Output OUT04 32 Output OUT05 34 Output OUT06 37 Output OUT07 39 Output OUT08 62 Output OUT09 64 Output OUT10 67 Output OUT11 69 Output OUT12 72 Output OUT13 74 Output OUT14 77 Output OUT15 79 Output A0 19 Input (pull down) A1 18 Input (pull down) A2 17 Input (pull down) A3 16 Input (pull down) MODE0 3 Input (pull down) MODE1 2 Input (pull down) SEL0 5 Input (pull down) SEL1 4 Input (pull down) Output Voltage Select. Used to switch the voltage applied to the addressed OUTxx pin. STROBE 15 Input (pull down) A rising edge on STROBE latches in the control signals after a tri-state delay. OE 6 Input (pull up) Asynchronous input controls whether the 16 OUTxx pins are active or are in a in high-impedance state. OE = 0 : Enabled. OE = 1 : High Z. RESET 59 Input (pull up) Resets the DLPA200 internal logic. Active low. Asynchronous. SCPEN 58 Input (pull up) Enables serial bus data transfers. Active low. SCPDI 57 Input (pull down) Serial bus data input. Clocked in on the falling edge of SCPCK. SCPCK 56 Input (pull down) Serial bus clock. Provided by chipset Controller. SCPDO 42 Output Serial bus data output (open drain). Clocked out on the rising edge of SCPCK. A 1kΩ pull up resistor to the Chip-Set Controller VDD supply is recommended. IRQ 43 Output Interrupt request output to the chipset Controller. Active low. A 1 kΩ pull up resistor to the Chip-Set Controller VDD supply is recommended. DEV_ID1 45 Input (pull up) DEV_ID0 44 Input (pull up) VBIAS 9 Output VBIAS_LHI 10 Input Current limiter output for VBIAS supply. (also the VBIAS switching inductor input) VBIAS_SWL 8 Input Connection point for VBIAS supply switching inductor. VBIAS_RAIL 21, 30, 31, 40, 61, 70, 71, 80 Input The internally-used VBIAS supply rail. Internally isolated from VBIAS. VRESET 13 Output VRESET_SWL 12 Input NAME DESCRIPTION 16 micromirror clocking waveform outputs (enabled by OE = 0). Output Address. Used to select which OUTxx pin is active at a given time. Mode Select. Used to determine the operating mode of the DLPA200. Serial bus device address: 00 = all; 01 = device 1; 10 = device 2; 11 = device 3. One of three specialized voltages which are generated by the DLPA200. One of three specialized voltages which are generated by the DLPA200. The package thermal pad is tied to this voltage level. Connection point for VRESET supply switching inductor.. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 5 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com Pin Functions (continued) PIN I/O (INPUT DEFAULT) NAME NO. VRESET_RAIL (1) 25, 26, 35,36, 65, 66, 75, 76 Input VOFFSET DESCRIPTION The internally-used VRESET supply rail. Internally isolated from VRESET. (1) 49 Output VOFFSET_RAIL 23, 28, 33, 38, 63, 68, 73, 78 Input The internally-used VOFFSET supply rail. Internally isolated from VOFFSET. GND 1, 7, 14, 20, 41, 46, 53, 55, 60 GND Common ground V5REG 47 Output P12V 11, 48, 50 Input NC 51, 52, 54 No Connect (1) 6 One of three specialized voltages which are generated by the DLPA200. The 5-volt logic supply output. The main power input to the DLPA200. No connect Exposed thermal pad is internally connected to VRESET_RAIL. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MAX UNIT Load supply voltage, P12V MIN 14 V Reset supply switching inductor connection Measured with respect to VRESET_RAIL point, VRESET_SWL –1 V Internally-used VBIAS supply rail, VBIAS_RAIL Measured with respect to VRESET_RAIL 60 V Internally-used VOFFSET supply rail, VOFFSET_RAIL Measured with respect to VRESET_RAIL 40.5 V VIN Logic inputs 7 V VOUT Open drain logic outputs TJ Maximum junction temperature TA Operating temperature Tstg Storage temperature (1) –0.3 7 V 125 °C 0 75 °C –55 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (1) (2) (3) Electrostatic discharge Human body model (HBM) (2) UNIT ±2000 Charged device model (CDM) (3) V 800 Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions at TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) (1) POWER IP12V1 P12V supply current (2) Global shadow at 50 kHz, OUT load = 39 Ω and 390 pF, V5REG = 30 mA, VBIAS = 26 V at 5 mA, VOFFSET = 10V at 30 mA, VRESET = –26 V Thermal shutdown temperature With device temperature rising Hysteresis Delta between thermal shutdown and thermal warning TJTWR (1) (2) NOM Thermal warning temperature With device temperature rising Hysteresis MAX UNIT 200 Outputs disabled and no external loads, VBIAS = 19 V, VOFFSET = 4.5 V, VRESET = –19 V IP12V2 TJTSDR MIN mA 22 mA 145 160 175 °C 5 10 15 °C 5 10 15 °C 125 140 155 °C 5 10 15 °C The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits. During power up the inrush power supply current can be as high as 1 A for a momentary period of time. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 7 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com 7.4 Thermal Information DLPA200 THERMAL METRIC (1) PFP (HTQFP) UNIT 80 PINS Thermal resistance, VBIAS = 26 V, VRESET = -26 V, VOFFSET = 10 V, Output load = 390 pF and 39R on each output, Phase by one with global mode, Channel repetition frequency = 50 kHz, Additional external loads: IBIAS = 5 mA, IOFFSET = 30 mA, I5REG = 30 mA Rc-j (1) 3 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics Control Logic TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) PARAMETER VIL Low-level logic input voltage VIH High-level logic input voltage TEST CONDITIONS MIN TYP MAX 0.8 1.97 UNIT V V IIH High-level logic input current VIN = 5 V, input with pulldown. See terminal functions table. IIL Low-level logic input current VIN = 0 V, input with pullup. See terminal functions table. IIH High-level logic input leakage current VIN = 0 V, input with pulldown –1 1 µA IIL Low-level logic input leakage current VIN = 5 V, input with pullup –1 1 µA VOL Open drain logic outputs I = 4 mA IOL Logic output leakage current V = 3.3 V 8 Submit Documentation Feedback 40 –50 50 –40 µA µA 0.4 V 1 µA Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 7.6 5-V Linear Regulator TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS TYP MAX 4.75 5 5.25 UNIT V5REG Output voltage IIL Output current: internal logic 4 20 mA IIE Output current: external circuitry 0 30 mA ICL5 Current limit VUV5 Undervoltage threshold VRIP Output ripple voltage (1) VOS5 Voltage overshoot at start up tss Power up (1) Average voltage, IOUT = 4 mA to 50 mA MIN V 80 IOUT = 50 mA mA V5REG voltage increasing, P12V = 5.4 V 4.1 V5REG voltage falling, P12V = 5.2 V 3.9 V Measured between 10 to 90% of V5REG 200 mVpk-pk 2 %V5REG 1 ms Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice. 7.7 Bias Voltage Boost Converter TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS IRL Output current: reset outputs Load = 400pF, 39 Ω, repetition frequency = 50 kHz IQL Output current: quiescent / drivers Load = 400 pF, 39 Ω, repetition frequency = 50 kHz IDL Output current: DMD load ICLFB Current limit flag Corresponding current on output at P12V = 10.8 V ICLB Current limit Measured on input VBIAS Output voltage VUVB VBIAS undervoltage threshold Bias voltage falling VUVLHI VBIAS_LHI undervoltage threshold VBIAS_LHI voltage increasing RDS Boost switch RDS(on) TJ = 25°C VRIP Output ripple voltage (1) FSW Switching frequency VOSB Voltage overshoot at start up tss Power up tdis Discharge current sink (1) MIN TYP 0 MAX UNIT 18 mA 3 mA 5 mA 0 30 mA 330 376 460 25.5 26 26.5 50 92 mA V %VBIAS 8 VBIAS_LHI voltage falling V 6.5 V 2 Ω 200 1.35 1.5 1.65 COUT = 3.3 µF, Measured between 10 to 90% of target VBIAS mVpk-pk MHz 2 %VBIAS 1 ms 400 mA Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 9 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com 7.8 Reset Voltage Buck-Boost Converter TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS IRL Output current: reset outputs Load = 400 pF, 39 Ω, repetition frequency = 50 kHz IQL Output current: quiescent / drivers Load = 400 pF, 39 Ω , repetition frequency = 50 kHz ICLFR Current limit flag Corresponding current on output at P12V = 10.8 V ICLR Current limit Measured on input VRESET Output voltage VUVR Undervoltage threshold Reset voltage falling RDS Buck-boost switch RDS(on) TJ = 25°C VRIP Output ripple voltage (1) FSW Switching frequency VOSR Voltage overshoot at start up tss Power up tdis Discharge current sink (1) MIN TYP 0 MAX 18 mA 3 mA 25 mA 400 –25.5 800 –26 50 –26.5 mA V 92 %VRESET Ω 8 1.35 UNIT 1.5 200 mVpk-pk 1.65 MHz 2 %VRESET COUT = 3.3 µF, Measured between 10 to 90% of target VRESET 1 400 ms mA Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice. 7.9 VOFFSET/DMDVCC2 Regulator TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN IRL Output current: reset outputs Load = 400 pF, 39 Ω, repetition frequency = 50 kHz IQL Output current: quiescent / drivers Load = 400 pF, 39 Ω, repetition frequency = 50 kHz IDL Output current: DMDVCC2 ICLO Current limit VOFFSET Output Voltage VUVO Undervoltage threshold 0 UNIT 12.2 mA 3 mA 30 mA VOSO Voltage overshoot at startup tss Power up tdis Discharge time constant mA DLP9500, DLP5500 8.25 8.5 8.75 DLP7000 7.25 7.5 7.75 VOFFSET voltage falling 50 (1) Output ripple voltage 10 0 MAX 100 VRIP (1) TYP V 92 %VOFFSET 100 mVpk-pk 2 %VOFFSET COUT = 4.7 µF, Measured between 10 to 90% of target VOFFSET 1 ms 100 μs Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 7.10 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL COMMUNICATION PORT INTERFACE A (1) Setup SCPEN low to SCPCK Reference to rising edge of SCPCK 360 ns B (1) Byte to byte delay Nominally 1 SCPCK cycle, rising edge to rising edge 1.9 µs C (1) Setup SCPDI to SCPEN high Last byte to slave disable 360 ns D (1) SCPCK frequency E (1) F (1) (2) 0 526 1.9 SCPCK high or low time 300 ns ns SCPDI set-up time Reference to falling edge of SCPCK 300 G (1) SCPDI hold time Reference from falling edge of SCPCK 300 H (1) SCPDO propagation delay Reference from rising edge of SCPCK 2 kHz SCPCK period µs ns 300 SCPEN, SCPCK, SCPDI, RESET filter (pulse reject) 150 ns ns OUTPUT MICROMIRROR CLOCKING PULSES FPREP Phased reset repetition frequency each output pin (non-overlapping) 50 kHz FGREP Global reset repetition frequency all output pins 50 kHz IRLK VRESET output leakage current OE = 1, VRESET_RAIL = -28.5V -1 -10 µA IBLK VBIAS output leakage current OE = 1, VBIAS_RAIL = 28.5V 1 10 µA IOLK VOFFSET output leakage current OE = 1, VOFFSET_RAIL = 10.25V 1 10 µA OUTPUT MICROMIRROR CLOCKING PULSE CONTROLS tSPW STROBE pulse width 10 tSP STROBE period 20 tOHZ Output time to high impedance OE Pin = High 100 ns tOEN Output enable time from high impedance OE Pin = Low 100 ns tSUS Set-up time From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge 8 ns tHOS Hold time From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge 8 ns tPBR tPRO Propagation time tPOB ns ns From STROBE to VBIAS/VRESET edge 50% point. 80 200 ns From STROBE to VRESET/VOFFSET edge 50% point. 80 200 ns From STROBE to VOFFSET/VBIAS edge 50% point. 80 200 ns tDEL Edge-to-edge propagation delta Maximum difference between the slowest and fastest propagation times for any given reset output. 40 ns tCHCH Output channel-to-channel propagation delta Maximum difference between the slowest and fastest propagation times for any two outputs for any given edge. 20 ns (1) (2) See Figure 1 There is no minimum speed for the serial port. It can be written to statically for diagnostic purposes. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 11 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com SCPEN D A E B Clock 1 Byte 1 SCPCK F SCPDI C E X Clock 2 Byte 1 G F X H Clock 3 Byte 1 Clock 8 Byte 1 Clock 1 Byte 2 G F X X X H Clock 8 Last byte G X H SCPDO X = Don’t care Figure 1. Serial Interface Timing 12 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 8 Detailed Description 8.1 Overview Reliable function and operation of the DLPA200 requires that it be used in conjunction with the other components of the chipset. It is typical for the DMD controller to operate the DMD micromirror driver. For more information on the chipset components, see the DLP 0.55 XGA Chipset data sheet or DLP Discovery 4100 Chipset data sheet (Table 8). The DLPA200 consists of three functional blocks: A High-Voltage Power Supply function, a DMD Micromirror Clock Generation function, and a Serial Communication function. The High-Voltage Power Supply function generates three specialized voltage levels: VBIAS (19 to 28 V), VRESET (–19 to –28 V), and VOFFSET (4.5 to 10 V). The Micromirror Clock Generation function uses the three voltages generated by the High-Voltage Power Supply function to create the sixteen micromirror clock pluses (output the OUTx pins of the DLPA200). The Serial Communication function allows the chipset Controller to control the generation of VBIAS, VRESET, and VOFFSET; control the generation of the micromirror clock pulses; status the general operation of the DLPA200. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 13 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com 8.2 Functional Block Diagram MODE[1:0] 2 SEL[1:0] Select, Latch, Output Logic and High-Voltage Output FET Switches 2 A[3:0] 4 STROBE 16 OUT(00–15) OE P12V Internal 5 V and Ref. Supplies V5REG VBIAS_RAIL VBIAS_LHI VBIAS Boost Converter VBIAS_SWL VBIAS VRESET_RAIL (SUBSTRATE) VRESET Buck-Boost Converter VRESET_SWL VRESET VOFFSET_RAIL VOFFSET Regulator VOFFSET SCPEN SCPCK Serial Bus Interface SCPDI Power-Up Initialization Fault Logic IRQ SCPDO DEV_ID[1:0] 2 GND RESET 14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 8.3 Feature Description 8.3.1 5-V Linear Regulator The 5-V linear regulator supplies the 5-V requirement of the DLPA200 internal logic. Figure 2 shows the block diagram of this module. The input decoupling capacitors are shared with other internal DLPA200 modules. See Component Selection Guidelines for recommended component values. 5 V Linear Regulator P12V V5REG GND Figure 2. 5-Volt Linear Regulator Block Diagram 8.3.2 Bias Voltage Boost Converter The bias voltage converter is a switching supply that operates at 1.5 MHz. The bias switching device switches 180° out-of-phase with the reset switching device. The converter supplies the internal bias voltage for the high voltage FET switches and the external VBIAS for the DMD border mirrors. The VBIAS voltage level can be different for different generations of DMDs. The VBIAS voltage level is configured by the DLP Controller chip over a serial communication interface. Four control bits select the voltage level while a fifth bit is the on/off control. The module provides two status bits to indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions. Figure 3 shows the block diagram of this module. The input decoupling capacitors are shared with other internal DLPA200 modules. See Component Selection Guidelines for recommended component values. Inductor VBIAS_LHI VBIAS_SWL P12V VBIAS V5REG BGAP REF OSC BIAS STATUS Serial Interface and Control BIAS CONTROL Bias Boost Converter and Current Limit 2 4 ENABLE GND Figure 3. Bias Voltage Boost Converter Block Diagram 8.3.3 Reset Voltage Buck-Boost Converter The reset voltage buck-boost converter is a switching supply that operates at 1.5 MHz. The reset switching device switches 180° out-of-phase with the bias switching device. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 15 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com Feature Description (continued) The converter supplies the internal reset voltage levels for the high voltage FET switches. The VRESET voltage level can be different for different generations of DMDs. The VRESET voltage level is configured by the DLP controller chip over a serial communication interface. Four control bits select the voltage level while a fifth bit is the on/off control. The module provides two status bits to indicate latched and unlatched status bits for undervoltage (VUV) and current-limit (CL) conditions. Figure 4 shows the block diagram of this module. The input decoupling capacitors are shared with other internal DLPA200 modules. See Component Selection Guidelines for recommended component values. P12V SWL VRESET V5REG BGAP REF OSC Serial Interface and Control RESET STATUS Reset Buck-Boost Converter and Current Limit VRESET_SWL 2 RESET CONTROL 4 Inductor ENABLE GND Figure 4. Reset Voltage Buck-Boost Converter Block Diagram 8.3.4 VOFFSET/DMDVCC2 Regulator The VOFFSET/DMDVCC2 regulator supplies the internal VOFFSET voltage for the high voltage FET switches and the external DMDVCC2 for the DMD. The VOFFSET voltage level can be different for different generations of DMDs. The VOFFSET voltage level is configured by the DLP Controller chip over a serial communication interface. Four control bits select the voltage level while a fifth bit is the on/off control. The module provides 2 status bits to indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions. Figure 5 shows the block diagram of this module. The input decoupling capacitors are shared with other DLPA200 modules. See Component Selection Guidelines for recommended component values. P12V VOFFSET DMDVCC2 V5REG BGAP REF VOFFSET Linear Serial Interface and Control OFFSET STATUS 2 Regulator and Current Limit OFFSET CONTROL 4 ENABLE GND Figure 5. Offset Voltage Boost Convertor Block Diagram 16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 Feature Description (continued) 8.3.5 Serial Communications Port (SCP) The SCP is a full duplex, synchronous, character-oriented (byte) port that allows exchange of data between the master ASIC or FPGA, and one or more slave DLPA200s (and/or other DLP devices). Table 2. Serial Communications Port Signal Definitions SIGNAL SCPCK I/O I FROM/TO SCP bus master to slave TYPE DESCRIPTION LVTTL compatible SCP bus serial transfer clock. The host processor (master) generates this clock. SCPEN I SCP bus master to slave LVTTL compatible SCP bus access enable (low true). When high, slave will reset to idle state, and SCPDO output will tristate. Pulling SCPEN low initiates a read or write access. SCPEN must remain low for an entire read/write access, and must be pulled high after the last data cycle. To abort a read or write cycle, pull SCPEN high at any point. SCPDI I SCP bus master to slave LVTTL compatible SCP bus serial data input. Data bits are valid and must be clocked in on the falling edge of SCPCK. SCPDO O SCP bus slave to master IRQ O SCP bus slave to master SCP bus serial data output. Data bits must clocked LVTTL, open drain w/tri-state out on the rising edge of SCPCK. A 1-kΩ pullup resistor to the 3.3 volt ASIC supply is required. LVTTL, open drain Not part of the SCP bus definition. Asynchronous interrupt signal from slave to request service from master. A 1-kΩ pullup resistor to the 3.3-V ASIC supply is required. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 17 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Component Selection Guidelines Table 3. 5-V Regulator COMPONENT VALUE TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 P12V filter capacitor 10 to 33 µF, 20 VDC, 1Ω max ESR Tantalum or ceramic Pos: P12V, pin 11 (locate near pin 11) Neg: Ground P12V bypass capacitor 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic P12V, pin 11 (locate near pin 11) Ground V5REG filter capacitor 0.1 (1) to 1.0 µF, 10 VDC, 2.5Ω max ESR Tantalum or ceramic Pos: V5REG, pin 47 (locate near pin 47) Neg: Ground Ceramic V5REG, pin 47 (locate near pin 47) Ground (1) V5REG bypass capacitor (1) 0.1 µF , 16 VDC, 0.1Ω max ESR To ensure stability of the linear regulator, the capacitance should not be less than 0.1 µF. Table 4. Bias Voltage Boost Converter COMPONENT VALUE TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 LHI filter capacitor 10 µF, 20 VDC, 1Ω max ESR Tantalum or ceramic Pos: VBIAS_LHI, pin 10 (locate near pin 10) Neg: Ground LHI bypass capacitor 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VBIAS_LHI, pin 10 (locate near pin 10) Ground VBIAS filter capacitor 1 to 10 µF, 35 VDC, 1Ω max ESR; (3.3 µF nominal value) Tantalum or ceramic Pos: VBIAS, pin 9 (locate near pin 9) Neg: Ground VBIAS bypass capacitor 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VBIAS, pin 9 (locate near pin 9) Ground VBIAS_RAIL bypass capacitors (2 required) 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VBIAS_RAIL, pins 30 and 71 (locate near pins 30 and 71) Ground Resistor jumper (optional) 0-Ω normally (1Ω for testing (1)) VBIAS, pin 9 VBIAS_RAIL, pins 21 or 80 Inductor 22 µH, 0.5 amp, 160 mΩ ESR Coil Craft DT1608C-223 (or equivalent) VBIAS_LHI, pin 10 VBIAS_SWL, pin 8 0.5A, 40V (minimum) Motorola MBR0540T1 or STMicroelectronics STPS0540Z, STPS0560Z (or equivalent) Anode: VBIAS_SWL, pin 8 Cathode: VBIAS, pin 9 Schottky diode (1) Allows for VBIAS current measurement. 18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 Table 5. Reset Voltage Boost Converter COMPONENT VALUE TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 VRESET filter capacitor 1 to 10 µF, 35 VDC, 1Ω max ESR; (3.3 µF nominal value) Tantalum or ceramic Neg: VRESET, pin 13 (locate near pin 13) Pos: Ground VRESET bypass capacitor 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VRESET, pin 13 (locate near pin 13) Ground VRESET_RAIL bypass capacitors (2 required) 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VRESET_RAIL, pins 35 and 66 (locate near pins 35 and 66) Ground Resistor jumper (optional) 0-Ω normally (1Ω for testing (1)) VRESET, pin 13 VRESET_RAIL, pins 25 or 76 Inductor 22 µH, 0.5A, 160 mΩ Coil Craft DT1608C-223 (or equivalent) VRESET_SWL, pin 12 Ground Schottky diode 0.5 A (minimum), 60 V STMicroelectronics STPS0560Z or International Rectifier 10MQ060N (or equivalent) Cathode: VRESET_SWL, pin 12 Anode: VRESET, pin 13 (1) Allows for VRESET current measurement. Table 6. Offset Voltage Regulator (1) (2) (3) (4) COMPONENT VALUE TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 VOFFSET/VCC2 filter capacitors (2 required) 1 (1) to 4.7 (2) µF, 35 VDC, 1Ω max ESR Tantalum or ceramic Pos: VOFFSET, pin 49 (1st near pin 49) Pos: DMDVCC2 pins (locate 2nd at DMD) Neg: Ground at DLPA200 Neg: Ground at DMD VOFFSET/VCC2 bypass capacitors (5 required) 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VOFFSET, pin 49 (locate 1 near pin 49) DMD DMDVCC2 pins (locate 4 near DMD pins) Ground at DLPA200 Ground at DMD VOFFSET_RAIL bypass capacitor (2 required) 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VOFFSET_RAIL, pins 28 and 73 (locate near pins 28 and 73) Ground Resistor jumper (optional) 0-Ω normal (1Ω for testing (3)) VOFFSET, pin 49 VOFFSET_RAIL, pins 38 or 63 Resistor jumper (optional) 0-ohm normal (1Ω for testing (4)) VOFFSET, pin 49 DMDVCC2 pins To ensure stability of the linear regulator, the absolute minimum output capacitance should not be less than 1.0 µF. Recommended value is 3.3 µF each. Different values are acceptable, provided that the sum of the two is 6.8 µF maximum. Allows for VOFFSET current measurement Allows for DMDVCC2 current measurement Table 7. Pullup Resistors COMPONENT VALUE TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 Resistor 1 kΩ SCPDO, pin 42 Chipset controller 3.3-V VDD Resistor 1 kΩ IRQ, pin 43 Chipset Controller 3.3-V VDD Resistor (optional) 1 kΩ OE, pin 6 Chipset Controller 3.3-V VDD Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 19 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com 10 Power Supply Recommendations 10.1 Power Supply Rail Guidelines Table 3 through Table 7 provides discrete component selection guidelines. The P12V filter and bypass capacitors should be distributed and connected to pin 11 and pins 48 & 50. These capacitors should be placed as near to their respective pins as possible and if necessary, should be placed on the bottom layer. The V5REG filter and bypass capacitors must be placed near and connected to pin 47. The VBIAS_RAIL etch runs should be routed in the following order: pin 40, pin 31, pin 30, pin 21, pin 80, pin 71, pin 70, and pin 61. The etch runs should be short and direct as they must carry 35 ns current spikes of up to 0.64 amps peak. Bypass capacitors should be located near and connected to pins 30 and 71 to provide bypassing on both sides. The VBIAS_LHI filter and bypass capacitors must be placed near and connected to pin 10. The VBIAS filter and bypass capacitors must be placed near and connected to pin 9. VBIAS pin 9 must also be connected (optionally with a 0-ohm resistor) to VBIAS_RAIL at or between pins 21 and 80. The VRESET_RAIL etch runs should be routed in the following order: pin 36, pin 35, pin 26, pin 25, pin 76, pin 75, pin 66, and pin 65. The etch runs should be short and direct as they must carry 35 ns current spikes of up to 0.64 amps peak. Bypass capacitors should be placed near and connected to pins 35 and 66 to provide bypassing on both sides. The VRESET filter and bypass capacitors must be located near and connected to pin 13. VRESET pin 13 must also be connected (optionally with a 0-ohm resistor) to VRESET_RAIL at or between pins 25 and 76. The VOFFSET_RAIL etch runs should be routed in the following order: pin 23, pin 28, pin 33, pin 38, pin 63, pin 68, pin 73, and pin 78. The etch runs should be short and direct as they must carry 35 ns current spikes of up to 0.64 amps peak. Bypass capacitors should be placed near and connected to pins 28 and 73 to provide bypassing on both sides. The VOFFSET filter and bypass capacitors must be placed near and connected to pin 49. VOFFSET pin 49 must also be connected (optionally with a 0-ohm resistor) to VOFFSET_RAIL at or between pins 38 and 63. NOTE Aluminum electrolytic capacitors may not be suitable for the DLPA200 application. At the switching frequencies used in the DLPA200 (up to 1.5MHz), aluminum electrolytic capacitors drop significantly in capacitance and increase in ESR resulting in voltage spikes on the power supply rails, which could cause the device to shut down or perform in an unreliable manner. 20 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 11 Layout 11.1 Layout Guidelines CAUTION Board layout and routing guidelines must be followed explicitly and all external components used must be in the range of values and of the quality recommended for proper operation of the DLPA200. Important: Thermal pad(s) must be tied to VRESET_RAIL, do not connect to ground. CAUTION Thermal pads must be tied to VRESET_RAIL. Do not connect to ground. Suitable Kelvin connections should be provided for the switching regulator feedback pins: VBIAS (pin 9) and VRESET (pin 13). The etch traces that connect the switching devices: VBIAS_SWL (pin 8) and VRESET_SWL (pin 12) should be as short and wide as possible to minimize leakage inductances. The etch traces that connect the switching converter components (inductors, flywheel diodes and filtering capacitors) should also be as short and wide as possible. The electrical loops that these components form should be as small and compact as possible, with the ground referenced components forming a star connection. Due to the fast switching transitions appearing on the sixteen reset OUTx pins, it is recommended to keep these traces as short as possible. Also, to minimize potential cross-talk between outputs, it is advisable to maintain as much clearance between each of the output traces. 11.1.1 Grounding Guidelines The PWB should have an internal ground plane that extends under the DLPA200. All 9 ground pins (1, 7, 14, 20, 41, 46, 53, 55, and 60) must be connected to the ground plane using the shortest possible runs and vias. All filter and bypass capacitors must be placed near the pin being filtered or bypassed for the shortest possible runs to the part and to the ground plane. 11.2 Thermal Considerations The DLPA200 package should be thermally bonded or soldered to an external thermal pad on the PWB surface. The recommended dimensions of the thermal pad are 10 × 10 mm centered under the part. The metal bottom of the package is tied internally to the substrate at the VRESET_RAIL voltage level. Therefore, the thermal pad on the board must be isolated from any other extraneous circuit or ground and no circuit vias are allowed inside the pad area. Thermal pads are required on both sides of the PWB and should be connected together through an array of 5 × 5 thermal vias, 0.5 mm in diameter. Thermal pads and the thermal vias are connected to VRESET_RAIL and isolated from ground, or any other circuit. An internal P12V or VBB plane should be located directly underneath the top layer and have an isolated area under the DLPA200. This isolated area must be a minimum of 20 cm2 and connect to the thermal pad of the DLPA200 through the thermal vias. The potential of the isolated area will also be at VRESET_RAIL. The internal ground plane should extend under the DLPA200 to help carry the heat away. Please refer to the PowerPAD Thermally Enhanced Package application report (SLMA002) for details on thermally efficient package design considerations. Careful consideration should be taken with respect to DLPA200 placement in the vicinity of local PWB hotspots. Heat generated from adjacent components may impact the DLPA200 thermal characteristics. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 21 DLPA200 DLPS015D – APRIL 2010 – REVISED MAY 2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Device Nomenclature The device marking consists of the fields shown in Figure 6. Figure 6. Device Marking (Device Top View) DLPA200PFP is functionally equivalent to 2506593-0005N. 12.2 Documentation Support 12.2.1 Related Documentation Table 8. Related Links Document TI Literature Number DLP 0.55 XGA Chip-Set data sheet DLPZ004 DLP5500 0.55 XGA DMD data sheet DLPS013 DLPC200 Digital Controller data sheet DLPS014 DLP® Discovery™ 4100 Chipset Datasheet DLPU008 DLP7000 0.7 XGA Type-A DMD data sheet DLPS026 DLP9500 0.95 1080p Type-A DMD data sheet DLPS025 DLPC410 Digital Controller data sheet DLPS024 DLPA200 DMD Micromirror Driver data sheet DLPS015 DLPR410 EEPROM data sheet DLPS027 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 22 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 DLPA200 www.ti.com DLPS015D – APRIL 2010 – REVISED MAY 2015 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLPA200 23 PACKAGE OPTION ADDENDUM www.ti.com 15-Dec-2014 PACKAGING INFORMATION Orderable Device Status (1) DLPA200PFP ACTIVE Package Type Package Pins Package Drawing Qty HTQFP PFP 80 5 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR Op Temp (°C) Device Marking (4/5) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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