ON MC100E016FN 5.0 v ecl 8−bit synchronous binary up counter Datasheet

MC10E016, MC100E016
5.0 VECL 8−Bit
Synchronous Binary
Up Counter
Description
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The MC10E/100E016 is a high−speed synchronous, presettable,
cascadable 8−bit binary counter. Architecture and operation are the
same as the MC10H016 in the MECL 10H™ family, extended to
8−bits, as shown in the logic symbol.
The counter features internal feedback of TC, gated by the TCLD
(terminal count load) pin. When TCLD is LOW (or left open, in which
case it is pulled LOW by the internal pull−downs), the TC feedback is
disabled, and counting proceeds continuously, with TC going LOW to
indicate an all−one state. When TCLD is HIGH, the TC feedback
causes the counter to automatically reload upon TC = LOW, thus
functioning as a programmable counter. The Qn outputs do not need to
be terminated for the count function to operate properly. To minimize
noise and power, unused Q outputs should be left unterminated.
The 100 series contains temperature compensation.
MARKING DIAGRAM*
Features
•
•
•
•
•
•
•
•
•
PLCC−28
FN SUFFIX
CASE 776
1
700 MHz Min. Count Frequency
1000 ps CLK to Q, TC
Internal TC Feedback (Gated)
8−Bit
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Pb−Free Packages are Available*
MCxxxE016G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 7
1
Publication Order Number:
MC10E016/D
MC10E016, MC100E016
PE CE
P7
P6
P5 VCCO TC
25
23
22
21
24
20
Table 1. PIN DESCRIPTION
PIN
MR
26
1
9 18
Q7
CLK
27
17
Q6
TCLD
28
16
VCC
15
Q5
VEE
1
NC
2
14
VCCO
P0
3
13
Q4
P1
4
12
Q3
5
6
P2
P3
7
8
9
P4 VCCO Q0
10
11
Q1
Q2
FUNCTION
P0 − P7
Q0 − Q7
CE
PE
MR
CLK
TC
TCLD
NC
VCC, VCCO
VEE
ECL Parallel Data (Preset) Inputs
ECL Data Outputs
ECL Count Enable Control Input
ECL Parallel Load Enable Control Input
ECL Master Reset
ECL Clock
ECL Terminal Count Output
ECL TC−Load Control Input
No Connect
Positive Supply
Negative Supply
All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 28−Lead Pinout Assignment (Top View)
Q1
Q0
Q7
PE
TCLD
Q0M
MASTER
CE
Q0M
SLAVE
Q0
CE
CE
Q
Q1 0
Q2
Q3
Q4
Q5
Q6
BIT 1
BIT 0
PO
P1
BIT 7
P7
MR
CLK
BITS 2−6
Note that this diagram is provided for understanding of
logic operation only. It should not be used for propagation
delays as many gate functions are achieved internally
without incurring a full gate delay.
TC
5
Figure 2. 8−Bit Binary Counter Logic Counter
Table 2. FUNCTION TABLE
FUNCTION
CE
PE
TCLD
MR
CLK
Load Parallel (Pn to Qn)
X
L
X
L
Z
Continuous Count
L
H
L
L
Z
Count; Load Parallel on TC = LOW
L
H
H
L
Z
Hold
H
H
X
L
Z
Masters Respond, Slaves Hold
X
X
X
L
ZZ
Reset (Qn : = LOW, TC : = HIGH)
X
X
X
H
X
Z = clock pulse (low to high);
ZZ = clock pulse (high to low)
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MC10E016, MC100E016
Table 3. EXPANDED FUNCTION TABLE
PE
CE
MR
TCLD
CLK
P7−P4
P3
P2
P1
P0
Q7−Q4
Q3
Q2
Q1
Q0
TC
Load
Function
L
X
L
X
Z
H
H
H
L
L
H
H
H
L
L
H
Count
H
L
L
L
Z
X
X
X
X
X
H
H
H
L
H
H
H
L
L
L
Z
X
X
X
X
X
H
H
H
H
L
H
H
L
L
L
Z
X
X
X
X
X
H
H
H
H
H
L
H
L
L
L
Z
X
X
X
X
X
L
L
L
L
L
H
Load
L
X
L
X
Z
H
H
H
L
L
H
H
H
L
L
H
Hold
H
H
L
X
Z
X
X
X
X
X
H
H
H
L
L
H
H
H
L
X
Z
X
X
X
X
X
H
H
H
L
L
H
Load On
H
L
L
H
Z
H
L
H
H
L
H
H
H
L
H
H
Terminal
H
L
L
H
Z
H
L
H
H
L
H
H
H
H
L
H
Count
H
L
L
H
Z
H
L
H
H
L
H
H
H
H
H
L
H
L
L
H
Z
H
L
H
H
L
H
L
H
H
L
H
H
L
L
H
Z
H
L
H
H
L
H
L
H
H
H
H
H
L
L
H
Z
H
L
H
H
L
H
H
L
L
L
H
X
X
H
X
X
X
X
X
X
X
L
L
L
L
L
H
Reset
Table 4. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
50 kW
Internal Input Pullup Resistor
50 kW
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
PLCC−28
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 200 V
Pb Pkg
Pb−Free Pkg
Level 1
Level 3
UL 94 V−0 @ 0.125 in
592 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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MC10E016, MC100E016
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
PECL Mode Power Supply
VEE = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
Tsol
Wave Solder
Condition 2
VI VCC
VI VEE
Rating
Unit
8
V
6
−6
V
50
100
mA
mA
0 to +85
°C
−65 to +150
°C
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
PLCC−28
22 to 26
°C/W
265
265
°C
Pb
Pb−Free
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 6. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
151
181
Min
85°C
Typ
Max
151
181
Min
Typ
Max
Unit
151
181
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E016, MC100E016
Table 7. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 3)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
151
181
Min
85°C
Typ
Max
151
181
Min
Typ
Max
Unit
151
181
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 4)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 8. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 5)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
151
181
151
181
174
208
mA
VOH
Output HIGH Voltage (Note 6)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 6)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E016, MC100E016
Table 9. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 7)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
151
181
Min
85°C
Typ
Max
151
181
Min
Typ
Max
Unit
174
208
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 8)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 10. AC CHARACTERISTICS VCCx= 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 9)
0°C
Symbol
Characteristic
fMAX
Maximum Toggle Frequency
fCOUNT
Maximum Count Frequency
tPLH, tPHL
Propagation Delay to Output
ts
th
Min
Typ
25°C
Max
Min
700
700
Typ
85°C
Max
Min
700
900
700
900
700
Typ
Max
Unit
700
MHz
900
MHz
ps
CLK to Q
500
725
900
500
725
900
500
725
900
MR to Q
500
775
900
500
775
900
500
775
900
CLK to TC
500
775
900
500
775
900
500
775
900
MR to TC
500
775
900
500
775
900
500
775
900
Setup Time (to CLK +)
ps
Pn
150
−30
150
−30
150
−30
CE
600
400
600
400
600
400
PE
600
400
600
400
600
400
TCLD
500
300
500
300
500
300
Hold Time (to CLK +)
Pn
350
100
350
100
350
100
CE
400
200
400
200
400
200
PE
0
200
0
200
0
200
100
−300
100
−300
100
−300
900
700
900
700
900
700
TCLD
tRR
Reset Recovery Time
tPW
Minimum Pulse Width
tJITTER
Random Clock Jitter (RMS)
tr, tf
Rise/Fall Times (20 − 80%)
ps
ps
CLK, MR
400
400
<1
200
510
400
<1
700
200
510
<1
700
200
510
ps
700
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
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MC10E016, MC100E016
APPLICATIONS INFORMATION
Cascading Multiple E016 Devices
Therefore, for an E016 in the chain to count, all of the lower
order terminal count outputs must be in the low state. The bit
width of the counter can be increased or decreased by simply
adding or subtracting E016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC
output and the necessary setup time of the CE input and the
propagation delay through the OR gate controlling it (for
16−bit counters the limitation is only the TC propagation
delay and the CE setup time). Figure 3 shows EL01 gates
used to control the count enable inputs, however, if the
frequency of operation is lower a slower, ECL OR gate can
be used. Using the worst case guarantees for these
parameters from the ECLinPS data book, the maximum
count frequency for a greater than 16−bit counter is
500 MHz and that for a 16−bit counter is 625 MHz.
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
For applications which call for larger than 8−bit counters
multiple E016s can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output
and count enable input (CE) greatly facilitate the cascading
of E016 devices. Two E016s can be cascaded without the
need for external gating, however for counters wider than 16
bits external OR gates are necessary for cascade
implementations.
Figure 3 below pictorially illustrates the cascading of 4
E016s to build a 32−bit high frequency counter. Note the
E101 gates used to OR the terminal count outputs of the
lower order E016s to control the counting operation of the
higher order bits. When the terminal count of the preceding
device (or devices) goes low (the counter reaches an all 1s
state) the more significant E016 is set in its count mode and
will count one binary digit upon the next positive clock
transition. In addition, the preceding devices will also count
one bit thus sending their terminal count outputs back to a
high state disabling the count operation of the more
significant counters and placing them back into hold modes.
LOAD
Q0 −> Q7
LO
CE
Q0 −> Q7
PE
TC
CLK
CE
E016
CLK
TC
P0 −> P7
TC
CLOCK
Figure 3. 32−Bit Cascaded E016 Counter
7
CLK
TC
EL01
P0 −> P7
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PE
E016
MSB
EL01
P0 −> P7
Q0 −> Q7
PE
CE
PE
E016
E016
LSB
CLK
CE
Q0 −> Q7
P0 −> P7
MC10E016, MC100E016
APPLICATIONS INFORMATION (continued)
Programmable Divider
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the E016 and the TC
output can feed the clock input of a toggle flip flop to create
a signal divided as desired with a 50% duty cycle.
The E016 has been designed with a control pin which
makes it ideal for use as an 8−bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads
the data present at the parallel input pin (Pn’s) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 4
below illustrates the input conditions necessary for utilizing
the E016 as a programmable divider set up to divide by 113.
H
PE
L
CE
H
TCLD
H
L
L
L
H
H
H
H
P7
P6
P5
P4
P3
P2
P1
P0
Table 11. Preset Values for Various Divide Ratios
TC
CLK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn’s = 256 − 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 4
will result in the waveforms of Figure 5. Note that the TC
output is used as the divide output and the pulse duration is
Load
1001 0000
1001 0001
Preset Data Inputs
Divide
Ratio
P7
P6
P5
P4
P3
P2
P1
P0
2
H
H
H
H
H
H
H
L
3
H
H
H
H
H
H
L
H
4
H
H
H
H
H
H
L
L
5
H
H
H
H
H
L
H
H
w
w
•
•
•
•
•
•
•
w
•
•
•
•
•
•
•
•
112
H
L
L
H
L
L
L
L
113
H
L
L
L
H
H
H
H
114
H
L
L
L
H
H
H
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
254
L
L
L
L
L
L
H
L
255
L
L
L
L
L
L
L
H
256
L
L
L
L
L
L
L
L
A single E016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256 are
needed multiple E016s can be cascaded in a manner similar
to that already discussed. When E016s are cascaded to build
larger dividers the TCLD pin will no longer provide a means
for loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must
be used for multiple E016 divider chains.
1111 1100
1111 1101
1111 1110
1111 1111
•••
Clock
•••
PE
•••
TC
DIVIDE BY 113
Figure 5. Divide by 113 E016 Programmable Divider Waveforms
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Load
MC10E016, MC100E016
APPLICATIONS INFORMATION (continued)
OUT
EL01
Q0 −> Q7
LO
CE
PE
E016
LSB
CLK
Q0 −> Q7
CE
Q0 −> Q7
PE
CE
E016
TC
PO −> P7
CLK
Q0 −> Q7
PE
CE
E016
TC
PO −> P7
CLK
EL01
PE
E016
MSB
TC
PO −> P7
CLK
EL01
TC
PO −> P7
CLOCK
Figure 6. 32−Bit Cascaded E016 Programmable Divider
Maximizing E016 Count Frequency
Figure 6 shows a typical block diagram of a 32−bit divider
chain. Once again to maximize the frequency of operation
EL01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EL01. Note that for a
16−bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant E016 must also feed the CE
input of the most significant E016. If the two TC outputs
were OR tied the cascaded count operation would not
operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
The E016 device produces 9 fast transitioning
single−ended outputs, thus VCC noise can become
significant in situations where all of the outputs switch
simultaneously in the same direction. This VCC noise can
negatively impact the maximum frequency of operation of
the device. Since the device does not need to have the Q
outputs terminated to count properly, it is recommended that
if the outputs are not going to be used in the rest of the system
they should be left unterminated. In addition, if only a subset
of the Q outputs are used in the system only those outputs
should be terminated. Not terminating the unused outputs
will not only cut down the VCC noise generated but will also
save in total system power dissipation. Following these
guidelines will allow designers to either be more aggressive
in their designs or provide them with an extra margin to the
published data book specifications.
http://onsemi.com
9
MC10E016, MC100E016
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package Type
Shipping †
MC10E016FN
PLCC−28
37 Units/Rail
MC10E016FNG
PLCC−28
(Pb−Free)
37 Units/Rail
MC10E016FNR2
PLCC−28
500 Units/Reel
MC10E016FNR2G
PLCC−28
(Pb−Free)
500 Units/Reel
MC100E016FN
PLCC−28
37 Units/Rail
MC100E016FNG
PLCC−28
(Pb−Free)
37 Units/Rail
MC100E016FNR2
PLCC−28
500 Units/Reel
MC100E016FNR2G
PLCC−28
(Pb−Free)
500 Units/Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
MC10E016, MC100E016
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N
−
0.007 (0.180)
B
Y BRK
U
T L −M
M
0.007 (0.180)
M
S
N
T L −M
S
S
N
S
D
−L
−
Z
−M
−
D
W
X
V
28
1
G1
0.010 (0.250)
S
T L −M
S
N
S
VIEW D−D
Z
C
A
0.007 (0.180)
R
0.007 (0.180)
M
M
T L −M
S
T L −M
S
N
S
N
S
H
0.007 (0.180)
M
T L −M
N
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
−T
−
T L −M
S
N
0.007 (0.180)
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM −T−, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
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11
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
0.025
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
0.020
2°
10°
0.410 0.430
0.040
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.79
2.29
0.33
0.48
1.27 BSC
0.81
0.66
0.51
0.64
11.58
11.43
11.58
11.43
1.07
1.21
1.07
1.21
1.42
1.07
0.50
2°
10°
10.42 10.92
1.02
M
T L −M
S
N
S
S
MC10E016, MC100E016
MECL is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
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12
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC10E106/D
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