Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 LM5106 100-V Half-Bridge Gate Driver With Programmable Dead-Time 1 Features 3 Description • The LM5106 is a high-voltage gate driver designed to drive both the high-side and low-side N-channel MOSFETs in a synchronous buck or half-bridge configuration. The floating high-side driver can work with rail voltages up to 100 V. The single control input is compatible with TTL signal levels and a single external resistor programs the switching transition dead-time through tightly matched turnon delay circuits. The robust level shift technology operates at high speed while consuming low power and provides clean output transitions. Undervoltage lockout (UVLO) disables the gate driver when either the low side or the bootstrapped high-side supply voltage is below the operating threshold. The LM5106 is offered in the 10-pin VSSOP or the thermally enhanced 10pin WSON plastic package. 1 • • • • • • • • • • • Drives Both a High-Side and Low-Side N-Channel MOSFET 1.8-A Peak Output Sink Current 1.2-A Peak Output Source Current Bootstrap Supply Voltage Range up to 118-V DC Single TTL Compatible Input Programmable Turnon Delays (Dead-Time) Enable Input Pin Fast Turnoff Propagation Delays (32 ns Typical) Drives 1000 pF With 15-ns Rise and 10-ns Fall Time Supply Rail Undervoltage Lockout Low Power Consumption 10-Pin WSON Package (4 mm × 4 mm) and 10Pin VSSOP Package Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) VSSOP (10) 3.00 mm × 3.00 mm WSON (10) 4.00 mm × 4.00 mm 2 Applications LM5106 • • • (1) For all available packages, see the orderable addendum at the end of the datasheet. Solid-State Motor Drives Half-Bridge and Full-Bridge Power Converters Two Switch Forward Power Converters Simplified Block Diagram VDD HB VDD HB UVLO LEVEL SHIFT DRIVER HO HS VDD UVLO IN VSS LEADING EDGE DELAY RDT LEADING EDGE DELAY EN VDD DRIVER LO 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application ................................................. 12 9 Power Supply Recommendations...................... 14 9.1 Power Dissipation Considerations .......................... 14 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Example .................................................... 16 11 Device and Documentation Support ................. 17 Detailed Description ............................................ 11 11.1 Trademarks ........................................................... 17 11.2 Electrostatic Discharge Caution ............................ 17 11.3 Glossary ................................................................ 17 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision B (March 2013) to Revision C • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 12 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 LM5106 www.ti.com SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 5 Pin Configuration and Functions 10-Pin VSSOP (DGS), WSON (DPR) Top View VDD 1 10 HB 2 9 VSS HO 3 8 IN HS 4 7 EN NC 5 6 RDT LO Pin Functions PIN NO. NAME 1 VDD 2 DESCRIPTION APPLICATION INFORMATION Positive gate drive supply Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to the IC as possible. HB High-side gate driver bootstrap rail Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC as possible. 3 HO High-side gate driver output Connect to the gate of high-side N-MOS device through a short, low inductance path. 4 HS High-side MOSFET source connection Connect to the negative terminal of the bootststrap capacitor and to the source of the high-side N-MOS device. 5 NC Not connected 6 RDT 7 Dead-time programming pin A resistor from RDT to VSS programs the turnon delay of both the high- and low-side MOSFETs. The resistor should be placed close to the IC to minimize noise coupling from adjacent PC board traces. EN Logic input for driver Disable/Enable TTL compatible threshold with hysteresis. LO and HO are held in the low state when EN is low. 8 IN Logic input for gate driver TTL compatible threshold with hysteresis. The high-side MOSFET is turned on and the low-side MOSFET turned off when IN is high. 9 VSS Ground return All signals are referenced to this ground. 10 LO Low-side gate driver output Connect to the gate of the low-side N-MOS device with a short, low inductance path. — EP Exposed Pad The exposed pad has no electrical contact. Connect to system ground plane for reduced thermal resistance. Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 3 LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT VDD to VSS –0.3 18 V HB to HS –0.3 18 V IN and EN to VSS –0.3 VDD + 0.3 V LO to VSS –0.3 VDD + 0.3 V HO to VSS HS – 0.3 HB + 0.3 V 100 V 118 V HS to VSS (3) HB to VSS RDT to VSS –0.3 Junction Temperature Storage temperature range, Tstg (1) –55 5 V 150 °C 150 °C Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Recommended Operating Conditions are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed –5 V. (2) (3) 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions VDD HS (1) HB MIN MAX 8 14 V –1 100 V HS + 8 HS + 14 HS Slew Rate Junction Temperature (1) 4 –40 UNIT V < 50 V/ns 125 °C In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed –5 V. Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 LM5106 www.ti.com SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 6.4 Thermal Information LM5102 THERMAL METRIC (1) DGS DPR (2) 10 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 165.3 37.9 RθJC(top) Junction-to-case (top) thermal resistance 58.9 38.1 RθJB Junction-to-board thermal resistance 54.4 14.9 ψJT Junction-to-top characterization parameter 6.2 0.4 ψJB Junction-to-board characterization parameter 83.6 15.2 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 4.4 (1) (2) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). Four-layer board with Cu finished thickness 1.5 oz, 1 oz, 1 oz, 1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50-mm × 50-mm ground and power planes embedded in PCB. See Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401). 6.5 Electrical Characteristics MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ = +25°C, VDD = HB = 12 V, VSS = HS = 0 V, EN = 5 V. No load on LO or HO. RDT= 100kΩ (1). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.34 0.6 mA 2.1 3.5 mA 0.06 0.2 mA mA SUPPLY CURRENTS IDD VDD Quiescent Current IN = EN = 0 V IDDO VDD Operating Current f = 500 kHz IHB Total HB Quiescent Current IN = EN = 0 V IHBO Total HB Operating Current f = 500 kHz 1.5 3 IHBS HB to VSS Current, Quiescent HS = HB = 100 V 0.1 10 IHBSO HB to VSS Current, Operating f = 500 kHz 0.5 µA mA INPUT IN and EN VIL Low Level Input Voltage Threshold VIH High Level Input Voltage Threshold 0.8 Rpd Input Pulldown Resistance Pin IN and EN 100 1.8 V 1.8 2.2 V 200 500 kΩ DEAD-TIME CONTROLS VRDT Nominal Voltage at RDT IRDT RDT Pin Current Limit RDT = 0 V 2.7 3 3.3 V 0.75 1.5 2.25 mA 6.2 6.9 7.6 V UNDERVOLTAGE PROTECTION VDDR VDD Rising Threshold VDDH VDD Threshold Hysteresis VHBR HB Rising Threshold VHBH HB Threshold Hysteresis 0.5 5.9 6.6 V 7.3 0.4 V V LO GATE DRIVER VOLL Low-Level Output Voltage ILO = 100 mA 0.21 0.4 V VOHL High-Level Output Voltage ILO = –100 mA, VOHL = VDD – VLO 0.5 0.85 V IOHL Peak Pullup Current LO = 0 V 1.2 A IOLL Peak Pulldown Current LO = 12 V 1.8 A HO GATE DRIVER VOLH Low-Level Output Voltage IHO = 100 mA VOHH High-Level Output Voltage IHO = –100 mA, VOHH = HB – HO (1) 0.21 0.4 V 0.5 0.85 V Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 5 LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ = +25°C, VDD = HB = 12 V, VSS = HS = 0 V, EN = 5 V. No load on LO or HO. RDT= 100kΩ(1). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOHH Peak Pullup Current HO = 0 V 1.2 A IOLH Peak Pulldown Current HO = 12 V 1.8 A See (2) (3) 40 °C/W THERMAL RESISTANCE θJA (2) (3) Junction to Ambient Four-layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50-mm × 50-mm ground and power planes embedded in PCB. See AN-1187 Leadless Leadframe Package (LLP), SNOA401. The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions. 6.6 Switching Characteristics MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ = +25°C, VDD = HB = 12 V, VSS = HS = 0 V, No Load on LO or HO (1). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX tLPHL Lower Turn-Off Propagation Delay 32 56 tHPHL Upper Turn-Off Propagation Delay 32 56 tLPLH Lower Turn-On Propagation Delay RDT = 100k 400 520 640 tHPLH Upper Turn-On Propagation Delay RDT = 100k 450 570 690 tLPLH Lower Turn-On Propagation Delay RDT = 10k 85 115 160 tHPLH Upper Turn-On Propagation Delay RDT = 10k 85 115 160 ten, tsd Enable and Shutdown propagation delay DT1, DT2 Dead-time LO OFF to HO ON & HO OFF to LO ON RDT = 100k 510 RDT = 10k 86 MDT Dead-time matching RDT = 100k 50 tR Either Output Rise Time CL = 1000pF 15 tF Either Output Fall Time CL = 1000pF 10 (1) UNIT ns 36 Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). IN EN LO ten tLPHL tHPHL tHPLH tLPLH DT1 DT2 DT1 DT2 tsd ten HO tsd Figure 1. LM5106 Input - Output Waveforms 6 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 LM5106 www.ti.com SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 IN VIH VIL tLPHL tLPLH 90% LO 10% 90% tHPLH tHPHL HO 10% Figure 2. LM5106 Switching Time Definitions: tLPLH, tLPHL, tHPLH, tHPHL 90% HO 10% DT1 DT2 90% MDT = |DT1-DT2| LO 10% Figure 3. LM5106 Dead-time: DT Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 7 LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 www.ti.com 6.7 Typical Characteristics 100 2.2 VDD = HB = 12V CL = 2200 pF VSS = HS = 0V RDT = 10K f = 500 kHz 2.0 VSS = HS = 0 CURRENT (mA) CL = 1000 pF CURRENT (mA) VDD = HB = 12V CL = 470 pF 10 1.8 CL = 0 pF IDDO 1.6 1.4 IHBO 1.2 CL = 0 pF 1 10 1 100 1.0 -50 -30 -10 10 30 50 70 90 110 130 150 1000 TEMPERATURE (oC) FREQUENCY (kHz) Figure 5. Operating Current vs Temperature Figure 4. VDD Operating Current vs Frequency 1.20 1.20 1.00 1.00 IDD @ RDT = 10k CURRENT (mA) VDD = HB VSS = HS = 0V 0.60 IDD @ RDT = 100k 0.40 0.20 0.00 9 VDD = HB = 12V VSS = HS = 0V 0.60 IDD @ RDT = 100k 0.40 0.20 IHB @ RDT = 10k, 100k 8 0.80 0.00 -50 10 11 12 13 14 15 16 17 18 IHB @ RDT = 10k, 100k -25 VDD, VHB (V) 75 100 125 150 2.00 1.40 HB = 12V, HS = 0V VDD = HB = 12V, HS = 0V 1.26 CL = 4400 pF SOURCE CURRENT (A) CL = 2200 pF 10000 CURRENT (PA) 50 Figure 7. Quiescent Current vs Temperature 100000 CL = 1000 pF 1000 100 CL = 0 pF 1.80 1.12 1.60 0.98 1.40 1.20 0.84 SOURCING 0.70 0.42 0.60 SINKING 0.28 0.40 0.14 0.20 CL = 470 pF 0.00 1 10 100 1.00 0.80 0.56 0 1000 2 4 6 8 10 0.00 12 HO, LO (V) FREQUENCY (kHz) Figure 8. HB Operating Current vs Frequency 8 25 TEMPERATURE (°C) Figure 6. Quiescent Current vs Supply Voltage 10 0.1 0 SINK CURRENT (A) CURRENT (mA) IDD @ RDT = 10k 0.80 Figure 9. HO and LO Peak Output Current vs Output Voltage Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 LM5106 www.ti.com SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 Typical Characteristics (continued) 0.60 7.30 THRESHOLD (V) 7.10 0.55 VHBR = HB - HS VDDH 7.00 VDDR 6.90 6.80 6.70 VHBR 6.60 0.50 HYSTERESIS (V) 7.20 VDDR = VDD - VSS 0.45 VHBH 0.40 6.50 0.35 6.40 6.30 -50 -25 0 25 50 0.30 -50 75 100 125 150 -25 0 25 Figure 10. Undervoltage Rising Threshold vs Temperature 100 125 150 Figure 11. Undervoltage Hysteresis vs Temperature 0.400 1.300 Output Current = 100 mA Output Current - 100 mA 0.350 1.100 VDD = HB = 8V VDD = HB = 8V 0.300 0.900 VOH (V) VDD = HB = 12V 0.250 0.200 VDD = HB = 12V 0.700 0.500 VDD = HB = 16V VDD = HB = 16V 0.150 0.100 -50 75 TEMPERATURE (oC) TEMPERATURE (°C) VOL (V) 50 0.300 -25 0 25 50 75 100 125 150 0.100 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. LO and HO - Low-Level Output Voltage vs Temperature Figure 13. LO and HO - High-Level Output Voltage vs Temperature 1.96 88 1.94 86 1.92 DEAD-TIME (ns) VIL, VIH (V) 1.90 1.88 1.86 1.84 1.82 1.80 84 VDD = HB = 12V VSS = HS = 0 82 80 78 1.78 76 -50 -30 -10 10 30 50 70 90 110 130 150 1.76 -50 -30 -10 10 30 50 70 90 110 130 150 TEMPERATURE (oC) TEMPERATURE (oC) Figure 14. Input Threshold vs Temperature Figure 15. Dead-Time vs Temperature (RT = 10k) Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 9 LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 600 590 VDD = HB = 12V DEAD-TIME (ns) VSS = HS = 0V 580 570 560 550 540 -50 -30 -10 10 30 50 70 90 110 130 150 TEMPERATURE (oC) Figure 16. Dead-Time vs Temperature (RT = 100k) 10 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 LM5106 www.ti.com SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 7 Detailed Description 7.1 Overview The LM5106 is a single PWM input gate driver with Enable that offers a programmable dead-time. The dead-time is set with a resistor at the RDT pin and can be adjusted from 100 ns to 600 ns. The wide dead-time programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETs and applications. The RDT pin is biased at 3 V and current limited to 1 mA maximum programming current. The time delay generator will accommodate resistor values from 5k to 100k with a dead-time time that is proportional to the RDT resistance. Grounding the RDT pin programs the LM5106 to drive both outputs with minimum dead-time. 7.2 Functional Block Diagram VDD HB VDD HB UVLO LEVEL SHIFT DRIVER HO HS VDD UVLO IN VSS LEADING EDGE DELAY RDT LEADING EDGE DELAY VDD DRIVER EN LO 7.3 Feature Description 7.3.1 Start-up and UVLO Both top and bottom drivers include undervoltage lockout (UVLO) protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (HB – HS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn on the external MOSFETs, and the UVLO hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of the LM5106, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9 V. Any UVLO condition on the bootstrap capacitor will disable only the high-side output (HO). 7.4 Device Functional Modes EN IN Pin LO Pin HO Pin L Any L L H H L H H L H L Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 11 LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM5106 is one of the latest generation of high-voltage gate drivers which are designed to drive both the high-side and low-side N-channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit. The floating high-side driver can operate with supply voltages up to 110 V. This allows for N-channel MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies. The outputs of the LM5106 are controlled from a single input. The rising edge of each output can be delayed with a programming resistor. Table 1. Highlights FEATURE BENEFIT Programmable Turnon Delay Allows optimization of gate drive timings in bridge topologies Enable Pin Reduces operating current when disabled to improved power system standby power Low Power Consumption Improves light load efficiency figures of the power stage. 8.2 Typical Application VIN VCC RGATE HB VDD VDD HO CBOOT OUT1 IN ENABLE EN CONTROLLER 0.1 PF HS LO 0.47 PF GND T1 LM5106 RDT RGATE VSS Figure 17. LM5106 Driving MOSFETs Connected in Half-Bridge Configuration 12 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 LM5106 www.ti.com SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 Typical Application (continued) 8.2.1 Design Requirements PARAMETERS VALUES Gate Drive IC LM5102 Mosfet CSD18531Q5A VDD 10 V Qgmax 43 nC Fsw 100 kHz DMax 95% IHBO 10 µA VDH 1.1 V VHBR 7.3 V VHBH 0.4 V 8.2.2 Detailed Design Procedure 8.2.2.1 Detailed Design Procedure ΔVHB = VDD – VDH – VHBL where • • • VDD = Supply voltage of the gate drive IC VDH = Bootstrap diode forward voltage drop Vgsmin = Minimum gate source threshold voltage CBOOT QTOTAL = DVHB QTOTAL DMax = Qgmax + IHBO ´ FSW (1) (2) (3) The quiescent current of the bootstrap circuit is 10 µA which is negligible compared to the Qgs of the MOSFET. 0.95 QTOTAL = 43nC + 10mA ´ 100kHz (4) QTOTAL = 43.01 nC (5) In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit. As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT. VHBL = VHBR – VHBH VHBL = 6.9 V ΔVHB = 10 V – 1.1 V – 6.9 V ΔVHB = 2.0 V CBOOT = 43.01nc / 2 V CBOOT = 21.5 nF (6) (7) (8) (9) (10) (11) The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across them and to ensure long-term reliability of the devices. The resistor values, RT, for setting turnon delay can be found in Figure 19. Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 13 LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 www.ti.com 8.2.3 Application Curves VIH EN LO or HO 90% tsd Figure 18. LM5106 Enable: tsd 900 800 DEAD-TIME (ns) 700 600 500 400 300 200 100 0 10 30 50 70 90 110 130 150 RDT (k:) Figure 19. Dead-Time vs RT Resistor Value 9 Power Supply Recommendations 9.1 Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 (12) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. Figure 20 shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the Equation 12. This plot can be used to approximate the power losses due to the gate drivers. 14 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 LM5106 www.ti.com SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 Power Dissipation Considerations (continued) 1.000 CL = 4400 pF CL = 2200 pF POWER (W) 0.100 CL = 1000 pF 0.010 CL = 470 pF CL = 0 pF 0.001 0.1 1.0 10.0 100.0 1000.0 SWITCHING FREQUENCY (kHz) Figure 20. Gate Driver Power Dissipation (LO + HO) VCC = 12 V 10 Layout 10.1 Layout Guidelines The optimum performance of high- and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. The following points are emphasized: 1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD and HB during the turnon of the external MOSFETs. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS). 3. To avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the source of the top MOSFET and the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding considerations: – The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close as possible to the MOSFETs. – The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 5. The resistor on the RDT pin must be placed very close to the IC and separated from the high current paths to avoid noise coupling to the time delay generator which could disrupt timer operation. 10.1.1 HS Transient Voltages Below Ground The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided: 1. HS must always be at a lower potential than HO. Pulling HO more than –0.3 V below HS can activate parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 15 LM5106 SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 www.ti.com Layout Guidelines (continued) externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must be placed as close to the IC pins as possible in order to be effective. 2. HB to HS operating voltage should be 15 V or less. Hence, if the HS pin transient voltage is –5 V, VDD should be ideally limited to 10V to keep HB to HS below 15 V. 3. Low ESR bypass capacitors from HB to HS and from VCC to VSS are essential for proper operation. The capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO and HO can be quite large. Any inductances in series with the bypass capacitor will cause voltage ringing at the leads of the IC which must be avoided for reliable operation. 10.2 Layout Example CBOOT Q HS C VDD LM5106 Q LS Figure 21. LM5106 Component Placement 16 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 LM5106 www.ti.com SNVS424D – JANUARY 2006 – REVISED DECEMBER 2014 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM5106 17 PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM5106MM NRND VSSOP DGS 10 1000 TBD Call TI Call TI -40 to 125 5106 LM5106MM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5106 LM5106MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5106 LM5106SD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5106SD LM5106SDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5106SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Oct-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5106MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5106MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5106SD/NOPB WSON DPR 10 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 LM5106SDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Oct-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5106MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5106MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LM5106SD/NOPB WSON DPR 10 1000 203.0 203.0 35.0 LM5106SDX/NOPB WSON DPR 10 4500 346.0 346.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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