AD AD7904BRUZ-REEL 4-channel, 1 msps, 8-/10-/12-bit adcs with sequencer in 16-lead tssop Datasheet

4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs
with Sequencer in 16-Lead TSSOP
AD7904/AD7914/AD7924
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
REFIN
VIN0
T/H
8-/10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
VIN1
I/P
MUX
VIN2
VIN3
SCLK
DOUT
SEQUENCER
CONTROL LOGIC
DIN
CS
AD7904/AD7914/AD7924
VDRIVE
AGND
03087-001
Fast throughput rate: 1 MSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power:
6 mW maximum at 1 MSPS with 3 V supplies
13.5 mW maximum at 1 MSPS with 5 V supplies
4 single-ended inputs with sequencer
Wide input bandwidth
AD7924, 70 dB SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface: SPI/QSPI™/
MICROWIRE™/DSP compatible
Shutdown mode: 0.5 µA maximum
16-lead TSSOP package
Qualified for automotive applications
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7904/AD7914/AD7924 are, respectively, 8-bit, 10-bit, and
12-bit, high speed, low power, 4-channel successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V
power supply and feature throughput rates up to 1 MSPS. The
parts contain a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
1.
The conversion process and data acquisition are controlled using
CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled
on the falling edge of CS and conversion is initiated at this
point. There are no pipeline delays associated with the part.
The AD7904/AD7914/AD7924 use advanced design techniques
to achieve very low power dissipation at maximum throughput
rates. At maximum throughput rates, the AD7904/AD7914/
AD7924 consume 2 mA maximum with 3 V supplies; with 5 V
supplies, the current consumption is 2.7 mA maximum.
Through the configuration of the control register, the analog
input range for the part can be selected as 0 V to REFIN or 0 V to
2 × REFIN, with either straight binary or twos complement output
coding. The AD7904/AD7914/AD7924 each feature four singleended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially.
The conversion time for the AD7904/AD7914/AD7924 is
determined by the SCLK frequency, which is also used as the
master clock to control the conversion.
Rev. C
2.
3.
4.
5.
High Throughput with Low Power Consumption.
The AD7904/AD7914/AD7924 offer throughput rates
up to 1 MSPS. At the maximum throughput rate with 3 V
supplies, the AD7904/AD7914/AD7924 dissipate only
6 mW of power maximum.
Four Single-Ended Inputs with Channel Sequencer.
A consecutive sequence of channels can be selected,
through which the ADC will cycle and convert on.
Single-Supply Operation with VDRIVE Function.
The AD7904/AD7914/AD7924 operate from a single 2.7 V
to 5.25 V supply. The VDRIVE function allows the serial interface to connect directly to 3 V or 5 V processor systems,
independent of VDD.
Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced by increasing
the serial clock speed. The parts also feature two shutdown
modes to maximize power efficiency at lower throughput
rates. Current consumption is 0.5 µA maximum when in
full shutdown.
No Pipeline Delay.
The parts feature a standard successive approximation
ADC with accurate control of the sampling instant via
the CS input and once-off conversion control.
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AD7904/AD7914/AD7924
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Information ........................................................................ 18
Functional Block Diagram .............................................................. 1
Converter Operation.................................................................. 18
General Description ......................................................................... 1
ADC Transfer Function ............................................................. 19
Product Highlights ........................................................................... 1
Typical Connection Diagram ................................................... 20
Revision History ............................................................................... 2
Modes of Operation ....................................................................... 22
Specifications..................................................................................... 3
Normal Mode (PM1 = PM0 = 1) ............................................. 22
AD7904 Specifications ................................................................. 3
Full Shutdown Mode (PM1 = 1, PM0 = 0) ............................. 22
AD7914 Specifications ................................................................. 5
Auto Shutdown Mode (PM1 = 0, PM0 = 1) ........................... 22
AD7924 Specifications ................................................................. 7
Powering Up the AD7904/AD7914/AD7924 ......................... 23
Timing Specifications .................................................................. 9
Power vs. Throughput Rate ........................................................... 25
Absolute Maximum Ratings .......................................................... 10
Serial Interface ............................................................................ 25
ESD Caution ................................................................................ 10
Applications Information .............................................................. 27
Pin Configuration and Function Descriptions ........................... 11
Microprocessor Interfacing ....................................................... 27
Typical Performance Characteristics ........................................... 12
Grounding and Layout .............................................................. 28
Terminology .................................................................................... 14
Outline Dimensions ....................................................................... 29
Control Register .............................................................................. 15
Ordering Guide .......................................................................... 29
Sequencer Operation ................................................................. 16
Automotive Products ................................................................. 29
REVISION HISTORY
6/13—Rev. B to Rev. C
2/09—Rev. 0 to Rev. A
Deleted Evaluating AD7904/AD7914/AD7924 Performance
Section .............................................................................................. 29
Changes to Ordering Guide .......................................................... 29
Updated Format .................................................................. Universal
Moved Figure 2 ..................................................................................9
Change to Table 5 ........................................................................... 10
Changes to Typical Performance Characteristics Section ........ 12
Moved Terminology Section ......................................................... 14
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
7/11—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Signal to (Noise + Distortion) (SINAD) Parameter
and Signal-to-Noise Ratio (SNR) Parameter in Table 1 .............. 3
Changes to Signal to (Noise + Distortion) (SINAD) Parameter
and Signal-to-Noise Ratio (SNR) Parameter in Table 2 .............. 5
Changes to Signal to (Noise + Distortion) (SINAD) Parameter
and Signal-to-Noise Ratio (SNR) Parameter in Table 3 .............. 7
Changes to Table 5 .......................................................................... 10
Changes to Ordering Guide .......................................................... 30
Added Automotive Products Section........................................... 30
11/02—Revision 0: Initial Version
Rev. C | Page 2 of 32
Data Sheet
AD7904/AD7914/AD7924
SPECIFICATIONS
AD7904 SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) (SINAD) 2
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation2
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
0 V to REFIN Input Range
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
0 V to 2 × REFIN Input Range
Positive Gain Error2
Positive Gain Error Match2
Zero Code Error2
Zero Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN 3
B Version 1
Unit
49
48.5
49
48.5
−66
−64
dB min
dB min
dB min
dB min
dB max
dB max
−90
−90
10
50
−85
8.2
1.6
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
8
±0.2
±0.2
Bits
LSB max
LSB max
±0.5
±0.05
±0.2
±0.05
LSB max
LSB max
LSB max
LSB max
Test Conditions/Comments
fIN = 50 kHz sine wave, fSCLK = 20 MHz
B models
W models
B models
W models
fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 8 bits
Straight binary output coding
−REFIN to +REFIN biased about REFIN with twos
complement output coding
±0.2
±0.05
±0.5
±0.1
±0.2
±0.05
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
0 to REFIN
0 to 2 × REFIN
±1
20
V
V
μA max
pF typ
RANGE bit set to 1
RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
2.5
±1
36
V
μA max
kΩ typ
±1% specified performance
0.7 × VDRIVE
0.3 × VDRIVE
±1
10
V min
V max
μA max
pF max
Rev. C | Page 3 of 32
fSAMPLE = 1 MSPS
Typically 10 nA, VIN = 0 V or VDRIVE
AD7904/AD7914/AD7924
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD 4
Normal Mode (Static)
Normal Mode (Operational)
Auto Shutdown Mode
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
Auto Shutdown Mode (Static)
Full Shutdown Mode
Data Sheet
B Version 1
Unit
Test Conditions/Comments
VDRIVE − 0.2
V min
0.4
V max
±1
μA max
10
pF max
Straight (natural) binary
Twos complement
CODING bit set to 1
CODING bit set to 0
800
300
300
1
ns max
ns max
ns max
MSPS max
16 SCLK cycles with SCLK at 20 MHz
Sine wave input
Full-scale step input
See the Serial Interface section
2.7/5.25
2.7/5.25
V min/V max
V min/V max
600
2.7
2
960
0.5
0.5
μA typ
mA max
mA max
μA typ
μA max
μA max
Digital inputs = 0 V or VDRIVE
AVDD = 2.7 V to 5.25 V, SCLK on or off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 250 kSPS
Static
SCLK on or off (20 nA typ)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
μW max
μW max
μW max
μW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
Temperature range for B versions: −40°C to +85°C.
See the Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
See the Power vs. Throughput Rate section.
1
2
Rev. C | Page 4 of 32
ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V
ISINK = 200 μA
Data Sheet
AD7904/AD7914/AD7924
AD7914 SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) (SINAD) 2
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation2
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
0 V to REFIN Input Range
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
0 V to 2 × REFIN Input Range
Positive Gain Error2
Positive Gain Error Match2
Zero Code Error2
Zero Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN 3
B Version 1
Unit
61
60.5
61
60.5
−72
−74
dB min
dB min
dB min
dB min
dB max
dB max
−90
−90
10
50
−85
8.2
1.6
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
10
±0.5
±0.5
Bits
LSB max
LSB max
±2
±0.2
±0.5
±0.2
LSB max
LSB max
LSB max
LSB max
Test Conditions/Comments
fIN = 50 kHz sine wave, fSCLK = 20 MHz
B models
W models
B models
W models
fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 10 bits
Straight binary output coding
−REFIN to +REFIN biased about REFIN with twos
complement output coding
±0.5
±0.2
±2
±0.2
±0.5
±0.2
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
0 to REFIN
0 to 2 × REFIN
±1
20
V
V
μA max
pF typ
RANGE bit set to 1
RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
2.5
±1
36
V
μA max
kΩ typ
±1% specified performance
0.7 × VDRIVE
0.3 × VDRIVE
±1
10
V min
V max
μA max
pF max
Rev. C | Page 5 of 32
fSAMPLE = 1 MSPS
Typically 10 nA, VIN = 0 V or VDRIVE
AD7904/AD7914/AD7924
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD 4
Normal Mode (Static)
Normal Mode (Operational)
Auto Shutdown Mode
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
Auto Shutdown Mode (Static)
Full Shutdown Mode
Data Sheet
B Version 1
Unit
Test Conditions/Comments
VDRIVE − 0.2
V min
0.4
V max
±1
μA max
10
pF max
Straight (natural) binary
Twos complement
CODING bit set to 1
CODING bit set to 0
800
300
300
1
ns max
ns max
ns max
MSPS max
16 SCLK cycles with SCLK at 20 MHz
Sine wave input
Full-scale step input
See the Serial Interface section
2.7/5.25
2.7/5.25
V min/V max
V min/V max
600
2.7
2
960
0.5
0.5
μA typ
mA max
mA max
μA typ
μA max
μA max
Digital inputs = 0 V or VDRIVE
AVDD = 2.7 V to 5.25 V, SCLK on or off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 250 kSPS
Static
SCLK on or off (20 nA typ)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
μW max
μW max
μW max
μW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
Temperature range for B versions: −40°C to +85°C.
See the Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
See the Power vs. Throughput Rate section.
1
2
Rev. C | Page 6 of 32
ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V
ISINK = 200 μA
Data Sheet
AD7904/AD7914/AD7924
AD7924 SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) (SINAD) 2
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation2
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
0 V to REFIN Input Range
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
0 V to 2 × REFIN Input Range
Positive Gain Error2
Positive Gain Error Match2
Zero Code Error2
Zero Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN 3
B Version 1
Unit
70
69.5
69
70
69.5
−77
−73
−78
dB min
dB min
dB min
dB min
dB min
dB max
dB max
dB max
−90
−90
10
50
−85
8.2
1.6
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
12
±1
−0.9/+1.5
Bits
LSB max
LSB max
±8
±0.5
±1.5
±0.5
LSB max
LSB max
LSB max
LSB max
Test Conditions/Comments
fIN = 50 kHz sine wave, fSCLK = 20 MHz
@ 5 V, B models
@ 5 V, W models
@ 3 V, typically 69.5 dB
B models
W models
@ 5 V, typically −84 dB
@ 3 V, typically −77 dB
@ 5 V, typically −86 dB
fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 12 bits
Straight binary output coding
Typically ±0.5 LSB
−REFIN to +REFIN biased about REFIN with twos
complement output coding
±1.5
±0.5
±8
±0.5
±1
±0.5
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
0 to REFIN
0 to 2 × REFIN
±1
20
V
V
μA max
pF typ
RANGE bit set to 1
RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
2.5
±1
36
V
μA max
kΩ typ
±1% specified performance
0.7 × VDRIVE
0.3 × VDRIVE
±1
10
V min
V max
μA max
pF max
Rev. C | Page 7 of 32
Typically ±0.8 LSB
fSAMPLE = 1 MSPS
Typically 10 nA, VIN = 0 V or VDRIVE
AD7904/AD7914/AD7924
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD 4
Normal Mode (Static)
Normal Mode (Operational)
Auto Shutdown Mode
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
Auto Shutdown Mode (Static)
Full Shutdown Mode
Data Sheet
B Version 1
Unit
Test Conditions/Comments
VDRIVE − 0.2
V min
0.4
V max
±1
μA max
10
pF max
Straight (natural) binary
Twos complement
CODING bit set to 1
CODING bit set to 0
800
300
300
1
ns max
ns max
ns max
MSPS max
16 SCLK cycles with SCLK at 20 MHz
Sine wave input
Full-scale step input
See the Serial Interface section
2.7/5.25
2.7/5.25
V min/V max
V min/V max
600
2.7
2
960
0.5
0.5
μA typ
mA max
mA max
μA typ
μA max
μA max
Digital inputs = 0 V or VDRIVE
AVDD = 2.7 V to 5.25 V, SCLK on or off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 250 kSPS
Static
SCLK on or off (20 nA typ)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
μW max
μW max
μW max
μW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
Temperature range for B versions: −40°C to +85°C.
See the Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
See the Power vs. Throughput Rate section.
1
2
Rev. C | Page 8 of 32
ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V
ISINK = 200 μA
Data Sheet
AD7904/AD7914/AD7924
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter 1
fSCLK 2
tCONVERT
tQUIET
AVDD = 3 V
10
20
16 × tSCLK
50
t2
t3 3
t4 3
t5
t6
t7
t8 4
t9
t10
t11
t12
10
35
40
0.4 × tSCLK
0.4 × tSCLK
10
15/45
10
5
20
1
Limit at TMIN, TMAX
AVDD = 5 V
10
20
16 × tSCLK
50
10
30
40
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
20
1
Unit
kHz min
MHz max
Description
ns min
Minimum quiet time required between the CS rising edge and the start
of the next conversion
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
Power-up time from full shutdown/auto shutdown modes
ns min
ns max
ns max
ns min
ns min
ns min
ns min/ns max
ns min
ns min
ns min
μs max
Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V (see Figure 2).
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
1
200µA
1.6V
CL
50pF
200µA
IOH
03087-002
TO
OUTPUT
PIN
IOL
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. C | Page 9 of 32
AD7904/AD7914/AD7924
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
AVDD to AGND
VDRIVE to AGND
Analog Input Voltage to AGND
Digital Input Voltage to AGND
Digital Output Voltage to AGND
REFIN to AGND
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Commercial (B Version)
Automotive (W Version)
Storage Temperature Range
Junction Temperature
TSSOP Package, Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 secs)
Infrared (15 secs)
ESD
1
Rating
−0.3 V to +7 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to +7 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
450 mW
150.4°C/W (TSSOP)
27.6°C/W (TSSOP)
215°C
220°C
1.5 kV
Transient currents of up to 100 mA will not cause SCR latch-up.
Rev. C | Page 10 of 32
Data Sheet
AD7904/AD7914/AD7924
SCLK 1
16
AGND
DIN 2
15
VDRIVE
14
DOUT
13
AGND
12
VIN0
CS 3
AGND 4
AVDD 5
AD7904/
AD7914/
AD7924
TOP VIEW
(Not to Scale)
AVDD 6
11
VIN1
REFIN 7
10
VIN2
AGND 8
9
VIN3
03087-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
SCLK
2
DIN
3
CS
4, 8, 13, 16
AGND
5, 6
AVDD
7
REFIN
9, 10, 11,
12
VIN3, VIN2,
VIN1, VIN0
14
DOUT
15
VDRIVE
Function
Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the AD7904/AD7914/AD7924 conversion process.
Data In, Logic Input. Data to be written to the control register of the AD7904/AD7914/AD7924 is provided on
this input and is clocked into the register on the falling edge of SCLK (see the Control Register section).
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7904/AD7914/AD7924 and frames the serial data transfer.
Analog Ground. Ground reference point for all analog circuitry on the AD7904/AD7914/AD7924. All analog
input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should
be connected together.
Analog Power Supply Input. The AVDD range for the AD7904/AD7914/AD7924 is from 2.7 V to 5.25 V. For the 0 V
to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V.
Reference Input for the AD7904/AD7914/AD7924. An external reference must be applied to this input. The
voltage range for the external reference is 2.5 V ± 1% for specified performance.
Analog Input 0 through Analog Input 3. The four single-ended analog input channels are multiplexed into the
on-chip track-and-hold. The analog input channel to be converted is selected using the address bits ADD1 and
ADD0 of the control register. The address bits, in conjunction with the SEQ1 and SEQ0 bits, allow the sequencer
to be programmed. The input range for all input channels can extend from 0 V to REFIN or from 0 V to 2 × REFIN
as selected via the RANGE bit in the control register. Any unused input channels should be connected to AGND
to avoid noise pickup.
Data Out, Logic Output. The conversion result from the AD7904/AD7914/AD7924 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7904 consists of two leading zeros, two address bits indicating which channel the conversion result
corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first.
The data stream from the AD7914 consists of two leading zeros, two address bits indicating which channel the
conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros,
provided MSB first. The data stream from the AD7924 consists of two leading zeros, two address bits indicating
which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided MSB
first. The output coding can be selected as straight binary or twos complement via the CODING bit in the
control register.
Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the serial interface
of the AD7904/AD7914/AD7924 operates.
Rev. C | Page 11 of 32
AD7904/AD7914/AD7924
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–50
4096 POINT FFT
AVDD = 5V
fSAMPLE = 1MSPS
fIN = 50kHz
SINAD = 71.147dB
THD = –87.229dB
SFDR = –90.744dB
–10
TA = 25°C
RANGE = 0V TO REFIN
AVDD = VDRIVE = 2.7V
–60
–65
–50
THD (dB)
SNR (dB)
–30
fSAMPLE = 1MSPS
–55
–70
AVDD = VDRIVE = 3.6V
–70
–75
–80
–90
AVDD = VDRIVE = 4.75V
–85
50
100
150
200
250
300
350
400
450
500
FREQUENCY (kHz)
–90
10
03087-004
0
Figure 4. AD7924 Dynamic Performance at 1 MSPS
100
1000
INPUT FREQUENCY (kHz)
03087-007
AVDD = VDRIVE = 5.25V
–110
Figure 7. AD7924 THD vs. Analog Input Frequency for Various Supply
Voltages at 1 MSPS
75
–50
AVDD = VDRIVE = 5.25V
fSAMPLE = 1MSPS
TA = 25°C
RANGE = 0V TO REFIN
AVDD = 5.25V
–55
AVDD = VDRIVE = 4.75V
70
–60
AVDD = VDRIVE = 3.6V
THD (dB)
65
RIN = 50Ω
–75
60
–80
AVDD = VDRIVE = 2.7V
55
10
100
1000
INPUT FREQUENCY (kHz)
–90
10
03087-005
TA = 25°C
RANGE = 0V TO REFIN
RIN = 10Ω
–85
Figure 5. AD7924 SINAD vs. Analog Input Frequency for Various Supply
Voltages at 1 MSPS, SCLK = 20 MHz
100
1000
INPUT FREQUENCY (kHz)
03087-008
fSAMPLE = 1MSPS
Figure 8. AD7924 THD vs. Analog Input Frequency for Various Source
Impedances
0
1.0
AVDD = 5V
200mV p-p SINE WAVE ON AVDD
REFIN = 2.5V, 1µF CAPACITOR
TA = 25°C
–10
–20
TA = 25°C
AVDD = VDRIVE = 5V
0.8
0.6
0.4
INL ERROR (LSB)
–30
PSRR (dB)
RIN = 100Ω
–70
–40
–50
–60
0.2
0
–0.2
–0.4
–70
–0.6
–80
0
100
200
300
400
500
600
700
800
SUPPLY RIPPLE FREQUENCY (kHz)
900
1000
03087-006
–0.8
–90
Figure 6. AD7924 PSRR vs. Supply Ripple Frequency (No Decoupling)
Rev. C | Page 12 of 32
–1.0
0
512
1024
1536
2048
2560
3072
CODE
Figure 9. AD7924 Typical INL
3584
4096
03087-009
SINAD (dB)
RIN = 1000Ω
–65
Data Sheet
AD7904/AD7914/AD7924
1.0
TA = 25°C
AVDD = VDRIVE = 5V
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
CODE
3584
4096
03087-010
DNL ERROR (LSB)
0.6
Figure 10. AD7924 Typical DNL
Rev. C | Page 13 of 32
AD7904/AD7914/AD7924
Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of the
transfer function are zero scale, a point 1 LSB below the first code
transition, and full scale, a point 1 LSB above the last code transition.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset Error
Offset error is the deviation of the first code transition (00 … 000
to 00 … 001) from the ideal, that is, AGND + 1 LSB.
Offset Error Match
Offset error match is the difference in offset error between any
two channels.
Gain Error
Gain error is the deviation of the last code transition (111 … 110
to 111 … 111) from the ideal, that is, REFIN − 1 LSB, after the
offset error has been adjusted out.
Gain Error Match
Gain error match is the difference in gain error between any
two channels.
Zero Code Error
Zero code error is the deviation of the midscale transition (all
0s to all 1s) from the ideal VIN voltage, that is, REFIN − 1 LSB. It
applies when using the twos complement output coding option
with the 2 × REFIN input range (−REFIN to +REFIN biased about
the REFIN point).
Zero Code Error Match
Zero code error match is the difference in zero code error
between any two channels.
Positive Gain Error
Positive gain error is the deviation of the last code transition
(011 … 110 to 011 … 111) from the ideal, that is, +REFIN − 1 LSB,
after the zero code error is adjusted out. It applies when using
the twos complement output coding option with the 2 × REFIN
input range (−REFIN to +REFIN biased about the REFIN point).
Positive Gain Error Match
Positive gain error match is the difference in positive gain error
between any two channels.
Negative Gain Error
Negative gain error is the deviation of the first code transition
(100 … 000 to 100 … 001) from the ideal, that is, −REFIN + 1 LSB,
after the zero code error is adjusted out. It applies when using
the twos complement output coding option with the 2 × REFIN
input range (−REFIN to +REFIN biased about the REFIN point).
Negative Gain Error Match
Negative gain error match is the difference in negative gain
error between any two channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale
400 kHz sine wave signal to all three nonselected input channels
and determining how much that signal is attenuated in the
selected channel with a 50 kHz signal. The figure is given worst
case across all four channels for the AD7904/AD7914/AD7924.
Power Supply Rejection (PSR)
Variations in power supply affect the full-scale transition but not
the linearity of the converter. PSR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 6).
Power Supply Rejection Ratio (PSRR)
PSRR is the ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 200 mV p-p sine wave applied to
the ADC AVDD supply of frequency fS.
PSRR(dB) = 10 log(Pf/Pfs)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS coupled onto the ADC AVDD supply.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of a conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of a conversion.
Signal to (Noise + Distortion) (SINAD) Ratio
SINAD is the measured ratio of signal to (noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise.
The theoretical SINAD ratio for an ideal N-bit converter with a
sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N +1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB, for a 10-bit
converter, it is 62 dB, and for an 8-bit converter, it is 50 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7904/AD7914/AD7924, it is defined as
THD(dB) = 20 log
V2 2 + V3 2 + V 4 2 + V5 2 + V6 2
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Rev. C | Page 14 of 32
Data Sheet
AD7904/AD7914/AD7924
CONTROL REGISTER
The control register of the AD7904/AD7914/AD7924 is a
12-bit, write-only register. Data is loaded from the DIN pin of
the AD7904/AD7914/AD7924 on the falling edge of SCLK. The
data is transferred on the DIN line at the same time that the
conversion result is read from the part. The data transferred on
the DIN line corresponds to the AD7904/AD7914/AD7924
configuration for the next conversion. This requires 16 serial
clocks for every data transfer. Only the information provided
on the first 12 falling clock edges (after the CS falling edge) is
loaded to the control register. MSB denotes the first bit in the
data stream. The bit functions are outlined in Table 8.
Table 7. Channel Selection
ADD1
0
0
1
1
ADD0
0
1
0
1
Analog Input Channel
VIN0
VIN1
VIN2
VIN3
Table 8. Control Register Bit Functions
MSB
11
WRITE
10
SEQ1
Bit
11
Mnemonic
WRITE
10
[9:8]
[7:6]
SEQ1
DONTC
ADD1,
ADD0
[5:4]
PM1, PM0
3
2
1
SEQ0
DONTC
RANGE
0
CODING
9
DONTC
8
DONTC
7
ADD1
6
ADD0
5
PM1
4
PM0
3
SEQ0
2
DONTC
1
RANGE
LSB
0
CODING
Description
The value written to this bit determines whether the following 11 bits will be loaded to the control register. If this bit
is set to 1, the following 11 bits will be written to the control register; if this bit is set to 0, the remaining 11 bits are not
loaded to the control register, which remains unchanged.
The SEQ1 bit is used in conjunction with the SEQ0 bit to control the use of the sequencer function (see Table 10).
Don’t care bits.
The two address bits are loaded at the end of the present conversion sequence and select which analog input
channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence
as described in Table 10. The selected input channel is decoded as shown in Table 7. The address bits corresponding
to the conversion result are also output on DOUT prior to the 12 bits of data (see the Serial Interface section). The next
channel to be converted on will be selected by the mux on the 14th SCLK falling edge.
The two power management bits decode the mode of operation of the AD7904/AD7914/AD7924 as described in
Table 9.
The SEQ0 bit is used in conjunction with the SEQ1 bit to control the use of the sequencer function (see Table 10).
Don’t care bit.
This bit selects the analog input range to be used on the AD7904/AD7914/AD7924. If it is set to 0, the analog input
range will extend from 0 V to 2 × REFIN. If it is set to 1, the analog input range will extend from 0 V to REFIN (for the next
conversion). For the 0 V to 2 × REFIN input range, VDD = 4.75 V to 5.25 V.
This bit selects the type of output coding that the AD7904/AD7914/AD7924 will use for the conversion result. If this
bit is set to 0, the output coding for the part will be twos complement. If this bit is set to 1, the output coding from
the part will be straight binary (for the next conversion).
Table 9. Power Mode Selection
PM1
1
PM0
1
Mode
Normal
operation
1
0
Full
shutdown
0
1
Auto
shutdown
0
0
Invalid
Description
In normal operation mode, the AD7904/AD7914/AD7924 remain in full power mode regardless of
the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the
AD7904/AD7914/AD7924.
In full shutdown mode, the AD7904/AD7914/AD7924 are in full shutdown with all circuitry on the
device powering down. The AD7904/AD7914/AD7924 retain the information in the control register
while in full shutdown. The part remains in full shutdown until these bits are changed.
In auto shutdown mode, the AD7904/AD7914/AD7924 automatically enter full shutdown mode at the
end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs;
the user should ensure that 1 μs has elapsed before attempting to perform a valid conversion on the
part in this mode.
Invalid selection. This configuration is not allowed.
Rev. C | Page 15 of 32
AD7904/AD7914/AD7924
Data Sheet
SEQUENCER OPERATION
The SEQ1 and SEQ0 bits in the control register allow the user to
select a mode of operation for the sequencer function. Table 10
outlines the three modes of operation of the sequencer.
Figure 11 shows the traditional operation of a multichannel
ADC, where each serial transfer selects the next channel for
conversion. In this mode of operation, the sequencer function
is not used.
Figure 12 shows how to program the AD7904/AD7914/AD7924
to continuously convert on a sequence of consecutive channels
from Channel 0 to a selected final channel. To exit this mode of
operation and revert to the traditional mode of operation of a
multichannel ADC (as shown in Figure 11), ensure that the
WRITE bit = 1 and SEQ1 = SEQ0 = 0 on the next serial transfer.
Table 10. Sequence Selection
SEQ1
0
SEQ0
X
Sequencer Function
Not used
1
0
Used (not interrupted
upon completion)
1
1
Continuous
conversions
Description
The sequencer function is not used. The analog input channel selected for each individual
conversion is determined by the contents of the channel address bits, ADD1 and ADD0, in each
previous write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without using the sequencer function, where each write to the AD7904/AD7914/
AD7924 selects the next channel for conversion (see Figure 11).
The sequencer function is not interrupted upon completion of the write operation. This configuration allows other bits in the control register to be altered between conversions while in a
sequence without terminating the cycle.
This configuration is used in conjunction with the channel address bits, ADD1 and ADD0, to
program continuous conversions on a consecutive sequence of channels from Channel 0 to a
selected final channel that is specified by the channel address bits in the control register (see
Figure 12).
POWER ON
DUMMY CONVERSION
CS
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL ADD1, ADD0 FOR CONVERSION.
SEQ1 = 0, SEQ0 = x
CS
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT ADD1, ADD0 FOR CONVERSION.
SEQ1 = 0, SEQ0 = x
WRITE BIT = 1,
SEQ1 = 0, SEQ0 = x
Figure 11. SEQ1 Bit = 0, SEQ0 Bit = x Flowchart
Rev. C | Page 16 of 32
03087-011
DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL ADD1, ADD0
Data Sheet
AD7904/AD7914/AD7924
POWER ON
DUMMY CONVERSION
CS
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL ADD1, ADD0 FOR CONVERSION.
SEQ1 = 1, SEQ0 = 1
DOUT: CONVERSION RESULT FROM CHANNEL 0
CS
CONTINUOUSLY CONVERTS ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
ADD1, ADD0 IN THE CONTROL REGISTER
WRITE BIT = 0
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT WILL ALLOW
RANGE, CODING, AND SO FORTH, TO CHANGE IN
THE CONTROL REGISTER WITHOUT INTERRUPTING WRITE BIT = 1,
THE SEQUENCE, PROVIDED SEQ1 = 1, SEQ0 = 0
SEQ1 = 1,
SEQ0 = 0
Figure 12. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart
Rev. C | Page 17 of 32
03087-012
CS
AD7904/AD7914/AD7924
Data Sheet
CIRCUIT INFORMATION
The AD7904/AD7914/AD7924 provide the user with an on-chip
track-and-hold ADC and serial interface housed in a 16-lead
TSSOP package. The AD7904/AD7914/AD7924 each have four
single-ended input channels with a channel sequencer, allowing
the user to select a channel sequence through which the ADC
can cycle with each consecutive CS falling edge. The serial clock
input accesses data from the part, controls the transfer of data
written to the ADC, and provides the clock source for the successive approximation ADC. The analog input range for the AD7904/
AD7914/AD7924 is 0 V to REFIN or 0 V to 2 × REFIN, depending on
the status of Bit 1 in the control register. For the 0 V to 2 × REFIN
range, the part must be operated from a 4.75 V to 5.25 V supply.
The AD7904/AD7914/AD7924 provide flexible power management
options to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by programming the power management bits, PM1 and PM0, in the
control register.
CONVERTER OPERATION
The AD7904/AD7914/AD7924 are 8-, 10-, and 12-bit SAR ADCs,
respectively, based around a capacitive DAC. The AD7904/
AD7914/AD7924 can convert analog input signals in the range
of 0 V to REFIN or 0 V to 2 × REFIN. Figure 13 and Figure 14
show simplified schematics of the ADC. The AD7904/AD7914/
AD7924 include control logic, the SAR ADC, and a capacitive
DAC, which are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. Figure 13 shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in Position A. The
comparator is held in a balanced condition and the sampling
capacitor acquires the signal on the selected VIN channel.
CAPACITIVE
DAC
B
CONTROL
LOGIC
SW2
4kΩ
A
VIN0
SW1
B
CONTROL
LOGIC
SW2
VIN3
COMPARATOR
AGND
Figure 14. ADC Conversion Phase
Analog Input
Figure 15 shows an equivalent circuit of the analog input structure
of the AD7904/AD7914/AD7924. The two diodes, D1 and D2,
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 200 mV. This will cause these diodes
to become forward-biased and start conducting current into the
substrate. The maximum current that these diodes can conduct
without causing irreversible damage to the part is 10 mA.
Capacitor C1 in Figure 15 is typically about 4 pF and can primarily
be attributed to pin capacitance. The resistor, R1, is a lumped
component made up of the on resistance of a track-and-hold
switch and the on resistance of the input multiplexer. The total
resistance is typically about 400 Ω. Capacitor C2 is the ADC
sampling capacitor and has a capacitance of 30 pF typically.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of a low-pass RC
filter on the relevant analog input pin. In applications where
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac performance
of the ADC. This may necessitate the use of an input buffer
amplifier. The choice of the op amp is a function of the
particular application.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of total harmonic distortion
(THD) that can be tolerated. The THD increases as the source
impedance increases, and performance will degrade (see Figure 8).
AVDD
COMPARATOR
AGND
D1
Figure 13. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 14), SW2 opens
and SW1 moves to position B, causing the comparator to
become unbalanced. The control logic and the capacitive DAC
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
Rev. C | Page 18 of 32
R1
VIN
C1
4pF
D2
C2
30pF
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
03087-015
VIN3
4kΩ
A
SW1
CAPACITIVE
DAC
03087-013
VIN0
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 16 and Figure 17 show the ADC transfer functions.
03087-014
The AD7904/AD7914/AD7924 are, respectively, 8-bit, 10-bit,
and 12-bit, high speed, 4-channel, single-supply ADCs. The parts
can be operated from a 2.7 V to 5.25 V supply. When operated
from either a 5 V or 3 V supply, the AD7904/AD7914/AD7924
are capable of throughput rates of 1 MSPS when provided with
a 20 MHz clock.
Figure 15. Equivalent Analog Input Circuit
Data Sheet
AD7904/AD7914/AD7924
ADC TRANSFER FUNCTION
111…111
111…110
•
•
111…000
•
011…111
•
•
000…010
000…001
000…000
1LSB
+VREF – 1LSB
ANALOG INPUT
NOTES
1. VREF IS EITHER REFIN OR 2 × REFIN.
Figure 17. Twos Complement Transfer Characteristic
with 0 V to 2 × REFIN Input Range
Handling Bipolar Input Signals
Figure 18 shows how the combination of the 0 V to 2 × REFIN
input range and the twos complement output coding scheme is
particularly useful for handling bipolar input signals. If the
bipolar input signal is biased about REFIN and twos complement
output coding is selected, REFIN becomes the zero code point,
−REFIN is negative full scale, and +REFIN becomes positive full
scale, with a dynamic range of 2 × REFIN.
Figure 16. Straight Binary Transfer Characteristic
VDD
VREF
0.1µF
AV
REFIN DD
VDD
VDRIVE
AD7904/
AD7914/
AD7924
R3
V
VIN0
R2
R1
R1 = R2 = R3 = R4
DOUT
VIN3
DSP/
MICROPROCESSOR
TWOS
COMPLEMENT
+REFIN
(= 2 × REFIN)
000…000
REFIN
–REFIN
Figure 18. Handling Bipolar Signals
Rev. C | Page 19 of 32
011…111
(= 0V)
100…000
03087-018
R4
V
0V
03087-017
ADC CODE
1LSB = 2 × VREF /256 AD7904
1LSB = 2 × VREF /1024 AD7914
1LSB = 2 × VREF /4096 AD7924
–VREF + 1LSB
+VREF – 1LSB
VREF – 1LSB
ANALOG INPUT
1LSB = VREF /256 AD7904
1LSB = VREF /1024 AD7914
1LSB = VREF /4096 AD7924
0V
011…111
011…110
•
•
000…001
000…000
111…111
•
•
100…010
100…001
100…000
03087-016
ADC CODE
The output coding of the AD7904/AD7914/AD7924 is either
straight binary or twos complement, depending on the status of
the LSB in the control register. The designed code transitions
occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so on).
For the 0 V to REFIN input range, the LSB size is REFIN/256 for
the AD7904, REFIN/1024 for the AD7914, and REFIN/4096 for
the AD7924. For the 0 V to 2 × REFIN input range, the LSB size
is 2 × REFIN/256 for the AD7904, 2 × REFIN/1024 for the AD7914,
and 2 × REFIN/4096 for the AD7924. The ideal transfer characteristic for the AD7904/AD7914/AD7924 when straight binary
coding is selected is shown in Figure 16; the ideal transfer
characteristic for the AD7904/AD7914/AD7924 when twos
complement coding is selected is shown in Figure 17.
AD7904/AD7914/AD7924
Data Sheet
TYPICAL CONNECTION DIAGRAM
Analog Input Selection
Figure 19 shows a typical connection diagram for the AD7904/
AD7914/AD7924. In this setup, the AGND pin is connected to
the analog ground plane of the system. In Figure 19, the REFIN
pin is connected to a decoupled 2.5 V supply from a reference
source, the AD780, to provide an analog input range of 0 V to
2.5 V (if the RANGE bit is set to 1) or 0 V to 5 V (if the RANGE
bit is set to 0).
Any one of four analog input channels can be selected for
conversion by programming the multiplexer with the address
bits ADD1 and ADD0 in the control register. The channel
configurations are shown in Table 7.
Although the AD7904/AD7914/AD7924 are connected to a VDD
of 5 V, the serial interface is connected to a 3 V microprocessor.
The VDRIVE pin of the AD7904/AD7914/AD7924 is connected to
the same 3 V supply as the microprocessor to allow a 3 V logic
interface (see the Digital Inputs section). The conversion result
is output in a 16-bit word. This 16-bit data stream consists of
two leading zeros, two address bits indicating which channel the
conversion result corresponds to, followed by the 12 bits of
conversion data for the AD7924 (10 bits of data for the AD7914
and 8 bits of data for the AD7904, each followed by two and
four trailing zeros, respectively). For applications where power
consumption is of concern, the power-down modes should be
used between conversions or bursts of several conversions to
improve power performance (see the Modes of Operation
section).
0.1µF
5V
SUPPLY
10µF
SERIAL
INTERFACE
VIN3
AVDD
SCLK
AD7904/
AD7914/
AD7924
AGND REF
IN
0.1µF
2.5V
AD780
MICROCONTROLLER/
MICROPROCESSOR
DOUT
CS
VDRIVE
DIN
0.1µF
10µF
3V SUPPLY
NOTES
1. ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND.
Figure 19. Typical Connection Diagram
03087-019
VIN0
0V TO REFIN
The AD7904/AD7914/AD7924 can also be configured to automatically cycle through a number of selected channels. The
sequencer feature is accessed via the SEQ1 and SEQ0 bits in the
control register (see Table 10). The AD7904/AD7914/AD7924
can be programmed to continuously convert on a number of
consecutive channels in ascending order from Channel 0 to a
selected final channel as determined by the channel address
bits, ADD1 and ADD0. This is possible if the SEQ1 and SEQ0
bits are set to 11. The next serial transfer will then act on the
sequence programmed by executing a conversion on Channel 0.
The next serial transfer will result in a conversion on Channel 1,
and so on, until the channel selected via the address bits, ADD1
and ADD0, is reached.
It is not necessary to write to the control register again after a
sequence operation has been initiated. To ensure that the control
register is not accidently overwritten or the sequence operation
interrupted, the WRITE bit must be set to 0 or the DIN line
must be tied low. If the control register is written to at any time
during the sequence, the SEQ1 and SEQ0 bits must be set to 10
to avoid interrupting the automatic conversion sequence. This
pattern continues until the AD7904/AD7914/AD7924 are
written to and the SEQ1 and SEQ0 bits are configured with a bit
combination other than 10, resulting in the termination of the
sequence. If the sequence is uninterrupted (WRITE bit = 0, or
WRITE bit = 1 and SEQ1 and SEQ0 bits are set to 10), then upon
completion of the sequence, the AD7904/AD7914/AD7924
sequencer returns to Channel 0 and restarts the sequence.
Regardless of the channel selection method used, the 16-bit
word output from the AD7924 during each conversion always
contains two leading zeros, two channel address bits that the
conversion result corresponds to, followed by the 12-bit conversion result; the AD7914 outputs two leading zeros, two
channel address bits that the conversion result corresponds to,
followed by the 10-bit conversion result and two trailing zeros;
the AD7904 outputs two leading zeros, two channel address bits
that the conversion result corresponds to, followed by the 8-bit
conversion result and four trailing zeros (see the Serial Interface
section).
Rev. C | Page 20 of 32
Data Sheet
AD7904/AD7914/AD7924
Digital Inputs
The digital inputs applied to the AD7904/AD7914/AD7924 can
go to 7 V and are not restricted by the AVDD + 0.3 V limit on the
analog inputs.
Because the SCLK, DIN, and CS inputs are not restricted by the
AVDD + 0.3 V limit, power supply sequencing issues are avoided.
If CS, DIN, or SCLK is applied before AVDD, there is no risk of
latch-up as there would be on the analog inputs if a signal
greater than 0.3 V is applied prior to AVDD.
VDRIVE
The AD7904/AD7914/AD7924 also include the VDRIVE feature.
VDRIVE controls the voltage at which the serial interface operates.
VDRIVE allows the ADC to easily interface to both 3 V and 5 V
processors. For example, if the AD7904/AD7914/AD7924 are
operated with a VDD of 5 V, the VDRIVE pin can be powered
from a 3 V supply. The AD7904/AD7914/AD7924 have better
dynamic performance with a VDD of 5 V while still being able to
interface to 3 V processors. Care should be taken to ensure that
VDRIVE does not exceed AVDD by more than 0.3 V (see the
Absolute Maximum Ratings section).
Reference
An external reference source should be used to supply the 2.5 V
reference to the AD7904/AD7914/AD7924. Errors in the reference source result in gain errors in the AD7904/AD7914/
AD7924 transfer function and add to the specified full-scale
errors of the part. A capacitor of at least 0.1 µF should be placed
on the REFIN pin. Suitable reference sources for the AD7904/
AD7914/AD7924 include the AD780, REF193, and AD1582.
If 2.5 V is applied to the REFIN pin, the analog input range can
be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the control register.
Rev. C | Page 21 of 32
AD7904/AD7914/AD7924
Data Sheet
MODES OF OPERATION
The AD7904/AD7914/AD7924 have three modes of operation.
These modes are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for differing application requirements. The mode of operation of the AD7904/AD7914/AD7924
is controlled by the power management bits, PM1 and PM0, in
the control register (see Table 9). When power supplies are first
applied to the AD7904/AD7914/AD7924, care should be taken to
ensure that the part is placed in the required mode of operation
(see the Powering Up the AD7904/AD7914/AD7924 section).
NORMAL MODE (PM1 = PM0 = 1)
Normal mode is intended for the fastest throughput rate performance. Because the AD7904/AD7914/AD7924 remain fully
powered up at all times, the user does not need to worry about
power-up times. Figure 20 shows the general diagram of the
operation of the AD7904/AD7914/AD7924 in this mode.
CS
1
12
16
SCLK
DIN
2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
DATA IN TO CONTROL REGISTER
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.
03087-020
DOUT
Figure 20. Normal Mode Operation
The conversion is initiated on the falling edge of CS; the trackand-hold enters hold mode as described in the Serial Interface
section. The data presented to the AD7904/AD7914/AD7924
on the DIN line during the first 12 clock cycles of the data
transfer is loaded into the control register (provided that the
WRITE bit is set to 1). In normal mode, the part remains fully
powered up at the end of the conversion as long as the PM1 and
PM0 bits are set to 1 in the write transfer during that same
conversion. To ensure continued operation in normal mode,
PM1 and PM0 must both be set to 1 on every data transfer,
assuming that a write operation is taking place. If the WRITE
bit is set to 0, the power management bits are left unchanged,
and the part remains in normal mode.
Sixteen serial clock cycles are required to complete the conversion
and to access the conversion result. The track-and-hold returns
to track mode on the 14th SCLK falling edge. CS may then idle
high until the next conversion or it may idle low until some
time prior to the next conversion (effectively idling CS low).
When a data transfer is complete (DOUT has returned to threestate), another conversion can be initiated after the quiet time,
tQUIET, has elapsed by bringing CS low again.
FULL SHUTDOWN MODE (PM1 = 1, PM0 = 0)
In full shutdown mode, all internal circuitry on the AD7904/
AD7914/AD7924 is powered down. The part retains information
in the control register during full shutdown. The AD7904/AD7914/
AD7924 remain in full shutdown until the power management
bits in the control register, PM1 and PM0, are changed.
If a write to the control register occurs while the part is in full
shutdown, and the power management bits are changed to
PM0 = PM1 = 1 (that is, normal mode), the part will begin to
power up on the CS rising edge. The track-and-hold, which was
in hold mode while the part was in full shutdown, returns to
track mode on the 14th SCLK falling edge.
To ensure that the part is fully powered up, tPOWER-UP (t12) should
have elapsed before the next CS falling edge. Figure 21 shows
the general diagram for this sequence.
AUTO SHUTDOWN MODE (PM1 = 0, PM0 = 1)
In auto shutdown mode, the AD7904/AD7914/AD7924 automatically enter shutdown at the end of each conversion when
the control register is updated. When the part is in auto shutdown,
the track-and-hold is in hold mode. Figure 22 shows the general
diagram of the operation of the AD7904/AD7914/AD7924 in
this mode.
In auto shutdown mode, all internal circuitry on the AD7904/
AD7914/AD7924 is powered down. The part retains information
in the control register during auto shutdown. The AD7904/
AD7914/AD7924 remain in shutdown until the next CS falling
edge that it receives. On this CS falling edge, the track-and-hold,
which was in hold mode while the part was in shutdown, returns
to track mode. Wake-up time from auto shutdown is 1 µs maximum, and the user should ensure that 1 µs has elapsed before
attempting a valid conversion.
When running the AD7904/AD7914/AD7924 with a 20 MHz
clock, one 16 SCLK dummy cycle should be sufficient to ensure
that the part is fully powered up. During this dummy cycle, the
contents of the control register should remain unchanged;
therefore, the WRITE bit should be set to 0 on the DIN line.
This dummy cycle effectively halves the throughput rate of the
part, with every other conversion result being valid. In auto
shutdown mode, the power consumption of the part is greatly
reduced because the part enters shutdown at the end of each
conversion. When the control register is programmed to move
into auto shutdown mode, it does so at the end of the conversion. The user can move the ADC in and out of the low
power state by controlling the CS signal.
Rev. C | Page 22 of 32
Data Sheet
AD7904/AD7914/AD7924
PART BEGINS TO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
PART IS IN FULL
SHUTDOWN
THE PART IS FULLY POWERED UP
ONCE tPOWER UP HAS ELAPSED
t12
CS
14
1
14
1
16
16
SCLK
DOUT
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL REGISTER
DATA IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
03087-021
DIN
TO KEEP THE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 21. Full Shutdown Mode Operation
PART ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 = 0, PM0 = 1
PART BEGINS
TO POWER
UP ON CS
FALLING EDGE
PART ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 = 0, PM0 = 1
PART IS FULLY
POWERED UP
DUMMY CONVERSION
CS
1
12
16
1
12
16
1
12
16
SCLK
DIN
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 = 0, PM0 = 1
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL REGISTER
CONTROL REGISTER CONTENTS SHOULD
NOT CHANGE, WRITE BIT = 0
TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1
IN CONTROL REGISTER OR SET WRITE BIT = 0
Figure 22. Auto Shutdown Mode Operation
POWERING UP THE AD7904/AD7914/AD7924
When supplies are first applied to the AD7904/AD7914/AD7924,
the ADC may power up in any of the operating modes of the
part. To ensure that the part is placed into the required operating
mode, the user should perform a dummy cycle operation as
shown in Figure 23, Figure 24, and Figure 25.
The dummy conversion operation must be performed to place
the part into the desired mode of operation. To ensure that the
part is in normal mode, this dummy cycle operation can be
performed with the DIN line tied high, that is, the PM1 and
PM0 bits are set to 11 (depending on other required settings in
the control register). However, the minimum power-up time of
1 µs must be allowed from the rising edge of CS, where the
control register is updated, before attempting the first valid
conversion. This power-up time allows for the possibility that
the part was initially powered up in shutdown mode.
If the desired mode of operation after supplies are applied is
auto shutdown mode, two dummy cycles are required: the first
dummy cycle with DIN tied high, and the second to set the
power management bits, PM1 and PM0, to 01. On the second CS
rising edge after the supplies are applied, the control register
contains the correct information and the part enters auto
shutdown mode as programmed. If power consumption is of
critical concern, then in the first dummy cycle, the user can set
PM1 and PM0 to 10, that is, full shutdown mode, and then place
the part into auto shutdown mode in the second dummy cycle.
For illustration purposes, Figure 25 is shown with DIN tied
high on the first dummy cycle in this case.
Figure 23, Figure 24, and Figure 25 show the required dummy
cycles after supplies are applied for normal mode, full shutdown
mode, and auto shutdown mode, respectively.
If the desired mode of operation is full shutdown, one dummy
cycle is required after supplies are applied. In this dummy cycle,
the user simply sets the power management bits, PM1 and PM0,
to 10 and, upon the rising edge of CS at the end of that serial
transfer, the part enters full shutdown mode.
Rev. C | Page 23 of 32
03087-022
DOUT
AD7904/AD7914/AD7924
Data Sheet
IF IN SHUTDOWN AT POWER-ON,
PART BEGINS TO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
ALLOW tPOWER TO ELAPSE
t12
CS
1
14
16
1
14
16
SCLK
DOUT
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN
03087-023
DATA IN TO CONTROL REGISTER
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
TO KEEP THE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 23. Placing the AD7904/AD7914/AD7924 into Normal Mode After Supplies Are First Applied
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
PART ENTERS SHUTDOWN ON
CS RISING EDGE AS PM1 = 1, PM0 = 0
CS
1
14
16
SCLK
INVALID DATA
DOUT
DATA IN TO CONTROL REGISTER
03087-024
DIN
CONTROL REGISTER IS LOADED ON
THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0
Figure 24. Placing the AD7904/AD7914/AD7924 into Full Shutdown Mode After Supplies Are First Applied
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
PART ENTERS AUTO SHUTDOWN ON
CS RISING EDGE AS PM1 = 0, PM0 = 1
CS
1
14
16
1
14
16
SCLK
INVALID DATA
INVALID DATA
DIN
DATA IN TO CONTROL REGISTER
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS. PM1 = 0, PM0 = 1
Figure 25. Placing the AD7904/AD7914/AD7924 into Auto Shutdown Mode After Supplies Are First Applied
Rev. C | Page 24 of 32
03087-025
DOUT
Data Sheet
AD7904/AD7914/AD7924
POWER vs. THROUGHPUT RATE
By operating the AD7904/AD7914/AD7924 in auto shutdown
mode, the average power consumption of the ADC decreases at
lower throughput rates. Figure 26 shows how, as the throughput
rate is reduced, the part remains in its shutdown state longer, and
the average power consumption over time drops accordingly.
For example, if the AD7924 is operated in continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz
(AVDD = 5 V), and the device is placed into auto shutdown mode
(PM1 = 0 and PM0 = 1), the power consumption is calculated
as described in this section.
The maximum power dissipation during normal operation is
13.5 mW (AVDD = 5 V). If the power-up time from auto shutdown
is one dummy cycle, that is, 1 µs, and the remaining conversion
time is another cycle, that is, 1 µs, then the AD7924 can be said
to dissipate 13.5 mW for 2 µs during each conversion cycle. For
the remainder of the conversion cycle, 8 µs, the part remains in
shutdown. The AD7924 can be said to dissipate 2.5 µW for the
remaining 8 μs of the conversion cycle. If the throughput rate is
100 kSPS, the cycle time is 10 µs and the average power dissipated
during each cycle is ((2/10) × 13.5 mW) + ((8/10) × 2.5 µW) =
2.702 mW.
Figure 26 shows the maximum power vs. throughput rate when
using the auto shutdown mode with 5 V and 3 V supplies.
10
AVDD = 5V
AVDD = 3V
POWER (mW)
1
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold returns
to track mode on the 14th SCLK falling edge, as shown by Point B
in Figure 27, Figure 28, and Figure 29. On the 16th SCLK falling
edge, the DOUT line returns to three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, the conversion is
terminated, the DOUT line returns to three-state, and the
control register is not updated; otherwise, DOUT returns to
three-state on the 16th SCLK falling edge, as shown in Figure 27,
Figure 28, and Figure 29.
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7904/AD7914/AD7924.
For the AD7904/AD7914/AD7924, the 8/10/12 bits of data are
preceded by two leading zeros and the two channel address bits,
ADD1 and ADD0, which identify the channel that the result
corresponds to. CS going low clocks out the first leading zero to
be read in by the microcontroller or DSP on the first falling edge of
SCLK. The first falling edge of SCLK also clocks out the second
leading zero to be read in by the microcontroller or DSP on the
second SCLK falling edge, and so on. The two address bits and
the 8/10/12 data bits are then clocked out by subsequent SCLK
falling edges beginning with the first address bit, ADD1; thus,
the second falling clock edge on the serial clock has the second
leading zero provided and also clocks out the address bit ADD1.
The final bit in the data transfer is valid on the 16th falling edge,
having been clocked out on the previous (15th) falling edge.
The writing of information to the control register takes place on
the first 12 falling edges of SCLK in a data transfer, assuming
that the MSB (the WRITE bit) has been set to 1.
0.01
0
50
100
150
200
250
300
THROUGHPUT (kSPS)
350
03087-026
0.1
Figure 26. AD7924 Power vs. Throughput Rate
SERIAL INTERFACE
Figure 27, Figure 28, and Figure 29 show the detailed timing
diagrams for serial interfacing to the AD7904, AD7914, and
AD7924, respectively. The serial clock provides the conversion
clock and controls the transfer of information to and from the
AD7904/AD7914/AD7924 during each conversion.
The AD7904 outputs two leading zeros, two channel address
bits that the conversion result corresponds to, followed by the
8-bit conversion result and four trailing zeros. The AD7914
outputs two leading zeros, two channel address bits that the
conversion result corresponds to, followed by the 10-bit
conversion result and two trailing zeros. The 16-bit word read
from the AD7924 always contains two leading zeros, two
channel address bits that the conversion result corresponds to,
followed by the 12-bit conversion result.
Rev. C | Page 25 of 32
AD7904/AD7914/AD7924
Data Sheet
CS
t2
3
4
t3
t9
WRITE
DB7
ADD0
ADD1
ZERO
THREESTATE
ZERO
6
SEQ1
DONTC
t5
t11
t8
DB0
DB6
2 IDENTIFICATION
BITS
16
15
14
13
12
11
t7
t4
DOUT
DIN
B
5
tQUIET
ZERO
ZERO
ZERO
ZERO
THREESTATE
4 TRAILING ZEROS
t10
DONTC
ADD1
ADD0
CODING DONTC
DONTC
DONTC
03087-027
2
1
SCLK
tCONVERT
t6
DONTC
Figure 27. AD7904 Serial Interface Timing Diagram
CS
t2
2
t3
ADD1
ZERO
THREESTATE
ZERO
t9
WRITE
DONTC
14
15
16
t5
t11
t8
DB2
DB8
DB9
ADD0
2 IDENTIFICATION
BITS
SEQ1
13
12
11
t7
t4
DOUT
DIN
B
6
5
4
3
DB0
DB1
tQUIET
ZERO
ZERO
2 TRAILING ZEROS
THREESTATE
t10
DONTC
ADD0
ADD1
CODING DONTC
DONTC
03087-028
1
SCLK
tCONVERT
t6
DONTC
DONTC
Figure 28. AD7914 Serial Interface Timing Diagram
CS
t2
2
3
4
t3
ZERO
THREESTATE
ZERO
WRITE
t9
ADD1
ADD0
DB11
DONTC
11
12
13
14
15
16
t5
t11
t8
DB10
DB4
DB3
DB2
DB1
tQUIET
DB0
THREESTATE
2 IDENTIFICATION
BITS
SEQ1
6
t7
t4
DOUT
DIN
B
5
t10
DONTC
ADD1
ADD0
CODING DONTC
DONTC
Figure 29. AD7924 Serial Interface Timing Diagram
Rev. C | Page 26 of 32
DONTC
DONTC
03087-029
1
SCLK
tCONVERT
t6
Data Sheet
AD7904/AD7914/AD7924
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
The SPORT0 control register of the ADSP-218x should be set
up as follows:
The serial interface of the AD7904/AD7914/AD7924 allows
the part to be directly connected to a range of different
microprocessors. This section explains how to interface the
AD7904/AD7914/AD7924 to some of the more common
microcontroller and DSP serial interface protocols.
AD7904/AD7914/AD7924 to TMS320C541
The serial interface of the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices such as the AD7904/
AD7914/AD7924. The CS input allows easy interfacing between
the TMS320C541 and the AD7904/AD7914/AD7924 without any
glue logic required. The serial port of the TMS320C541 is set up
to operate in burst mode with internal CLKX0 (TX serial clock
on Serial Port 0) and FSX0 (TX frame sync from Serial Port 0).
The serial port control (SPC) register must have the following
setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection
diagram is shown in Figure 30. Note that for signal processing
applications, it is imperative that the frame synchronization
signal from the TMS320C541 provide equidistant sampling.
The VDRIVE pin of the AD7904/AD7914/AD7924 takes the same
supply voltage as the TMS320C541. This allows the ADC to
operate at a higher voltage than the serial interface, that is, the
TMS320C541, if necessary.
AD7904/
AD7914/
AD7924*
SCLK
TFSW = RFSW = 1, alternate framing
INVRFS = INVTFS = 1, active low frame signal
DTYPE = 00, right justify data
SLEN = 1111, 16-bit data-words
ISCLK = 1, internal serial clock
TFSR = RFSR = 1, frame every word
IRFS = 0
ITFS = 1
The connection diagram is shown in Figure 31. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT0 control register is set up as
described. The frame synchronization signal generated on the
TFS is tied to CS and, as with all signal processing applications,
equidistant sampling is necessary. However, in this example, the
timer interrupt is used to control the sampling rate of the ADC,
and under certain conditions equidistant sampling may not be
achieved.
AD7904/
AD7914/
AD7924*
ADSP-218x*
SCLK
SCLK
DOUT
DR
CS
TMS320C541*
RFS
TFS
DIN
DT
VDRIVE
CLKX
DR
DIN
DT
VDRIVE
VDD
*ADDITIONAL PINS REMOVED FOR CLARITY.
FSX
FSR
Figure 31. Interfacing to the ADSP-218x
VDD
*ADDITIONAL PINS REMOVED FOR CLARITY.
03087-030
CS
03087-031
CLKR
DOUT
Figure 30. Interfacing to the TMS320C541
AD7904/AD7914/AD7924 to ADSP-218x
The ADSP-218x family of DSPs interfaces directly to the
AD7904/AD7914/AD7924 without any glue logic required.
The VDRIVE pin of the AD7904/AD7914/AD7924 takes the same
supply voltage as the ADSP-218x. This allows the ADC to
operate at a higher voltage than the serial interface, that is, the
ADSP-218x, if necessary.
The timer register, for example, is loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and thus the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (that is, AX0 = TX0), the state of the SCLK is checked.
The DSP waits until SCLK goes high, low, and high again before
transmission starts. If the timer and SCLK values are chosen in
such a way that the instruction to transmit occurs on or near
the rising edge of SCLK, the data may be transmitted or it may
wait until the next clock edge.
For example, if the ADSP-2189 has a 20 MHz crystal so that its
master clock frequency is 40 MHz, then the master cycle time is
25 ns. If the SCLKDIV register is loaded with the value 3, then
an SCLK of 5 MHz is obtained and eight master clock periods
elapse for every one SCLK period.
Rev. C | Page 27 of 32
AD7904/AD7914/AD7924
Data Sheet
Depending on the throughput rate selected, if the timer register
is loaded with a value such as 803 (803 + 1 = 804), then 100.5
SCLKs will occur between interrupts and subsequently between
transmit instructions. This setup results in nonequidistant
sampling because the transmit instruction occurs on an SCLK
edge. If the number of SCLKs between interrupts is a whole
integer value N, equidistant sampling is implemented by the DSP.
AD7904/AD7914/AD7924 to DSP563xx
The connection diagram in Figure 32 shows how the AD7904/
AD7914/AD7924 can be connected to the ESSI (synchronous
serial interface) of the DSP563xx family of DSPs from Motorola.
Each ESSI (two on board) is operated in synchronous mode
(SYN bit in CRB = 1) with internally generated 1-bit clock
period frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 =
0 in CRB). Normal operation of the ESSI is selected by setting
MOD = 0 in the CRB. Set the word length to 16 by setting bits
WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should
be set to 1 so that the frame sync is negative. Note that for signal
processing applications, it is imperative that the frame synchronization signal from the DSP563xx provide equidistant sampling.
In the example shown in Figure 32, the serial clock is taken from
the ESSI so the SCK0 pin must be set as an output (SCKD = 1).
The VDRIVE pin of the AD7904/AD7914/AD7924 takes the same
supply voltage as the DSP563xx. This allows the ADC to operate
at a higher voltage than the serial interface, that is, the DSP563xx,
if necessary.
AD7904/
AD7914/
AD7924*
SCLK
DSP563xx*
SCK
DOUT
SRD
CS
STD
DIN
SC2
VDD
*ADDITIONAL PINS REMOVED FOR CLARITY.
Figure 32. Interfacing to the DSP563xx
03087-032
VDRIVE
GROUNDING AND LAYOUT
The AD7904/AD7914/AD7924 have very good immunity to
noise on the power supplies (see Figure 6). However, care
should be taken with regard to grounding and layout.
The PCB that houses the AD7904/AD7914/AD7924 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes because it
provides the best shielding. All four AGND pins of the AD7904/
AD7914/AD7924 should be sunk in the AGND plane. Digital
and analog ground planes should be joined at only one place. If
the AD7904/AD7914/AD7924 are in a system where multiple
devices require an AGND-to-DGND connection, the connection
should still be made at one point only: a star ground point
established as close as possible to the AD7904/AD7914/AD7924.
Avoid running digital lines under the device because these lines
couple noise onto the die. The analog ground plane should be
allowed to run under the AD7904/AD7914/AD7924 to avoid
noise coupling. The power supply lines to the AD7904/AD7914/
AD7924 should use as large a trace as possible to provide low
impedance paths and reduce the effects of glitches on the power
supply line. Fast switching signals such as clocks should be
shielded with digital ground to avoid radiating noise to other
sections of the board, and clock signals should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at
right angles to each other to reduce the effects of feedthrough
through the board. A microstrip technique is by far the best, but
is not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to AGND. To achieve the best performance
from these decoupling components, place them as close as
possible to the device, ideally right up against the device. The
0.1 μF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the common
ceramic types or surface-mount types, which provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
Rev. C | Page 28 of 32
Data Sheet
AD7904/AD7914/AD7924
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 33. 16-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
AD7904BRU
AD7904BRU-REEL
AD7904BRUZ
AD7904BRUZ-REEL
AD7904BRUZ-REEL7
AD7904WYRUZ-REEL7
AD7914BRU-REEL
AD7914BRUZ
AD7914BRUZ-REEL7
AD7914WYRUZ-REEL7
AD7924BRU
AD7924BRU-REEL7
AD7924BRUZ
AD7924BRUZ-REEL
AD7924BRUZ-REEL7
AD7924WYRUZ-REEL7
Notes
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
Linearity Error (LSB)3
±0.2
±0.2
±0.2
±0.2
±0.2
±0.2
±0.5
±0.5
±0.5
±0.5
±1
±1
±1
±1
±1
±1
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
1
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
3
Linearity error refers to integral linearity error.
2
AUTOMOTIVE PRODUCTS
The AD7904W/AD7914W/AD7924W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. C | Page 29 of 32
AD7904/AD7914/AD7924
Data Sheet
NOTES
Rev. C | Page 30 of 32
Data Sheet
AD7904/AD7914/AD7924
NOTES
Rev. C | Page 31 of 32
AD7904/AD7914/AD7924
Data Sheet
NOTES
©2002–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03087-0-6/13(C)
Rev. C | Page 32 of 32

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