INNOVASIC IA82510PLC28IR2 Asynchronous serial controller Datasheet

IA82510
Asynchronous Serial Controller
Data Sheet
February 25, 2011
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Asynchronous Serial Controller
Data Sheet
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Data Sheet
February 25, 2011
Copyright 2008 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
Intel is a registered trademark of Intel Corporation
MILES™ is a trademark of Innovasic Semiconductor, Inc.
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February 25, 2011
TABLE OF CONTENTS
List of Figures ..................................................................................................................................4
List of Tables ...................................................................................................................................5
1.
Features ...................................................................................................................................6
2.
Description ..............................................................................................................................8
3.
Functional Overview ............................................................................................................10
3.1 Transmitter ..................................................................................................................10
3.2 Receiver .......................................................................................................................10
3.3 Bus Interface ...............................................................................................................10
3.4 Register Description ....................................................................................................11
4.
Maximum Ratings and AC/DC Parameters ..........................................................................12
5.
Packaging Information..........................................................................................................15
5.1 PDIP Package ..............................................................................................................15
5.2 PLCC Package .............................................................................................................16
6.
Innovasic Part Number Cross-Reference..............................................................................17
7.
Errata.....................................................................................................................................18
7.1 Summary .....................................................................................................................18
7.2 Detail ...........................................................................................................................19
8.
Revision History ...................................................................................................................24
9.
For Additional Information...................................................................................................25
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LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Package Pinout ................................................................................................................7
Functional Block Diagram ..............................................................................................9
PDIP Physical Package Dimensions .............................................................................15
PLCC Physical Package Dimensions ............................................................................16
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Data Sheet
February 25, 2011
LIST OF TABLES
Table 1.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Register Summary...........................................................................................................11
Absolute Maximum Ratings ...........................................................................................12
AC Parameters ................................................................................................................13
DC Parameters ................................................................................................................14
Innovasic Part Number Cross-Reference for the PDIP ..................................................17
Innovasic Part Number Cross-Reference for the PLCC .................................................17
Summary of Errata ..........................................................................................................18
Revision History .............................................................................................................24
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1.
Data Sheet
February 25, 2011
Features
Form, Fit, and Function Compatible with the Intel 82510
Packaging options available: 28-Pin Plastic (PDIP) or, 28-Lead Plastic Leaded Chip
Carrier (PLCC), Leaded or RoHS packages available (see Figure 1, Package Pinout)
Asynchronous Serial Channel Operation
Separate Transmit and Receive FIFOs with Programmable Threshold
Programmable Baud Rate Generators up to 288K Baud
Special Protocol Features
– Control Character Recognition
– Auto Echo and Loopback Modes
– 9-Bit Protocol Support
– 5 to 9 Bit Character Format
The IA82510 is a "plug-and-play" drop-in replacement for the original IC. Innovasic produces
replacement ICs using its MILES™, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while
ensuring they are compatible with the original IC. MILES™ captures the design of a clone so it
can be produced even as silicon technology advances. MILES™ also verifies the clone against
the original IC so that even the "undocumented features" are duplicated. This data sheet
documents all necessary engineering information about the IA82510 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
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Data Sheet
February 25, 2011
D7
D6
D5
D4
D3
D2
D1
(4)
(3)
(2)
(1)
(28)
(27)
(26)
D4
(1)
(28)
D3
D5
(2)
(27)
D2
D6
(3)
(26)
D1
D7
(4)
(25)
D0
INT
(5)
(24)
A2
INT
(5)
(25)
D0
(23)
A1
TXD
(6)
(24)
A2
(22)
A0
VSS
(7)
(23)
A1
(22)
A0
X1 or CLK
(9)
(20)
RDn
X1 or CLK
(9)
SCLK or RIn
VDD
(10)
(19)
WRn
DSRn or TA or OUT0n
(11)
(18)
CSn
DCDn or ICLK or OUT1n
(12)
(17)
RESET
RXD
(13)
(16)
RTSn
CTSn
(14)
(15)
DSRn or TA or OUT0n
IA82510
28-Pin PLCC
(21)
VDD
(10)
(20)
RDn
(11)
(19)
WRn
(12) (13) (14) (15) (16) (17) (18)
DTRn or TB
DCDn or ICLK or OUT1n
SCLK or RIn
(21)
(8)
CSn
(8)
X2 or OUT2n
RESET
X2 or OUT2n
28-Pin PDIP
RTSn
(7)
DTRn or TB
VSS
IA82510
RXD
(6)
CTSn
TXD
Figure 1. Package Pinout
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2.
Data Sheet
February 25, 2011
Description
The IA82510 is an asynchronous serial controller that provides a CPU interface to one transmit
and one receive channel. It is Form, Fit, and Function compatible with the Intel 82510.
Configuration registers are used to control the serial channel, interrupts, and modes of operation.
The CPU controls this device via address and data lines with read/write control. The CPU also
uses this interface to read and write data to receive and transmit data through the serial channel.
FIFOs and various serial modes can be used to help off-load the CPU from transmitting and
receiving data. An interrupt line provides an indication to the CPU that the device requires
servicing. The device can be configured for 8250A/16450 compatibility. See Figure 2,
Functional Block Diagram.
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IA82510
A(2:0)
D(7:0)
RDn
WRn
CSn
TRANSMITTER
TXD
RECEIVER
RXD
BUS INTERFACE
(Reset Logic,
Registers,
Interrupt Generation,
INT
RESET
CTSn
RTSn
TIMING
(Baud Rate
Generators A & B,
Clocking
CONFIG., STATUS, RXDATA
TXDATA
PIN
CONFIGURATION
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
DTRn or TB
MODEM
X1 or CLK
X2 or OUT2n
SCLK or RIn
Figure 2. Functional Block Diagram
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3.
Functional Overview
3.1
Transmitter
Data Sheet
February 25, 2011
The Transmit function consists of a 4 11 bit FIFO, and a Transmit Engine. The 4 11 FIFO is
configurable as any depth between one and four words inclusive. The transmit engine is
responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin.
The transmit engine is highly configurable to be compatible with numerous formats, including
16450 and 8250 modes of communication. Transmit Communication parameters that can be
programmed include:
Parity modes
Stop Bits
Character Length
FIFO Depth
Clocking Options
RTS and CTS modes
For more details, see Section 3.4, Register Description.
3.2
Receiver
The Receiver function consists of a 4 11 configurable FIFO and a Receive Engine. The receive
engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing
the data in the FIFO. The receive engine is highly configurable with parameters that include:
Parity modes
Stop Bits
Character Length
FIFO Depth
Clocking Options
Address Matching Options
Control Character Detection
RTS and CTS modes
For more details, see Section 3.4, Register Description.
3.3
Bus Interface
The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read
and write the IA82510 Registers. It consists of the following I/O lines:
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A0, A1, A2:
D0-D7:
RDn:
WRn:
CSn:
INT:
RESET:
3.4
Data Sheet
February 25, 2011
3 Bit Address
8 Bit Data
Active Low Read Enable
Active Low Write Enable
Active Low Chip Select
Interrupt Output
Chip Reset
Register Description
Table 1 presents the register summary.
Table 1. Register Summary
Register
ACR0
ACR1
BACF
BAH
BAL
BANK
BBCF
BBH
BBL
CLCF
FLR
FMD
GER
GIR_BANK
GSR
ICM
IMD
LCR
LSR
MCR
MIE
MSR
PMD
RCM
RIE
RMD
ADDR
111
101
001
001
000
010
011
001
000
000
100
001
001
010
111
111
100
011
101
100
100
101
110
110
100
101
110
111
Bank
00
10
11
00
00
X
11
11
11
11
01
10
00
X
01
01
10
00
00
00
01
11
00
01
11
01
10
10
®
DLAB
X
X
0
1
1
X
X
1
1
0
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Mode
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R
W
R/W
R/W
R/W
R/W
W
R/W
R/W
R
R/W
W
R/W
R/W
Default
00000000
00000000
00000100
00000000
00000010
00000000
10000100
00000000
00000101
00000000
00000000
00000000
00000000
00000001
00010010
N/A
00001100
00000000
01100000
00000000
00001111
00000000
11111100
N/A
00011110
00000000
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Table 2. Register Summary (Continued)
Register
RST
RXDATA
ADDR
101
000
RXF
TCM
TMCR
TMD
TMIE
TMST
TXDATA
001
110
011
011
110
011
000
TXF
001
4.
Bank
01
00
01
01
01
01
10
11
01
00
01
01
DLAB
X
0
X
X
X
X
X
X
X
0
X
X
Mode
R
R
Default
00000000
Unknown
R
W
W
R/W
R/W
R
W
Unknown
N/A
N/A
00000000
00000000
00110000
N/A
W
N/A
Maximum Ratings and AC/DC Parameters
Stresses beyond those listed in Table 2 may cause permanent damage to the device. Operating the
device beyond the conditions indicated in the “recommended operating conditions” section is not
recommended. Operation at the “absolute maximum ratings” may adversely affect device
reliability.
Table 3. Absolute Maximum Ratings
Parameter
Supply Voltage, VDD
Input Voltage, VIN
Input Pin Current, IIN
Operating Temperature Range
Ambient temperature under bias
Storage temperature
Lead Temperature
Power dissipation
Rating
-0.3V to +6.0V
-0.3V to VDD +0.3V
±10 mA, 25 C
-40 C to +85°C
-40°C to +85°C *
-55°C to +150°C
+300°C, 10 sec.
155 mW, 125°C, 25MHz, 15% Toggle
* The input and output parametric values are directly related to ambient temperature and DC supply
voltage. A temperature or supply voltage range other than those specified in the Operating Conditions
above will affect these values and part performance is not guaranteed by Innovasic.
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Table 4. AC Parameters
Parameter
CLK period
CLK period
CLK Low Time
CLK High Time
CLK Rise Time
Min
–
Max
250 ns
108 ns
–
–
10 ns
CLK Fall Time
–
10 ns
CLK Rise Time
CLK Fall Time
Crystal Frequency
Reset Width
RTS/DTR Low Setup to Reset
inactive
RTS/DTR Low Hold after
Reset inactive
RDn Active Width
–
–
15 ns
15 ns
20 Mhz
–
–
54 ns
54 ns
25 ns
25 ns
Address/CSn Setup Time to
RDn Active
Address/CSn Hold after RDn
Inactive
RDn or WRn Inactive to Active
Delay
Data Out Float Delay after
RDn Inactive
WRn Active Width
Address CSn Setup Time to
WRn Active
Address and CSn hold Time
after WRn
Data in Setup Time to WRn
Inactive
Data In Hold Time after WRn
Inactive
SCLK Period
SCLK Period
RXD Setup Time to SCLK High
RXD Hold Time after SCLK
High
TXD Valid after SCLK Low
TXD Delay after RXD
®
1 Mhz
8 * Clock Period
6 * Clock Period
–
Clock Period
–20 ns
–
2* clock period
+65 ns
7 ns
Notes
Divide by Two
No Divide by
–
–
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
No Divide by
No Divide by
–
–
–
–
–
–
–
0 ns
–
–
Clock Period
+15 ns
–
–
–
–
40 ns
2 * Clock Period
+15 ns
7 ns
–
–
–
–
0 ns
–
–
90 ns
–
–
12 ns
–
–
216 ns
3500 ns
250 ns
250 ns
–
–
–
–
–
–
170 ns
170 ns
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16x Clocking Mode
1x Clocking Mode
–
–
–
Remote Loopback
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Table 5. DC Parameters
Symbol
VIL
VIH1
VIH2
VOL
VOH
ILI
ILO
ICC
IPU
ISTBY
IOHR
IOLR
CIN
CIO
CXTAL
Parameter
Input Low Voltage
Input High Voltage-Cerdip
Input High Voltage-LCC
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Leakage Current
Power Supply Current
Strapping Pullup Resistor
Standby Supply Current
RTSn, DTRn Strapping Current
RTSn, DTRn Strapping Current
Input Capacitance
I/O Capacitance
X1, X2 Load
Notes
(1)
(1)
(2)
(2),(8)
(3),(8)
(4)
(5)
(6)
(12)
(9)
(10)
(11)
(7)
(7)
Min
-0.5
2.1
2.1
Max
0.3
VDD+.3
VDD+.3
0.4
2.4
-28.3
1
10
1.12
-137
100
1.92
N/A
5
6
6
Unit
V
V
V
V
V
A
A
mA/MHz
A
A
mA
mA
pF
pF
pF
Notes:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @IOL = 1.92 mA.
3. @IOH = 1.92 mA.
4. 0< VIN <VCC.
5. 0.4V < VOUT < VCC – 0.4V.
6. VDD = 5.5V, VIL = 0.7V (max), VIH = VDD – 0.7V (min), Typ. Val = 1.12 mA/MHz (Not Tested), Ext. 1X
CLK, IOL = IOH = 0.
7. Freq. = 1 MHz.
8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
9. Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output drive
requirements and is measured with the clocks stopped and all inputs tied to VDD or VSS, configured
to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH.
11. Applies only during hardware reset for clock configuration options. Strapping current for logic LOW.
12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V, VDD = 5.5V.
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5.
Packaging Information
5.1
PDIP Package
E1
E
Lead 1
Identifier
eA
Lead Count 1
Direction
C
eB
Top
Side View (Width)
Legend:
A
D
A1
L
B
B1
Symbol
A
A1
B
B1
C
E
E1
e
eA
eB
L
B2
S
28 (in Inches)
Min
Max
0.200
0.015
0.015
0.020
0.050
0.070
0.008
0.012
0.580
0.610
0.520
0.560
0.100 TYP
0.580
0.686
0.100 Min
-
e
Side View (Length)
Figure 3. PDIP Physical Package Dimensions
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2 PLCS
PLCC Package
D
Pin 1
Identifier & Zone
D1
E1
E
E3
1.22/1.07
5.2
Data Sheet
February 25, 2011
D3
Top View
Bottom View
0.81/0.66
A1
A
Seating Plane
0.10
e
0.51 Min.
R 1.14/0.64
0.53/0.33
Legend:
Symbol
A
A1
D
D1
D2
D3
e
E
E1
E2
E3
Min
Max
4.20
4.57
2.29
3.04
12.32
12.57
11.43
11.58
9.91
10.92
7.62 BSC
1.27 BSC
12.32
12.57
11.43
11.58
9.91
10.92
7.62 BSC
D2 /E2
Note: Controlling dimension in
millimeters.
Side View
Figure 4. PLCC Physical Package Dimensions
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6.
Data Sheet
February 25, 2011
Innovasic Part Number Cross-Reference
Table 6. Innovasic Part Number Cross-Reference for the PDIP
Innovasic Part Number
Intel Part Number
Package Type
IA82510-PDW28I-R-01
P82510
28-Pin Plastic Dual Inlead-free (RoHS-compliant) TP82510
Line Package (PDIP)
(600 mils)
Temperature Grades
Industrial
Table 7. Innovasic Part Number Cross-Reference for the PLCC
Innovasic Part Number
Intel Part Number
Package Type
IA82510PLC28IR2
N82510
28-Lead Plastic Leaded
lead-free (RoHS-compliant) TN82510
Chip Carrier (PLCC)
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Temperature Grades
Industrial
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7.
Data Sheet
February 25, 2011
Errata
The following errata are known problems with the IA82510. This is inclusive of all package types
and environment grades. A workaround to the identified problem has been provided where
possible. All errata listed in production Version 00 have been fixed in Version 01 of the device
unless otherwise noted. Version 02 is the result of a migration to a new fab process to ensure
long-term supply. It retains the same functionality and errata as the Version 01 device.
7.1
Summary
Table 8 presents a summary of errata.
Table 8. Summary of Errata
Errata
No.
Problem
Ver. 00
Ver. 01
Ver. 02
1
Scrambled data during boot code shuts down UART, however
device works for application code.
Exists
Fixed
Fixed
2
Device does not operate at 8 MHz in divide-by-one mode.
Exists
Fixed
Fixed
3
Setting CLCF to x30, which effectively generates the TX clock
from the incoming SCLK signal, kills all transmits.
Exists
Fixed
Fixed
4
Receiving streamed data has many framing errors and corrupt
data when connected to some modems.
Exists
Fixed
Fixed
5
Transmission of streamed data does not return interrupt.
Exists
Fixed
Fixed
6
Receiving streamed data has many framing errors at fast baud
rates (divisor=6) through bad modem lines.
Exists
Fixed
Fixed
7
Difficulty starting oscillator with crystal.
Exists
Fixed
Fixed
8
Intermittent and temperature sensitive crystal oscillator
operation when cycling power.
Exists
Fixed
Fixed
9
Auto-acknowledge of interrupts via writing of LSR does not
work.
Exists
Fixed
Fixed
10
ICM Status Clear command does not clear LSR/RST overrun
error.
Exists
Fixed
Fixed
11
In semi-automatic/uLAN mode, the RX FIFO is only opened
when an address character matches the ACR1 or ACR0
registers (like full auto mode).
Exists
Fixed
Fixed
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Table 7. Summary of Errata (Continued)
Errata
No.
7.2
Problem
Ver. 00
Ver. 01
Ver. 02
Exists
Fixed
Fixed
12
Device fails to reset interrupt signal in auto acknowledge mode
when character is read from RX FIFO.
13
RX FIFO locks up unexpectedly just after configuration and
before starting reception.
NA
Exists
Exists
14
Unreliable transmits in AUTO TX mode.
NA
Exists
Exists
Detail
Errata No. 1
Problem: Scrambled data during boot code shuts down UART, however device works for
application code.
Description: The RX FIFO is locked, configuration of all registers is done, then the RX FIFO is
unlocked just before entering loopback mode in both boot and application code before normal
operations begin. Boot code additionally does a blind block read of all registers before normal
operations including two reads from the unwritten RX Data FIFO. RX unlock command is
inadvertently incrementing the write pointer. For boot code, the two reads of RX data cause the
read/write pointers to be permanently out of sync. For application code, the pointers end up
synched to the same location, only because the code waits for four characters before reading. This
ends up causing an RX overrun, but to our favor because the pointers are now synched.
Workaround: Execute a “Flush RX FIFO” command (via RCM register) after configuration and
block read is complete.
Errata No. 2
Problem: Device does not operate at 8 MHz in divide-by-one mode.
Description: System testing revealed this operational deficiency.
Workaround: Switch to divide-by-two mode using 2X clock input.
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Errata No. 3
Problem: Setting CLCF to x30, which effectively generates the TX clock from the incoming
SCLK signal, kills all transmits.
Description: Configuration of PMD inadvertently set so RI function is selected instead of SCLK
function. Original Intel device allows SCLK through anyway, IA82510 suppresses it.
Workaround: Set correct configuration for PMD allows TX clock generation.
Errata No. 4
Problem: Receiving streamed data has many framing errors and corrupt data when connected to
some modems.
Description: Shortened stop bit followed immediately by next start bit does not correctly detect
that start bit.
Workaround: Configure external modem to transmit two stop bits.
Errata No. 5
Problem: Transmission of streamed data does not return interrupt.
Description: Stray read of GIR sets TX FIFO interrupt hold logic, but this logic does not reset
when GER[1] is de-asserted.
Workaround: Reset logic with write to TX data or avoid stray reads of GIR.
Errata No. 6
Problem: Receiving streamed data has many framing errors at fast baud rates (divisor=6) through
bad modem lines.
Description: DPLL is not robust for RXD signal with more than 1/16 bit time of variation.
Workaround: None.
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Errata No. 7
Problem: Difficulty starting oscillator with crystal.
Description: No internal feedback resistor between X1 and X2.
Workaround: Install external 1-10Mohm resistor.
Errata No. 8
Problem: Intermittent and temperature sensitive crystal oscillator operation when cycling power.
Description: Strapping state elements apparently transparent latches instead of flip flops. If flip
flop powers up to wrong state, crystal oscillator is disabled while reset is active. OK after first
reset following power-up.
Workaround: None.
Errata No. 9
Problem: Auto-acknowledge of interrupts via writing of LSR does not work.
Description: Writing LSR directly sets/resets bits 4 through 0. Also writing 0 to LSR(0) – RX
FIFO – clears the RX FIFO level as seen by FLR. Writing zero to any other LSR bits clears the
corresponding LSR/RST flag, but also corrupts the FIFO location the write pointer is set to, then
increments both the write and read pointers.
Workaround: Use other means to service interrupts, such as read of RST or RXD.
Errata No. 10
Problem: ICM Status Clear command does not clear LSR/RST overrun error.
Description: ICM Status Clear command should clear everything in RST/LSR, MSR, and TMST
except RST/LSR(0). Overrun error was missed.
Workaround: Use other means to service interrupts.
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Errata No. 11
Problem: In semi-automatic/uLAN mode, the RX FIFO is only opened when an address
character matches the ACR1 or ACR0 registers (like full auto mode).
Description: In semi-auto mode, the RX FIFO should open on any address character.
Workaround: None.
Errata No. 12
Problem: Device fails to reset interrupt signal in auto acknowledge mode when character is read
from RX FIFO.
Description: RD strobe is outside the CS enable, which is outside of the Intel datasheet, but
apparently still works in the Intel device. Such a bus cycle allows the read data out, but fails to
generate the necessary internal strobe to change pointers. The same problem is found on write
accesses.
Workaround: Force bus interface to bracket RD strobe inside the CS enable.
Errata No. 13
Problem: RX FIFO locks up unexpectedly just after configuration and before starting reception.
Description: An RCM command is executed with data of xB8. This is an “enable RX”, “flush
RX machine”, “flush RX FIFO”, and “lock RX FIFO” command done in a single instruction. The
“flush RX machine” should unlock the RX FIFO, creating a conflict with the simultaneous “lock
RX FIFO” command. The original Intel device apparently ignores or gives the “lock RX FIFO”
command lower priority in this case. The IA82510 has this priority reversed. Apparently, the
application software in this case expected the “lock RX FIFO” command to fail.
Workaround: Do not execute a “flush RX FIFO” and “lock RX FIFO” command simultaneously.
Break up into separate RCM commands.
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Errata No. 14
Problem: Unreliable transmits in AUTO TX mode.
Description: Many systems use the RTS output to activate the line transceiver. When the
Transmit Mode field in the TMD register is set to semi-auto or automatic mode, RTS is controlled
by the TX state machine. On the first character, RTS asserts at the same time as the start bit on
the TXD output, whereas the original Intel device asserts RTS a full bit time before assertion of
the start bit on TXD. At full temperature range, the width of the start bit can be altered to the
point of confusing the downstream receiver.
Workaround: Change firmware to Manual TX mode to control RTS vs. start of character.
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8.
Data Sheet
February 25, 2011
Revision History
Table 9 presents the sequence of revisions to document IA211001219.
Table 9. Revision History
Date
August 19, 2008
Revision
03
October 8, 2008
04
February 25, 2011
05
®
Description
Corrected control number and reformatted some elements
to meet publication standards.
Corrected part number on cover page, enlarged package
pinout and functional block diagram figures, corrected
trademark references (p. 2), changed “pin” to “lead” in
PLCC package pinout figure, changed “lead” to “pin” in
PDIP physical page dimensions figure and part number
table, formatted part cross-reference table and errata to
meet publication standards, changed part number from
“IA82510-PLC28I-R-01” to “IA82510PLC28IR2” to reflect
current inventory, added “For Additional Information”
chapter.
Page(s)
NA
Removed packaging options to support the elimination of
SnPb lead plating options.
17
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9.
Data Sheet
February 25, 2011
For Additional Information
The IA82510 is a "plug-and-play" drop-in replacement for the original IC. This data sheet
documents all necessary engineering information about the IA82510 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
The Innovasic Support Team is continually planning and creating tools for your use. Visit
http://www.Innovasic.com for up-to-date documentation and software. Our goal is to provide
timely, complete, accurate, useful, and easy-to-understand information. Please feel free to contact
our experts at Innovasic at any time with suggestions, comments, or questions.
Innovasic Support Team
3737 Princeton NE
Suite 130
Albuquerque, NM 87107
(505) 883-5263
Fax: (505) 883-5477
Toll Free: (888) 824-4184
E-mail: [email protected]
Website: http://www.Innovasic.com
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