TI1 LM98555 Ccd driver Datasheet

LM98555
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SNAS290D – DECEMBER 2005 – REVISED APRIL 2013
LM98555 CCD Driver
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FEATURES
DESCRIPTION
•
•
The LM98555 is a highly integrated driver circuit
intended for CCD driving applications. It combines 25
drivers of varying drive strengths into one chip to
provide a complete CCD driving solution. Due to this
one-chip integration, optimal skew control is achieved
for this demanding application.
1
2
•
•
•
•
•
All CCD Drivers Integrated into One Package
High Strength Drivers Designed Specifically
for CCD Loads
Ability to Scale Clock Driver Strength
Skew Specifications Ensured
Separate Input and Output Power Supplies
CMOS Process Technology
64-Pin HTSSOP Package with Extended Power
Handling Capability
KEY SPECIFICATIONS
•
•
•
Supply Voltage
– Inputs 3.0 to 5.5V
– Drivers 4.5 to 5.8V
Maximum Output Skew Between P1A and P2A
Outputs 0.5 ns
Maximum Power Handling 2.0W
Functional Description
VDD1
CPOUT
VDD0
RSOUT
GND1
P2BOUT
GND0
P1AOUT0
P1AOUT1
P2BIN
RSIN
P1AOUT2
CPIN
P1AOUT3
EN0
EN1
DRIVER ENABLE LOGIC (SEE
TRUTH TABLE)
P1AOUT4
P1AOUT5
P1AOUT6
P1AIN
P1AOUT7
P2AIN
PsAOUT0
P2AOUT1
P2AOUT2
SHIN
P2AOUT3
AFEIN
P2AOUT5
SHDIN
P2AOUT6
MCLIN
P2AOUT7
P2AOUT4
MCLOUT
SHOUT0
SHDOUT
SHOUT1
AFEOUT
SHOUT2
NOTE: PRE-DRIVERS NOT SHOWN
Figure 1. Functional Block Diagram
1
2
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM98555
SNAS290D – DECEMBER 2005 – REVISED APRIL 2013
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Connection Diagram
VDDO
1
64
GNDO
CPOUT
2
63
P1AOUT7
RSOUT
3
62
P1AOUT6
GNDO
4
61
GNDO
P2BOUT
5
60
VDDO
SHOUT2
6
59
P1AOUT5
VDDO
7
58
P1AOUT4
P2BIN
8
57
VDDO
RSIN
9
56
GNDO
CPIN
10
55
P1AOUT3
EN0
11
54
P1AOUT2
EN1
12
53
VDDO
GNDI
13
52
GNDO
VDDI
14
51
P1AOUT1
P1AIN
15
50
P1AOUT0
VDDI
16
49
VDDO
GNDI
17
48
GNDO
P2AIN
18
47
P2AOUT0
GNDI
19
46
P2AOUT1
VDDI
20
45
VDDO
SHIN
21
44
GNDO
AFEIN
22
43
P2AOUT2
MCLIN
23
42
P2AOUT3
SHDIN
24
41
GNDO
GNDO
25
40
VDDO
SHOUT0
26
39
P2AOUT4
SHOUT1
27
38
P2AOUT5
SHDOUT
28
37
VDDO
VDDO
29
36
GNDO
MCLOUT
30
35
P2AOUT6
AFEOUT
31
34
P2AOUT7
VDDO
32
33
GNDO
Figure 2. HTSSOP Package
See Package Number DCA0064A
2
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Pin Descriptions
Pin Name
Pin No.
Type
Description
P2BIN
8
Input
CMOS logic input for the P2B driver.
RSIN
9
Input
CMOS logic input for the RS driver.
CPIN
10
Input
CMOS logic input for the CP driver.
P1AIN
15
Input
CMOS logic input for the P1A ganged (8) driver set.
P2AIN
18
Input
CMOS logic input for the P2A ganged (8) driver set.
SHIN
21
Input
CMOS logic input for the SH ganged (3) driver set.
AFEIN
22
Input
CMOS logic input for the AFE driver.
MCLIN
23
Input
CMOS logic input for the MCL driver.
SHDIN
24
Input
CMOS logic input for the SHD driver.
SHDOUT
28
Output; LowStrength
Driver output for the SHDIN input signal.
MCLOUT
30
Output; LowStrength
Driver output for the MCLIN input signal.
AFEOUT
31
Output; LowStrength
Driver output for the AFEIN input signal.
CPOUT
2
Output; LowStrength
Driver output for the CPIN input signal. Typically used to drive the Clamp Gate input of
the CCD.
RSOUT
3
Output; LowStrength
Driver output for the RSIN input signal. Typically used to drive the Reset Gate input of
the CCD.
P2BOUT
5
Output; LowStrength
Driver output for the P2BIN input signal.
P2AOUT0
47
P2AOUT1
46
Output; TRISTATE; HighStrength
Ganged driver outputs for the P2AIN input. Typically the user may join together these
outputs to drive the φ2 clock input of the CCD. Some of these outputs may be disabled
using the EN(1:0) inputs - see Application Information.
P2AOUT2
43
P2AOUT3
42
P2AOUT4
39
P2AOUT5
38
P2AOUT6
35
P2AOUT7
34
P1AOUT0
50
P1AOUT1
51
Output; TRISTATE; HighStrength
Ganged driver outputs for the P1AIN input. Typically the user may join together these
outputs to drive the φ1 clock input of the CCD. Some of these outputs may be disabled
using the EN(1:0) inputs - see Application Information.
P1AOUT2
54
P1AOUT3
55
P1AOUT4
58
P1AOUT5
59
P1AOUT6
62
P1AOUT7
63
SHOUT0
26
SHOUT1
27
Output; LowStrength
Ganged driver outputs for the SHIN input signal. Typically used to drive the Shift Gate
input of the CCD.
SHOUT2
6
Input
Driver enable control. Some of the P1A and P2A drivers can be disabled using these
inputs. See Application Information.
Driver inputs
Driver Outputs
Logic Inputs
EN0
11
EN1
12
Power & Ground Pins
VDDI
14
16
20
Power
VDD for pre-drivers.
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Pin Descriptions (continued)
Pin No.
Type
VDDO
Pin Name
1
7
29
32
37
40
45
49
53
57
60
Power
VDD for final-stage driver.
GNDI
13
17
19
Ground
Ground connection for all circuitry other than the Final-Stage Drivers.
GNDO
4
25
33
36
41
44
48
52
56
61
64
Ground
Ground connection for the Final-Stage Drivers.
4
Description
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
−0.5V to 6.2V
Supply Voltage
Package Power Rating at 25°C (3)
2.0 Watts
−0.5V to VDD+0.5V
Voltage on Any Input or Output Pin
DC Input Current at Any Pin
25 mA
DC Package Input Current
50 mA
−65°C to +150°C
Storage Temperature
Lead temperature (Soldering, 10 sec.)
300°C
Human Body Model
ESD Susceptibility
(1)
(2)
(3)
2000V
Machine Model
200V
Absolute maximum ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the device should be operated at these limits.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Package power rating assumes the exposed thermal pad is soldered to the printed circuit board as recommended, with significant heat
spreading provided by vias to internal or bottom heat dissipation planes or pad. If this is not the case, then the package power rating
should be reduced. See THERMAL GUIDELINES in Application Information for more information.
Operating Conditions
Supply Voltage
VDDI
+3.0V to +5.5V
Supply Voltage
VDDO
+4.5V to +5.8V
Supply Sequencing
(1)
VDDI < VDDO+0.2V
Ambient Temperature (TA)
0 to 70°C
Operating Frequency
30 MHz
Power Dissipation (2)
(1)
(2)
2.0W
When powering up and down, transient voltage levels on VDDI must be lower than (VDDO + 0.2V)
This is the power dissipated on-chip due to all currents flowing through the device - both DC and AC. This operating condition will be
violated if all driver outputs are fully loaded and operating at the same time at the rated FMAX. The system design must constrain the
chip's operating conditions (loads, power supply, number of parallel drivers enabled, frequency of operation) to make certain that this
limit is never exceeded.
Package Thermal Resistances
(1)
Package
θJ-A
64-Lead HTSSOP
36.8°C / W
(1)
θJ-PAD
(Thermal Pad)
6.2°C / W
Package thermal resistance for junction to ambient is based on a 5.5 inch by 3 inch, 4 layer printed circuit board, with thermal vias
connecting the heat sinking pad to a full internal ground plane. Tests were done in still air, with a power dissipation of 2.0 W, at an
ambient temperature of 22°C.
DC Electrical Characteristics
The following specifications apply for GND = 0V, VDDI = 3.3V, VDDO = 5.0V, unless noted otherwise. Boldface limits apply
for TA= TMIN to TMAX; all other limits TA= 25°C
Parameter
II
VIT
ΔVIT
Test Conditions
Min
Typical
Max
Units
Logic 1 Input Current
VI = VDDI
-1
0.004
1
µA
Logic 0 Input Current
VI = GNDI
-1
0.006
1
µA
Input Threshold
VDDI = 3.3V
1.41
1.57
1.75
V
Input Threshold
VDDI = 5.0V
Input Threshold Hysteresis
VDDI = 3.3V
-72
Input Threshold Variation
Between P1A, P2A inputs
-100
2.48
11
V
100
mV
100
mV
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DC Electrical Characteristics (continued)
The following specifications apply for GND = 0V, VDDI = 3.3V, VDDO = 5.0V, unless noted otherwise. Boldface limits apply
for TA= TMIN to TMAX; all other limits TA= 25°C
Parameter
Test Conditions
Min
Typical
Max
Units
6.1
9.9
Ω
10.2
17.4
Ω
ILOAD = 525 mA
Output Impedance P1A and P2A
Outputs
RO
RO = (VDDO - VO)/IOH or
RO = VO/IOL
ILOAD = 280 mA
Output Impedance All Other
Outputs
RO
RO = (VDDO - VO)/IOH or
RO = VO/IOL
AC Electrical Characteristics
The following specifications apply for GND = 0V, VDDI = 3.3V, VDDO = 5.0V, unless noted otherwise. Boldface limits apply
for TA= TMIN to TMAX; all other limits TA= 25°C
Parameter
Test Conditions
Min
Typical
Max
Units
3.06
4.6
6.55
ns
tPHL
Prop Delay: High-to-Low
P1A and P2A Outputs
CL = 220 pF, RL = 10Ω (1)
tPHL
Prop Delay: High-to-Low
CP, RS, P2B Outputs
CL = 82 pF, RL = 10Ω (1)
tPLH
Prop Delay: Low-to-High
P1A and P2A Outputs
CL = 220 pF, RL = 10Ω (3)
tPLH
Prop Delay: Low-to-High
CP, RS, P2B Outputs
CL = 82 pF, RL = 10Ω (3) (2)
4.2
tSKEW
Prop Delay Skew High-to-Low
Between any P1A or P2A Outputs
on a Single Unit
CL = 220 pF, RL = 10Ω
109
387
157
490
Prop Delay Skew Low-to-High
(1)
(2)
(3)
(2)
4.1
3.38
4.9
ns
6.68
ns
ns
ps
Propagation Delay High-to-Low with output low trigger voltage at VDDO*0.75.
Typical values determined from characterization testing only. Not production tested or ensured.
Propagation Delay Low-to-High with output high trigger voltage at VDDO*0.25.
Test Conditions
tR = 0.8 ns
tF = 0.8 ns
90%
VDDI/2
INPUT
90%
VDDI/2
10%
10%
tPHL
tPLH
OUTPUT
0.75 x VDDO
0.25 x VDDO
Figure 3. AC Test Conditions
6
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APPLICATION INFORMATION
The LM98555 is a fully integrated clock driver/buffer for high speed CCD applications. It provides high
performance low impedance drivers, with optimized low skew performance of the P1 and P2 outputs. Enable
inputs allow use of two, four, six, or all eight P1 and P2 drivers to optimize the amount of drive for the application.
The 64 pin thermally enhanced HTSSOP provides excellent power handling through the use of an exposed heat
transfer pad on the underside of the package.
THERMAL GUIDELINES
The LM98555's maximum power dissipation limit, shown in Operating Conditions, must be strictly adhered to.
The product's multiple high-strength drivers, with their ability to drive a wide-range of loads, make it possible to
be within spec on each output and yet violate the aggregate maximum power dissipation limit for the total
product. Special caution must be paid to this by limiting the chip's operating conditions (loads, power supply,
number of parallel drivers enabled, frequency of operation) to make certain that the maximum power dissipation
limit is never exceeded.
Thermal characterization of the device has been done to provide reference points under specific conditions. θ
junction to ambient was measured using a 5.5 inch by 3 inch, 4 layer PCB. The thermal contact pad on the board
was connected using vias to a full ground plane on one of the internal layers. The recommended thermal pad is
shown in Figure 4.
Exposed thermal pad mounting area.
3.81 mm
5.81 mm
Vias are 0.3 mm diameter at 1.2 mm pitch.
Recommended via plating of 1 oz copper.
Figure 4. Exposed Pad Land Pattern
The vias shown provide a path for heat to flow from the pad to a heat sinking or dissipating area of the printed
circuit board. The following figures show several typical examples of how this can be done, and illustrate how
heat is conducted away from the IC to larger areas where it is dissipated.
Vias couple thermal energy to internal ground plane to transfer heat away from package.
Figure 5. 4 Layer PCB - Example 1
Vias couple thermal energy to internal ground planes and heat spreader pad on bottom
layer to transfer heat away from package.
Figure 6. 4 Layer PCB - Example 2
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Vias couple thermal energy to copper plane on bottom layer to transfer heat away from package.
Figure 7. 2 Layer PCB
In multi-layer board applications, one or more internal planes are usually dedicated as a ground plane.
Connecting the thermal pad to this ground plane with vias will usually provide adequate heat management. In 2
layer boards, it is important to provide a large heat spreading pad on the opposite side of the board. The vias will
provide a good thermal connection between the pad under the IC, and the heat spreading pad on the bottom of
the board. Thermal modelling can be done using the θ junction to pad information provided, to calculate the
required area of copper based on the ambient temperature of the system, and the calculated amount of thermal
dissipation in the LM98555.
POWER DISSIPATION
The amount of power dissipated in the device can be determined by considering the following factors:
• Power dissipated delivering energy to the load capacitance
• Power dissipated delivering energy to parasitic capacitance
• Power dissipated due to leakage in the IC
The amount of power dissipated due to leakage is very small in this CMOS device. Most of the power will be due
to the load capacitance being switched, with a small additional amount caused by the parasitic capacitance of the
output circuitry, output pins, and PCB traces. A typical parasitic capacitance would be on the order of 5 pF. Since
the load capacitance will be on the order of 100 pF or more, this usually dominates the power dissipation
calculation. The following equation can be used to calculate the power dissipation due to capacitive switching of
the loads:
P = Sum[Output Frequency x Load Capacitance x Output Voltage Squared] (summed for all outputs)
INPUT SIGNALS
Care should be taken to match the trace lengths between timing signals that require low skew. Usually, the P1A
and P2A signals will be the most critical. In some applications, the timing of P2B with respect to P1A and P2A
can also be important, and that input trace should also be carefully designed.
Trace shape and width should also be carefully controlled. The trace geometry will determine the characteristic
impedance of each trace. The impedance should be set to give reasonable immunity to noise coupling into the
trace. With a known trace impedance, the signals can be terminated using a series resistor at the source that is
equal to the characteristic impedance. This will provide a signal with minimum overshoot and ringing, and will
contribute to better performance of the final signal reaching the CCD.
OUTPUT CONNECTIONS AND LOADING EXAMPLES
The LM98555 can be used with a wide variety of different CCD sensors. The P1Aoutx and P2Aoutx outputs can
be selectively enabled to provide 2, 4, 6, or 8 drivers. This allows the available drive strength to be optimized for
the sensor and application. Connecting multiple outputs together in parallel as shown in the typical application
circuit provides lower drive impedance as needed to suit the load being driven. When driving smaller loads, lower
switching noise will be generated if the minimum necessary outputs are enabled and used.
The output signal traces should also be designed for a known impedance. Source terminating resistors should be
used in series with each output to provide good matching to the trace characteristic impedance. The resistors
should be located as close as possible to each output pin. If multiple outputs will be combined to drive a single
load pin, the output signals should be combined after the termination resistors. This will provide the best
summing of adjacent outputs. The combined signal should then pass through an EMI type ferrite bead. This
component can be selected to change the bandwidth or shape of the clocking signal to achieve the best CCD
transfer efficiency.
8
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Several other techniques will also help maintain signal quality, and minimize timing differences between critical
signals. Vias should not be used for critical timing signals. These can add impedance discontinuities that will
affect the waveform quality. Traces should have gradual bends and avoid sharp changes in direction that can
also introduce impedance discontinuities.
SELECTIVE DRIVER ENABLING
With the Enable pins, the user has the capability to enable only the drivers that are required for the application,
thus eliminating unnecessary outputs switching. The following table shows the details.
EN1
EN0
Driver-set State
0
0
P1Aout(1:0) and P2Aout(1:0) are enabled; all others disabled.
0
1
P1Aout(3:0) and P2Aout(3:0) are enabled; all others disabled.
1
0
P1Aout(5:0) and P2Aout(5:0) are enabled; all others disabled.
1
1
All P1Aout and P2Aout drivers are enabled.
Note: The disabled drivers' outputs are in TRI-STATE.
POWER SUPPLY SEQUENCING
During device power-up and power-down, VDDI must be maintained less than (VDDO + 0.2V) to prevent excessive
current flow through the internal ESD protection circuitry. Since most applications will involve 3V on VDDI and 5V
on VDDO, this can be easily met. If this voltage relationship cannot be met, then the DC pin and package limits for
input current must be maintained by controlling the source impedance of the VDDI supply.
POWER AND GROUND - PLANES VERSUS BUSES
The best performance will be achieved by using planes rather than traces for power and ground. Planes provide
lower electrical and thermal impedance. Ground bounce and ringing are reduced, electromagnetic emissions are
minimized and the best thermal performance will be realized.
A single common ground plane should be used for all power and signal domains.
Another circuit board layer can be used to provide power to the various circuitry. Different power buses can be
provided by isolated planes within this layer of the circuit board.
EMI MANAGEMENT
Good EMI control will be achieved by addressing the following items:
• Provide proper source termination of output signals
• Limit length of output traces
• Ensure adequate power supply decoupling
• Provide power and ground planes as much as possible
• Provide common ground plane for all signals, especially between LM98555 outputs and load CCD
• Enable and use the minimum number of outputs needed
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
10
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
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8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM98555CCMH/NOPB
ACTIVE
HTSSOP
DCA
64
28
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-4-260C-72 HR
0 to 70
LM98555
CCMH
LM98555CCMHX/NOPB
ACTIVE
HTSSOP
DCA
64
1000
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-4-260C-72 HR
0 to 70
LM98555
CCMH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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Addendum-Page 2
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