LINER LTM4613 10a step-down dc/dc î¼module regulator Datasheet

LTM4649
10A Step-Down DC/DC
µModule Regulator
FEATURES
DESCRIPTION
10A DC Output Current
nn Input Voltage Range: 4.5V to 16V
nn Output Voltage Range: 0.6V Up to 3.3V
nn No Heat Sink or Current Derating Up to 85°C Ambient Temperature
nn ±1.5% Total DC Voltage Output Error
nn Multiphase Operation with Current Sharing
nn Remote Sense Amplifier
nn Built-In General Purpose Temperature Monitor
nn Selectable Pulse-Skipping Mode/Burst Mode® Operation for High Efficiency at Light Load
nn Soft-Start/Voltage Tracking
nn Protection: Output Overvoltage and Overcurrent
Foldback
nn 9mm × 15mm × 4.92mm BGA Package
The LTM®4649 is a complete 10A high efficiency switching
mode step-down DC/DC µModule® regulator in a 9mm ×
15mm × 4.92 BGA package. Included in the package are the
switching controller, power FETs, inductor, and all support
components. Operating over an input voltage range of 4.5V
to 16V, the LTM4649 supports an output voltage range of
0.6V to 3.3V, set by a single external resistor. This high
efficiency design delivers 10A continuous current. Only
bulk input and output capacitors are needed.
APPLICATIONS
Fault protection features include output overvoltage and
overcurrent protection. The LTM4649 is offered in a small
9mm × 15mm × 4.92mm BGA package available with SnPb
or RoHS compliant terminal finish.
nn
nn
nn
High switching frequency and a current mode architecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, programmable multiphase
operation, and output voltage tracking for supply rail
sequencing.
Telecom, Networking and Industrial Equipment
Point of Load Regulation
L, LT, LTC, LTM, Burst Mode, µModule, PolyPhase, Linear Technology and the Linear logo
are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678,
6144194, 6177787, 6304066, 6580258 and 8163643. Other patents pending.
TYPICAL APPLICATION
4.5V to 16V Input, 1.5V Output DC/DC
µModule Regulator
VIN
INTVCC
VOUT_LCL
SW
DIFFOUT
RUN
MODE
LTM4649
PHMODE
TRACK/SS
TEMP
GND
0.1µF
100µF
6.3V
×2
DIFFP
DIFFN
VFB
COMP
6.65k
PGOOD
CLKOUT
VOUT
1.5V
10A
95
3.0
12
90
2.5
10
85
2.0
80
1.5
75
1.0
70
4649 TA01a
65
VIN = 12V
VIN = 5V
0
2
4
6
LOAD CURRENT (A)
10
8
4649 TA01b
POWER LOSS (W)
22µF
16V
×2
FREQ
VOUT
Current Derating: 12V Input,
1.5VOUT, No Heat Sink
LOAD CURRENT (A)
CLKIN
EFFICIENCY (%)
VIN
4.5V TO 16V
Efficiency and Power Loss
at 12V and 5V Input
8
6
4
0.5
2
0
0
400LFM
200LFM
0LFM
0
40
60
80
100
20
AMBIENT TEMPERATURE (°C)
120
4649 TA01c
4649fc
For more information www.linear.com/LTM4649
1
LTM4649
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VIN.............................................................. –0.3V to 18V
VOUT........................................................... –0.3V to 3.6V
INTVCC, PGOOD, RUN................................... –0.3V to 6V
MODE, CLKIN, TRACK/SS, DIFFP, DIFFN,
DIFFOUT, PHMODE................................ –0.3V to INTVCC
VFB............................................................. –0.3V to 2.7V
COMP (Note 3)........................................... –0.3V to 2.7V
INTVCC Peak Output Current.................................100mA
Internal Operating Temperature Range
(Note 2)................................................... –55°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Solder Reflow Package Body Temperature.... 245°C
A
B
GND
1
CLKIN
PHMODE
MODE
F
G
RUN
GND
VIN
CLKOUT
2
NC
FREQ
3
INTVCC
4
TRACK/SS
5
TEMP 6
PGOOD
TOP VIEW
C D
E
NC
COMP
SW
VFB
DIFFN
7
8
DIFFP
DIFFOUT
9
VOUT_LCL
10
11
VOUT
GND
BGA PACKAGE
68-LEAD (9mm × 15mm × 4.92mm)
TJMAX = 125°C, θJA = 14°C/W, θJCbottom = 5°C/W, θJCtop = 20°C/W
θJB + θBA = 14°C/W, WEIGHT = 1.7g
ORDER INFORMATION
PART NUMBER
PAD OR BALL FINISH
LTM4649EY#PBF
SAC305 (RoHS)
http://www.linear.com/product/LTM4649#orderinfo
PART MARKING*
DEVICE
FINISH CODE
PACKAGE
TYPE
LTM4649Y
e1
BGA
MSL
RATING
3
TEMPERATURE RANGE
(Note 2)
–40°C to 125°C
LTM4649IY#PBF
SAC305 (RoHS)
LTM4649Y
e1
BGA
3
–40°C to 125°C
LTM4649IY
SnPb (63/37)
LTM4649Y
e0
BGA
3
–40°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Pb-free and Non-Pb-free Part Markings:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
4649fc
2
For more information www.linear.com/LTM4649
LTM4649
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V per typical application.
SYMBOL
PARAMETER
VIN
Input DC Voltage
CONDITIONS
l
4.5
16
V
VOUT(RANGE)
Output Voltage Range
l
0.6
3.3
V
VOUT(DC)
Output Voltage, Total Variation with
Line and Load
l
1.477
1.50
1.523
V
1.1
1.25
1.4
V
CIN = 10µF × 1,COUT = 100µF Ceramic,
100µF POSCAP, RFB = 6.65k, MODE = GND,
VIN = 4.5V to 16V, IOUT = 0A to 10A
MIN
TYP
MAX
UNITS
Input Specifications
VRUN
RUN Pin On Threshold
VRUN(HYS)
RUN Pin On Hysteresis
IQ(VIN)
Input Supply Bias Current
IS(VIN)
Input Supply Current
VRUN Rising
150
mV
VIN = 12V, VOUT = 1.5V, Burst Mode Operation
VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode
VIN = 12V, VOUT = 1.5V, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
5
15
75
70
mA
mA
mA
µA
VIN = 12V, VOUT = 1.5V, IOUT = 10A
1.5
A
Output Specifications
IOUT(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 1.5V (Note 4)
ΔVOUT(LINE)
VOUT
Line Regulation Accuracy
VOUT = 1.5V, VIN from 4.5V to 16V IOUT = 0A
l
0
0.010
0.04
10
%/V
ΔVOUT(LOAD)
VOUT
Load Regulation Accuracy
VOUT = 1.5V, IOUT = 0A to 10A, VIN = 12V
(Note 4)
l
0.15
0.5
%
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF Ceramic, 100µF
POSCAP, VIN = 12V, VOUT = 1.5V
15
mV
ΔVOUT(START)
Turn-On Overshoot
COUT = 100µF Ceramic, 100µF POSCAP,
VOUT = 1.5V, IOUT = 0A, VIN = 12V
20
mV
tSTART
Turn-On Time
COUT = 100µF Ceramic, 100µF POSCAP,
No Load, TRACK/SS = 0.01µF, VIN = 12V
5
ms
ΔVOUTLS
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load,
COUT = 100µF Ceramic, 100µF POSCAP,
VIN = 12V, VOUT = 1.5V
60
mV
tSETTLE
Settling Time for Dynamic Load Step
Load: 0% to 50% to 0% of Full Load,
COUT = 100µF Ceramic, 100µF POSCAP,
VIN = 12V, VOUT=1.5V
20
µs
IOUTPK
Output Current Limit
VIN = 12V, VOUT = 1.5V (Note 4)
12
A
A
Control Specifications
VFB
Voltage at VFB Pin
IOUT = 0A, VOUT = 1.5V
(Note 3)
IFB
Current at VFB Pin
VOVL
Feedback Overvoltage Lockout
ITRACK/SS
Track Pin Soft-Start Pull-Up Current
TRACK/SS = 0V
tON(MIN)
Minimum On-Time
(Note 3)
RFBHI
Resistor Between VOUT_LCL and VFB
Pins
DIFFP, DIFFN CM
RANGE
Common Mode Input Range
VIN = 12V, Run > 1.4V
VDIFFOUT(MAX)
Maximum DIFFOUT Voltage
IDIFFOUT = 300µA
VOS
Input Offset Voltage
VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA
AV
Differential Gain
(Note 3)
l
0.593
0.60
0.607
V
l
0.64
–12
–25
nA
0.66
0.68
V
1.0
1.2
1.4
µA
10.10
kΩ
90
9.90
10
0
ns
3.6
INTVCC-1.4
V
V
4
1
mV
V/V
4649fc
For more information www.linear.com/LTM4649
3
LTM4649
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V per typical application.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SR
Slew Rate
(Note 5)
2
V/µs
GBP
Gain Bandwidth Product
(Note 5)
3
MHz
CMRR
Common Mode Rejection
(Note 3)
IDIFFOUT
DIFFOUT Current
Sourcing
60
dB
RIN
Input Resistance
DIFFP, DIFFN to GND
80
kΩ
VPGOOD
PGOOD Trip Level
VFB With Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
–10
10
%
%
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
0.1
0.3
V
5
5.2
V
2
mA
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
VINTVCC Load Reg INTVCC Load Regulation
4.8
ICC = 0mA to 50mA
0.9
%
Oscillator and Phase-Locked Loop
fSYNC
Frequency Sync Capture Range
250
fS
Nominal Switching Frequency
400
RMODE
MODE Input Resistance
VIH_CLKIN
Clock Input Level High
VIL_CLKIN
Clock Input Level Low
450
800
kHz
500
kHz
250
kΩ
2.0
V
0.8
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Notes are automatically numbered when you apply
the note style.
Note 2: The LTM4649 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4649E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4649I is guaranteed to meet specifications over the
–40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
V
Note 3: 100% tested at wafer level.
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: Guaranteed by design.
4649fc
4
For more information www.linear.com/LTM4649
LTM4649
TYPICAL PERFORMANCE CHARACTERISTICS
100
95
95
90
90
85
80
VOUT = 1V, 450kHz
VOUT = 1.2V, 450kHz
VOUT = 1.5V, 450kHz
VOUT = 2.5V, 750kHz
VOUT = 3.3V, 750kHz
70
65
0
2
4
6
90
85
80
VOUT = 1V, 450kHz
VOUT = 1.2V, 450kHz
VOUT = 1.5V, 450kHz
VOUT = 2.5V, 450kHz
VOUT = 3.3V, 450kHz
70
65
VIN = 12V
VOUT = 1.5V
80
75
10
8
100
EFFICIENCY (%)
100
75
CCM, Burst Mode and PulseSkipping Mode Efficiency
5VIN Efficiency
EFFICIENCY (%)
EFFICIENCY (%)
12VIN Efficiency
0
2
4
6
60
50
40
30
10
0
0.01
LOAD CURRENT (A)
LOAD CURRENT (A)
12VIN, 1VOUT Load Transient
5VIN, 1VOUT Load Transient
0.1
1
LOAD CURRENT (A)
10
4649 G03
4649 G02
4649 G01
CCM
PULSESKIPPPING
Burst Mode
OPERATION
20
10
8
70
5VIN, 1.5VOUT Load Transient
IOUT
5A/DIV
AC
IOUT
5A/DIV
AC
IOUT
5A/DIV
AC
VOUT
100mV/DIV
AC
VOUT
100mV/DIV
AC
VOUT
100mV/DIV
AC
4649 G04
50µs/DIV
5VIN, 1VOUT, 5A TO 10A LOAD STEP
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
NO CFF CAPACITOR
4649 G05
50µs/DIV
12VIN, 1VOUT, 5A TO 10A LOAD STEP
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
NO CFF CAPACITOR
4649 G06
50µs/DIV
5VIN, 1.5VOUT, 5A TO 10A LOAD STEP
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
NO CFF CAPACITOR
12VIN, 1.5VOUT Load Transient
5VIN, 2.5VOUT Load Transient
12VIN, 2.5VOUT Load Transient
IOUT
5A/DIV
AC
IOUT
5A/DIV
AC
IOUT
5A/DIV
AC
VOUT
100mV/DIV
AC
VOUT
100mV/DIV
AC
VOUT
100mV/DIV
AC
4649 G07
50µs/DIV
12VIN, 1.5VOUT, 5A TO 10A LOAD STEP
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
NO CFF CAPACITOR
4649 G08
50µs/DIV
5VIN, 2.5VOUT, 5A TO 10A LOAD STEP
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
NO CFF CAPACITOR
4649 G09
50µs/DIV
12VIN, 2.5VOUT, 5A TO 10A LOAD STEP, 750kHz
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
NO CFF CAPACITOR
4649fc
For more information www.linear.com/LTM4649
5
LTM4649
TYPICAL PERFORMANCE CHARACTERISTICS
5VIN, 3.3VOUT Load Transient
12VIN, 3.3VOUT Load Transient
IOUT
5A/DIV
AC
IOUT
5A/DIV
AC
VOUT
100mV/DIV
AC
VOUT
100mV/DIV
AC
Soft-Start with No Load
IIN
1A/DIV
VOUT
0.5V/DIV
VSW
10V/DIV
4649 G10
50µs/DIV
5VIN, 3.3VOUT, 5A TO 10A LOAD STEP
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
NO CFF CAPACITOR
4649 G11
50µs/DIV
12VIN, 3.3VOUT, 5A TO 10A LOAD STEP, 750kHz
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
NO CFF CAPACITOR
12VIN, 1.5VOUT
IO = 0A START-UP
CSS = 0.1µF
Soft-Start with Full Load
Short-Circuit Protection
with No Load
Short-Circuit Protection
with Full Load
IIN
1A/DIV
VOUT
0.5V/DIV
VSW
10V/DIV
20ms/DIV
12VIN, 1.5VOUT
IO = 10A START-UP
CSS = 0.1µF
4649 G13
20ms/DIV
IIN
1A/DIV
VOUT
0.5V/DIV
IIN
1A/DIV
VOUT
1V/DIV
VSW
10V/DIV
VSW
10V/DIV
4649 G14
20µs/DIV
12VIN, 1.5VOUT
SHORT CIRCUIT WITH NO LOAD
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
4649 G12
4649 G15
20µs/DIV
12VIN, 1.5VOUT
SHORT CIRCUIT WITH FULL LOAD
COUT = 2 • 220µF 4V CERAMIC CAPACITOR
4649fc
6
For more information www.linear.com/LTM4649
LTM4649
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
PGOOD (C7): Output Voltage Power Good Indicator. Opendrain logic output that is pulled to ground when the output
voltage is not within ±10% of the regulation point.
GND (A1-A5, A7-A11, B1, B9-B11, E1, F3, F5, G1-G7):
Ground Pins for Both Input and Output Returns. All ground
pins need to connect with large copper areas underneath
the unit.
VOUT_LCL (G9): This pin is connected to the top of the
internal top feedback resistor for the output. When the
remote sense amplifier is used, connect the remote sense
amplifier output DIFFOUT to VOUT_LCL to drive the 10k top
feedback resistor. When the remote sense amplifier is not
used, connect VOUT_LCL to VOUT directly.
TEMP (A6): Onboard Temperature Diode for Monitoring
the VBE Junction Voltage Change with Temperature. See
the Applications Information section.
CLKIN (B3): External Synchronization Input to Phase Detector Pin. A clock on this pin will enable synchronization
with forced continuous operation. See the Applications
Information section.
PHMODE (B4): This pin can be tied to GND, tied to INTVCC
or left floating. This pin determines the relative phases
between the internal controllers and the phasing of the
CLKOUT signal. See Table 2 in the Operation section.
MODE (B5): Mode Select Input. Connect this pin to
INTVCC to enable Burst Mode operation. Connect to ground
to enable forced continuous mode of operation. Floating
this pin will enable pulse-skipping mode.
NC (B7-B8, C3-C4): No Connection Pins. Either float these
pins or connect them to GND for thermal purpose.
VIN (C1, C8, C9, D1, D3-D5, D7-D9 and E8): Power Input
Pins. Apply input voltage between these pins and GND
pins. Recommend placing input decoupling capacitance
directly between VIN pins and GND pins.
VOUT (C10-C11, D10-D11, E9-E11, F9-F11, G10-G11):
Power Output Pins. Apply output load between these pins
and GND pins. Recommend placing output decoupling
capacitance directly between these pins and GND pins.
SW (C5): Switching Node of the Circuit. This pin is used
to check the switching frequency. Leave pin floating. A
resistor-capacitor snubber can be placed from SW to GND
to eliminate high frequency switch node ringing. See the
Applications Information section.
FREQ (E3): Frequency Set Pin. A 10µA current is sourced
from this pin. A resistor from this pin to ground sets a
voltage, that in turn, programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage that
can set the operating frequency. See the Applications Information section. The LTM4649 has an internal resistor
to program the frequency to 450kHz.
TRACK/SS (E5): Output Voltage Tracking Pin and SoftStart Inputs. The pin has a 1.2µA pull-up current source.
A capacitor from this pin to ground will set a soft-start
ramp rate. In tracking, the regulator output can be tracked
to a different voltage. The different voltage is applied to
a voltage divider then the slave output’s track pin. This
voltage divider is equal to the slave output’s feedback
divider for coincidental tracking. See the Applications
Information section.
VFB (E7): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT_LCL with a 10k precision
resistor. Different output voltages can be programmed
with an additional resistor between VFB and ground pins.
In PolyPhase operation, tying the VFB pins together allows
for parallel operation. See the Applications Information
section for details.
RUN (F1): Run Control Pin. A voltage above 1.25V will turn
on the module. The RUN pin has a 1µA pull-up current,
and then once the RUN pin reaches 1.2V an additional
4.5µA pull-up current is added to this pin.
4649fc
For more information www.linear.com/LTM4649
7
LTM4649
PIN FUNCTIONS
CLKOUT (F2): Output Clock Signal for PolyPhase Operation. The phase of CLKOUT is determined by the state of
the PHMODE pin.
DIFFN (F7): Input to the Remote Sense Amplifier. This pin
connects to the ground remote sense point. Connect to
ground when not used.
INTVCC (F4): Internal 5V LDO for Driving the Control Circuitry and the Power MOSFET Drivers. The 5V LDO has
an absolute maximum 100mA peak current limit.
DIFFP (F8): Input to the Remote Sense Amplifier. This
pin connects to the output remote sense point. Connect
to ground when not used.
COMP (F6): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. Tie all COMP pins
together in parallel operation.
DIFFOUT (G8): Output of the Remote Sense Amplifier.
This pin connects to the VOUT_LCL pin for remote sense
applications. Otherwise float when not used.
4649fc
8
For more information www.linear.com/LTM4649
LTM4649
BLOCK DIAGRAM
INTVCC
VOUT_LCL
1M
VIN
VIN
RUN
1µF
CLKOUT
VIN
4.5V TO 16V
+
CIN
COMP
10k
SW
M1
INTERNAL
COMP
0.35µH
GND
POWER
CONTROL
VFB
FREQ
6.65k
RfSET
115k
VOUT
COUT
M2
+
VOUT
1.5V
10A
GND
INTERNAL
LOOP
FILTER
PHMODE
TRACK/SS
INTVCC
CLKIN
MODE
DIFF
AMP
–
250k
+
CSS
+
R2
> 1.4V = ON
< 1.1V = OFF
MAX = 6V
10k
PGOOD
–
R1
VOUT
DIFFN
DIFFP
DIFFOUT
INTVCC
TEMP
1µF
4649 F01
Figure 1. Simplified LTM4649 Block Diagram
4649fc
For more information www.linear.com/LTM4649
9
LTM4649
OPERATION
Power Module Description
The LTM4649 is a high performance single output standalone nonisolated switching mode DC/DC power supply.
It can provide up to 10A output current with few external input and output capacitors. This module provides
precisely regulated output voltage programmable via
an external resistor from 0.6VDC to 3.3VDC over a 4.5V
to 16V input range. The typical application schematic is
shown in Figure 17.
The LTM4649 has an integrated constant-frequency current mode regulator, power MOSFETs, inductor, and other
supporting discrete components. The typical switching
frequency is 450kHz. For switching noise-sensitive applications, it can be externally synchronized from 400kHz
to 800kHz. See the Applications Information section.
With current mode control and internal feedback loop
compensation, the LTM4649 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, especially with all ceramic
output capacitors.
Current mode control provides cycle-by-cycle fast current
limit in an overcurrent condition. An internal overvoltage
monitor protects the output voltage in the event of an
overvoltage >10%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
Pulling the RUN pin below 1.1V forces the regulator into a
shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking during
start-up. See the Application Information section.
The LTM4649 is internally compensated to be stable over
all operating conditions. Table 3 provides a guideline for
input and output capacitances for several operating conditions. LTpowerCAD™ is available for transient and stability
analysis. The VFB pin is used to program the output voltage
with a single external resistor to ground.
A remote sense amplifier is provided in the LTM4649 for
accurately sensing output voltages ≤3.3V at the load point.
Multiphase operation can be easily employed with the
synchronization inputs using an external clock source.
See application examples.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE pin. These
light load features will accommodate battery operation.
Efficiency graphs are provided for light load operation in
the Typical Performance Characteristics section.
A TEMP pin is provided to allow the internal device temperature to be monitored using an onboard diode connected
PNP transistor. This diode connected PNP transistor is
grounded in the module and can be used as a general
temperature monitor using a device that is designed to
monitor the single-ended connection.
The switching node pin is available for functional operation monitoring. A resistor-capacitor snubber circuit can
be carefully placed from the switching node pin to ground
to dampen any high frequency ringing on the transition
edges. See the Applications Information section for details.
4649fc
10
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
The typical LTM4649 application circuit is shown in
Figure 17. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 3 for specific external capacitor
requirements for particular applications.
VIN to VOUT Step-Down Ratios
There are restrictions in the VIN to VOUT step-down ratio
that can be achieved for a given input voltage. The VIN to
VOUT minimum dropout is a function of load current and
at very low input voltage and high duty cycle applications
output power may be limited as the internal top power
MOSFET is not rated for 10A operation at higher ambient
temperatures. At very low duty cycles a minimum 110ns
on-time should be maintained. See the Frequency Adjustment section and temperature derating curves.
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 10k internal feedback
resistor connects the VOUT_LCL and VFB pins together.
When the remote sense amplifier is used, then DIFFOUT
is connected to the VOUT_LCL pin. If the remote sense
amplifier is not used, then VOUT_LCL connects to VOUT. The
output voltage will default to 0.6V with no feedback resistor. Adding a resistor RFB from VFB to ground programs
the output voltage:
VOUT
VOUT(V)
0.6
1.0
1.2
1.5
1.8
2.5
3.3
OPEN
15
10
6.65
4.99
3.16
2.21
For parallel operation of N LTM4649, the following equation can be used to solve for RFB:
RFB =
Input Capacitors
The LTM4649 module should be connected to a low AC
impedance DC source. Additional input capacitors are
needed for the RMS input ripple current rating. The ICIN(RMS)
equation which follows can be used to calculate the input
capacitor requirement. Typically 22µF X7R ceramics are a
good choice with RMS ripple current ratings of ~2A each.
A 47µF to 100µF surface mount aluminum electrolytic bulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedance is compromised by long inductive leads, traces
or not enough source capacitance. If low impedance power
planes are used, then this bulk capacitor is not needed.
For a buck converter, the switching duty cycle can be
estimated as:
D=
VOUT
VIN
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN(RMS) =
10k +RFB
= 0.6V •
RFB
Table 1. VFB Resistor Table vs Various Output Voltages
RFB(k)
error due to this current, an additional VOUT_LCL pin can
be tied to VOUT, and an additional RFB resistor can be used
to lower the total Thevenin equivalent resistance seen by
this current.
10k
N
VOUT
–1
0.6
In parallel operation the VFB pins have an IFB current of
25nA maximum each channel. To reduce output voltage
IOUT(MAX)
η%
• D • (1−D)
In the previous equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcher-rated
aluminum electrolytic capacitor or a polymer capacitor.
Output Capacitors
The LTM4649 is designed for low output voltage ripple
noise. The bulk output capacitors defined as COUT are
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, low
ESR Polymer capacitor or ceramic capacitors. The typical
output capacitance range is from 200µF to 470µF. Additional
output filtering may be required by the system designer
if further reduction of output ripple or dynamic transient
4649fc
For more information www.linear.com/LTM4649
11
LTM4649
APPLICATIONS INFORMATION
spikes is required. Table 3 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to optimize the transient performance. Stability criteria
are considered in the Table 3 matrix, and LTpowerCAD is
available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
a function of stability and transient response. LTpowerCAD
can calculate the output ripple reduction as the number of
implemented phase’s increases by N times.
Burst Mode Operation
The LTM4649 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enable Burst Mode operation, simply tie the MODE pin to
INTVCC. During Burst Mode operation, the peak current
of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though
the voltage at the COMP pin indicates a lower value. The
voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the
COMP voltage drops below 0.5V, the burst comparator
trips, causing the internal sleep line to go high and turn
off both power MOSFETs.
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMP to rise, the internal
sleep line goes low, and the LTM4649 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency
at intermediate currents are desired, pulse-skipping mode
should be used. Pulse-skipping operation allows the
LTM4649 to skip cycles at low output loads, thus increasing
efficiency by reducing switching loss. Floating the MODE
pin enables pulse-skipping operation. With pulse-skipping
mode at light load, the internal current comparator may
remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode
operation and maintains a higher frequency operation than
Burst Mode operation.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE pin to ground. In this mode,
inductor current is allowed to reverse during low output
loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4649’s output
voltage is in regulation.
Frequency Selection
The LTM4649 device is internally programmed to 450kHz
switching frequency to improve power conversion efficiency. It is recommended for all applications with low
VIN or low VOUT. For applications with high VIN (VIN ≥
12V) and high VOUT (VOUT ≥ 1.8V), 750kHz is the recommended operating frequency to limit inductor ripple
current. Simply tie FREQ to INTVCC. Table 3 lists different
frequency and FREQ pin recommendations for different
VIN, VOUT conditions.
If desired, a resistor can be connected from the FREQ pin
to INTVCC to adjust the FREQ pin DC voltage to increase the
switching frequency between the default 450kHz and the
maximum 750kHz. Figure 2 shows a graph of frequency
versus FREQ pin DC voltage. Figure 18 shows an example
where the frequency is programmed to 650kHz. Please be
aware the FREQ pin has an internal 10µA current sourced
from this pin when calculating the resistor value.
4649fc
12
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
Multiphase Operation
900
800
For outputs that demand more than 10A of load current,
multiple LTM4649 devices can be paralleled to provide
more output current and reduced input and output voltage ripple.
FREQUENCY (kHz)
700
600
500
400
The CLKOUT signal together with CLKIN pin can be used
to cascade additional power stages to achieve a multiphase
power supply solution. Tying the PHMODE pin to INTVCC,
GND, or leaving it floating generates a phase difference
(between CLKIN and CLKOUT) of 180°, 120°, or 90°
respectively as shown in Table 2. A total of 4 phases can
be cascaded to run simultaneously with respect to each
other by programming the PHMODE pin of each LTM4649
channel to different levels. Figure 3 shows a 3-phase design and 4-phase design example for clock phasing with
the PHMODE table.
300
200
100
0
0
0.5
1
1.5
2
FREQ PIN VOLTAGE (V)
2.5
4649 F02
Figure 2. Operating Frequency vs FREQ Pin Voltage
PLL and Frequency Synchronization
The LTM4649 device operates over a range of frequencies to improve power conversion efficiency. The nominal
switching frequency is 450kHz. It can also be synchronized
from 400kHz to 800kHz with an input clock that has a high
level above 2V and a low level below 0.8V at the CLKIN pin.
Once the LTM4649 is synchronizing to an external clock
frequency, it will always be running in Forced Continuous
operation. Although synchronization to 250kHz is possible,
400kHz is the lowest recommended operating frequency
to limit inductor ripple current.
Table 2. PHMODE and CLKOUT Signal Relationship
PHMODE
GND
FLOAT
INTVCC
CLKOUT
120°
90°
180°
The LTM4649 device is an inherently current mode controlled device, so parallel modules will have good current
sharing. This will balance the thermals in the design. Tie
the COMP, VFB, TRACK/SS and RUN pins of each LTM4649
together to share the current evenly. Figures 19 and 20
each show a schematic of a parallel design.
3-PHASE DESIGN
120 DEGREE
120 DEGREE
CLKOUT
0 PHASE
GND
CLKOUT
CLKIN
120 PHASE
VOUT
GND
PHMODE
CLKOUT
CLKIN
240 PHASE
VOUT
GND
PHMODE
CLKIN
VOUT
PHMODE
4-PHASE DESIGN
CLKOUT
0 PHASE
FLOAT
CLKIN
VOUT
PHMODE
90 DEGREE
90 PHASE
FLOAT
CLKOUT
CLKIN
VOUT
PHMODE
90 DEGREE
180 PHASE
FLOAT
CLKOUT
90 DEGREE
CLKIN
VOUT
PHMODE
270 PHASE
FLOAT
CLKOUT
CLKIN
VOUT
PHMODE
4649 F03
Figure 3. Examples of 3-Phase, 4-Phase Operation with PHMODE Table
4649fc
For more information www.linear.com/LTM4649
13
LTM4649
APPLICATIONS INFORMATION
A multiphase power supply could significantly reduce
the amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage
is greater than the number of phases used times the output
voltage). The output ripple amplitude is also reduced by
the number of phases used.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases
(see Figure 4).
Minimum On-Time
Minimum on-time tON is the smallest time duration that
the LTM4649 is capable of turning on the top MOSFET.
0.60
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
VOUT
> tON(MIN)
VIN • FREQ
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple and current will increase. The minimum on-time can be increased by lowering the switching
frequency. A good rule of thumb is to assume a 110ns
minimum on-time.
Soft-Start
The TRACK/SS pin of the master can be controlled by a
capacitor placed from the master regulator TRACK/SS pin to
ground. A 1.2µA current source will charge the TRACK/SS
pin up to the reference voltage and then proceed up to
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VO/VIN)
4649 F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
4649fc
14
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
INTVCC. After ramping to 0.6V, the TRACK/SS pin will no
longer be in control, and the internal voltage reference
will control output regulation from the feedback divider.
Foldback current limit is disabled during this sequence of
turn-on during tracking or soft-starting. The TRACK/SS
pin is pulled low when the RUN pin is below 1.2V. The
total soft-start time can be calculated as:
as soon as VFB is below 0.54V regardless of the setting
on the MODE pin.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4649 uses an
accurate 10k resistor internally for the top feedback resistor. Figure 6 shows the coincident tracking characteristic.
 C 
tSS =  SS  • 0.6V
 1.2µA 
Regardless of the mode selected by the MODE pin, the
regulator will always start in pulse-skipping mode up to
TRACK/SS = 0.5V. Between TRACK/SS = 0.5V and 0.54V,
it will operate in forced continuous mode and revert to the
selected mode once TRACK/SS > 0.54V. In order to track
with another regulator once in steady state operation,
the LTM4649 is forced into continuous mode operation
VIN
C7
22µF
16V
C10
22µF
16V
SOFT-START
CAPACITOR
CSS
R2
10k
VIN
 10k 
VSLAVE = 1+
 • VTRACK
 RTA 
VTRACK is the track ramp applied to the slave’s track pin.
VTRACK has a control range of 0V to 0.6V, or the internal
reference voltage. When the master’s output is divided
INTVCC
C3
22µF
16V
C2
MASTER RAMP
22µF
OR OUTPUT
16V
R1
10k
C11
100µF
6.3V
×2
VOUT_LCL
TRACK/SS
LTM4649
DIFFOUT
RUN
FREQ
DIFFP
MODE
DIFFN
GND
VIN
PGOOD
VOUT
COMP
RTA
10k
RTB
10k
VIN
INTVCC
RUN
RFB1
6.65k
PGOOD
VOUT
COMP
TRACK/SS
VFB
LTM4649
DIFFOUT
DIFFP
MODE
DIFFN
GND
C6
100µF
6.3V
×2
VOUT_LCL
FREQ
VFB
VOUT2
1.5V
10A
VOUT1
1.2V
10A
4649 F05
RFB
10k
Figure 5. Dual Outputs (1.5V and 1.2V) with Tracking
4649fc
For more information www.linear.com/LTM4649
15
LTM4649
APPLICATIONS INFORMATION
OUTPUT VOLTAGE (V)
MASTER OUTPUT
SLAVE OUTPUT
TIME
4649 F06
Figure 6. Output Coincident Tracking Characteristic
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
tracking is disabled when VTRACK is more than 0.6V. RTA
in Figure 5 will be equal to RFB for coincident tracking.
Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the master’s TRACK/SS pin. As mentioned above, the TRACK/SS
pin has a control range from 0V to 0.6V. The master’s
TRACK/SS pin slew rate is directly equal to the master’s
output slew rate in Volts/Time. The equation for RTB:
MR
• 10k = RTB
SR
Each of the TRACK/SS pins will have the 1.3µA current
source on when a resistive divider is used to implement
tracking on that specific channel. This will impose an offset
on the TRACK/SS pin input. Smaller value resistors with
the same ratios as the resistor values calculated from the
previous equations can be used. For example, where the
10k value is calculated then a 1.0k can be used to reduce
the TRACK/SS pin offset to a negligible value.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point. A pull-up
resistor can be connected from PGOOD to a supply voltage no greater than 6V.
Stability Compensation
The module has already been internally compensated for
all output voltages. Table 3 is provided for most application
requirements. LTpowerCAD is available for other control
loop optimization.
Run Enable
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus RTB
is equal to 10k. RTA is derived from equation:
RTA =
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
0.6V
VFB VFB VTRACK
+
−
10k RFB
RTB
where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since RTB is equal to the 10k top
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then RTA is equal to RFB with VFB
= VTRACK. Therefore RTB = 10k, and RTA = 10k in Figure 5.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. RTB can be solved for when SR is
The RUN pin has an enable threshold of 1.4V maximum,
typically 1.25V with 150mV of hysteresis. It controls the
turn-on of the µModule. The RUN pin can be pulled up to
VIN for 5V operation, or a 5V Zener diode can be placed
on the pin and a 10k to 100k resistor can be placed up to
higher than 5V input for enabling the µModule. The RUN
pin can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tied together and
controlled from a single control. See the Typical Application circuits in Figures 19 and 20. The RUN pin can also
be left floating. The RUN pin has a 1µA pull-up current
source that increases to 4.5µA during ramp-up.
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is provided
in the LTM4649 to sense low output voltages accurately
at the remote load points. This is especially applicable for
4649fc
16
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
high current loads. It is very important that the DIFFP and
DIFFN are connected properly at the output, and DIFFOUT
is connected to VOUT_LCL. Review the parallel schematics
in Figures 19 and 20.
SW Pins
The SW pin is generally used for testing purposes. The
SW pin can also be used to dampen out switch node ringing caused by LC parasitic in the switched current path.
Usually a series R-C combination is used, referred to as a
snubber circuit. The resistor will dampen the resonance and
the capacitor is chosen to only affect the high frequency
ringing across the resistor.
If the stray inductance or capacitance can be measured
or approximated then a somewhat analytical technique
can be used to select the snubber values. The inductance
is usually easier to determine. It combines the power
path board inductance in combination with the MOSFET
interconnect bond wire inductance.
First the SW pin can be monitored using a wide bandwidth scope with a high frequency scope probe. The ring
frequency can be measured for its value. The impedance
Z can be calculated:
ZL = 2π • f • L
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by:
1
2π • f • C
These values are a good place to start. Modification to
these components should be made to attenuate the ringing with the least amount of power loss.
ZC =
Temperature Monitoring
A diode connected PNP transistor is used for the TEMP
monitor function by monitoring its voltage over temperature. The temperature dependence of this diode voltage
can be understood in the equation:
I 
VD = nVT ln  D 
 IS 
where VT is the thermal voltage (kT/q), and n, the ideality
factor, is 1 for the diode connected PNP transistor being used in the LTM4649. IS is expressed by the typical
empirical equation:
 –V 
IS = I0 exp  G0 
 VT 
where I0 is a process and geometry dependent current, (I0
is typically around 20k orders of magnitude larger than IS
at room temperature) and VG0 is the band gap voltage of
1.2V extrapolated to absolute zero or –273°C.
If we take the IS equation and substitute into the VD equation, then we get:
 k  I 
kT
VD = VG0 –  T  ln  0  ,VT =
q
 q   ID 
The expression shows that the diode voltage decreases
(linearly if I0 were constant) with increasing temperature
and constant diode current. Figure 7 shows a plot of VD
vs Temperature over the operating temperature range of
the LTM4649.
If we take this equation and differentiate it with respect to
temperature T, then:
V −V
dVD
= − G0 D
dT
T
This dVD /dT term is the temperature coefficient equal to
about –2mV/K or –2mV/°C. The equation is simplified for
the first order derivation.
Solving for T, T = –(VG0 – VD)/(dVD/dT) provides the
temperature.
4649fc
For more information www.linear.com/LTM4649
17
LTM4649
APPLICATIONS INFORMATION
0.8
ID = 100µA
DIODE VOLTAGE (V)
0.7
0.6
0.5
0.4
0.3
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
4649 F07
Figure 7. Diode Voltage VD vs Temperature T(°C)
1st Example: Figure 7 for 27°C, or 300K the diode voltage
is 0.598V, thus, 300K = –(1200mV – 598mV)/–2.0mV/K).
2nd Example: Figure 7 for 75°C, or 350K the diode voltage
is 0.5V, thus, 350K = –(1200mV – 500mV)/–2.0mV/K).
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temperature and subtracting 273 from it.
Measure the forward voltage at 27°C to establish a reference point. Then using the above expression while measuring the forward voltage over temperature will provide a
general temperature monitor. Connect a resistor between
TEMP and VIN to set the current to 100µA. See Figure 21
for an example.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment and a
test vehicle such as the demo board to predict the µModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a
manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:
1. θJA: the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3. θJCtop: the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB: the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance
where almost all of the heat flows through the bottom
of the µModule package and into the board, and is really
the sum of the θJCbottom and the thermal resistance of
4649fc
18
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
the bottom of the part through the solder joints and
through a portion of the board. The board temperature
is measured a specified distance from the package.
A graphical representation of the aforementioned thermal resistances is given in Figure 8; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal operating conditions of a μModule regulator. For example, in
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4649, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA software
is used to accurately build the mechanical geometry of
the LTM4649 and the specified PCB with all of the correct material coefficients along with accurate power loss
source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4649 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
process and due diligence yields the set of derating curves
shown in this data sheet. After these laboratory tests have
been performed and correlated to the LTM4649 model,
then the θJB and θBA values are summed together to
correlate quite well with the µModule model for θJA with
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4649 F08
µMODULE DEVICE
Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients
4649fc
For more information www.linear.com/LTM4649
19
LTM4649
APPLICATIONS INFORMATION
no airflow or heat sinking in a properly defined chamber.
This θJB + θBA value is shown in the Pin Configuration
section and should accurately equal the θJA value because
approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top
mounted heat sink.
3.0
12
2.5
2.5
10
2.0
2.0
1.5
1.0
0.5
0
2
4
6
LOAD CURRENT (A)
1.0
0
10
8
1.5
0.5
VOUT = 3.3V
VOUT = 1.5V
0
LOAD CURRENT (A)
3.0
POWER LOSS (W)
POWER LOSS (W)
The 5VIN and 12VIN power loss curves in Figures 9 and 10
can be used in coordination with the load current derating
curves in Figures 11 to 14 for calculating an approximate
θJA thermal resistance for the LTM4649 with various
heat sinking and airflow conditions. The power loss
curves are taken at room temperature, and are increased
with a multiplicative factor according to the ambient
temperature. This approximate factor is: 1.4 for 120°C.
The derating curves are plotted with the output current
starting at 10A and the ambient temperature at 40°C. The
output voltages are 1.5V and 3.3V. These are chosen to
include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a
controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored
2
4
6
LOAD CURRENT (A)
4649 F09
10
10
10
400LFM
200LFM
0LFM
2
0
0
LOAD CURRENT (A)
12
LOAD CURRENT (A)
12
4
8
6
4
400LFM
200LFM
0LFM
2
40
60
80
100
20
AMBIENT TEMPERATURE (°C)
120
4649 F12
Figure 12. No Heat Sink with
12VIN to 1.5VOUT
40
60
80
100
20
AMBIENT TEMPERATURE (°C)
0
0
120
Figure 11. No Heat Sink with 5VIN
to 1.5VOUT
12
6
0
4649 F11
Figure 10. 12VIN, 3.3VOUT
and 1.5VOUT Power Loss
8
400LFM
200LFM
0LFM
4649 F10
Figure 9. 5VIN, 3.3VOUT and
1.5VOUT Power Loss
LOAD CURRENT (A)
4
0
10
8
6
2
VOUT = 3.3V
VOUT = 1.5V
0
8
8
6
4
400LFM
200LFM
0LFM
2
40
60
80
100
20
AMBIENT TEMPERATURE (°C)
120
4649 F13
Figure 13. No Heat Sink with
5VIN to 3.3VOUT
0
0
40
60
80
100
20
AMBIENT TEMPERATURE (°C)
120
4649 F14
Figure 14. No Heat Sink with
12VIN to 3.3VOUT
4649fc
20
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
while ambient temperature is increased with and without
airflow. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature. The
decreased output current will decrease the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operating
temperature specifies how much module temperature rise
can be allowed. As an example in Figure 12 the load current
is derated to ~8A at ~90°C with no air or heat sink and
the power loss for the 12V to 1.5V at 8A output is about
2.24W. The 2.24W loss is calculated with the 1.6W room
temperature loss from the 12V to 1.5V power loss curve
at 8A, and the 1.40 multiplying factor at 120°C junction. If
the 90°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 30°C divided
by 2.24W equals a 13°C/W θJA thermal resistance. Table 4
specifies a 14°C/W value which is very close. Table 4 and
Table 5 provide equivalent thermal resistances for 1.5V
and 3.3V outputs with and without airflow. The derived
thermal resistances in Tables 4 and 5 for the various conditions can be multiplied by the calculated power loss as
a function of ambient temperature to derive temperature
rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics
section and adjusted with the above ambient temperature
multiplicative factors. The printed circuit board is a 1.6mm
thick four layer board with two ounce copper for the two
outer layers and one ounce copper for the two inner layers.
The PCB dimensions are 95mm × 76mm.
Safety Considerations
The LTM4649 module does not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
48.1°C
48.8°C
4649 F15
Figure 15. Thermal Image 12V to 1.5V at 10A
(No Heat Sink, No Air Flow. At Room Temperature Ambient)
4649fc
For more information www.linear.com/LTM4649
21
LTM4649
APPLICATIONS INFORMATION
Layout Checklist/Example
The high integration of LTM4649 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current path,
including VIN, GND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on the pads, unless they are
capped.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
Figure 16 gives a good example of the recommended layout.
VOUT
GND
COUT
CIN
GND
VIN
4649 F16
Figure 16. Recommended PCB Layout
4649fc
22
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
Table 3. Output Voltage Response vs Component Matrix (Refer to Figure 18) 0A to 5A Load Step Typical Measured Values
CIN
(BULK)*
150µF,
16V
VENDORS
CIN
PART NUMBER (CERAMIC)
SANYO OSCON 25HVH150MT
VENDORS
22µF, 16V
MURATA
PART NUMBER
COUT
(CERAMIC) VENDORS
GRM32ER71C226KE18L 100µF, 6.3V MURATA
220µF, 4V
VOUT
1V
VIN
CIN
CIN
COUT
(BULK)* (CERAMIC) (CERAMIC)
CFF
LOAD STEP
VDROOP
VP-P
MURATA
RECOVERY LOAD STEP
TIME
SPEED
PART NUMBER
GRM32ER60J107ME20L
GRM31CR60G227M
RFB
SW FREQ
FREQ
PIN
5V, 12V 120µF*
22µF × 2
100µF × 3
None
75% to 100%
45mV
90mV
40µs
1A/µs
15kΩ
450kHz
Float
1.2V 5V, 12V 120µF*
22µF × 2
100µF × 3
None
75% to 100%
50mV
100mV
50µs
1A/µs
10kΩ
450kHz
Float
1.5V 5V, 12V 120µF*
22µF × 2
100µF × 3
None
75% to 100%
57mV
114mV
60µs
1A/µs
6.65kΩ
450kHz
Float
2.5V
5V
120µF*
22µF × 2
100µF × 3
None
75% to 100%
75mV
150mV
70µs
1A/µs
3.16kΩ
450kHz
Float
2.5V
12V
120µF*
22µF × 2
100µF × 3
None
75% to 100%
75mV
150mV
70µs
1A/µs
3.16kΩ
750kHz
INTVCC
3.3V
5V
120µF*
22µF × 2
100µF × 3
None
75% to 100%
95mV
190mV
70µs
1A/µs
2.21kΩ
450kHz
Float
3.3V
12V
120µF*
22µF × 2
100µF × 3
None
75% to 100%
95mV
190mV
70µs
1A/µs
2.21kΩ
750kHz
INTVCC
5V, 12V 120µF*
22µF × 2
220µF × 2
None
50% to 100%
70mV
140mV
30µs
1A/µs
15kΩ
450kHz
Float
1.2V 5V, 12V 120µF*
1V
22µF × 2
220µF × 2
None
50% to 100%
75mV
150mV
40µs
1A/µs
10kΩ
450kHz
Float
1.5V 5V, 12V 120µF*
22µF × 2
220µF × 2
None
50% to 100%
90mV
180mV
40µs
1A/µs
6.65kΩ
450kHz
Float
2.5V
5V
120µF*
22µF × 2
220µF × 2
None
50% to 100%
135mV 270mV
50µs
1A/µs
3.16kΩ
450kHz
Float
2.5V
12V
120µF*
22µF × 2
220µF × 2
None
50% to 100%
135mV 270mV
50µs
1A/µs
3.16kΩ
750kHz
INTVCC
3.3V
5V
120µF*
22µF × 2
220µF × 2
None
50% to 100%
175mV 350mV
60µs
1A/µs
2.21kΩ
450kHz
Float
3.3V
12V
120µF*
22µF × 2
220µF × 2
None
50% to 100%
175mV 350mV
60µs
1A/µs
2.21kΩ
750kHz
INTVCC
*Bulk capacitor is optional if VIN has very low input impedance.
Table 4. 1.5V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
θJA(°C/W)
Figures 11, 12
5, 12
Figure 9
0
None
14
Figures 11, 12
5, 12
Figure 9
200
None
12
Figures 11, 12
5, 12
Figure 9
400
None
10
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
θJA(°C/W)
Figures 13, 14
5, 12
Figure 10
0
None
14
Figures 13, 14
5, 12
Figure 10
200
None
12
Figures 13, 14
5, 12
Figure 10
400
None
10
Table 5. 3.3V Output
4649fc
For more information www.linear.com/LTM4649
23
LTM4649
TYPICAL APPLICATIONS
FREQ
VIN
4.5V TO 16V
CIN
22µF
16V
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
RUN
LTM4649
MODE
PHMODE
TEMP
GND
DIFFP
COUT2
100µF
6.3V
DIFFN
VFB
TRACK/SS
C1
0.1µF
COUT1
100µF
6.3V
VOUT
1.5V
10A
COMP
PGOOD
CLKOUT
RFB
6.65k
4649 F17
Figure 17. 4.5V to 16VIN, 1.5V at 10A Design
1M
VIN
4.5V TO 16V
FREQ
CIN
22µF
16V
CIN
22µF
16V
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
RUN
MODE
LTM4649
PHMODE
TRACK/SS
C1
0.1µF
TEMP
GND
100µF
6.3V
×2
VOUT
3.3V
8A
DIFFP
DIFFN
VFB
COMP
PGOOD
CLKOUT
RFB
2.21k
4649 F18
Figure 18. 4.5V to 16V VIN, 3.3VOUT at 8A Design with Increased 650kHz Frequency
4649fc
24
For more information www.linear.com/LTM4649
LTM4649
TYPICAL APPLICATIONS
VIN
4.5V TO 16V
CIN1
22µF
16V
RUN
FREQ
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
RUN
MODE
LTM4649
PHMODE
C1
0.1µF
CIN2
22µF
16V
PGOOD
CLKOUT
FREQ
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
LTM4649
FREQ
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
LTM4649
TRACK/SS
TEMP
GND
COUT5
100µF
6.3V
COUT6
100µF
6.3V
COMP
PGOOD
CLKOUT
PHMODE
COUT4
100µF
6.3V
DIFFP
DIFFN
TEMP
GND
MODE
COUT3
100µF
6.3V
VFB
TRACK/SS
RUN
RFB
6.65k
COMP
PHMODE
CIN3
22µF
16V
DIFFP
DIFFN
TEMP
GND
MODE
COUT2
100µF
6.3V
VFB
TRACK/SS
RUN
COUT1
100µF
6.3V
VOUT
1.5V
30A
DIFFP
DIFFN
4649 F19
VFB
COMP
PGOOD
CLKOUT
PGOOD
Figure 19. Three LTM4649 in Parallel, 1.5V at 30A Design
4649fc
For more information www.linear.com/LTM4649
25
LTM4649
TYPICAL APPLICATIONS
VIN
4.5V TO 16V
CIN1
22µF
16V
FREQ
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
RUN
MODE
LTM4649
PHMODE
CIN2
22µF
16V
VOUT1
R3
10k
R4
3.09k
DIFFP
COMP
PGOOD
CLKOUT
FREQ
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
MODE
COUT2
100µF
6.3V
LTM4649
PHMODE
COUT4
100µF
6.3V
DIFFP
VOUT2
2.5V
10A
TRACK/SS
COMP
TEMP
GND
PGOOD
CLKOUT
LTM4649
DIFFP
FREQ
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
LTM4649
TEMP
GND
R5
4.99k
COUT7
100µF
6.3V
DIFFP
COUT8
100µF
6.3V
VOUT4
1.5V
10A
DIFFN
PHMODE
R10
6.65k
COUT6
100µF
6.3V
VOUT3
1.8V
10A
VFB
COMP
PGOOD
CLKOUT
TRACK/SS
COUT5
100µF
6.3V
DIFFN
TEMP
GND
MODE
R9
10k
R2
3.09k
DIFFOUT
RUN
VOUT1
VFB
VOUT_LCL
SW
TRACK/SS
CIN4
22µF
16V
DIFFN
INTVCC
PHMODE
R7
4.87k
COUT3
100µF
6.3V
CLKIN
VOUT
MODE
R6
10k
R1
2.21k
FREQ
VIN
RUN
VOUT1
DIFFN
TEMP
GND
RUN
CIN3
22µF
16V
VFB
TRACK/SS
C1
0.1µF
VOUT1
3.3V
8A
COUT1
100µF
6.3V
VFB
COMP
PGOOD
CLKOUT
R2
6.65k
4649 F20
Figure 20. Quad Outputs 4-Phase LTM4649 Regulator with Tracking Function
VIN
4.5V TO 16V
FREQ
CIN
22µF
16V
0.1µF
VIN
CLKIN
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
RUN
MODE
LTM4649
PHMODE
TRACK/SS
C1
0.1µF
TEMP
GND
COUT1
100µF
6.3V
COUT2
100µF
6.3V
DIFFP
VOUT
1.5V
10A
DIFFN
VFB
COMP
PGOOD
CLKOUT
RFB
6.65k
R7 =
VIN
R7
VIN – 0.6V
100µA
UC
A/D
4649 F21
Figure 21. Single LTM4649 10A Design with Temperature Monitoring
4649fc
26
For more information www.linear.com/LTM4649
0.630 ±0.025 Ø 68x
SUGGESTED PCB LAYOUT
TOP VIEW
2.540
PACKAGE TOP VIEW
1.270
4
0.3175
0.000
0.3175
PIN “A1”
CORNER
E
1.270
aaa Z
2.540
Y
For more information www.linear.com/LTM4649
6.350
5.080
3.810
2.540
1.270
0.000
3.810
5.080
6.350
D
X
aaa Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
b1
DETAIL A
NOM
4.92
0.60
4.32
0.75
0.63
15.00
9.00
1.27
12.70
7.62
0.32
4.00
MAX
5.12
0.70
4.42
0.90
0.66
DIMENSIONS
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
DETAIL B
PACKAGE SIDE VIEW
A2
SUBSTRATE THK
0.37
MOLD CAP HT
4.05
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 68
0.27
3.95
MIN
4.72
0.50
4.22
0.60
0.60
H1
SUBSTRATE
Z
ddd M Z X Y
eee M Z
DETAIL B
H2
MOLD
CAP
ccc Z
A1
A
Z
3.810
3.810
(Reference LTC DWG# 05-08-1892 Rev B)
Øb (68 PLACES)
// bbb Z
BGA Package
68-Lead (15.00mm × 9.00mm × 4.92mm)
F
e
G
E
D
C
B
PACKAGE BOTTOM VIEW
F
A
DETAIL A
11
10
9
8
7
6
5
4
3
2
1
PIN 1
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
6
!
BGA 68 0617 REV B
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
6
SEE NOTES
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
b
3
SEE NOTES
G
LTM4649
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4649#packaging/ for the most recent package drawings.
4649fc
27
LTM4649
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4649 BGA Pin Assignment Table
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
D1
VIN
E1
GND
F1
RUN
G1
GND
A1
GND
B1
GND
C1
VIN
A2
GND
B2
–
C2
–
D2
–
E2
–
F2
CLCKOUT
G2
GND
E3
FREQ
F3
GND
G3
GND
A3
GND
B3
CLKIN
C3
NC
D3
VIN
E4
–
F4
INTVCC
G4
GND
A4
GND
B4
PHMODE
C4
NC
D4
VIN
E5 TRACK/SS
F5
GND
G5
GND
A5
GND
B5
MODE
C5
SW
D5
VIN
A6
TEMP
B6
–
C6
–
D6
–
E6
–
F6
COMP
G6
GND
E7
FB
F7
DIFFN
G7
GND
A7
GND
B7
NC
C7
PGOOD
D7
VIN
D8
VIN
E8
VIN
F8
DIFFP
G8
DIFFOUT
A8
GND
B8
NC
C8
VIN
D9
VIN
E9
VOUT
F9
VOUT
G9
VOUT_LCL
A9
GND
B9
GND
C9
VIN
A10
GND
B10
GND
C10
VOUT
D10
VOUT
E10
VOUT
F10
VOUT
G10
VOUT
A11
GND
B11
GND
C11
VOUT
D11
VOUT
E11
VOUT
F11
VOUT
G11
VOUT
PACKAGE PHOTO
4649fc
28
For more information www.linear.com/LTM4649
LTM4649
REVISION HISTORY
REV
DATE
DESCRIPTION
A
2/14
Added SnPb (lead) BGA package.
1, 2
Figures 9 and 10 changed Y-Axis to Power Loss (W).
20
B
C
12/15
7/17
PAGE NUMBER
Corrected RFB (k) for 2.5V from 3.06 to 3.16.
11
Revised Temperature Monitoring discussion.
17
Added CLKOUT, PHMODE and SW pins on Block Diagram.
9
Corrected note number to COMP from Note 6 to Note 3.
2
4649fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTM4649
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
29
LTM4649
TYPICAL APPLICATION
VIN
4.5V TO 16V
CIN1
22µF
16V
CLKIN
VIN
VOUT_LCL
SW
DIFFOUT
RUN
MODE
INTVCC
LTM4649
PHMODE
MASTER
SLOPE
FREQ
VOUT
INTVCC
TRACK/SS
TEMP
GND
CLOCK
VOUT
1.2V
10A
COUT1
100µF
6.3V
DIFFP
CIN2
22µF
16V
COUT2
100µF
6.3V
DIFFN
VFB
R1
10k
PGOOD
CLKOUT
R3
10k
FREQ
VOUT
INTVCC
VOUT_LCL
SW
DIFFOUT
RUN
R2
10k INTVCC
COMP
CLKIN
VIN
MODE
LTM4649
PHMODE
TRACK/SS
TEMP
GND
COUT3
100µF
6.3V
DIFFP
VOUT
1.8V
COUT4 10A
100µF
6.3V
DIFFN
VFB
COMP
PGOOD
CLKOUT
R4
4.99k
4649 F22
Figure 22. Dual Output 1.2V, 1.8V 2-Phase LTM4649 Regulator with Tracking
DESIGN RESOURCES
SUBJECT
µModule Design and Manufacturing Resources
µModule Regulator Products Search
DESCRIPTION
Manufacturing:
Design:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• PCB Design, Assembly and Manufacturing Guidelines
• Free Simulation Tools
• Package and Board Level Reliability
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
LTM4627
20V, 15A Step-Down µModule Regulator
LTM4620A
LTM4613
LTM8045
LTM8061
LTM8048
LTC2974
Dual 16V, 13A or Single 26A Step-Down µModule
Regulator
36VIN, 8A EN55022 Class B Certified DC/DC Step-Down
µModule Regulator
Inverting or SEPIC µModule DC/DC Converter with Up to
700mA Output Current
32V, 2A Step-Down µModule Battery Charger with
Programmable Input Current Limit
1.5W, 725VDC Galvanically Isolated µModule Converter
with LDO post regulator
Quad Digital Power Supply Manager with EEPROM
COMMENTS
4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, PLL input, Remote Sense Amplifier,
VOUT Tracking, 15mm × 15mm × 4.3mm LGA and 15mm × 15mm × 4.9mm
BGA
4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V, PLL Input, Remote Sense Amplifier,
VOUT Tracking, 15mm × 15mm × 4.41mm LGA
5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, PLL Input, VOUT Tracking and Margining,
15mm × 15mm × 4.32mm LGA
2.8V ≤ VIN ≤ 18V, ±2.5V ≤ VOUT ≤ ±15V, Synchronizable,
6.25mm × 11.25mm × 4.92mm BGA
CC-CV Charging Single and Dual Cell Li-Ion or Li-Poly Batteries,
4.95V ≤ VIN ≤ 32V, C/10 or Adjustable Timer Charge Termination,
9mm × 15mm × 4.32mm LGA
3.1V ≤ VIN ≤ 32V, 2.5V ≤ VOUT ≤ 12V, 1mVPP Output Ripple, Internal Isolated
Transformer, 9mm × 11.25mm × 4.92mm BGA
I2C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel
Voltage, Current and Temperature Measurements
4649fc
30
LT 0717 REV C • PRINTED IN USA
For more information www.linear.com/LTM4649
www.linear.com/LTM4649
 LINEAR TECHNOLOGY CORPORATION 2013