K4C89183AF 288Mb x18 Network-DRAM2 Specification Version 0.7 - 1 - REV. 0.7 Jan. 2005 K4C89183AF Revision History Version 0.0 (Oct. 2002) - First Release Version 0.01 (Nov. 2002) - Changed die revision from D-die to F-die - Corrected typo - Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram. Version 0.1 (Apr. 2003) - Added 800Mbps(400Mhz) product - Changed operating temperature from Ta to Tc. - Changed capacitance of ADDR/CMD/CLK From Addr/CMD/CLK To Min Max Min Max 1.5 2.5 1.5 3.0 - Changed tDSS(DS input Falling Edge to Clock Setup Time) From To F6 FB F5 G7 F6 FB F5 CL4 0.9 0.9 1.0 0.75 0.75 0.8 1.0 CL5 0.9 0.9 1.0 0.75 0.75 0.8 1.0 CL6 0.9 0.9 1.0 0.75 0.75 0.8 1.0 CL7 - - - 0.75 - - - - Added CL7 for 800Mbps - Deleted TSOP package outline Version 0.11 (Apr. 2003) - Corrected typo in page 3.(Deleted bi-directional strobe) - Corrected min. Vref to VDDQ/2x95% in page 7 Version 0.2 (Aug. 2003) - Added package physical dimension - Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future) - Changed DC test condition From To Changed point IDD1S,IDD2N,IDD2P,IDD5,IDD6 IDD1S,IDD2N,IDD2P,IDD5B,IDD6 Changed condition - IDD4W, IDD4R newly inserted - Changed low frequency spec like below From To Unit : ns F6 FB F5 F6 FB F5 tCK max@CL=4 7.5 7.5 7.5 6.0 6.0 6.0 tCK max@CL=5 7.5 7.5 7.5 6.0 6.0 6.0 tCK max@CL=6 7.5 7.5 7.5 6.0 6.0 6.0 - Changed AC test load picture Version 0.3 (Nov. 2003) - Changed Packge type from die-exposed to full molded - Changed Package code in Partnumber - 2 - REV. 0.7 Jan. 2005 K4C89183AF Version 0.31 (Mar., 2004) - Corrected typo. in page 7 (Changed operating Temperature to 85’C, case temperature) Version 0.4 (Jun., 2004) - Changed from "target" to "Preliminary" - Changed min. tCK@CL5 to 3.5ns in "-F6" tCK Clock Cycle Time (min) From To F6 F6 CL = 4 4.0 ns 4.0 ns CL = 5 3.33 ns 3.5 ns CL = 6 3.0ns 3.0ns Version 0.5 (Aug., 2004) - Deleted self-refresh function and BL2 from spec Version 0.51 (Aug., 2004) - Corrected error in page 54, "Package Out line Drawing". (Just 4 balls were missing in drawing) Version 0.6 (Nov., 2004) - Deleted "preliminary" - Changed current value in page 9 Version 0.7 (Jan., 2005) - Deleted the tDQSQA in page 11 - Deleted the tSSK in page 11 - 3 - REV. 0.7 Jan. 2005 K4C89183AF 4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM DESCRIPTION K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as 4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can operate fast core cycle compared with regular DDR SDRAM. K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition. FEATURES K4C89183AF Parameter tCK Clock Cycle Time (min) F6 FB F5 CL = 4 4.0 ns 4.5 ns 5.0 ns CL = 5 3.5 ns 3.75 ns 4.5 ns CL = 6 3.0ns 3.33 ns 4.0 ns tRC Random Read/Write Cycle Time (min) 20.0 ns 22.5 ns 25 ns tRAC Random Access Time (min) 20.0 ns 22.5 ns 25 ns IDD1S Operating Current (single bank) (max) 320mA 300mA 280mA IDD2P Power Down Current (max) 70mA 65mA 60mA • • • • • • • • • • • • • • • • Fully Synchronous Operation - Double Data Rate (DDR) - Data input/output are synchronized with both edges of DS / QS. - Differential Clock (CLK and CLK) inputs - CS, FN and all address input signals are sampled on the positive edge of CLK. - Output data (DQs and QS) is aligned to the crossings of CLK and CLK. Fast clock cycle time of 3.0 ns minimum - Clock : 333 MHz maximum - Data : 666 Mbps/pin maximum Quad Independent Banks operation Fast cycle and Short Latency Uni-directional Data Strobe Distributed Auto-Refresh cycle in 3.9us Power Down Mode Variable Write Length Control Write Latency = CAS Latency-1 Programable CAS Latency and Burst Length - CAS Laatency = 4, 5, 6 - Burst Length = 4 Organization : 4,194,304 words x 4 banks x 18 bits Power Supply Voltage VDD : 2.5V ± 0.125V VDDQ : 1.4V ∼ 1.9V 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD - 4 - REV. 0.7 Jan. 2005 K4C89183AF PIN ASSIGNMENT (TOP VIEW) Pin Names Pin Name A0 ~ A14 Address Input BA0, BA1 Bank Address DQ0 ~ DQ17 Data Input/Output CS Chip Select FN Function Control PD Power Down Control CLK, CLK Clock Input DS/QS Write/Read data strobe VDD Power (+2.5V) VSS Ground VDDQ Power (+1.8V) (for I/O buffer) VSSQ Ground (for I/O buffer) VREF Reference Voltage NC No Connection ball pitch=1.0 x 1.0mm x18 1 2 3 4 5 6 Index A Vss DQ17 DQ0 VDD B DQ16 VssQ VDDQ DQ1 C DQ15 VDDQ VssQ DQ2 D DQ14 DQ13 DQ4 DQ3 E DQ12 VssQ VDDQ DQ5 F DQ11 VDDQ VssQ DQ6 G DQ10 VssQ VDDQ DQ7 H DQ9 DS QS DQ8 J VREF Vss VDD A14 K CLK CLK FN A13 L A12 PD CS NC M A11 A9 BA1 BA0 N A8 A7 A0 A10 P A5 A6 A2 A1 R VSS A4 A3 VDD - 5 - REV. 0.7 Jan. 2005 K4C89183AF Block Diagram CLK DLL CLK CLOCK PD BUFFER To Each Block BANK #3 COMMAND BANK #2 CONTROL SIGNAL DECODER A0 ~ A14 ADDRESS BA0, BA1 BUFFER GENERATOR BANK #0 ROW DECODER FN BANK #1 MODE REGISTER UPPER ADDRESS LATCH REFRESH COUNTER DATA CONTROL AND LATCH CIRCUIT CS MEMORY CELL ARRAY COLUMN DECODER LOWER ADDRESS LATCH BURST COUNTER READ DATA BUFFER WRITE ADDRESS LATCH ADDRESS COMPARATOR DS QS WRITE DATA BUFFER DQ BUFFER DQ0 ~ DQ17 Note : The K4C89183AD configuration is 4 Bank of 32768 x 128 x 18 of cell array with the DQ pins numbered DQ0~DQ17. - 6 - REV. 0.7 Jan. 2005 K4C89183AF Absolute Maximum Ratings Symbol Parameter Rating Units VDD Power Supply Voltage -0.3 ~ 3.3 V VDDQ Power Supply Voltage (for I/O buffer) -0.3 ~ VDD + 0.3 V VIN Input Voltage -0.3 ~ VDD + 0.3 V VOUT DQ pin Voltage -0.3 ~ VDDQ + 0.3 V VREF Input Reference Voltage -0.3 ~ VDDQ + 0.3 V TOPR Operating Temperature 0 ~ 85 O TSTG Storage Temperature -55 ~ 150 O TSOLDER Soldering Temperature(10s) 260 O PD Power Dissipation 2 W IOUT Short Circuit Output Current ± 50 mA Notes Case Temp. C C C Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability. Recommended DC,AC Operating Conditions (Notes : 1) Symbol VDD Parameter Power Supply Voltage (Tcase = 0 ~ 85 OC) Min Typ Max Units 2.375 2.5 2.625 V 1.7 1.8 1.9 V Notes VDDQ Power Supply Voltage (for I/O Buffer) VREF Input Reference Voltage VDDQ/2x95% VDDQ/2 VDDQ/2x105% V 2 VIH (DC) Input DC high Voltage VREF+0.125 - VDDQ+0.2 V 5 VIL(DC) Input DC Low Voltage -0.1 - VREF-0.125 V 5 VICK (DC) Differential Clock DC Input Voltage -0.1 - VDDQ+0.1 V 10 VID (DC) Input Differential Voltage. CLK and CLK Inputs (DC) 0.4 - VDDQ+0.2 V 7,10 VIH (AC) Input AC High Voltage VREF+0.2 - VDDQ+0.2 V 3,6 VIL (AC) Input AC Low Voltage -0.1 - VREF-0.2 V 4,6 VID (AC) Input Differential Voltage. CLK and CLK Inputs (AC) 0.55 - VDDQ+0.2 V 7,10 VX (AC) Differential AC Input Cross Point Voltage VDDQ/2-0.125 - VDDQ/2+0.125 V 8,10 Differential Clock AC Middle Level VDDQ/2-0.125 - VDDQ/2+0.125 V 9,10 VISO (AC) - 7 - REV. 0.7 Jan. 2005 K4C89183AF Notes: 1. All voltages are referenced to Vss, VssQ. 2. VREF is expected to track variations in VddQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed ± 2% of VREF (DC). 3. Overshoot Iimit : VIH(max.) = VddQ + 0.7V with a pulse width <= 5ns 4. Undershoot Iimit : VIL(min.) = -0.7V with a pulse width <= 5ns 5. VIH(DC) and VIL(DC) are levels to maintain the current logic state. 6. VIH(AC) and VIL(AC) are levels to change to the new logic state. 7. VID is magnitude of the difference between CLK input level and CLK input level. 8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device. 9. VISO means [VICK(CLK) + VICK(CLK)]/2 10. Refer to the figure below. CLK VX VX VX VX VX VID(AC) CLK VICK VICK VICK VICK VSS VID(AC) 0 V Differential VISO VISO(min) VISO(max) VSS 11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of VREF(DC) ± 0.04V. Pin Capacitance (VDD= 2.5V, VDDQ = 1.8V, f = 1 MHz, Ta = 25oC) Symbol Parameter Min Max Delts Units CIN Input Pin Capacitance 1.5 3.0 0.25 pF CINC Clock Pin (CLK, CLK) Capacitance 1.5 3.0 0.25 pF CI/O DQ, DS, QS Capacitance 2.5 3.5 0.5 pF CNC NC Pin Capacitance - 1.5 - pF Note : These parameters are periodically sampled and not 100% tested. - 8 - REV. 0.7 Jan. 2005 K4C89183AF DC Characteristics and Operating Conditions Parameter (VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C) Symbol Max F6 FB F5 Units Notes Operating Current One bank Read or Write operation; tCK = min, IRC = min, IOUT = 0mA; Burst Length = 4, CAS Latency = 6, Free running QS mode; 0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ; Address inputs change up to 2 times during minimum IRC, Read data change twice per clock cycle IDD1S 320 300 280 1, 2 Standby Current All Banks : inactive state; tCK=min, CS = VIH, PD = VIH; 0V ≤ VIN ≤ VIL(AC)(max.), VIH(AC)(min.) ≤ VIH ≤ VDDQ; Other input signals change one time during 4*tCK, DQ and DS inputs change twice per clock cycle IDD2N 100 95 90 1 Standby (Power Down) Current All Banks : inactive state; tCK=min, PD = VIL (Power Down); CAS Latency = 6, Free running QS mode; 0V ≤ VIN ≤ VIL(AC)(max), VIH(AC)(min) ≤ VIN ≤ VDDQ; Other input signals change one time during 4*tCK, DQ and DS inputs are floating(VDDQ/2) IDD2P 70 65 60 1 mA Write Operating Current(4 Banks) 4 Bank intereaved continuous burst write operation; tCK = min, IRC = min; Burst Length = 4, CAS Latency = 6, Free running QS mode; 0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ; Address inputs change once per clock cycle, DQ and DS inputs change twice per clock cycle IDD4W 650 600 550 1 Read Operating Current(4 Banks) 4 Bank intereaved continuous burst write operation; tCK = min, IRC = min, IOUT = 0mA; Burst Length = 4, CAS Latency = 6, Free running QS mode; 0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ; Address inputs change once per clock cycle, Read data change twice per clock cycle IDD4R 650 600 550 1,2 Burst Auto-Refresh Current Refresh command at every IREFC interval; tCK = min, IREFC= min; CAS Latency = 6, Free running QS mode; 0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC) (min.) ≤ VIN ≤ VDDQ; Address change up to 2 times during minimum IREFC, DQ and DS inputs change twice per clock cycle IDD5B 250 235 210 1,3 - 9 - REV. 0.7 Jan. 2005 K4C89183AF DC Characteristics and Operating Conditions (VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C) Parameter Symbol Min Max Unit Input Leakage Current (0V<=VIN<=VddQ, All other pins not under test = 0V) ILI -5 5 uA Output Leakage Current (Output disabled, 0V<=VOUT<=VddQ) ILO -5 5 uA 5 uA VREF Current Normal Output Driver Strong Output Driver Output DC Current (VDDQ = 1.7 ~ 1.9V) Weak Output Driver Normal Output Driver Strong Output Driver Weak Output Driver Output DC Current (VDDQ = 1.4 ~ 1.6V) Notes IREF -5 VOH = 1.420V IOH(DC) -5.6 - 4 VOL = 0.280V IOL(DC) 5.6 - 4 VOH = 1.420V IOH(DC) -9.8 - 4 mA VOL = 0.280V IOL(DC) 9.8 VOH = 1.420V IOH(DC) VOL = 0.280V IOL(DC) VOH = VDDQ - 0.4 - 4 -2.8 - 4 2.8 - IOH(DC) -4 - 3 VOL = 0.4V IOL(DC) -4 - 3 VOH = VDDQ - 0.4 IOH(DC) -8 - VOL = 0.4V IOL(DC) -8 - Not defined IOH(DC) - - Not defined IOL(DC) - - 3 mA 3 Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters depend on the output loading. The specified values are obtained with the output open. 3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to tREFI specification 4. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register. - 10 - REV. 0.7 Jan. 2005 K4C89183AF AC Characteristics and Operating Conditions (Notes : 1, 2) Symbol tRC tCK F6 Parameter Min Random Cycle Time Clock Cycle Time FB Max Min F5 Max Min Max Units Notes 20.0 - 22.5 - 25 - 3 CL = 4 4.0 6.0 4.5 6.0 5.0 6.0 3 CL = 5 3.33 6.0 3.75 6.0 4.5 6.0 3 CL = 6 3.0 6.0 3.33 6.0 4.0 6.0 3 - 20.0 - 22.5 - 25 3 - 0.45*tCK - 0.45*tCK - 3 tRAC Random Access Time tCH Clock High Time 0.45*tCK tCL Clock Low Time 0.45*tCK - 0.45*tCK - 0.45*tCK - 3 tCKQS QS Access Time from CLK -0.45 0.45 -0.45 0.45 -0.5 0.5 3, 8 tQSQ Data Output Skew from QS - 0.2 - 0.25 - 0.3 4 tAC Data Access Time from CLK -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8 tOH Data Output Hold Time from CLK -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8 - min(tCH, tCL) - min(tCH, tCL) - 3 tHP CLK half period ( minium of Actual tCH, tCL) min(tCH, tCL) tQSP QS(Read) Pulse Width tHP-tQHS - tHP-tQHS - tHP-tQHS - 4, 8 tQSQV Data Output Valid Time from QS tHP-tQHS - tHP-tQHS - tHP-tQHS - 4, 8 - 0.055x tCK+0.17 - 0.055x tCK+0.17 - 0.055x tCK+0.17 tQHS DQ, QS Hold skew factor tDQSS DS(Write) Low to High Setup Time 0.8*tCK 1.2*tCK 0.8*tCK 1.2*tCK 0.8*tCK 1.2*tCK tDSPRE DS(Write) Preamble Pulse Width 0.4*tCK - 0.4*tCK - 0.4*tCK - 4 tDSPRES DS First Input Setup Time 0 - 0 - 0 - 3 - 3 ns 3 tDSPREH DS First Low Input Hold Time 0.3*tCK - 0.3*tCK - 0.3*tCK tDSP DS High or Low Input Pulse Width 0.45*tCK 0.55*tCK 0.45*tCK 0.55*tCK 0.45*tCK 0.55*tCK 4 CL = 4 0.75 - 0.8 - 1.0 - 3, 4 CL = 5 0.75 - 0.8 - 1.0 - 3, 4 CL = 6 0.75 - 0.8 - 1.0 - 3, 4 CL = 7 - - - - - - 3, 4 0.45*tCK - 0.45*tCK 0.45*tCK - 4 3, 4 tDSS tDSPST tDSPSTH DS Input Falling Edge to Clock Setup Time DS(Write) Postamble Pulse Width DS(Write) Postamble Hold Time CL = 4 0.75 - 0.8 - 1.0 - CL = 5 0.75 - 0.8 - 1.0 - CL = 6 0.75 - 0.8 - 1.0 CL = 7 - - - - - 3, 4 3, 4 - 3, 4 tDS Data Input Setup Time from DS 0.3 - 0.35 - 0.4 - 4 tDH Data Input Hold Time from DS 0.3 - 0.35 - 0.4 - 4 tIS Command / Address Input Setup Time 0.6 - 0.6 - 0.7 - 3 tIH Command / Address Input Hold Time 0.6 - 0.6 - 0.7 - 3 - 11 - REV. 0.7 Jan. 2005 K4C89183AF AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued) Symbol F6 Parameter FB F5 Max Min Max Min Max -0.5 - -0.5 - -0.6 - 3, 6, 8 3, 7, 8 tLZ Data-out Low Impedance Time from CLK tHZ Data-out High Impedance Time from CLK - 0.5 - 0.5 - 0.6 tQPDH Last Output to PD High Hold Time 0 - 0 - 0 - tPDEX Power Down Exit Time 0.6 - 0.6 - 0.7 - tT Input Transition Time 0.1 1 0.1 1 0.1 1 tFPDL PD Low Input Window for Self-Refresh Entry -0.5*tCK 5 -0.5*tCK 5 -0.5*tCK 5 tREFI Auto-Refresh Average Interval 0.4 3.9 0.4 3.9 0.4 3.9 tPAUSE Pause Time after Power-up 200 - 200 - 200 - IRC IRCD IRAS 3 3 5 us CL = 4 5 - 5 - 5 - Random Read/Write Cycle Time CL = 5 6 - 6 - 6 - (Applicable to Same Bank) CL = 6 7 - 7 - 7 - CL = 7 - - - - - - 1 1 1 1 1 1 RDA/WRA to LAL Command Input Delay (Applicable to Same Bank) LAL to RDA/WRA Command Input Delay (Applicable to Same Bank) IRBD Random Bank Access Delay (Applicable to Other Bank) IRWD LAL following RDA to WRA Delay (Applicable to Other Bank) IWRD LAL following WRA to RDA Delay (Applicable to Other Bank) IRSC Units Notes Min Mode Register Set Cycle Time CL = 4 4 - 4 - 4 - CL = 5 5 - 5 - 5 - CL = 6 6 - 6 - 6 - CL = 7 - - - - - - 2 - 2 - 2 - 3 - 3 - 3 - 1 - 1 - 1 - BL = 4 CL = 4 7 - 7 - 7 - CL = 5 7 - 7 - 7 - CL = 6 7 - 7 - 7 - - 2 - 2 - 2 Cycle CL = 7 IPD PD Low to Inactive State of Input Buffer IPDA PD High to Active State of Input Buffer IPDV Power down mode valid from REF command 1 - 1 - 1 - CL = 4 19 - 19 - 19 - CL = 5 23 - 23 - 23 - CL = 6 25 - 25 - 25 - CL = 7 IREFC Auto-Refresh Cycle Time CL = 4 19 - 19 - 19 - CL = 5 23 - 23 - 23 - CL = 6 25 - 25 - 25 - 200 - 200 - 200 - CL = 7 ILOCK DLL Lock-on Time (Applicable to RDA command) - 12 - REV. 0.7 Jan. 2005 K4C89183AF AC Test Conditions Symbol Parameter Value Units V VIH(min) Input high voltage (minimum) VREF + 0.2 VIL (max) Input low voltage (maximum) VREF - 0.2 V VddQ/2 V VREF V 0.7 V VX(AC) V VREF Input reference voltage VTT Termination voltage VSWING VR Input signal peak to peak swing Differential clock input reference level VID(AC) Input differential voltage 1.0 V SLEW Input signal minimum slew rate 2.5 V/ns VOTR Output timing measurement reference voltage VddQ/2 V Notes 9 VddQ VTT VIH min(AC) VSWING 25 Ω VREF Output VIL max(AC) Measurement Point Vss ∆T ∆T AC Test Load Slew=(VIHmin(AC) - VILmax(AC))/∆T Notes : 1. Transition times are measured between VIH min(DC) and VIL max(DC). Transition (rise and fall) of input signals have a fixed slope. 2. If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.8*tCK, tCK = 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.) 3. These parameters are measured from the differential clock (CLK and CLK) AC cross point. 4. These parameters are measured from signal transition point of DS crossing VREF level. 5. The tREFI (MAX.) applies to equally distributed refresh method. The tREFI (MIN.) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the maximum. 6. Low Impedance State is speified at VddQ/2± 0.2V from steady state. 7. High Impedance State is specified where output buffer is no longer driven. 8. These parameters depend on the clock jitter. These parameters are measured at stable clock. 9. Output timing is measured by using Normal driver strength at VDDQ = 1.7V ~ 1.9V. Output timing is measured by using Strong driver strength at VDDQ = 1.4V ~ 1.6V - 13 - REV. 0.7 Jan. 2005 K4C89183AF Power Up Sequence 1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection. 2. Apply VDD before or at the same time as VDDQ. 3. Apply VDDQ before or at the same time as VREF. 4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.). 5. After stable power and clock, apply DESL and take PD = H. 6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1) 7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1) 8. Issue two or more Auto-Refresh commands. (Note:1) 9. Ready for normal operation after 200 clocks from Extended Mode Register programming. Note : 1. Sequence 6, 7 and 8 can be issued in random order. 2. L=Logic Low, H = Logic High ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ 0.9V(TYP) ∼ 1.8V(TYP) ∼ VDDQ ∼ 2.5V(TYP) ∼ VDD VREF ∼ CLK ∼ ∼ CLK tPDEX 200 µs(min) IPDA lRSC lRSC RDA MRS WRA REF DESL ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ DS DESL op-code EMRS DQ DESL WRA REF ∼ DESL ∼ RDA MRS ∼ DESL op-code Address ∼ 200 clock cycle(min) ∼ ∼ Command lREFC ∼ ∼ ∼ ∼ PD lREFC Hi-Z QS (Uni-QS mode) - 14 - Low ∼ MRS ∼ EMRS ∼ ∼ QS (Free Running mode) MRS Auto Refresh cycle Normal Operation REV. 0.7 Jan. 2005 K4C89183AF Basic Timing Diagrams Input Timing Command and Address tCK tCH tCK tCL CK ~ CK CS tIH tIS 1st tIH ~~ tIS 2nd tIPW tIS tIS tIH ~~ 2nd 1st FN tIH tIPW A0-A14 BA0.BA1 tIS tIH tIH ~~ tIS LA UA, BA ~ Data DS tDH tDS tDH tDS tDH tDS tDH ~~ ~~ tDS DQn (Input) DQm (Input) Refer to the Command Truth Table. Timing of the CLK, CLK tCH tCL CLK CLK tT tT VIH VIH(AC) VIL(AC) VIL tCK CLK VIH CLK VIL VID(AC) VX VX - 15 - VX REV. 0.7 Jan. 2005 K4C89183AF Read Timing (Burst Length = 4) Unidirectional DS/QS mode 0 1 2 tCH 3 tCL 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tCK CK CK tIS Input (Control & Addresses) tIH LAL(after RDA) DESL LDS/UDS (Input) tCKQS tCKQS CAS latency = 4 LQS/UQS (Output) tQSP Low Low tQSQV tLZ DQ (Output) tCKQS tQSP tQSQ tQSQ tQSQ tQSQV Q0 Q1 Q2 tHZ High-Z tAC tAC Q3 tAC tOH tCKQS tCKQS CAS latency = 5 LQS/UQS (Output) tQSP Low Low tQSQV tLZ DQ (Output) tCKQS tQSP tQSQ tQSQ tQSQ tQSQV Q0 Q1 Q2 tHZ High-Z tAC tAC Q3 tAC tOH tCKQS tCKQS CAS latency = 6 LQS/UQS (Output) tQSP Low Low tQSQV tLZ DQ (Output) tCKQS tQSP tQSQ tQSQ tQSQ tQSQV Q0 Q1 Q2 tHZ High-Z tAC tAC tAC Q3 tOH Note : DQ0 to DQ17 are aligned with LQS. DQ18 to DQ35 are aligned with UQS. - 16 - REV. 0.7 Jan. 2005 K4C89183AF Read Timing (Burst Length = 4) Unidirectional DS/Free Running QS mode 0 1 2 tCH 3 tCL 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tCK CK CK tIS Input (Control & Addresses) tIH LAL(after RDA) DESL LDS/UDS (Input) tCKQS tCKQS CAS latency = 4 tCKQS tQSP tQSP LQS/UQS (Output) tQSQV tLZ DQ (Output) tQSQ tQSQ tQSQ tQSQV Q0 Q1 Q2 tHZ High-Z tAC tAC Q3 tAC tOH tCKQS tCKQS CAS latency = 5 tCKQS tQSP tQSP LQS/UQS (Output) tQSQV tLZ DQ (Output) tQSQ tQSQ tQSQ tQSQV Q0 Q1 Q2 tHZ High-Z tAC tAC Q3 tAC tOH tCKQS tCKQS CAS latency = 6 tCKQS tQSP tQSP LQS/UQS (Output) tQSQV tLZ DQ (Output) tQSQ tQSQ tQSQ tQSQV Q0 Q1 Q2 tHZ High-Z tAC tAC tAC Q3 tOH Note : DQ0 to DQ17 are aligned with LQS. DQ18 to DQ35 are aligned with UQS. LQS/UQS is always asserted in Free Running QS mode. - 17 - REV. 0.7 Jan. 2005 K4C89183AF Write Timing (Burst Length = 4) Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode 0 1 2 tCH 3 tCL 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tCK CK CK tIS Input (Control & Addresses) tIH LAL(after RDA) DESL tDSPSTH tDQSS tDSS tDSPRES CAS latency = 4 tDSPREH tDSP tDSP LDS/UDS (Input) tDSS Preamble tDSPRE tDS tDS tDH DQ (Input) tDSP Postamble tDS tDH Q0 Q1 tDSPST tDH Q2 Q3 tDSS tDSPSTH tDQSS tDSS tDSPRES CAS latency = 5 tDSPREH tDSP tDSP tDSP tDSPST LDS/UDS (Input) Preamble tDH DQ (Input) Postamble tDSPRE tDS tDS Q0 tDS tDH tDH Q2 Q3 Q1 tDSS tDSPSTH tDQSS tDSS tDSPRES CAS latency = 6 tDSPREH tDSP tDSP tDSP tDSPST LDS/UDS (Input) Preamble tDH DQ (Input) Q0 LQS/UQS (Uni-QS) Postamble tDSPRE tDS tDS Q1 tDS tDH tDH Q2 Q3 Low LQS/UQS (Free Runninig) Note : DQ0 to DQ17 are sampled at both edges of LDS. DQ18 to DQ35 are sampled at both edges of UDS. - 18 - REV. 0.7 Jan. 2005 K4C89183AF ~ tREFI, tPAUSE, Ixxxx Timing CLK tIS Input (Control & Addresses) tIH Command tREFI,tPAUSE,IXXXX ~ CLK tIS tIH Command Note. "IXXXX"means "IRC", "IRCD", "IRAS", etc. - 19 - REV. 0.7 Jan. 2005 K4C89183AF Function Truth Table (Notes : 1,2,3) Command Truth Table (Notes : 4) •The First Command Symbol Function CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 DESL Device Deselect H X X X X X X RDA Read with Auto-close L H BA UA UA UA UA WRA Write with Auto-close L L BA UA UA UA UA •The Second Command (The next clock of RDA or WRA command) Symbol Function CS FN BA1-BA0 A14-A13 A12-A11 A10-A9 A8 A7 A6-A0 LAL Lower Address Latch H X X V X X X X LA REF Auto-Refresh L X X X X X X X X MRS Mode Register Set L X V L L L L V V Notes : 1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), BA = Bank Address, UA = Upper Address, LA = Lower Address. 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the command table below. Read Command Table Command (Symbol) CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 RDA (1st) L H BA UA UA UA UA LAL (2nd) H X X X X X LA Notes Write Command Table Command (Symbol) CS FN BA1BA0 A14 A13 A12 A11 A10~ A9 A8 A7 A6-A0 WRA (1st) L L BA UA UA UA UA UA UA UA UA LAL (2nd) H X X VW0 VW1 X X X X X LA Notes : 5. A14~A13 are used for Variable Write Length (VW) control at Write Operation. VW Truth Table Function BL = 4 VW0 VW1 Reserved L L Write All Words H L Write First Two Words L H Write First One Word H H - 20 - REV. 0.7 Jan. 2005 K4C89183AF Function Truth Table (Continued) Mode Register Set Command Truth Table Command (Symbol) CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 RDA (1st) L H X X X X X MRS (2nd) L X V L L V V Notes 6 Note : 6. Refer to "Mode Register Table". Auto-Refresh Command Table PD Command (Symbol) Current State n-1 n Active WRA(1st) Standby H Auto-Refresh REF(2nd) Active H Function CS FN BA1-BA0 A14-A9 H L L X H L X X A8 A7 A6-A0 X X X X X X X X Notes Power Down Table Function Power Down Entry Power Down Continue Power Down Exit PD Command (Symbol) Current State n-1 n CS FN BA1BA0 A14-A9 A8 A7 PDEN Standby H L H X X X X X X - Power Down L L X X X X X X X PDEX Power Down L H H X X X X X X A6-A0 Notes 8 9 Notes : 7. PD has to be brought to Low within tFPDL from REF command. 8. PD should be brought to Low after DQ’s state turned high impedance. 9. When PD is brought to High from Low, this function is executed asynchronously. - 21 - REV. 0.7 Jan. 2005 K4C89183AF Function Truth Table (Continued) Current State Idle Row Active for Read Row Active for Write Read Write Auto-Refreshing Mode Register Accessing Power Down PD CS Address Command X X DESL NOP H L BA, UA BA, UA RDA WRA Row activate for Read Row activate for Write X X X X PDEN - Power Down Entry Illegal X H X X X LA LAL H L X Op-Code MRS/EMRS L H X X PDEN H L L X X MRS/EMRS Illegal L X X X X - Invalid H H H X LA LAL Begin Write H H L X X REF Auto-Refresh H L H X X PDEN H L L X X REF (Self) n-1 H n H H H H H H L L H H L L H L L H X H H H FN Action Notes 10 Refer to Power Down state Begin read Access to Mode Register Illegal Illegal Self-Refresh entry L X X X X - H H H H H L X H X BA, UA DESL RDA Invalid Continue burst read to end Illegal 11 H H L L BA, UA WRA Illegal 11 H L H X X PDEN Illegal H L L X L X X X X X - Illegal Invalid H H H H H L X H X BA, UA DESL RDA Data write & continue burst write to end Illegal H H H L L H L X BA, UA X WRA PDEN Illegal Illegal H L L X L X X X X X - Illegal Invalid H H H X X DESL NOP-> Idle after IREFC H H L H BA, UA RDA Illegal H H H L L H L X BA, UA X WRA PDEN H L L X L X X X X X - H H H X X DESL Nop-> Idle after IRSC H H L H BA, UA RDA Illegal H H H L L H L X BA, UA X WRA PDEN Illegal Illegal H L L X L X X X X X - Illegal Invalid H L X L X X X X X X - Invalid Maintain Power Down Mode L H H X X RDEX L H L X X - 11 11 Illegal Self-Refresh entry 12 Illegal Refer to Self-Refreshing state Exit Power Down Mode->Idle after tPDEX Illegal Notes : 10. Illegal if any bank is not idle. 11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA). 12. Illegal if tFPDL is not Stisfied. - 22 - REV. 0.7 Jan. 2005 K4C89183AF Mode Register Table Regular Mode Register (Notes : 1) Address BA1*1 BA0*1 A14-A8 A7*3 A6-A4 A3 A2-A0 Register 0 0 0 TM CL BT BL A7 Test Mode (TE) A3 Burst Type (BT) 0 Regular (Default) 0 Sequential 1 Test Mode Entry 1 Interleave A6 A5 A4 CAS Latency (CL) A2 A1 A0 Burst Length (BL) 0 0 X Reserved *2 0 0 0 Reserved *2 0 1 0 Reserved *2 0 0 1 Reserved *2 0 1 1 Reserved *2 0 1 0 4 1 0 0 4 0 1 1 1 0 1 5 1 X X 1 1 0 6 1 1 1 Reserved *2 Reserved *2 Extended Mode Register (Notes : 4) Address BA1*4 BA0*4 A14-A7 A6~A5 A4-A3 A2~A1 A0*5 Register 0 1 0 SS DIC(QS) DIC(DQ) DS A6 A5 Strobe Select 0 0 Reserved 0 1 Reserved*2 1 0 Unidirectional DS/QS 1 1 Unidirectional DS/Free Running QS *2 QS DQ A4 A3 A2 A1 Output Driver Impedance Control (DIC) 0 0 0 0 Normal Output Driver 0 1 0 1 Strong Output Driver 1 0 1 0 Weak Output Driver 1 1 1 1 Reserved Note : 1. Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0. 2. "Reserved" places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to "0"(Low state). Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation. - 23 - A0 DLL Switch (DS) 0 DLL Enable 1 DLL Disable REV. 0.7 Jan. 2005 K4C89183AF State Diagram Power Down PDEX (PD = H) PDEN (PD = L) Standby (Idle) PD = H AutoRefresh Mode Register WRA RDA REF MRS Active (Restore) Active LAL LAL Write (Buffer) Read Command Input Automatic Return The second command at Active state must be issued 1clock after RDA or WRA command input - 24 - REV. 0.7 Jan. 2005 K4C89183AF Timing Diagrams Single Bank Read Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRC=5cycles Command RDA LAL lRCD=1cycle Address UA Bank Add. #0 DESL lRAS=4cycles LA lRC=5cycles RDA LAL lRCD=1cycle UA DESL lRAS=4cycles LA lRC=5cycles RDA lRCD=1cycle UA #0 LAL DESL RDA lRAS=4cycles LA UA #0 #0 Unidirectional DS/QS mode DS (Input) QS (Output) Low CL=4 DQ (Output) Hi-Z CL=4 Q0 Q1 Q2 Q3 CL=4 Q0 Q1 Q2 Q3 Q0 Unidirectional DS/Free Running QS mode DS (Input) QS (Output) CL=4 DQ (Output) CL=4 CL=4 Hi-Z Q0 Q1 Q2 Q3 - 25 - Q0 Q1 Q2 Q3 Q0 REV. 0.7 Jan. 2005 K4C89183AF Single Bank Read Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RDA LAL 14 15 CLK CLK lRC=6cycles Command RDA LAL lRCD=1cycle Address UA Bank Add. #0 DESL lRAS=5cycles LA lRC=6cycles RDA LAL DESL lRCD=1cycle lRAS=5cycles UA LA UA #0 DESL lRCD=1cycle LA #0 Unidirectional DS/QS mode DS (Input) QS (Output) Low CL=5 DQ (Output) Hi-Z CL=5 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Unidirectional DS/Free Running QS mode DS (Input) QS (Output) CL=5 DQ (Output) Hi-Z CL=5 Q0 Q1 Q2 Q3 - 26 - Q0 Q1 Q2 Q3 REV. 0.7 Jan. 2005 K4C89183AF Single Bank Read Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA LAL CLK CLK lRC=7cycles Command RDA LAL lRCD=1cycle Address UA Bank Add. #0 DESL lRC=7cycles RDA lRAS=6cycles LAL lRCD=1cycle LA UA DESL lRAS=6cycles LA lRCD=1cycle UA #0 LA #0 Unidirectional DS/QS mode DS (Input) QS (Output) Low CL=6 DQ (Output) CL=6 Hi-Z Q0 Q1 Q2 Q3 Q0 Q1 Q2 Unidirectional DS/Free Running QS mode DS (Input) QS (Output) CL=6 DQ (Output) CL=6 Hi-Z Q0 Q1 Q2 Q3 - 27 - Q0 Q1 Q2 REV. 0.7 Jan. 2005 K4C89183AF Single Bank Write Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRC=5cycles Command WRA LAL lRCD=1cycle Address UA Bank Add. #0 DESL lRAS=4cycles LA lRC=5cycles WRA LAL lRCD=1cycle UA DESL lRAS=4cycles LA lRC=5cycles WRA lRCD=1cycle UA #0 LAL DESL WRA lRAS=4cycles LA UA #0 #0 Unidirectional DS/QS mode DS (Input) QS (Output) Low WL=3 DQ (Input) WL=3 D0 D1 D2 D3 WL=3 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional DS/Free Running QS mode DS (Input) QS (Output) WL=3 DQ (Input) WL=3 D0 D1 D2 D3 WL=3 D0 D1 D2 D3 - 28 - D0 D1 D2 D3 REV. 0.7 Jan. 2005 K4C89183AF Single Bank Write Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 WRA LAL 14 15 CLK CLK lRC=6cycles Command WRA LAL lRCD=1cycle Address UA Bank Add. #0 DESL lRAS=5cycles LA lRC=6cycles WRA LAL lRCD=1cycle UA DESL lRAS=5cycles LA lRCD=1cycle UA #0 DESL LA #0 Unidirectional DS/QS mode DS (Input) QS (Output) Low WL=4 DQ (Input) WL=4 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional DS/Free Running QS mode DS (Input) QS (Output) WL=4 DQ (Input) WL=4 D0 D1 D2 D3 - 29 - D0 D1 D2 D3 REV. 0.7 Jan. 2005 K4C89183AF Single Bank Write Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WRA LAL CLK CLK lRC=7cycles Command WRA LAL lRCD=1cycle Address UA Bank Add. #0 lRC=7cycles DESL WRA lRAS=6cycles LA LAL lRCD=1cycle UA DESL lRAS=6cycles LA lRCD=1cycle UA #0 LA #0 Unidirectional DS/QS mode DS (Input) QS (Output) Low WL=5 DQ (Input) WL=5 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional DS/Free Running QS mode DS (Input) QS (Output) WL=5 DQ (Input) WL=5 D0 D1 D2 D3 - 30 - D0 D1 D2 D3 REV. 0.7 Jan. 2005 K4C89183AF Single Bank Read-Write Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRC=5cycles Command RDA LAL Address UA LA Bank Add. #0 DESL lRC=5cycles WRA LAL UA LA DESL #0 lRC=5cycles RDA LAL UA LA DESL WRA UA #0 #0 Unidirectional DS/QS mode DS (input) QS (Output) Low CL=4 DQ WL=3 CL=4 Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=4 DQ WL=3 CL=4 Hi-Z Q0 Q1 Q2 Q3 - 31 - D0 D1 D2 D3 Q0 REV. 0.7 Jan. 2005 K4C89183AF Single Bank Read-Write Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RDA LAL UA LA 14 15 CLK CLK lRC=6cycles Command RDA LAL Address UA LA Bank Add. #0 DESL lRC=6cycles WRA LAL UA LA DESL #0 DESL #0 Unidirectional DS/QS mode DS (input) QS (Output) Low CL=5 DQ WL=4 Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=5 DQ WL=4 Hi-Z Q0 Q1 Q2 Q3 Read data - 32 - D0 D1 D2 D3 Write data REV. 0.7 Jan. 2005 K4C89183AF Single Bank Read-Write Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA LAL UA LA CLK CLK lRC=7cycles RDA LAL Address UA LA Bank Add. #0 Command lRC=7cycles DESL WRA LAL UA LA DESL #0 #0 Unidirectional DS/QS mode DS (input) QS (Output) Low CL=6 DQ WL=5 Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=6 DQ WL=5 Hi-Z Q0 Q1 Q2 Q3 Read data - 33 - D0 D1 D2 D3 Write data REV. 0.7 Jan. 2005 K4C89183AF Multiple Bank Read Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRBD=2cycles Command Address Bank Add. lRBD=2cycles RDA LAL RDA LAL UA LA UA LA Bank "a" DESL Bank "b" lRBD=2cycles lRBD=2cycles lRBD=2cycles RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA UA LA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" lRC(Bank"a")=5cycles lRC(Bank"b")=5cycles Unidirectional DS/QS mode DS (input) QS (Output) Low CL=4 CL=4 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=4 CL=4 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Note : lRC to the same bank must be satisfied - 34 - REV. 0.7 Jan. 2005 K4C89183AF Multiple Bank Read Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRBD=2cycles Command Address Bank Add. lRBD=2cycles RDA LAL RDA LAL UA LA UA LA Bank "a" DESL Bank "b" lRBD=2cycles lRBD=2cycles lRBD=2cycles RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL UA LA UA LA UA LA UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" lRC(Bank"a")=6cycles lRC(Bank"6")=6cycles Unidirectional DS/QS mode DS (input) QS (Output) Low CL=5 CL=5 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=5 CL=5 DQ (Output) Hi-Z Note : lRC to the same bank must be satisfied - 35 - REV. 0.7 Jan. 2005 K4C89183AF Multiple Bank Read Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRBD=2cycles Command Address Bank Add. lRBD=2cycles RDA LAL RDA LAL UA LA UA LA Bank "a" DESL Bank "b" lRBD=2cycles lRBD=2cycles lRBD=2cycles RDA LAL RDA LAL RDA LAL RDA LAL RDA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" lRC(Bank"a")=7cycles Unidirectional DS/QS mode lRC(Bank"b")=7cycles DS (input) QS (Output) Low CL=6 CL=6 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=6 CL=6 DQ (Output) Hi-Z Note : lRC to the same bank must be satisfied - 36 - REV. 0.7 Jan. 2005 K4C89183AF Multiple Bank Write Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRBD=2cycles Command Address Bank Add. lRBD=2cycles WRA LAL WRA LAL UA LA UA LA Bank "a" DESL Bank "b" lRBD=2cycles lRBD=2cycles lRBD=2cycles WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA UA LA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" lRC(Bank"a")=5cycles lRC(Bank"b")=5cycles Unidirectional DS/QS mode DS (input) QS (Output) Low WL=3 WL=3 DQ (Input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1 Unidirectional DS/Free Running QS mode DS (input) QS (Output) WL=3 WL=3 DQ (Input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1 Note : lRC to the same bank must be satisfied - 37 - REV. 0.7 Jan. 2005 K4C89183AF Multiple Bank Write Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRBD=2cycles Command Address Bank Add. lRBD=2cycles WRA LAL WRA LAL UA LA UA LA DESL Bank "b" Bank "a" lRBD=2cycles lRBD=2cycles lRBD=2cycles WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL UA LA UA LA UA LA UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" lRC(Bank"a")=6cycles lRC(Bank"b")=6cycles Unidirectional DS/QS mode DS (input) QS (Output) Low WL=4 WL=4 DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Unidirectional DS/Free Running QS mode DS (input) QS (Output) WL=4 WL=4 DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Note :IRC to the same bank must be satisfied. - 38 - REV. 0.7 Jan. 2005 K4C89183AF Multiple Bank Write Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lRBD=2cycles Command Address Bank Add. lRBD=2cycles WRA LAL WRA LAL UA LA UA LA DESL Bank "b" Bank "a" lRBD=2cycles lRBD=2cycles lRBD=2cycles WRA LAL WRA LAL WRA LAL WRA LAL WRA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" lRC(Bank"a")=7cycles lRC(Bank"a")=7cycles Unidirectional DS/QS mode DS (input) QS (Output) Low WL=5 WL=5 DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Unidirectional DS/Free Running QS mode DS (input) QS (Output) WL=5 WL=5 DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Note :IRC to the same bank must be satisfied. - 39 - REV. 0.7 Jan. 2005 K4C89183AF Multiple Bank Read-Write Timing (BL=4) 0 1 2 3 RDA LAL 4 5 6 7 8 9 WRA LAL RDA LAL 10 11 12 13 14 15 WRA LAL RDA LAL CLK CLK lRBD=2cycles Command WRA LAL lWRD=1cycle Address Bank Add. UA LA UA DESL lRWD=3cycles LA UA Bank "b" Bank "a" lWRD=1cycle LA Bank "c" UA DESL lRWD=3cycles LA lWRD=1cycle UA Bank "d" Bank "a" LA UA LA Bank "b" lRC(Bank"a") lRC(Bank"a") Unidirectional DS/QS mode CL =4 DS (Input) QS (Output) Low DQ (Output) Hi-Z CL=4 WL=3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 CL =5 DS (Input) QS (Output) Low DQ (Output) Hi-Z WL=4 CL=5 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 CL =6 DS (Input) QS (Output) Low DQ (Output) Hi-Z WL=5 CL=6 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Note :IRC to the same bank must be satisfied. - 40 - REV. 0.7 Jan. 2005 K4C89183AF Multiple Bank Read-Write Timing (BL=4) 0 1 2 3 RDA LAL 4 5 6 7 8 9 WRA LAL RDA LAL 10 11 12 13 14 15 WRA LAL RDA LAL CLK CLK lRBD=2cycles Command WRA LAL lWRD=1cycle Address Bank Add. UA LA UA DESL lRWD=3cycles LA UA Bank "b" Bank "a" lWRD=1cycle LA Bank "c" UA DESL lRWD=3cycles LA lWRD=1cycle UA Bank "d" Bank "a" LA UA LA Bank "b" lRC(Bank"a") lRC(Bank"a") Unidirectional DS/Free Running QS mode CL =4 DS (Input) QS (Output) CL=4 WL=3 DQ (Output) Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 CL =5 DS (Input) QS (Output) WL=4 DQ (Output) CL=5 Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 CL =6 DS (Input) QS (Output) WL=5 DQ (Output) CL=6 Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Note :IRC to the same bank must be satisfied. - 41 - REV. 0.7 Jan. 2005 K4C89183AF Write with Variable Write Length (VW) Control(CL=4) 0 1 2 3 4 5 6 WRA LAL UA LA=#1 VW=1 7 8 9 10 11 12 13 14 15 CLK CLK BL=2, SEQUENTIAL MODE Command Address WRA LAL UA LA=#3 VW=All DESL VW0 = Low VW1 = don’t care Bank Add. DESL VW0 = High VW1 = don’t care Bank "a" Bank "a" DS (Input) DQ (Input) D0 D1 D0 Lower Address #3 #2 #1 (#0) Last one data is masked. BL=4, SEQUENTIAL MODE Command Address WRA LAL UA LA=#3 VW=All DESL WRA LAL UA LA=#1 VW=1 VW0 = High VW1 = Low Bank Add. DESL WRA LAL UA LA=#2 VW=2 VW0 = High VW1 = High VW0 = Low VW1 = High Bank "a" Bank "a" DESL Bank "a" DS (Input) DQ (Input) D0 D1 D2 D3 Lower Address #3 #0 D0 #1 #2 #1 (#2) (#3) (#0) Last three data are masked. D0 D1 #2 #3 (#0) (#1) Last two data are masked. Note : DS input must be continued till end of burst count even if some of laster data is masked. - 42 - REV. 0.7 Jan. 2005 K4C89183AF Power Down Timing (CL=4, BL=4) Read cycle to Power Down Mode 0 1 2 3 4 5 6 7 8 9 CLK BL=2, SEQUENTIAL MODE Command Address RDA LAL UA DESL LA tIH tIS IPD=2 cycle tQPDH n+1 n+2 DESL RDA or WRA n+3 IPDA UA tPDEX ∼ DS (input) ∼ ∼ Low CL=4 DQ (Output) n IRC(min), tREFI(max) Unidirectional DS/QS mode QS (Output) n-1 ∼ PD 10 ∼ ∼ ∼ CLK Hi-Z Q0 Q1 Q2 Q3 Hi-Z Unidirectional DS/Free Running QS mode ∼ ∼ ∼ DS (input) QS (Output) CL=4 DC (Output) Hi-Z Q0 Q1 Q2 Q3 Power Down Entry Hi-Z Power Down Exit Note : PD must be kept "High" level until end of Burst data output. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" and a stable clock signal must be maintained. When PD is brought to "High", a valid executable command may be applied IPDA cycles later. - 43 - REV. 0.7 Jan. 2005 K4C89183AF Power Down Timing (CL=4, BL=4) Write cycle to Power Down Mode 0 1 2 3 4 5 6 7 8 CLK Command Address WRA LAL UA LA DESL tIH tIS WL=3 n-1 n n+1 n+2 n+3 IPDA DESL RDA or WRA UA tPDEX IPD=2 cycle IRC(min), tREFI(max) Unidirectional DS/QS mode ∼ DS (input) Low ∼ ∼ QS (Output) 10 ∼ PD IPD=2 cycle 9 ∼ ∼ ∼ CLK WL=3 DC (Output) D0 D1 D2 D3 Unidirectional DS/Free Running QS mode ∼ ∼ ∼ DS (input) QS (Output) WL=3 DC (Output) D0 D1 D2 D3 Note : PD must be kept "High" level until end of Burst data output. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" and a stable clock signal must be maintained. When PD is brought to "High", a valid executable command may be applied IPDA cycles later. - 44 - REV. 0.7 Jan. 2005 K4C89183AF Mode Register Set Timing (CL=4, BL=4) From Write operation to Mode Register Set operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="0" BA1="0" BA CLK CLK lRC=7cycles WRA LAL A14~A0 UA LA BA0, BA1 BA Command DESL RDA MRS DESL WL + BL/2 Unidirectional DS/QS mode DS (input) QS (Output) Low DC (input) D0 D1 D2 D3 Unidirectional DS/Free Running QS mode DS (input) QS (Output) DC (input) D0 D1 D2 D3 Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2. - 45 - REV. 0.7 Jan. 2005 K4C89183AF Extended Mode Register Set Timing (CL=4, BL=4) From Write operation to Extended Mode Register Set operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="0" BA1="0" BA CLK CLK lRC=7cycles WRA LAL A14~A0 UA LA BA0, BA1 BA Command DESL RDA MRS DESL WL + BL/2 Unidirectional DS/QS mode DS (input) QS (Output) Low DQ DC (input) D0 D1 D2 D3 Unidirectional DS/Free Running QS mode DS (input) QS (Output) DQ (input) D0 D1 D2 D3 Note : When DQ strobe mode is changed by EMRS, QS output is invalid for IRSC period. DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2. - 46 - REV. 0.7 Jan. 2005 K4C89183AF Auto-Refresh Timing (CL=4, BL=4) Unidirectional DS/QS mode 0 1 2 3 4 5 6 7 n-1 n n+1 n+2 RDA or WRA LAL or MRS or REF RDA or WRA LAL or MRS or REF CLK CLK lRC=5cycles RDA LAL Bank, Address Bank, UA LA DESL lRCD=1cycle lRAS=4cycles REF DESL lRCD=1cycle Low ∼ QS (output) WRA ∼ ∼ Command lREFC=19cycles CL=4 Hi-Z Q0 Q1 Q2 Q3 ∼ DQ (output) Low Hi-Z Unidirectional DS/Free Running QS mode CLK CLK lRC=5cycles RDA LAL Bank, Address Bank, UA LA DESL lRCD=1cycles WRA lRAS=4cycles ∼ ∼ ∼ Command lREFC=19cycles REF DESL lRCD=1cycles QS (output) CL=4 Hi-Z Q0 Q1 Q2 Q3 ∼ DQ (output) Hi-Z Note : In case of CL=4, IREFC must be meet 19 clock cycles. When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command specified by tREFI must be satisfied. tREFI is average interval time in 8 Refresh cycles that is sampled randomly. t1 t2 ∼ WRA REF t8 ∼ WRA REF t7 ∼ WRA REF ∼ ∼ CLK t3 WRA REF WRA REF 8 Refresh cycle tREFI = Total time of 8 Refresh cycle = t1+t2+t3+t4+t5+t6+t7+t8 8 8 tREFI is specified to avoid partly concentrated current of Refresh operation that is acivated larger are than Read/Write operation. - 47 - REV. 0.7 Jan. 2005 K4C89183AF Function Description Network - DRAM Network - DRAM is an acronym of Double Data Rate Network - DRAM. Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer. Pin Functions Clock Inputs : CLK & CLK The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS, FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK. The QS and DQ output data are aligned to the crossing point of CLK and CLK. The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Power Down : PD The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed. Chip Select & Function Control : CS & FN The CS and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs. Bank Addresses : BA0 & BA1 The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS). BA0 BA1 Bank #0 0 0 Bank #1 1 0 Bank #2 0 1 Bank #3 1 1 Address Inputs : A0 to A14 Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. K4C89183AF Upper Address Lower Address A0 to A14 A0 to A6 - 48 - REV. 0.7 Jan. 2005 K4C89183AF Functional Description (Continued) Data Input/Output : DQ0 ~ DQ17 The input data of DQ0 to DQ17 are taken in synchronizing with the both edges of DS input signal. The output data of DQ0 to DQ17 are outputted synchronizing with the both edges of QS output signal. Data Strobe : DS or QS Method of data strobe is chosen by Extended mode register. (1) Unidirectional DS/QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. During Write. Auto-Refresh and NOP cycle, QS assert always "Low" level. QS is Hi-Z in Self-Refresh mode. (2) Unidirectional DS/Free running QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe type is easy to use for pin to pin connect application. Power Supply : VDD, VDDQ, VSS, VSSQ VDD and VSS are supply pins for memory core and peripheral circuits. VDDQ and VSSQ are power supply pins for the output buffer. Reference Voltage : VREF VREF is reference voltage for all input signals. - 49 - REV. 0.7 Jan. 2005 K4C89183AF Command Functions and Operations K4C89093AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. Read Operation (1st command + 2nd command = RDA + LAL) Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state after IRC. Write Operation (1st command + 2nd command = WRA + LAL) Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS have to be provided for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after IRC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table. Auto-Refresh Operation (1st command + 2nd command = WRA + REF) K4C89093AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by IREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum. Power Down Mode( PD="L" ) When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89183AF become Power Down Mode by asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD, CLK, CLK and QS. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued for IPDA cycle after PD goes high. The Power Down exit function is asynchronous operation. Mode Register Set (1st command + 2nd command = RDA + MRS) When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The K4C89183AF have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields. - 50 - REV. 0.7 Jan. 2005 K4C89183AF The four fields are as follows : (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) CAS Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has two function fields. The two fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. (E-3) Data Strobe Select Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation. • Regular Mode Register/Extended Mode Register change bits (BA0, BA1) These bits are used to choose either Regular MRS or Extended MRS BA1 BA0 A14~A0 0 0 Regular MRS cycle 0 1 Extended MRS cycle 1 X Reserved Regular Mode Register Fields (R-1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 4 words. A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 1 Reserved 0 1 0 4 words 0 1 1 Reserved 1 X X Reserved (R-2) Burst Type field (A3) This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words. A3 Burst Type 0 Sequential 1 Interleave • Addressing sequence of Sequential mode (A3) A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. - 51 - REV. 0.7 Jan. 2005 K4C89183AF CAS Latency = 4 (Free Running QS mode) CK CK Command RDA LAL QS DQ Data 0 Data 1 Data 2 Data 3 Addressing sequence for Sequential mode Data Access Address Data 0 n Data 1 n+1 Data 2 n+2 Data 3 n+3 Burst Length 4 words(Address bits is LA1, LA0) not carried from LA1~LA2 Functional Description (Continued) • Addressing sequence of Inteleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. Addressing sequence for Interleave mode Data Access Address Data 0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 Burst Length Data 1 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 4 words (R-3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of clock which should input write data is CAS Latency cycles - 1. Addressing sequence for Interleave mode A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 - 52 - REV. 0.7 Jan. 2005 K4C89183AF (R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation. (R-5) Reserved field in the Regular Mode Register • Reserved bits (A8 to A14) These bits are reserved for future operations. They must be set to "0" for normal operation. Extended Mode Register Fields (E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled. (E-2) Output Driver Impedance Control field (A1 to A4) This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength. QS DQ Output Driver Impedance Control A4 A3 A2 A1 0 0 0 0 0 1 0 1 Strong Output Driver 1 0 1 0 Weaker Output Driver 1 1 1 1 Reserved Normal Output Driver (E-3) Strobe Select (A6/A5) Two types of strobe are supported. This field is used to choose the type of data strobe. (1) Unidirectional DS/QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data at Read operation. (2) Unidirectional DS/Free running QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data and always clocking A6 A5 Strobe Select 0 0 Reserved 0 1 Reserved 1 0 Unidirectional DS/QS mode 1 1 Unidirectional DS/Free running QS mode (E-4)Reserved fied (A7 to A14) These bits are reserved for future operations and must be set to "0" for normal operation. - 53 - REV. 0.7 Jan. 2005 K4C89183AF Package Outline Drawing (FBGA 60ball, 1.0 x 1.0 mm) 10.50 ± 0.10 #A1 1.00 x 5 = 5.00 #A1 Mark (Option) 0.10 Max 2.50 1.50 1.50 Window Mold Area 6 10.50 ± 0.10 5 4 3 2 1.00 1 1.00 A B C 1.00 G H 0.5 ± 0.05 15.50 ± 0.10 15.50 ± 0.10 F J 15.50 ± 0.10 E 1.00 x 14 = 14.00 7.00 D 7.00 K L M N P R 0.35 ± 0.05 TOP VIEW 1.10± 0.10 - 54 - 60 - ∅0.45 solder ball BOTTOM VIEW REV. 0.7 Jan. 2005 K4C89183AF General Information Organization F6 (667Mbps@CL6) FB (600Mbps@CL6 ) F5 (500Mbps@CL6 ) 288M(x9) K4C89093AF-ACF6 K4C89093AF-ACFB K4C89093AF-AC(I)F5 288M(x18) K4C89183AF-ACF6 K4C89183AF-ACFB K4C89183AF-AC(I)F5 288M(x36) K4C89363AF-GCF6 K4C89363AF-GCFB K4C89363AF-GC(I)F5 1 5 2 3 4 6 7 8 9 10 11 K 4 C XX XX X X X - X X XX Memory Speed DRAM Temperature & Power Small Classification Package Density and Refresh Version Organization Bank Interface (VDD & VDDQ) 1. SAMSUNG Memory : K 8. Version F : 7th Generation 2. DRAM : 4 3. Small Classification C : Network-DRAM 9. Package A : 60 FBGA G : 144 FBGA 4. Density & Refresh 89 : 288M 8K/32ms 10. Temperature & Power C : (Commercial, Normal) I : (Industrial, Normal) 5. Organization 08 09 16 18 : x8 : x9 : x16 : x18 11. Speed F6 : 667Mbps/pin (333MHz, CL=6) FB : 600Mbps /pin (300MHz, CL=6) F5 : 500Mbps/pin (250MHz, CL=6) 6. Bank 3 : 4 Bank 7. Interface (VDD & VDDQ) A: SSTL-2(2.5V, 1.8V) - 55 - REV. 0.7 Jan. 2005