ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 Low-Power Bidirectional I2C Isolators Check for Samples: ISO1540, ISO1541 • • • • • • Isolated Bidirectional, I C Compatible, Communications Supports up to 1 MHz Operation 3-V to 5.5-V Supply Range Open Drain Outputs with 3.5-mA Side 1 and 35-mA Side 2 Sink Current Capability -40°C to 125°C Operating Temperature ±50 kV/µs Transient Immunity (Typical) HBM ESD Protection of 4 kV on All Pins; 8 kV on Bus Pins APPLICATIONS • • • • • • Isolated I2C Bus SMBus and PMBus Interfaces Open-drain Networks Motor Control Systems Battery Management I2C Level Shifting SAFETY AND REGULATORY APPROVALS • • • • 4000-VPK Isolation per DIN EN 60747-5-2 (VDE 0884 Part 2) (Pending) 2500-VRMS Isolation for 1 minute per UL 1577 (Approved) CSA Component Acceptance Notice 5A (Pending) IEC 60950-1 and IEC 61010-1 End Equipment Standards (Pending) ISO1540 VCC1 1 SDA1 2 SCL1 3 GND1 4 Side 1 Side 2 ISO1541 8 VCC2 VCC1 1 7 SDA2 SDA1 2 6 SCL2 SCL1 3 5 GND2 GND1 4 8 VCC2 Isolation • 2 2 Isolation FEATURES 1 7 SDA2 6 SCL2 5 GND2 Side 1 Side 2 DESCRIPTION The ISO1540 and ISO1541 are low-power, bidirectional isolators that are compatible with I2C interfaces. These devices have their logic input and output buffers separated by TI’s Capacitive Isolation technology using a silicon dioxide (SiO2) barrier. When used in conjunction with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. This isolation technology provides for function, performance, size, and power consumption advantages when compared to opto-couplers. The ISO1540 and ISO1541 enable a complete isolated I2C interface to be implemented within a small form factor. The ISO1540 has two isolated bidirectional channels for clock and data lines while the ISO1541 has a bidirectional data and a unidirectional clock channel. The ISO1541 is useful in applications that have a single Master while the ISO1540 is ideally fit for multi-master applications. Isolated bidirectional communications is accomplished within these devices by offsetting the Side 1 Low-Level Output Voltage to a value greater than the Side 1 High-Level Input Voltage thus preventing an internal logic latch that otherwise would occur with standard digital isolators. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of NXP B.V Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated ISO1540 ISO1541 SLLSEB6 – JULY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN FUNCTIONS ISO1540 and ISO1541 I/O NAME PIN VCC1 1 - - SDA1 2 I/O I/O SCL1 3 I/O I Serial Clock Input/Output, Side 1 Serial Clock Input, Side 1 GND1 4 - - Ground, Side 1 Ground, Side 1 GND2 5 - - Ground, Side 2 Ground, Side 2 SCL2 6 I/O O Serial Clock Input/Output, Side 2 Serial Clock Output, Side 2 SDA2 7 I/O I/O VCC2 8 - - DESCRIPTION ISO1540 ISO1541 ISO1540 ISO1541 Supply Voltage, Side 1 Supply Voltage, Side 1 Serial Data, Side 1 Input/Output Serial Data, Side 1 Input/Output Serial Data Input/Output, Side 2 Serial Data Input/Output, Side 2 Supply Voltage, Side 2 Supply Voltage, Side 2 AVAILABLE OPTIONS PRODUCT RATED ISOLATION PACKAGE ISO1540 4000-VPK and 2500-VRMS (1) MARKED AS Both SDA and SCL are Bidirectional IS1540 SDA is Bidirectional SCL is Unidirectional IS1541 ORDERING NUMBER ISO1540D (rail) ISO1540DR (reel) D-8 ISO1541 (1) CHANNEL DIRECTION ISO1541D (rail) ISO1541DR (reel) See the Regulatory Information table for detailed Isolation specifications. Table 1. FUNCTION TABLE (1) (1) (2) 2 POWER STATE INPUT OUTPUT Z VCC1 or VCC2 < 2.1 V X VCC1 and VCC2 > 2.8 V L L VCC1 and VCC2 > 2.8 V H Z VCC1 and VCC2 > 2.8 V Z (2) ? H = High Level; L = Low Level; Z = High Impedance or Float; X = Irrelevant; ? = Indeterminate Invalid input condition as an I2C system requires that a pull-up resistor to VCC is connected. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 ABSOLUTE MAXIMUM RATINGS (1) (2) VALUES MIN Supply voltage Output current Electrostatic Discharge VCC1, VCC2 –0.5 6 V SDA1, SCL1 –0.5 VCC1 + 0.5 V SDA2, SCL2 –0.5 VCC2 + 0.5 V SDA1, SCL1 ±20 mA SDA2, SCL2 ±100 mA Bus Pins ±8 kV All Pins ±4 Human Body Model ESDA, JEDEC JS-001-2012 Field-Induced-Charged Device Model JEDEC JESD22-C101E Machine Model JEDEC JESD22-A115-A TJ(MAX) Maximum junction temperature TSTG Storage temperature range (1) (2) UNIT MAX ±1.5 All Pins –65 kV ±200 V 150 °C 150 °C Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability. All voltage values here within are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values. THERMAL INFORMATION ISO1540 ISO1541 THERMAL METRIC (1) UNITS D (8 PINS) θJA Junction-to-ambient thermal resistance 114.6 θJCtop Junction-to-case (top) thermal resistance 69.6 θJB Junction-to-board thermal resistance 55.3 ψJT Junction-to-top characterization parameter 27.2 ψJB Junction-to-board characterization parameter 54.7 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VCC1, VCC2 Supply Voltage 3 5.5 VSDA1, VSCL1 Input/Output Signal Voltages, Side 1 0 VCC1 VSDA2, VSCL2 Input/Output Signal Voltages, Side 2 0 VCC2 VIL1 Low-Level Input Voltage, Side 1 0 0.5 VIH1 High-Level Input Voltage, Side 1 0.7 x VCC1 VCC1 VIL2 Low-Level Input Voltage, Side 2 0 0.3 x VCC2 VIH2 High-Level Input Voltage, Side 2 0.7 x VCC2 VCC2 IOL1 Output Current, Side 1 0.5 3.5 IOL2 Output Current, Side 2 0.5 35 Cb1 Maximum Capacitive Load, Side 1 40 Cb2 Maximum Capacitive Load, Side 2 400 fMAX Maximum Operating Frequency TA Ambient Temperature –40 125 °C TJ Junction Temperature –40 136 °C TSD Thermal Shutdown 139 171 °C (1) V mA pF (1) 1 MHz This represents the maximum frequency with the maximum bus load (Cb) and the maximum current sink (IO). If the system has less bus capacitance, then higher frequencies can be achieved. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 3 ISO1540 ISO1541 SLLSEB6 – JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX 2.4 3.6 2.1 3.3 1.7 2.7 2.5 3.8 2.3 3.6 1.9 3.1 3.1 4.7 2.8 4.4 2.3 3.7 3.1 4.7 2.9 4.5 2.5 4 MIN TYP MAX UNIT SUPPLY CURRENT (3V ≤ VCC1, VCC2 ≤ 3.6V) ICC1 Supply Current, Side 1 ICC2 Supply Current, Side 2 ICC1 Supply Current, Side 1 ICC2 Supply Current, Side 2 ISO1540 ISO1541 ISO1540 and ISO1541 ISO1540 ISO1541 ISO1540 and ISO1541 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2 See Figure 1; R1,R2 = Open, C1,C2 = Open mA SUPPLY CURRENT (4.5 V ≤ VCC1, VCC2 ≤ 5.5 V) ICC1 Supply Current, Side 1 ICC2 Supply Current, Side 2 ICC1 Supply Current, Side 1 ICC2 Supply Current, Side 2 ISO1540 ISO1541 ISO1540 and ISO1541 ISO1540 ISO1541 ISO1540 and ISO1541 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2 PARAMETER See Figure 1; R1,R2 = Open, C1,C2 = Open TEST CONDITIONS mA UNIT SIDE 1 (Only) VILT1 Voltage Input Threshold “Low”, Side 1 (SDA1, SCL1) 500 550 660 VIHT1 Voltage Input Threshold “High”, Side 1 (SDA1, SCL1) 540 610 700 VHYST1 Voltage Input Hysteresis, Side 1 VIHT1- VILT1 40 60 VOL1 Low-Level Output Voltage, Side 1 (SDA1,SCL1) (1) ΔVOIT1 (1) (2) 650 Low-Level Output Voltage to High-Level Input Voltage Threshold Difference, Side 1 (SDA1, SCL1) 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA mV 800 50 SIDE 2 (Only) VILT2 Voltage Input Threshold “Low”, Side 2 (SDA2, SCL2) 0.3 x VCC2 0.4 x VCC2 VIHT2 Voltage Input Threshold “High”, Side 2 (SDA2, SCL2) 0.4 x VCC2 0.5 x VCC2 VHYST2 Voltage Input Hysteresis, Side 2 VIHT2 - VILT2 0.05 x VCC2 VOL2 Low-Level Output Voltage, Side 2 (SDA2, SCL2) 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 35 mA |II| Input Leakage Currents (SDA1, SCL1, SDA2, SCL2) VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2 0.01 CI Input Capacitance to Local Ground (SDA1, SCL1, SDA2, SCL2) VI = 0.4 x sin(2E6πt) + 2.5 V 7 pF CMTI Common-Mode Transient Immunity See Figure 3 25 50 kV/µs VCCUV (3) VCC Undervoltage Lockout Threshold (Side 1 and Side 2) 2.1 2.5 mV 400 BOTH SIDES (1) (2) (3) 4 10 2.8 µA V This parameter does not apply to the ISO1541 SCL1 line as it is uni-directional. ∆VOIT1 = VOL1 – VIHT1. This represents the minimum difference between a Low-Level Output Voltage and a High-Level Input Voltage Threshold to prevent a permanent latch condition that would otherwise exist with bi-directional communication. Any VCC voltages, on either side, less than the minimum will ensure device lockout. Both VCC voltages above the maximum will prevent device lockout. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 SWITCHING CHARACTERISTICS Over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 V ≤ VCC1, VCC2 ≤ 3.6 V Output Signal Fall Time (SDA1, SCL1) See Figure 1 R1 = 953 Ω, C1 = 40 pF 0.7 x VCC1 to 0.3 x VCC1 tf1 tf2 Output Signal Fall Time (SDA2, SCL2) See Figure 1 R2 = 95.3 Ω, C2 = 400 pF tpLH1-2 Low-to-High Propagation Delay, Side 1 to Side 2 tPHL1-2 High-to-Low Propagation Delay, Side 1 to Side 2 PWD1-2 Pulse Width Distortion |tpHL1-2 – tpLH1-2| tPLH2-1 (1) Low-to-High Propagation Delay, Side 2 to Side 1 tPHL2-1 (1) High-to-Low Propagation Delay, Side 2 to Side 1 PWD2-1 (1) Pulse Width Distortion |tpHL2-1 – tpLH2-1| tLOOP1 (1) Round-trip propagation delay on Side 1 See Figure 1 R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF See Figure 2; R1 = 953 Ω, C1 = 40 pF R2 = 95.3 Ω, C2 = 400 pF 8 17 29 0.9 x VCC1 to 900 mV 16 29 48 0.7 x VCC2 to 0.3 x VCC2 14 23 47 0.9 x VCC2 to 400 mV 35 50 100 0.55 V to 0.7 x VCC2 33 65 ns 0.7 V to 0.4 V 90 181 ns 55 123 ns 0.4 x VCC2 to 0.7 x VCC1 47 68 ns 0.4 x VCC2 to 0.9 V 67 109 ns 20 49 ns 100 165 ns 6 11 20 0.4 V to 0.3 x VCC1 ns ns 4.5V ≤ VCC1, VCC2 ≤ 5.5V Output Signal Fall Time (SDA1, SCL1) See Figure 1 R1 = 1430 Ω, C1 = 40 pF 0.7 x VCC1 to 0.3 x VCC1 tf1 0.9 x VCC1 to 900 mV 13 21 39 Output Signal Fall Time (SDA2, SCL2) See Figure 1 R2 = 143 Ω, C2 = 400 pF 0.7 x VCC2 to 0.3 x VCC2 10 18 35 tf2 0.9 x VCC2 to 400 mV 28 41 76 tpLH1-2 Low-to-High Propagation Delay, Side 1 to Side 2 0.55 V to 0.7 x VCC2 31 62 ns tPHL1-2 High-to-Low Propagation Delay, Side 1 to Side 2 0.7 V to 0.4 V 70 139 ns PWD1-2 Pulse Width Distortion |tpHL1-2 – tpLH1-2| 38 80 ns tPLH2-1 (1) Low-to-High Propagation Delay, Side 2 to Side 1 0.4 x VCC2 to 0.7 x VCC1 55 80 ns tPHL2-1 (1) High-to-Low Propagation Delay, Side 2 to Side 1 0.4 x VCC2 to 0.9 V 47 85 ns PWD2-1 (1) Pulse Width Distortion |tpHL2-1 – tpLH2-1| 8 21 ns tLOOP1 (1) Round-trip propagation delay on Side 1 110 180 ns MAX UNIT (1) See Figure 1 R1 = 1430 Ω, R2 = 143 Ω, C1, 2 = 10 pF See Figure 2; R1 = 1430 Ω, C1 = 40 pF R2 = 143 Ω, C2 = 400 pF 0.4 V to 0.3 x VCC1 ns ns This parameter does not apply to the ISO1541 SCL1 line as it is uni-directional. TIMING CHARACTERISTICS PARAMETER TEST CONDITIONS tSP Input Noise Filter tUVLO Time to recover from Undervoltage Lock-out See Figure 4 2.7 V to 0.9 V MIN TYP 5 12 30 50 ns 110 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 µs 5 ISO1540 ISO1541 SLLSEB6 – JULY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC1 R1 + + R1 R2 VCC2 R2 SDA1 SDA2 ISO1540/1 SCL1 SCL2 C1 C1 C2 C2 Figure 1. Test Diagram VCC1 + SDA1 or SCL1 Output - R1 C1 R2 Isolation VCC1 GND1 VCC2 SDA1 SCL1 [ISO1540 Only] C2 tLOOP 1 0.3VCC1 0.4V GND1 GND2 Figure 2. tLoop1 Setup and Timing Diagram VCCx VCCy 2 kW 2 kW Isolation Input + Output GNDx GNDy VCMTI Figure 3. Common-Mode Transient Immunity Test Circuit 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 PARAMETER MEASUREMENT INFORMATION (continued) VCCx VCCy VCCx Ry SDAx or SCLx Isolation 0V Side x, Side y Vccx, Vccy Ry 1, 2 3.3V, 3.3V 95.3Ω 2, 1 3.3V, 3.3V 953Ω + Output - GNDx GNDy or VCCx VCCy VCCy Ry 0V Isolation SDAx or SCLx + Output - GNDx GNDy VCCx or VCCy 2.7V tUVLO 0.9V Output Figure 4. tUVLO Test Circuit and Timing Diagrams Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 7 ISO1540 ISO1541 SLLSEB6 – JULY 2012 www.ti.com DEVICE INFORMATION Table 2. IEC INSULATION AND SAFETY-RELATED SPECIFICATION FOR D-8 PACKAGE Over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface CTI Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 >400 V Minimum internal gap (internal clearance) Distance through the insulation 0.014 mm RIO Isolation resistance, input to output (1) CIO Barrier capacitance, input to output (1) CI Input capacitance (2) (1) (2) 4.8 mm 4.3 mm VIO = 500 V, TA < 100°C >1012 Ω VIO = 500 V, 100°C ≤ TA >1011 Ω 1 pF VIO = 0.4 x sin(2E6πt) See Electrical Characteristics pF All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. spacer NOTE Creepage and clearance requirements should be applied according to the specific application isolation standards. Care should be taken to maintain these distances on a board design to ensure that the mounting pads for the isolator do not reduce this distance. Creepage and clearance on the printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on the printed circuit board are used to help increase these specifications. Table 3. IEC 60747-5-2 INSULATION CHARACTERISTICS (1) Over recommended operating conditions, unless otherwise noted PARAMETER VIORM TEST CONDITIONS SPECIFICATION Maximum working insulation voltage 566 Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 sec, Partial Discharge < 5 pC Method b1, After environmental tests subgroup 1, Input-to-Output test voltage per IEC VPR = VIORM x 1.875, t = 1 sec (100% production), 60747-5-2 Partial Discharge < 5 pC VPR 906 1062 After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 sec, Partial Discharge < 5 pC 680 VIOTM Transient overvoltage per IEC 60747-5-2 VTEST = VOITM t = 60 sec (qualification) t = 1 sec (100% production) 4000 RS Insulation resistance VIO = 500 V at TS >109 Pollution degree (1) 8 UNIT VPEAK Ω 2 Climatic Classification 40/125/21 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 Table 4. IEC 60664-1 RATINGS TABLE PARAMETER Basic isolation group Installation classification TEST CONDITIONS SPECIFICATION Material group II Rated mains voltage ≤ 150 VRMS I–IV Rated mains voltage ≤ 300 VRMS I–III Rated mains voltage ≤ 400 VRMS I–II Table 5. REGULATORY INFORMATION VDE CSA UL Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2) and EN 61010-1 Approved under CSA Component Acceptance Notice #5A, CSA/IEC 60950-1 & CSA/IEC 61010-1 Basic Insulation Maximum Transient Overvoltage, 4000 VPK Maximum Surge Voltage, 4000 VPK Maximum Working Voltage, 566 VPK Basic insulation per CSA 60950-1-07 and IEC 60950-1 (2nd Ed), 390 VRMS maximum working voltage Basic insulation per CSA 61010-1-04 and IEC 61010-1 Single Protection Isolation Voltage, (2nd Ed), 300 VRMS maximum working voltage 2500 VRMS (1) Reinforced insulation per CSA 61010-1-04 and IEC 61010-1 (2nd Ed), 150 VRMS maximum working voltage File number: 40016131 (pending) File number: 220991 (pending) (1) Recognized under UL 1577 Component Recognition Program File number: E181974 Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577. IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER IS Safety input, output, or supply current TS Maximum case temperature TEST CONDITIONS D-8 MIN TYP MAX θJA = 114.6°C/W, VI = 5.5V, TJ = 150°C, TA = 25°C 198 θJA = 114.6°C/W, VI = 3.6V, TJ = 150°C, TA = 25°C 303 150 UNIT mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. ISO154x THERMAL DERATING 350 VCC1 = VCC2 = 3.6 V Safety Limiting Current (mA) 300 250 200 VCC1 = VCC2 = 5.5 V 150 100 50 0 0 50 100 150 200 o Case Temperature ( C) Figure 5. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 9 ISO1540 ISO1541 SLLSEB6 – JULY 2012 www.ti.com APPLICATION INFORMATION I2C™ Bus Overview The I2C (Inter-Integrated Circuit) bus is a single-ended, multi-master, 2-wire bus for efficient inter-IC communication in half-duplex mode. I2C uses open-drain technology, requiring two lines, Serial Data (SDA) and Serial Clock (SCL), to be connected to VDD by resistors (see Figure 6). Pulling the line to ground is considered a logic Zero while letting the line float is a logic One. This is used as a channel access method. Transitions of logic states must occur while SCL is Low, transitions while SCL is high indicate START and STOP conditions. Typical supply voltages are 3.3 V and 5 V, although systems with higher or lower voltages are permitted. VDD RPU RPU RPU RPU RPU RPU RPU RPU SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL GND GND GND GND μC Master ADC Slave DAC Slave μC Slave Figure 6. I2C BUS I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112 nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified, total bus capacitance of 400 pF, which restricts communication distances to a few meters. The specified signaling rates for the ISO1540 and ISO1541 are 100 kbps (Standard mode), 400 kbps (Fast mode), 1 Mbps (Fast mode plus). The bus has two roles for nodes: master and slave. A master node issues the clock, slave addresses, and also initiates and ends data transactions. A slave node receives the clock and addresses and responds to requests from the master. Figure 7 shows a typical data transfer between master and slave. 7-bit ADDRESS SDA SCL R/W ACK 8 9 1 -7 8-bit DATA 1 -8 ACK 9 8-bit DATA 1 -8 ACK / NACK 9 S P START Condition STOP condition Figure 7. Timing Diagram of a Complete Data Transfer The master initiates a transaction by creating a START condition, following by the 7-bit address of the slave it wishes to communicate with. This is followed by a single Read/Write bit, representing whether the master wishes to write to (0), or to read from (1) the slave. The master then releases the SDA line to allow the slave to acknowledge the receipt of data. The slave responds with an acknowledge bit (ACK) by pulling SDA low during the entire high time of the 9th clock pulse on SCL, after which the master continues in either transmit or receive mode (according to the R/W bit sent), while the slave continues in the complementary mode (receive or transmit, respectively). 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by a high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of SDA while SCL is high. If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the master is in master-transmit mode and the slave is in slave-receive mode. If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the receipt of every byte but the last one (see Figure 8). In this situation the master is in master-receive mode and the slave is in slave-transmit mode. The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for further transfers. S Slave Address W A From Master to Slave DATA A DATA AP A = acknowledge A = not acknowledge Master Transmitter writing to Slave Receiver S = Start From Slave to Master P = Stop S Slave Address R A DATA A DATA AP Master Receiver reading from Slave Transmitter R = Read W = Write Figure 8. Transmit or Receive Mode Changes During a Data Transfer When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when receiving acknowledgment from the slave. When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a transaction. Note, that the master ends a reading sequence by not acknowledging (NACK) the last byte received. This procedure resets the slave state machine and allows the master to send the STOP command. Isolator Functional Principle To isolate a bidirectional signal path (SDA or SCL), the ISO1540 internally splits a bidirectional line into two unidirectional signal lines, each of which is isolated via a single-channel digital isolator. Each channel output is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1540 connects to a lowcapacitance I2C node, while Side 2 is designed for connecting to a fully loaded I2C bus with up to 400 pF capacitance. VCC1 VCC2 A RPU1 RPU2 B SDA1 VC-out SDA2 ISO1540 Cnode 40mV Cbus C 50mV D GND1 VREF VSDA1 GND2 VILT1 VIHT1 VOL1 Figure 9. SDA Channel Design and Voltage Levels at SDA1 At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up. However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode drop to approximately 0.75 V, and the input buffer (C) that consists of a comparator with defined hysteresis. The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V maximum driven directly by SDA1 and the buffered output low-level of B. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 11 ISO1540 ISO1541 SLLSEB6 – JULY 2012 www.ti.com Figure 10 demonstrate the switching behavior of the I2C isolator, ISO1540, between a master node at SDA1 and a heavy loaded bus at SDA2 VCC2 SDA2 VCC1 VCC1 VCC2 VOL1 SDA1 50% VIHT1 30% receive delay VCC1 receive delay transmit delay VCC1 VCC2 VCC2 transmit delay SDA1 receive delay VIHT2 SDA2 50% 30% Figure 10. SDA Channel Timing in Receive and Transmit Directions Receive Direction (left diagram) When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. Its output low will be the buffered output of VOL1 = 0.75 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum input-low voltage of VIL = 0.9 V at 3 V supply levels. Once SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed by RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the time-constant RPU1 x Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before SDA2 reaches VCC2 potential. Transmit Direction (right diagram) When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns low it also causes the output of buffer B to turn low but at a higher 0.75 V level. This level cannot be observed immediately as it is overwritten by the master’s lower low-level. However, when the master releases SDA1, its voltage potential increases and first must pass the upper input threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered output level of VOL1 = 0.75 V, maintained by the receive path. Once comparator C turns high, SDA2 is released after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases SDA1 to move towards VCC1 potential. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 Typical Application Circuit VS 3.3V 0.1μF 2 Vcc D2 3 1:2.2 MBR0520L 1 SN6501 GND D1 10μF 0.1μF 4,5 OUT 5 ON GND 5VISO 0.1μF 8 VDD 10μF LP2981-50 3 1 10μF IN 9 2 10 1Ω 1 MBR0520L SDA 0.1μF 0.1μF 1.5k 2 5 6 DVcc XOUT MSP430 XIN G2132 SDA SCL 9 8 DVss 4 0.1μF 1.5k 1.5k 1.5k 1 8 VCC1 VCC2 2 7 SDA1 SDA2 ISO1541 3 6 SCL1 SCL2 GND1 GND2 4 5 SCL SDA 5VISO 4 4 Analog Inputs SCL ADS1115 ADDR GND RDY 3 ISO-BARRIER AIN0 AIN3 7 2 5VISO 6 22μF 0.1μF VOUT REF5040 15 4 12 3 A2 VDD IOVDD VREFH 11 1 SDA VOUTA 10 SCL DAC8574 9 LDAC 14 A1 VOUTD 8 A0 A3 GND VREFL 13 16 6 5VISO 2 VIN 1μF GND 4 4 Analog Outputs 5 Figure 11. Isolated I2C Data Acquisition System In Figure 11, the ultra low-power micro controller, MSP430G2132, controls the I2C data traffic of configuration data and conversion results for the analog inputs and outputs. Low-power data converters build the analog interface to sensors and actuators. The ISO1541 provides the necessary isolation between different ground potentials of the system controller, remote sensor, and actuator circuitry to prevent ground loop currents that otherwise may falsify the acquired data. The entire circuit operates from a single 3.3 V supply. A low-power push-pull converter, SN6501, drives a centertapped transformer whose output is rectified and linearly regulated to provide a stable 5 V supply for the data converters. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 13 ISO1540 ISO1541 SLLSEB6 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS SIDE 1 OUTPUT LOW VOLTAGE vs FREE-AIR TEMPERATURE SIDE 1 OUTPUT LOW CURRENT vs SDA1 or SCL1 APPLIED VOLTAGE 3.0 0.800 o 0.760 0.740 IOL1 = 3.5 mA 0.720 0.700 TA = 25 C 2.5 Output Current, IOL1 (mA) Output Voltage, VOL1 (V) 0.780 IOL1 = 0.5 mA 0.680 0.660 0.640 2.0 1.5 1.0 0.5 0.0 0.620 -0.5 0.600 95 110 125 0 0.5 0.6 0.7 SIDE 1 OUTPUT FALL TIME vs FREE-AIR TEMPERATURE 18 16 14 14 12 10 8 VCC1 = 3.3 V C1 = 40 pF Fall Time measured from 70% to 30% VCC1 0 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 8 6 2 VCC1 = 5 V C1 = 40 pF Fall Time measured from 70% to 30% VCC1 0 −40 −25 −10 110 125 G001 R1 = 1430 Ω R1 = 2.2 kΩ 5 20 35 50 65 80 Free-Air Temperature (°C) 95 SIDE 2 OUTPUT FALL TIME vs FREE-AIR TEMPERATURE SIDE 2 OUTPUT FALL TIME vs FREE-AIR TEMPERATURE 30 25 25 Fall Time, tf2 (ns) 30 20 15 10 95 20 15 10 5 R2 = 95.3 Ω R2 = 2.2 kΩ 110 125 110 125 G002 Figure 15. 5 20 35 50 65 80 Free-Air Temperature (°C) 0.9 10 4 R1 = 953 Ω R1 = 2.2 kΩ VCC2 = 3.3 V C2 = 400 pF Fall Time measured from 70% to 30% VCC2 0.8 12 Figure 14. 0 −40 −25 −10 VCC2 = 5 V C2 = 400 pF Fall Time measured from 70% to 30% VCC2 0 −40 −25 −10 G003 Figure 16. 14 0.4 SIDE 1 OUTPUT FALL TIME vs FREE-AIR TEMPERATURE 16 5 0.3 Figure 13. 20 2 0.2 Figure 12. 18 6 0.1 Applied Voltage, VSDA1, VSCL1 (V) 20 4 Fall Time, tf2 (ns) 5 20 35 50 65 80 Free−Air Temperature (°C) Fall Time, tf1 (ns) Fall Time, tf1 (ns) −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) R2 = 143 Ω R2 = 2.2 kΩ 95 110 125 G004 Figure 17. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 TYPICAL CHARACTERISTICS (continued) tPLH1-2 PROPAGATION DELAY vs FREE-AIR TEMPERATURE tPHL1-2 PROPAGATION DELAY vs FREE-AIR TEMPERATURE 40 120 C2 = 10 pF 35 30 25 20 15 10 VCC1 and VCC2 = 3.3 V, R2 = 95.3 Ω VCC1 and VCC2 = 5 V, R2 = 143 Ω 5 0 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 100 80 60 40 20 G005 Figure 19. tPLH1-2 PROPAGATION DELAY vs FREE-AIR TEMPERATURE tPHL1-2 PROPAGATION DELAY vs FREE-AIR TEMPERATURE 90 1045 80 1040 1035 1030 1025 1020 1015 1010 R2 = 2.2 kΩ C2 = 400 pF 1000 −40 −25 −10 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 5 20 35 50 65 80 Free-Air Temperature (°C) 95 95 110 125 G006 70 60 50 40 30 20 10 R2 = 2.2 kΩ C2 = 400 pF 0 −40 −25 −10 110 125 G007 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 5 20 35 50 65 80 Free-Air Temperature (°C) Figure 20. Figure 21. tPLH2-1 PROPAGATION DELAY vs FREE-AIR TEMPERATURE tPHL2-1 PROPAGATION DELAY vs FREE-AIR TEMPERATURE 70 95 110 125 G008 80 C1 = 10 pF C1 = 10 pF 60 Propagation Delay, tPHL2−1 (ns) Propagation Delay, tPLH2−1 (ns) 5 20 35 50 65 80 Free-Air Temperature (°C) Figure 18. 1050 1005 VCC1 and VCC2 = 3.3 V, R2 = 95.3 Ω VCC1 and VCC2 = 5 V, R2 = 143 Ω 0 −40 −25 −10 110 125 Propagation Delay, tPHL1−2 (ns) Propagation Delay, tPLH1−2 (ns) C2 = 10 pF Propagation Delay, tPHL1−2 (ns) Propagation Delay, tPLH1−2 (ns) 45 50 40 30 20 10 0 −40 −25 −10 VCC1 and VCC2 = 3.3 V, R1 = 953 Ω VCC1 and VCC2 = 5 V, R1 = 1430 Ω 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 70 60 50 40 30 20 10 0 −40 −25 −10 G009 Figure 22. VCC1 and VCC2 = 3.3 V, R1 = 953 Ω VCC1 and VCC2 = 5 V, R1 = 1430 Ω 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 G010 Figure 23. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 15 ISO1540 ISO1541 SLLSEB6 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) tPLH2-1 PROPAGATION DELAY vs FREE-AIR TEMPERATURE tPHL2-1 PROPAGATION DELAY vs FREE-AIR TEMPERATURE 148 Propagation Delay, tPHL2−1 (ns) Propagation Delay, tPLH2−1 (ns) 146 80 R1 = 2.2 kΩ C1 = 40 pF 144 142 140 138 136 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 134 132 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 70 60 50 40 30 20 10 R1 = 2.2 kΩ C1 = 40 pF VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 0 −40 −25 −10 110 125 5 20 35 50 65 80 Free-Air Temperature (°C) G011 Figure 24. 140 120 110 125 G012 Figure 25. tLOOP1 vs FREE-AIR TEMPERATURE tLOOP1 vs FREE-AIR TEMPERATURE 600 C1 = 40 pF C2 = 400 pF 595 tLOOP1 (ns) 100 tLOOP1 (ns) 95 80 60 R1 = 2.2 kΩ C1 = 40 pF R2 = 2.2 kΩ C2 = 400 pF 590 585 40 20 580 VCC1 and VCC2 = 3.3 V, R1 = 953Ω, R2 = 95.3Ω VCC1 and VCC2 = 5 V, R1 = 1430Ω, R2 = 143Ω 0 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 575 −40 −25 −10 110 125 G013 5 20 35 50 65 80 Free-Air Temperature (°C) Figure 26. 95 110 125 G014 Figure 27. CMTI vs FREE-AIR TEMPERATURE 70 60 CMTI (kV/µs) 50 40 30 20 10 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 0 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 G015 Figure 28. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 ISO1540 ISO1541 www.ti.com SLLSEB6 – JULY 2012 TYPICAL CHARACTERISTICS (continued) SIDE 1 LOW-TO-HIGH TRANSITION o 500 mV/div TA = 25 C VCC1 = 3.6 V 900 mV VOL1 GND1 Time - 50 ns/div Figure 29. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ISO1540 ISO1541 17 PACKAGE OPTION ADDENDUM www.ti.com 21-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ISO1540D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ISO1540DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ISO1541D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ISO1541DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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