CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 IDT72021 IDT72031 IDT72041 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • First-In/First-Out Dual-Port memory • Bit organization – IDT72021—1K x 9 – IDT72031—2K x 9 – IDT72041—4K x 9 • Ultra high speed – IDT72021—25ns access time – IDT72031—35ns access time – IDT72041—35ns access time • Easily expandable in word depth and/or width • Asynchronous and simultaneous read and write • Functionally equivalent to IDT7202/03/04 with Output Enable (OE) and Almost Empty/Almost Full Flag (AEF) • Four status flags: Full, Empty, Half-Full (single device mode), and Almost Empty/Almost Full (7/8 empty or 7/8 full in single device mode) • Output Enable controls the data output port • Auto-retransmit capability • Available in 32-pin DIP and PLCC • Military product compliant to MIL-STD-883, Class B • Industrial temperature range (-40oC to +85oC) is avail able, tested to military electrical specifications IDT72021/031/041s are high-speed, low-power, dual-port memory devices commonly known as FIFOs (First-In/FirstOut). Data can be written into and read from the memory at independent rates. The order of information stored and extracted does not change, but the rate of data entering the FIFO might be different than the rate leaving the FIFO. Unlike a Static RAM, no address information is required because the read and write pointers advance sequentially. The IDT72021/ 031/041s can perform asynchronous and simultaneous read and write operations. There are four status flags, (HF, FF, EF, AEF) to monitor data overflow and underflow. Output Enable (OE) is provided to control the flow of data through the output port. Additional key features are Write (W), Read (R), Retransmit (RT), First Load (FL), Expansion In (XI) and Expansion Out (XO). The IDT72021/031/041s are designed for those applications requiring data control flags and Output Enable (OE) in multiprocessing and rate buffer applications. The IDT72021/031/041s are fabricated using IDT’s CMOS technology. Military grade product is manufactured in compliance with the latest version of MIL-STD-883, Class B, for high reliability systems. FUNCTIONAL BLOCK DIAGRAM W DATA INPUT (D0–D8) 1 2 WRITE CONTROL RAM ARRAY 1024 x 9 2048 x 9 4096 x 9 WRITE POINTER READ POINTER 1024/ 2048/ 4096 OE THREESTATE BUFFERS R RESET LOGIC RS FL/RT DATA OUTPUTS (Q0–Q8) READ CONTROL EF FF FLAG LOGIC AEF XI EXPANSION LOGIC XO/HF 2677 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.09 DECEMBER 1996 DSC-2677/7 1 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 4 3 2 D5 VCC D4 VCC D3 D8 INDEX W PIN CONFIGURATIONS 32 31 30 1 D2 D1 5 6 29 28 D0 Q0 Q1 7 8 9 10 11 12 27 26 25 24 23 22 Q7 Q2 13 21 Q6 XI AEF FF J32-1 D6 D7 FL/RT RS OE EF XO/HF R Q4 Q5 GND Q3 Q8 GND 14 15 16 17 18 19 20 MILITARY AND COMMERCIAL TEMPERATURE RANGES VCC 1 32 VCC W 2 31 D4 D8 3 30 D5 D3 4 29 D6 D2 5 28 D7 D1 6 27 D0 7 26 XI AEF FF 8 9 24 10 23 FL/RT RS OE EF XO/HF D32-1 25 Q0 11 22 Q7 Q1 12 21 Q6 Q2 13 20 Q5 Q3 14 19 Q4 Q8 15 18 R GND 16 17 GND 2677 drw 03 2677 drw 02 PLCC TOP VIEW DIP TOP VIEW PIN DESCRIPTIONS Symbol Name I/O Description D0–D8 Inputs I RS Reset I W Write I When WRITE is LOW, data can be written into the RAM array sequentially, independent of READ. In order for WRITE to be active, FF must be HIGH. When the FIFO is full (FF-LOW), the internal WRITE operation is blocked. R Read I FL/RT When READ is LOW, data can be read from the RAM array sequentially, independent of WRITE. In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF-LOW), the internal READ operation is blocked. The three-state output buffer is controlled by the read signal and the external output control (OE). First Load/ I Retransmit Data inputs for 9-bit wide data. When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM array. HF and FF go HIGH, and AEF and EF go LOW. A reset is required before an initial WRITE after power-up. R and W must be HIGH during RS cycle. This is a dual-purpose input. In the single device configuration (XI grounded), activating retransmit (FL/RT-LOW) will set the internal READ pointer to the first location. There is no effect on the WRITE pointer. R and W must be HIGH before setting FL/RT LOW. Retransmit is not compatible with depth expansion. In the depth expansion configuration, FL/RT-LOW indicates the first activated device. XI Expansion In I OE Output Enable I FF Full Flag O When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH, the device is not full. EF Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the device is not empty. Almost-Empty/ Almost-Full Flag Expansion Out/ Half-Full Flag O When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH, the device is greater than 1/8 full, but less than 7/8 full. AEF XO/HF Q0–Q8 In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion, XI is connected to XO (expansion out) of the previous device. When OE is set HIGH, the data flow through the three-state output buffer is inhibited regardless of an active READ operation. A read operation does increment the read pointer in this situation. When OE is set LOW, Q0-Q8 are still in a HIGH impedance condition if no READ occurs. For a complete READ operation with data appearing on Q0-Q8, both R and OE should be asserted LOW. Outputs O O This is a dual purpose output. In the single device configuration (XI grounded), the device is more than half full when HF is LOW. In the depth expansion configuration (XO connected to XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array is filled. Data outputs for 9-bit wide data. 2677 tbl 01 5.09 2 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 STATUS FLAG MILITARY AND COMMERCIAL TEMPERATURE RANGES CAPACITANCE (TA = +25°C, f = 1.0 MHz) Number of Words in FIFO FF AEF HF EF 0 H L H L 1-255 1-511 H L H H 128-512 256-1024 512-2048 H H H H 1K 2K 4K 0 0 1-127 513-896 1025-1792 2049-3584 H H L H 897-1023 1793-2047 3585-4095 H L L H 1024 2048 4096 L L L H Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Condition VIN = 0V VOUT = 0V Max. 10 10 NOTE: 1. These parameters are sampled and not 100% tested. Unit pF pF 2677 tbl 03 RECOMMENDED DC OPERATING CONDITIONS 2677 tbl l 02 Min. Typ. Max. Unit VCCM Symbol Military Supply Voltage 4.5 5.0 5.5 V VCCC Commercial Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage Commercial 2.0 — — V VIH Input High Voltage Military 2.2 — — V VIL(1) Input Low Voltage Commercial and Military — — 0.8 V (1) ABSOLUTE MAXIMUM RATINGS Symbol Rating VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current Com’l. Mil. Unit –0.5 to +7.0 –0.5 to +7.0 V –55 to +125 °C –55 to +125 –65 to +135 °C –55 to +125 –65 to +155 °C 0 to +70 50 50 mA Parameter NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. 2677 tbl 05 NOTE: 2677 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 5.09 3 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS — IDT72021 (Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5V±10%, TA = –55°C to +125°C) IDT72021 Commercial tA =25,35ns Symbol IDT72021 Commercial tA =50ns IDT72021 Military tA =50ns Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Input Leakage Current (Any Input) –1 — 1 –10 — 10 –1 — 1 –10 — 10 µA ILO(2) Output Leakage Current –10 — 10 –10 — 10 –10 — 10 –10 — 10 µA VOH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — 2.4 — — 2.4 — — V VOL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 — — 0.4 — — 0.4 V ICC1(3,4) Active Power Supply Current Standby Current (R = W = RS = FL/RT = VIH) — — 120 — — 140 — 50 80 — 70 100 mA — — 12 — — 20 — 5 8 — 8 15 mA Power Down Current (All Input = VCC – 0.2V) — — 500 — — 900 — — 500 — — 900 µA ILI(1) ICC2(3) ICC3(3) Parameter IDT72021 Military tA =30,40ns Typ. Max. Unit 2677 tbl 06 DC ELECTRICAL CHARACTERISTICS — IDT72031, IDT72041 (Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5V±10%, TA = –55°C to +125°C) IDT72031 IDT72041 Commercial tA =35,50ns Symbol Min. Typ. Input Leakage Current (Any Input) –1 Output Leakage Current –10 VOH Output Logic “1” Voltage IOUT = –2mA VOL ICC1(3,5) ICC2(3) ICC3(3) ILI(1) ILO(2) Parameter IDT72031 IDT72041 Military tA =40,50ns Max. Min. — 1 –10 — 10 µA — 10 –10 — 10 µA 2.4 — — 2.4 — — V Output Logic “0” Voltage IOUT = 8mA — — 0.4 — — 0.4 V Active Power Supply Current — 75 120 — 100 150 mA Standby Current (R = W = RS = FL/RT = VIH) — 8 12 — 12 25 mA Power Down Current (All Input = VCC – 0.2V) — — 2 — — 4 mA NOTES: 1. Measurements with 0.4 ≤ VIN ≤ VCC. 2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 3. ICC measurements are made with OE = HIGH. 4. Tested at f = 20MHz. 5. Tested at f = 15.3 MHz. Typ. Max. Unit 2677 tbl 07 5.09 4 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS — IDT72021(1) (Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5V±10%, TA = –55°C to +125°C) Symbol Parameter Com’l Mil. Com’l Mil. Com’l & Mil. 72021L25 72021L30 72021L35 72021L40 72021L50 Min. Max. Min. Max. Min. Max. fS Shift Frequency Min. Max. — 28.5 — 25 — 22.2 — 20 Min. Max. Unit — 15 MHz tRC R Cycle Time 35 — 40 — 45 — 50 — 65 — ns tA Access Time — 25 — 30 — 35 — 40 — 50 ns 10 — 10 — 10 — 10 — 15 — ns 25 — 30 — 35 — 40 — 50 — ns 5 — 5 — 5 — 5 — 10 — ns 5 — 5 — 5 — 5 — 5 — ns 5 — 5 — 5 — 5 — 5 — ns tWR R Recovery Time R Pulse Width(2) R Pulse LOW to Data Bus at Low-Z(3) W Pulse HIGH to Data Bus at Low-Z(3,4) Data Valid from R Pulse HIGH R Pulse HIGH to Data Bus at High-Z(3) W Cycle Time W Pulse Width(2) W Recovery Time 10 — 10 — 10 — 10 — 15 — ns tDS Data Set-up Time 15 — 18 — 18 — 20 — 30 — ns tDH Data Hold Time 0 — 0 — 0 — 0 — 5 — ns tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tRSC tRS tRSS tRSR tRTC tRT tRTR tRSF1 tRSF2 tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tRF tWF tOEHZ tOELZ tAOE RS Cycle Time RS Pulse Width(2) RS Set-up Time RS Recovery Time RT Cycle Time RT Pulse Width(2) RT Recovery Time RS to EF and AEF LOW RS to HF and FF HIGH R LOW to EF LOW R HIGH to FF HIGH R Pulse Width After EF HIGH W HIGH to EF HIGH W LOW to EF LOW W LOW to HF LOW R HIGH to HF HIGH W Pulse Width after FF HIGH R HIGH to Transitioning AEF W LOW to Transitioning AEF OE HIGH to High-Z (Disable)(3) OE LOW to Low-Z (Enable)(3) OE LOW Data Valid (Q0–Q8) — 18 — 20 — 20 — 25 — 30 ns 35 — 40 — 45 — 50 — 65 — ns 25 — 30 — 35 — 40 — 50 — ns 35 — 40 — 45 — 50 — 65 — ns 25 — 30 — 35 — 40 — 50 — ns 25 — 30 — 35 — 40 — 50 — ns 10 — 10 — 10 — 10 — 15 — ns 35 — 40 — 45 — 50 — 65 — ns 25 — 30 — 35 — 40 — 50 — ns 10 — 10 — 10 — 10 — 15 — ns — 35 — 40 — 45 — 50 — 65 ns — 35 — 40 — 45 — 50 — 65 ns — 25 — 30 — 30 — 35 — 45 ns — 25 — 30 — 30 — 35 — 45 ns 25 — 30 — 35 — 40 — 50 — ns — 25 — 30 — 30 — 35 — 45 ns — 25 — 30 — 30 — 35 — 45 ns — 35 — 40 — 45 — 50 — 65 ns — 35 — 40 — 45 — 50 — 65 ns 25 — 30 — 35 — 40 — 50 — ns — 35 — 40 — 45 — 50 — 65 ns — 35 — 40 — 45 — 50 — 65 ns 0 12 0 15 0 17 0 20 0 25 ns 0 12 0 15 0 17 0 20 0 25 ns — 15 — 18 — 20 — 25 — 30 ns NOTES: 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum value are not allowed. 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode. 2677 tbl 08 5.09 5 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS — IDT72031, IDT72041(1) (Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5V±10%, TA = –55°C to +125°C) Com'l 72031L35 72041L35 Symbol Parameter Mil. Com'l and Mil. 72031L40 72041L40 72031L50 72041L50 Min. Max. Min. Max. Min. Max. Unit fS Shift Frequency — 22.2 — 20 — 15 MHz tRC R Cycle Time 45 — 50 — 65 — ns tA Access Time — 35 — 40 — 50 ns 10 — 10 — 15 — ns 35 — 40 — 50 — ns 5 — 5 — 10 — ns 5 — 5 — 5 — ns 5 — 5 — 5 — ns tWR R Recovery Time R Pulse Width(2) R Pulse LOW to Data Bus at Low-Z(3) W Pulse HIGH to Data Bus at Low-Z(3,4) Data Valid from R Pulse HIGH R Pulse HIGH to Data Bus at High-Z(3) W Cycle Time W Pulse Width(2) W Recovery Time 10 — 10 — 15 — ns tDS Data Set-up Time 18 — 20 — 30 — ns tDH Data Hold Time 0 — 0 — 5 — ns tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tRSC tRS tRSS tRSR tRTC tRT tRTR tRSF1 tRSF2 tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tRF tWF tOEHZ tOELZ tAOE RS Cycle Time RS Pulse Width(2) RS Set-up Time RS Recovery Time RT Cycle Time RT Pulse Width(2) RT Recovery Time RS to EF and AEF LOW RS to HF and FF HIGH R LOW to EF LOW R HIGH to FF HIGH R Pulse Width After EF HIGH W HIGH to EF HIGH W LOW to EF LOW W LOW to HF LOW R HIGH to HF HIGH W Pulse Width after FF HIGH R HIGH to Transitioning AEF W LOW to Transitioning AEF OE HIGH to High-Z (Disable)(3) OE LOW to Low-Z (Enable)(3) OE LOW Data Valid (Q0–Q8) NOTES: 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum value are not allowed. 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode. — 20 — 25 — 30 ns 45 — 50 — 65 — ns 35 — 40 — 50 — ns 45 — 50 — 65 — ns 35 — 40 — 50 — ns 35 — 40 — 50 — ns 10 — 10 — 15 — ns 45 — 50 — 65 — ns 35 — 40 — 50 — ns 10 — 10 — 15 — ns — 45 — 50 — 65 ns — 45 — 50 — 65 ns — 30 — 35 — 45 ns — 30 — 35 — 45 ns 35 — 40 — 50 — ns — 30 — 35 — 45 ns — 30 — 35 — 45 ns — 45 — 50 — 65 ns — 45 — 50 — 65 ns 35 — 40 — 50 — ns — 45 — 50 — 65 ns — 45 — 50 — 65 ns 0 17 0 20 0 25 ns 0 17 0 20 0 25 ns — 20 — 25 — 30 ns 2677 tbl 09 5.09 6 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES 5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure 1 1.1K TO OUTPUT PIN 30pF* 680Ω 2677 tbl 10 2677 drw 04 or equivalent circuit Figure 1. Output Load * Includes scope and jig capacitances. t RSC t RS RS t RSR t RSS W t RSS R t RSF1 AEF, EF t RSF2 HF, FF 2677 drw 05 Figure 2. Reset NOTES: 1. EF, FF, HF, and AEF may change status during Reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS. t RC t RPW t RR tA tA R t RLZ t DV Q 0 –Q 8 t RHZ DATA OUT VALID DATA OUT VALID t WC t WPW t WR W t DS D 0 –D 8 t DH DATA IN VALID DATA IN VALID 2677 drw 06 Figure 3. Asynchronous Write and Read Operation NOTE: 1. Assume OE is asserted LOW. 5.09 7 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 LAST WRITE IGNORED WRITE FIRST READ MILITARY AND COMMERCIAL TEMPERATURE RANGES ADDITIONAL READS FIRST WRITE R W t WFF t RFF FF 2677 drw 07 Figure 4. Full Flag From Last Write to First Read LAST READ IGNORED READ FIRST WRITE ADDITIONAL WRITES FIRST READ W R t REF t WEF EF tA (1) DATA OUT VALID VALID 2677 drw 08 Figure 5. Empty Flag From Last Read to First Write NOTE: 1. Assume OE is asserted LOW. tRTC tRT RT t RTR W,R AEF, HF, EF, FF FLAG VALID 2677 drw 09 Figure 6. Retransmit 5.09 8 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES W t WEF EF t RPE R 2677 drw 10 Figure 7. Empty Flag Timing Figure 9. Almost-Empty/Almost-Full Flag and Half-Full Timings R t RFF FF t WPF W 2677 drw 11 Figure 8. Full Flag Timing W R t RHF t WHF HALF–FULL HALF–FULL (1/2) (1/2) HF HALF–FULL + 1 t RF t WF (7/8 FULL) AEF AEF (7/8 FULL) ALMOST–FULL (7/8 FULL + 1) ALMOST–EMPTY (1/8 FULL–1) (1/8 FULL) ALMOST–EMPTY (1/8 FULL–1) 2677 drw 12 Figure 9. Almost-Empty/Almost-Full Flag and Half-Full Timings tRC tRR R TERMINATE READ CYCLE tA OE tRLZ Q0-8 SECOND READ BY CONTROLLING OE tAOE tOELZ tOEHZ DATA 1 DATA 1 tDV HIGH IMPEDANCE 2677 drw 13 Figure 10. Output Enable and Read Operation Timings 5.09 9 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION W R t XOH t XOL t XOL t XOH XO 2677 drw 14 Figure 11. Expansion Out t t XIR XI XI t W XIS WRITE TO FIRST PHYSICAL LOCATION t XIS R READ FROM FIRST PHYSICAL LOCATION 2677 drw 15 Figure 12. Expansion In OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION The IDT72021/031/041 is in the Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 13). (HALF–FULL FLAG) HF AEF WRITE (W) READ (R) 9 DATA IN (D) FULL FLAG (FF) 9 IDT 72021/031/041 RESET (RS) DATA OUT (Q) EMPTY FLAG (EF) RETRANSMIT (RT) OUTPUT ENABLE (OE) EXPANSION IN (XI) 2677 drw 16 Figure 13. Block Diagram of Single 1K/2K/4K x 9 FIFO 5.09 10 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF, HF, and AEF) can be detected from any one AEF 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES device. Figure 14 demonstrates an 18-bit word width by using two IDT72021/031/041 devices. Any word width can be attained by adding additional IDT72021/031/041s. HF AEF 9 HF 9 DATA IN (D) OUTPUT ENABLE (OE) WRITE (W) FULL FLAG (FF) IDT 72021/031/041 READ (R) IDT 72021/031/041 EMPTY FLAG (EF) RESET (RS) 9 RETRANSMIT (RT) 9 XI XI 18 DATA OUT (Q) 2677 drw 17 Figure 14. Block Diagram of 1K/2K/4K x 18 FIFO Memory Used in Width Expansion Configuration NOTE: 1. Flag detection is accomplished by monitoring the FF, EF, HF and AEF signals on either (any) device used in the width expansion configuration. Do not connect any output signals together. DEPTH EXPANSION (DAISY CHAIN) MODE The IDT72021/031/041 can easily be adapted to applications when the requirements are for greater than 1K/2K/4K words. Figure 15 demonstrates Depth Expansion using three IDT72021/031/041s. Any depth can be attained by adding additional devices. The IDT72021/031/041 operates in the Depth Expansion configuration when the following conditions are met: 1. The first device must be designed by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 15. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 15. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. For additional information refer to Tech Note 9: “Cascading FIFOs or FIFO Modules”. COMPOUND EXPANSION MODE The two expansion techniques described above can be applied together in a straight forward manner to achieve large FIFO arrays (see Figure 16). BIDIRECTIONAL MODE Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT72021/031/041s as shown in Figure 17. Care must be taken to assure that the appropriate flag is monitored by each system (i.e., FF is monitored on the device where W is used; EF is monitored on the device where R is used). Both Depth Expansion and Width Expansion may be used in this mode. DATA FLOW-THROUGH MODES Two types of flow-through modes are permitted: a read flow-through and write flow-through mode. For the read flowthrough mode (Figure 18), the FIFO permits the reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W, called the first write edge. It remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. In the interval of time that R was LOW, more words can be written to the FIFO (the subsequent writes after the first write edge will be deassert the Empty Flag); however, the same word (written on the first write edge), presented to the output bus as the read pointer, would not be incremented when R was LOW. On toggling R, the other words that are written to the FIFO will appear on the output bus as in the read cycle timings. 5.09 11 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line, being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W MILITARY AND COMMERCIAL TEMPERATURE RANGES line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. For additional information refer to Tech Note 8: “Operating FIFOs on Full and Empty Boundary Conditions” and Tech Note 6: “Designing with FIFOs”. TRUTH TABLES TABLE I—RESET AND RETRANSMIT Single Device Configuration/Width Expansion Mode RT XI 0 1 X 0 0 0 Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Unchanged 1 1 0 Increment(1) RS Mode Reset Retransmit Read/Write Inputs Increment(1) Outputs EF FF HF AEF 0 X 1 X 1 X 0 X X X X X NOTE: 1. Pointer will increment if flag is HIGH. 2677 tbl 11 TABLE II—RESET AND FIRST LOAD TRUTH TABLE Depth Expansion/Compound Expansion Mode Mode Reset First Device Reset All Other Devices Read/Write RS Inputs FL XI 0 0 0 1 (1) (1) 1 X (1) Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Location Zero X EF X Outputs FF 0 0 1 1 X X NOTE: 2677 tbl 12 1. XI is connected to XO of previous device. See Figure 15. RS = Reset Input FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output, XI = Expansion Input, HF = Half-Full Flag Output, AEF = Almost Empty/Almost Full Flag. XO R W FF D 9 9 IDT 72021/ 031/041 EF 9 Q FL VCC EF EMPTY XI XO FF FULL IDT 72021/ 031/041 9 FL XI XO FF 9 EF IDT 72021/ 031/041 RS FL XI 2677 drw 18 Figure 15. Block Diagram of 3K/6K/12K x 9 FIFO Memory (Depth Expansion) NOTE: 1. IDT only guarantees depth expansion with identical IDT part numbers and speed. 5.09 12 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES ••• IDT72021/ 031/041 DEPTH EXPANSION BLOCK R, W, RS IDT72021/ 031/041 DEPTH EXPANSION BLOCK D 0 –D N ••• Q 0 –Q N IDT72021/ 031/041 DEPTH EXPANSION BLOCK ••• 2677 drw 19 Figure 16. Compound FIFO Expansion NOTES: 1. For depth expansion block see section od Depth Expansion and Figure 15. 2. For Flag detection see section on Width Expansion and Figure 14. WA FFA IDT IDT 72021/ 7201A 031/041 DA 0-8 RB EF B HFB Q B 0-8 AEF SYSTEM A SYSTEM B Q A 0-8 RA HFA EF A D B 0-8 IDT 72021/ 031/041 WB FF B 2677 drw 20 AEF Figure 17. Bidirectional FIFO Mode DATA IN W t RPE R EF t REF t WEF t WLZ DATA OUT (1) tA DATA OUT VALID 2677 drw 21 Figure 18. Read Data Flow-Through Mode NOTE: 1. Assume OE is asserted LOW. 5.09 13 IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES R t WPF W t RFF FF t WFF DATA IN DATA IN VALID tA DATA OUT t DH t DS (1) DATA OUT VALID 2677 drw 22 Figure 19. Write Data Flow-Through Mode NOTE: 1. Assume OE is asserted LOW. ORDERING INFORMATION IDT XXXXX Device Type X X X X Power Speed Package Process/ Temperature Range Blank Commercial (0°C to+70°C) B Military (–55°C to+125°C) Compliant to MIL-STD-883, Class B D J CERDIP Plastic Leaded Chip Carrier 25 30 35 40 50 72021–Com’l. Only 72021–Mil. Only 72021/031/041–Com’l. Only 72021/031/041–Mil. Only 72021/031/041–Com'l & Mil. L Low Power 72021 72031 72041 1024 x 9-Bit FIFO 2048 x 9-Bit FIFO 4096 x 9-Bit FIFO Access Time (tA) Speed in Nanoseconds 2677 drw 23 5.09 14