EL1511 ® Data Sheet April 10, 2007 FN7016.2 Medium Power Differential Line Driver Features The EL1511 is a dual operational amplifier designed for customer premise line driving in DMT ADSL solutions. This device features a high drive capability of 360mA while consuming only 7.5mA of supply current per amplifier and operating from a single 5V to 15V supply. This driver achieves a typical distortion of less than -85dBc, at 150kHz into a 25Ω load. The EL1511 is available in the thermallyenhanced 16 Ld SOIC (0.150") and a 16 Ld QFN (4x4mm) packages. The EL1511 is specified for operation over the full -40°C to +85°C temperature range. Electrical characteristics are given for typical 15V supply operation. • Drives up to 360mA from a +15V supply The EL1511 has two control pins, C0 and C1, which allow the selection of full IS power, 3/4-IS, 1/2-IS, and power-down modes. Applications The EL1511 is ideal for ADSL, SDSL, and HDSL2 line driving applications for single power supply, high voltage swing, and low power. • ADSL full rate CPE line driving The EL1511 maintains excellent distortion and load driving capabilities even in the lowest power settings. • 24VP-P differential output drive into 25Ω and 26VP-P differential output drive into 100Ω • -85dBc typical driver output distortion at full output at 150kHz • Low quiescent current of 3.5mA per amplifier at 1/2-IS current mode • Disable down to 1.5mA • Pb-free plus anneal available (RoHS compliant) • ADSL CSA line driving • G.SHDSL, HDSL2 line driver • Video distribution amplifier • Video twisted-pair line driver Pinouts NC 1 VIN-A 3 14 VIN-B GND* 4 13 GND* GND* 5 12 GND* VIN+A 6 11 VIN+B INA- 2 AMP A + INA+ 3 VS- 8 10 C1 NC 5 POWER CONTROL LOGIC 13 OUTB 12 NC 11 INB10 INB+ POWER CONTROL LOGIC GND 4 GND 7 AMP B + 9 C1 C0 8 15 VOUTB 14 VS+ + - VS- 7 + - NC 6 VOUTA 2 16 OUTA 16 VS+ NC 1 15 NC EL1511 (16 LD QFN) TOP VIEW EL1511 [16 LD SO (0.150”)] TOP VIEW 9 C0 NOTE: * These GND pins are heat spreaders 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL1511 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL1511CS EL1511CS - 16 Ld SO (0.150”) MDP0027 EL1511CS-T7 EL1511CS 7” 16 Ld SO (0.150”) MDP0027 EL1511CS-T13 EL1511CS 13” 16 Ld SO (0.150”) MDP0027 EL1511CSZ (See Note) EL1511CSZ - 16 Ld SO (0.150”) (Pb-Free) MDP0027 EL1511CSZ-T7 (See Note) EL1511CSZ 7” 16 Ld SO (0.150”) (Pb-Free) MDP0027 EL1511CSZ-T13 (See Note) EL1511CSZ 13” 16 Ld SO (0.150”) (Pb-Free) MDP0027 EL1511CL 1511CL - 16 Ld QFN MDP0046 EL1511CL-T7 1511CL 7” 16 Ld QFN MDP0046 EL1511CL-T13 1511CL 13” 16 Ld QFN MDP0046 EL1511CLZ (See Note) 1511CLZ - 16 Ld QFN (Pb-Free) MDP0046 EL1511CLZ-T7 (See Note) 1511CLZ 7” 16 Ld QFN (Pb-Free) MDP0046 EL1511CLZ-T13 (See Note) 1511CLZ 13” 16 Ld QFN (Pb-Free) MDP0046 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7016.2 April 10, 2007 EL1511 Absolute Maximum Ratings (TA = +25°C) VS+ to VS- Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V VS+ Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16.5V VS- Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . -16.5V to 0.3V Input C0/C1 to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+ Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 75mA Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-60°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS = ±7.5V, RF = 1.5kΩ, RL = 100Ω to mid supply, TA = +25°C unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth AV = +4 70 MHz HD Total Harmonic Distortion f = 150kHz, VO = 16VP-P, RL = 25Ω -85 dBc dG Differential Gain AV = +2, RL = 37.5Ω 0.15 % dθ Differential Phase AV = +2, RL = 37.5Ω 0.1 ° SR Slewrate VOUT from -3V to +3V 500 V/µs DC PERFORMANCE VOS Offset Voltage -20 20 mV ΔVOS VOS Mismatch -10 10 mV ROL Transimpedance 2.5 MΩ VOUT from -4.5V to +4.5V 0.7 1.4 INPUT CHARACTERISTICS IB+ Non-Inverting Input Bias Current -5 5 µA IB- Inverting Input Bias Current -30 30 µA ΔIB- IB- Mismatch -30 30 µA eN Input Noise Voltage 2.8 nV/√ Hz iN -Input Noise Current 19 pA/√ Hz VIH Input High Voltage C0 and C1 inputs VIL Input Low Voltage C0 and C1 inputs IIH1 Input High Current for C1 C1 = 5V IIH0 Input High Current for C0 IIL Input Low Current for C1or C0 2.3 V 1.5 V 0.2 8 µA C0 = 5V 0.1 4 µA C1 = 0V, C0 = 0V -1 1 µA OUTPUT CHARACTERISTICS VOUT IOUT Loaded Output Swing (single ended) VS = ±7.5, RL = 100Ω to GND ±6.3 ±6.5 V VS = ±7.5, RL = 25Ω to GND ±5.7 ±6.0 V 450 mA Output Current RL = 0Ω VS Supply Voltage Single supply IS+ (Full Power) Positive Supply Current per Amplifier All outputs at 0V, C0 = C1 = 0V IS- (Full Power) Negative Supply Current per Amplifier IS+ (3/4 Power) Positive Supply Current per Amplifier SUPPLY 3 5 15 V 7 9.25 mA All outputs at 0V, C0 = C1 = 0V -6.4 -8.75 mA All outputs at 0V, C0 = 5V, C1 = 0V 5.3 7.25 mA FN7016.2 April 10, 2007 EL1511 Electrical Specifications VS = ±7.5V, RF = 1.5kΩ, RL = 100Ω to mid supply, TA = +25°C unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT IS- (3/4 Power) Negative Supply Current per Amplifier All outputs at 0V, C0 = 5V, C1 = 0V -4.7 -6.75 mA IS+ (1/2 Power) Positive Supply Current per Amplifier All outputs at 0V, C0 = 0V, C1 = 5V 3.3 5.75 mA IS- (1/2 Power) Negative Supply Current per Amplifier All outputs at 0V, C0 = 0V, C1 = 5V -2.7 -5.2 mA IS+ (Power Down) Positive Supply Current per Amplifier All outputs at 0V, C0 = C1 = 5V 0.6 1.025 mA IS- (Power Down) Negative Supply Current per Amplifier All outputs at 0V, C0 = C1 = 5V 0 -0.525 mA IGND GND Supply Current per Amplifier All outputs at 0V 0.6 1 mA Pin Descriptions EL1511CS 16 Ld SO (0.150”) EL1511CL 16 Ld QFN PIN NAME PIN FUNCTION 1 1, 5, 6, 12, 15 NC Not Connected 2, 15 13, 16 OUT Output EQUIVALENT CIRCUIT VS+ OUT VSCIRCUIT 1 3, 14 2, 11 VIN- Inverting Input VS+ IN+ IN- VSCIRCUIT 2 4, 5, 7, 12, 13 4 GND Ground Pins 6, 11 3, 10 VIN+ Non-inverting Input 8 7 VS- Negative Supply 9 8 C0 Power Control Reference Circuit 2 VS+ IBIAS 1.8V + – Q1 Q3 500Ω C0 Q2 CIRCUIT 3 10 9 C1 4 Power Control Reference Circuit 3 FN7016.2 April 10, 2007 EL1511 Typical Performance Curves 28 24 22 VS=±6V AV=10 RL=100Ω 18 20 RF=2kΩ 16 RF=1.5kΩ 12 14 RF=2kΩ 10 6 8 100K 1M 10M 2 100K 100M FREQUENCY (Hz) 20 RF=2kΩ 16 18 RF=1kΩ VS=±6V AV=5 RL=100Ω RF=1kΩ RF=1.5kΩ GAIN (dB) GAIN (dB) 100M 22 VS=±6V AV=10 RL=100Ω RF=1.5kΩ 12 14 RF=2kΩ 10 6 8 100K 1M 10M 2 100K 100M FREQUENCY (Hz) 1M 10M 100M FREQUENCY (Hz) FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE (3/4 POWER MODE) FIGURE 4. DIFFERENTIAL FREQUENCY RESPONSE (3/4 POWER MODE) 28 22 VS=±6V AV=10 RL=100Ω RF=1.5kΩ 18 RF=1kΩ GAIN (dB) GAIN (dB) 10M FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE (FULL POWER MODE) 28 24 1M FREQUENCY (Hz) FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE (FULL POWER MODE) 24 RF=1kΩ RF=1kΩ GAIN (dB) GAIN (dB) RF=1.5kΩ VS=±6V AV=5 RL=100Ω 20 RF=2kΩ 16 12 8 100K VS=±6V AV=5 RL=100Ω RF=1kΩ RF=1.5kΩ 14 RF=2kΩ 10 6 1M 10M 100M FREQUENCY (Hz) FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE (1/2 POWER MODE) 5 2 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE (1/2 POWER MODE) FN7016.2 April 10, 2007 EL1511 Typical Performance Curves (Continued) 28 24 22 VS=±7.5V AV=10 RL=100Ω 18 VS=±7.5V AV=5 RL=100Ω RF=1kΩ RF=1.5kΩ GAIN (dB) GAIN (dB) RF=1kΩ 20 RF=1.5kΩ 16 14 10 RF=2kΩ RF=2kΩ 12 6 8 100K 1M 10M 2 100K 100M FREQUENCY (Hz) 100M FIGURE 8. DIFFERENTIAL FREQUENCY RESPONSE (FULL POWER MODE) 28 22 VS=±7.5V AV=10 RL=100Ω 18 RF=1kΩ 20 RF=1.5kΩ 16 VS=±7.5V AV=5 RL=100Ω RF=1kΩ RF=1.5kΩ GAIN (dB) GAIN (dB) 10M FREQUENCY (Hz) FIGURE 7. DIFFERENTIAL FREQUENCY RESPONSE (FULL POWER MODE) 24 1M 14 RF=2kΩ 10 RF=2kΩ 12 6 8 100K 1M 10M 2 100K 100M FREQUENCY (Hz) 100M FIGURE 10. DIFFERENTIAL FREQUENCY RESPONSE (3/4 POWER MODE) 28 22 VS=±7.5V AV=10 RL=100Ω RF=1kΩ 18 VS=±7.5V AV=5 RL=100Ω RF=1kΩ RF=1.5kΩ GAIN (dB) RF=1.5kΩ GAIN (dB) 10M FREQUENCY (Hz) FIGURE 9. DIFFERENTIAL FREQUENCY RESPONSE (3/4 POWER MODE) 24 1M 20 RF=2kΩ 16 12 8 100K 14 RF=2kΩ 10 6 1M 10M 100M FREQUENCY (Hz) FIGURE 11. DIFFERENTIAL FREQUENCY RESPONSE (1/2 POWER MODE) 6 2 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 12. DIFFERENTIAL FREQUENCY RESPONSE (1/2 POWER MODE) FN7016.2 April 10, 2007 EL1511 Typical Performance Curves (Continued) 30 30 26 CL=22pF 22 14 10 CL=0pF 6 2 -2 -6 CL=22pF CL=10pF GAIN (dB) GAIN (dB) 22 CL=10pF 18 VS=±6V RF=1.5kΩ AV=5 RL=100Ω -10 100K 14 CL=0pF 6 VS=±7.5V RF=1.5kΩ AV=5 RL=100Ω -2 1M 10M -10 100k 100M FIGURE 13. DIFFERENTIAL FREQUENCY RESPONSE vs CL (FULL POWER MODE) 30 22 22 GAIN (dB) GAIN (dB) 14 10 CL=0pF 6 VS=±6V RF=1.5kΩ AV=5 RL=100Ω -10 100K 14 CL=0pF 6 -2 10M 1M VS=±7.5V RF=1.5kΩ AV=5 RL=100Ω -10 100K 100M 1M FIGURE 15. DIFFERENTIAL FREQUENCY RESPONSE vs CL (3/4 POWER MODE) 30 CL=22pF 26 22 CL=22pF 22 CL=10pF CL=10pF GAIN (dB) GAIN (dB) 18 14 CL=0pF 10 6 -6 100M FIGURE 16. DIFFERENTIAL FREQUENCY RESPONSE vs CL (3/4 POWER MODE) 30 -2 10M FREQUENCY (Hz) FREQUENCY (Hz) 2 CL=22pF CL=10pF CL=10pF 18 -6 100M CL=22pF 26 2 10M FIGURE 14. DIFFERENTIAL FREQUENCY RESPONSE vs CL (FULL POWER MODE) 30 -2 1M FREQUENCY (Hz) FREQUENCY (Hz) VS=±6V RF=1.5kΩ AV=5 RL=100Ω -10 100K 14 CL=0pF 6 -2 10M 1M 100M FREQUENCY (Hz) FIGURE 17. DIFFERENTIAL FREQUENCY RESPONSE vs CL (1/2 POWER MODE) 7 VS=±7.5V RF=1.5kΩ AV=5 RL=100Ω -10 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 18. DIFFERENTIAL FREQUENCY RESPONSE vs CL (1/2 POWER MODE) FN7016.2 April 10, 2007 EL1511 Typical Performance Curves (Continued) 70 FULL POWER VS=±2.5V AV=5 RF=2kΩ RL=100Ω f=150kHz -50 -55 50 THD (dB) BANDWIDTH (MHz) 60 -45 AV=5 RF=1.5kΩ RL=100Ω 3/4 POWER 40 30 1/2 POWER -60 FULL POWER -65 -70 3/4 POWER -75 1/2 POWER -80 20 -85 2.5 4.5 3.5 5.5 6.5 7.5 2 2.5 3 3.5 FIGURE 19. DIFFERENTIAL BANDWIDTH vs SUPPLY VOLTAGE -55 -60 THD (dB) PEAKING (dB) 6 8 4 VS=±6V AV=5 RF=1.5kΩ RL=100Ω f=150kHz -50 1/2 POWER 3/4 POWER -65 -70 FULL POWER -75 3/4 POWER -80 0 FULL POWER 1/2 POWER -85 -90 3.5 4.5 5.5 6.5 7.5 2 4 6 8 ±VS (V) 10 12 14 16 18 20 VOP-P (V) FIGURE 21. DIFFERENTIAL PEAKING vs SUPPLY VOLTAGE FIGURE 22. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE -10 -30 VS=±7.5V AV=5 RF=1.5kΩ RL=100Ω f=150kHz -20 -40 -30 -40 -50 THD (dB) ISOLATION (dB) 5.5 -45 AV=5 RF=1.5kΩ RL=100Ω 12 -50 -60 5 FIGURE 20. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE 16 -4 2.5 4.5 4 VOP-P (V) ±VS (V) B→A -70 FULL POWER -70 A→B -80 -60 3/4 POWER -90 1/2 POWER -80 -100 -110 10k -90 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 23. CHANNEL ISOLATION vs FREQUENCY 8 2 6 10 14 18 22 26 VOP-P (V) FIGURE 24. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE FN7016.2 April 10, 2007 EL1511 Typical Performance Curves (Continued) -45 -45 VS=±2.5V AV=5 RF=2kΩ RL=100Ω f=1MHz -55 HD (dB) -60 VS=±6V AV=5 RF=1.5kΩ RL=100Ω f=1MHz -50 -55 -65 HD (dB) -50 HD3 -70 -75 -80 -60 HD3 -65 -70 HD2 -75 HD2 -80 -85 -90 -85 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 2 4 6 8 VOP-P (V) FIGURE 25. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE) 14 16 18 20 -45 VS=±2.5V AV=5 RF=2kΩ RL=100Ω f=1MHz -55 -60 VS=±6V AV=5 RF=1.5kΩ RL=100Ω f=1MHz -50 -55 HD (dB) -50 HD (dB) 12 FIGURE 26. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE) -45 HD3 -65 -70 -75 -80 -60 -65 HD3 -70 HD2 -75 HD2 -80 -85 -85 -90 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2 6 4 6 8 10 12 14 16 18 20 VOP-P (V) VOP-P (V) FIGURE 27. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (3/4 POWER MODE) FIGURE 28. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (3/4 POWER MODE) -45 -50 VS=±2.5V AV=5 RF=2kΩ RL=100Ω f=1MHz -60 VS=±6V AV=5 RF=1.5kΩ RL=100Ω f=1MHz -50 -55 -65 HD (dB) -55 HD (dB) 10 VOP-P (V) HD3 -70 -75 -60 HD3 -65 -70 HD2 -75 HD2 -80 -80 -85 -85 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VOP-P (V) FIGURE 29. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (1/2 POWER MODE) 9 2 4 6 8 10 12 14 16 18 20 VOP-P (V) FIGURE 30. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (1/2 POWER MODE) FN7016.2 April 10, 2007 EL1511 Typical Performance Curves (Continued) -30 -45 VS=±7.5V AV=5 RF=1.5kΩ RL=100Ω f=1MHz HD (dB) -50 VS=±2.5V AV=5 RF=2kΩ RL=100Ω f=1MHz -50 -55 THD (dB) -40 -60 HD3 -70 -60 1/2 POWER -65 -70 3/4 POWER HD2 -80 -75 -90 FULL POWER -80 2 6 10 14 18 22 26 1 1.5 2 2.5 VOP-P (V) 4 4.5 5 5.5 6 FIGURE 32. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE -30 -45 VS=±7.5V AV=5 RF=1.5kΩ RL=100Ω f=1MHz -50 VS=±6V AV=5 RF=1.5kΩ RL=100Ω f=1MHz -50 -55 -60 THD (dB) -40 HD (dB) 3.5 VOP-P (V) FIGURE 31. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE) HD3 -70 -60 -65 1/2 POWER -70 -75 HD2 -80 FULL POWER -80 3/4 POWER -85 -90 2 6 10 14 18 22 26 2 4 6 8 10 12 14 16 18 20 VOP-P (V) VOP-P (V) FIGURE 33. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (3/4 POWER MODE) FIGURE 34. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE -30 -30 VS=±7.5V AV=5 RF=1.5kΩ RL=100Ω f=1MHz -50 VS=±7.5V AV=5 RF=1.5kΩ RL=100Ω f=1MHz -40 -50 THD (dB) -40 HD (dB) 3 HD3 -60 -70 1/2 POWER -60 -70 FULL POWER HD2 -80 -80 -90 -90 3/4 POWER 2 6 10 14 18 22 26 VOP-P (V) FIGURE 35. DIFFERENTIAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (1/2 POWER MODE) 10 2 6 10 14 18 22 26 VOP-P (V) FIGURE 36. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE FN7016.2 April 10, 2007 EL1511 Typical Performance Curves (Continued) 0.14 VS=±6V AV=2 RF=1.5kΩ 0.12 CH 2 dG (%) 0.1 VOUT 0.08 1/2 POWER 0.06 C0, C1 3/4 POWER 0.04 0.02 CH 1=2V/DIV CH 2=2V/DIV CH 1 FULL POWER 0 1.5 1 2 2.5 3 4 3.5 400ns/DIV NUMBER OF 150Ω LOADS FIGURE 37. DIFFERENTIAL GAIN FIGURE 38. DISABLE TIME 0.15 VS=±6V AV=2 RF=1.5kΩ 0.14 0.13 dP (°) 0.12 CH 1=2V/DIV CH 2=2V/DIV 1/2 POWER VOUT CH 2 0.11 0.1 C0, C1 CH 1 3/4 POWER 0.09 FULL POWER 0.08 0.07 1 1.5 2 3 2.5 3.5 4 40ns/DIV NUMBER OF 150Ω LOADS FIGURE 39. DIFFERENTIAL PHASE FIGURE 40. ENABLE TIME 16 10 14 IS- (FULL POWER) INPUT BIAS CURRENT (µA) IS+ (FULL POWER) IS+ (3/4 POWER) IS (mA) 12 10 8 IS- (3/4 POWER) 6 4 IS+ (1/2 POWER) IS+ (1/2 POWER) 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 ±VS (V) FIGURE 41. SUPPLY CURRENT vs SUPPLY VOLTAGE 11 6 IB- 4 2 0 -2 IB+ -4 -6 -8 2 2 8 -10 -50 -25 0 25 50 75 100 125 150 DIE TEMPERATURE (°C) FIGURE 42. INPUT BIAS CURRENT vs TEMPERATURE FN7016.2 April 10, 2007 EL1511 Typical Performance Curves (Continued) 7 6 14 OFFSET VOLTAGE (mV) SUPPLY CURRENT (mA) 16 FULL POWER 12 3/4 POWER 10 8 1/2 POWER 6 4 DISABLED 2 0 -50 -25 0 25 50 75 5 4 3 2 1 0 -1 -2 100 125 -3 -50 150 -25 DIE TEMPERATURE (°C) 0 25 50 75 100 125 150 DIE TEMPERATURE (°C) FIGURE 43. POSITIVE SUPPLY CURRENT vs TEMPERATURE FIGURE 44. OFFSET VOLTAGE vs TEMPERATURE 5.2 3 5.15 TRANSIMPEDANCE (MΩ) OUTPUT VOLTAGE (±V) RL=100Ω 5.1 50.5 5 4.95 4.9 4.85 4.8 -50 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 125 -50 150 FIGURE 45. OUTPUT VOLTAGE vs TEMPERATURE 25 50 75 100 125 150 30 20 510 10 500 0 490 PSRR (dB) SLEW RATE (V/µs) 0 FIGURE 46. TRANSIMPEDANCE vs TEMPERATURE 520 480 470 -10 -20 -30 -40 460 PSRR- -50 450 440 -50 -25 DIE TEMPERATURE (°C) DIE TEMPERATURE (°C) PSRR+ -60 -25 0 25 50 75 100 125 150 DIE TEMPERATURE (°C) FIGURE 47. SLEW RATE vs TEMPERATURE 12 -70 10K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 48. POWER SUPPLY REJECTION vs FREQUENCY FN7016.2 April 10, 2007 EL1511 Typical Performance Curves (Continued) 100 OUTPUT IMPEDANCE (Ω) VOLTAGE NOISE (nV/√Hz), CURRENT NOISE (pA/Hz) 100 IB10 eN 10 VS=±6V AV=1 RF=1.5kΩ 1 0.1 0.01 IB+ 1 10 100 1K 10K 100K 1M 10M 0.001 10K 100M 100K FREQUENCY (Hz) FIGURE 49. VOLTAGE AND CURRENT NOISE vs FREQUENCY 10M 100k -100 -150 10k -200 1k -250 1K 10K 100K 1M 10M -300 100M POWER DISSIPATION (W) -50 PHASE PHASE (°) MAGNITUDE (Ω) 4 0 GAIN 100 100 100M FIGURE 50. OUTPUT IMPEDANCE vs FREQUENCY (ALL POWER LEVELS) 50 1M 10M 1M FREQUENCY (Hz) USING EL1511CS/EL1511CL DEMOBOARD, 2”X2” (4-LAYER) DEMOBOARD WITH HEATSINK VIA INTERNAL GROUND PLANE 3.5 3 37°C/W QF N 47°C/W 2.5 SO 2 16 1.5 (0. 15 16 0” ) 1 0.5 0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) FREQUENCY (Hz) FIGURE 51. TRANSIMPEDANCE (ROL) vs FREQUENCY FIGURE 52. PACKAGE POWER DISSIPATION AND THERMAL RESISTANCE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 POWER DISSIPATION (W) 4 3.5 3.125W 3 2.5 40 2 QF N1 6 °C /W 1.5 1 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 53. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 13 FN7016.2 April 10, 2007 EL1511 Applications Information Product Description The EL1511 is a dual operational amplifier designed for customer premise driver functions in DMT ADSL solutions and is built using Elantec's proprietary complimentary bipolar process. Due to the current feedback architecture, the EL1511 closed-loop 3dB bandwidth is dependent on the value of the feedback resistor. First the desired bandwidth is selected by choosing the feedback resistor, RF, and then the gain is set by picking the gain resistor, RG. The curves at the beginning of the Typical Performance Curves section show the effect of varying both RF and RG. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended. Lead lengths should be as short as possible, below ¼. The power supply pins must be well bypassed to reduce the risk of oscillation. A 1.0µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor is adequate for each supply pin. For good AC performance, parasitic capacitances should be kept to a minimum, especially at the inverting input (see Capacitance at the Inverting Input section). This implies keeping the ground plane away from this pin. Carbon resistors are acceptable, while use of wire-wound resistors should not be used because of their parasitic inductance. Similarly, capacitors should be low inductance for best performance. Use of sockets, particularly for the SO (0.150") package, should be avoided. Sockets add parasitic inductance and capacitance which will result in peaking and overshoot. Capacitance at the Inverting Input Due to the topology of the current feedback amplifier, stray capacitance at the inverting input will affect the AC and transient performance of the EL1511 when operating in the non-inverting configuration. In the inverting gain mode, added capacitance at the inverting input has little effect since this point is at a virtual ground and stray capacitance is therefore not “seen” by the amplifier. Feedback Resistor Values The EL1511 has been designed and specified with RF = 1.5kΩ for AV = +5. This value of feedback resistor yields relatively flat frequency response with <1.5dB peaking out to 60MHz. As is the case with all current feedback amplifiers, wider bandwidth, at the expense of slight peaking, can be obtained by reducing the value of the feedback resistor. Inversely, larger values of feedback resistor will cause rolloff to occur at a lower frequency. By reducing RF to 1kΩ, bandwidth can be extended to 70MHz with 3.0dB of peaking. See the curves in the Typical Performance Curves section which show 3dB bandwidth and peaking vs frequency for various feedback resistors. 14 Power Dissipation The EL1511 amplifier combines both high speed and large output current drive capability at a moderate supply current in very small packages. It is possible to exceed the maximum junction temperature allowed under certain supply voltage, temperature, and loading conditions. To ensure that the EL1511 remains within its absolute maximum ratings, the following discussion will help to avoid exceeding the maximum junction temperature. The maximum power dissipation allowed in a package is determined by its thermal resistance and the amount of temperature rise according to: T JMAX – T AMAX P DMAX = --------------------------------------------θ JA The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage plus the power in the IC due to the load, or: V OUT P DMAX = 2 × V S + ( V S – V OUT ) × ---------------RL where IS is the supply current. (To be more accurate, the quiescent supply current flowing in the output driver transistor should be subtracted from the first term because, under loading and due to the class AB nature of the output stage, the output driver current is now included in the second term.) In general, an amplifier's AC performance degrades at higher operating temperature and lower supply current. Unlike some amplifiers, the EL1511 maintains almost constant supply current over temperature so that AC performance is not degraded as much over the entire operating temperature range. Estimating Line Driver Power Dissipation in ADSL CPE Application The below figure shows a typical ADSL CPE line driver implementation. The average line power requirement for the ADSL CPE application is 13dBM (20mW) into a 100W line. The average line voltage is 1.41VRMS. The ADSL DMT peak to average ratio (crest factor) of 5.3 implies peak voltage of 7.5V into the line. Using a differential drive configuration and transformer coupling with standard back termination, a transformer ratio of 1:2 is selected. With 1:2 transformer ratio, the impedance across the driver side of the transformer is 25Ω, the average voltage is 0.705VRMA and the average current is 28.2mA. The power dissipated in the EL1511 is a combination of the quiescent power and the output stage power when driving the line: PD = P quiescent + P output-stage PD = V S × I Q + ( V S – 2 × V OUT-RMS ) × I OUT-RMS In the ½ power mode, the EL1511 consumes typically 6.6mA quiescent current and still able to maintain very low distortion. The distortion results are shown in typical FN7016.2 April 10, 2007 EL1511 performance section of the data sheet. When driving a load, a large portion (about 50%) of the quiescent current becomes output load current: PD = 12 × ( 6.6mA × 50% ) + ( 12V – 2 × 0.705 ) × 28.2mA where: PD = 338mW Assuming a maximum ambient temperature of 85°C and keeping the junction temperature less than 150°C, the maximum thermal resistance from junction to ambient required is: TOP (16 Ld QFN) 150 – 85 Θ JA = ---------------------- = 192°C/W 338mW With proper layout, the EL1511CS package can achieve 47°C/W, well below the thermal resistance required by the application. TX+ + - From AFE 2RG 464 TX- VS+ VSRF RT 12.5 1.5k + - VS+ VSRF TXFR 1:2 INTERNAL GROUND PLANE (16 Ld QFN) 100 RT 12.5 1.5k PCB Layout Considerations for Thermal Packages The EL1511 die is packaged in two different thermal efficient packages, the 16 Ld SO and 16 Ld QFN packages. The 16 Ld SO package has the same dimensions as standard 0.15" wide narrow body 16 Ld SO package with a special fused lead frame that extends out through the center ground pins. Both packages can use PCB surface metal vias areas and internal ground planes, to spread heat away from the package. The larger the PCB area the lower the junction temperature of the device will be. In XDSL applications, multiple layer circuit boards with internal ground plane are generally used. 13 mil vias are recommended to connect the metal area under the device with the internal ground plane. Examples of the PCB layouts are shown in the figures below that result in thermal resistance θJA of 37°C/W for the QFN package and 47°C/W for the SO package. The thermal resistance is obtained with the EL1511CL and CS demo boards. The demo board is a 4-layer board built with 2oz. copper and has a dimension of 4in2. Note, the user must follow the thermal layout guideline to achieve these results. TOP (16 Ld SO) INTERNAL GROUND PLANE (16 Ld SO) A separate Application Note for the QFN package and layout recommendations is also available. 15 FN7016.2 April 10, 2007 EL1511 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN38 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN24 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 N LEADS DETAIL X 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 16 FN7016.2 April 10, 2007 EL1511 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 17 FN7016.2 April 10, 2007 EL1511 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7016.2 April 10, 2007