ON LMV393MUTAG Single, dual, quad general purpose, low voltage comparator Datasheet

LMV331, LMV393, LMV339
Single, Dual, Quad General
Purpose, Low Voltage
Comparators
The LMV331 is a CMOS single channel, general purpose, low
voltage comparator. The LMV393 and LMV339 are dual and quad
channel versions, respectively. The LMV331/393/339 are specified
for 2.7 V to 5 V performance, have excellent input common−mode
range, low quiescent current, and are available in several space saving
packages.
The LMV331 is available in a 5−pin SC−70, a TSOP−5, and a
ULLGA8 package. The LMV393 is available in a 8−pin Micro8t,
SOIC−8, and a UDFN8 package, and the LMV339 is available in a
SOIC−14 and a TSSOP−14 package.
The LMV331/393/339 are cost effective solutions for applications
where space saving, low voltage operation, and low power are the
primary specifications in circuit design for portable applications.
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1
TSOP−5
CASE 483
SC−70
CASE 419A
1
1
ULLGA8
CASE 613AG
Features
•
•
•
•
•
•
•
5
1
Guaranteed 2.7 V and 5 V Performance
Input Common−mode Voltage Range Extends to Ground
Open Drain Output for Wired−OR Applications
Low Quiescent Current: 60 mA/channel TYP @ 5 V
Low Saturation Voltage 200 mV TYP @ 5 V
Propagation Delay 200 ns TYP @ 5 V
These are Pb−Free Devices
Micro8
CASE 846A
8
8
1
1
SOIC−8
CASE 751
UDFN8
CASE 517AJ
Typical Applications
•
•
•
•
Battery Monitors
Notebooks and PDA’s
General Purpose Portable Devices
General Purpose Low Voltage Applications
1
1
SOIC−14
CASE 751A
TSSOP−14
CASE 948G
ORDERING INFORMATION
+VCC
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
R1
VIN
VCC
RPULL−UP
−
VO
VO
VT2
V+
RLOAD
+
VT1
0
VIN
Figure 2. Hysteresis Curve
R3
R2
Figure 1. Inverting
Comparator with Hysteresis
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 3
1
Publication Order Number:
LMV331/D
LMV331, LMV393, LMV339
MARKING DIAGRAMS
TSOP−5
CASE 483
SC−70
CASE 419A
UDFN8
CASE 517AJ
5
3CAAYWG
G
CCAMG
G
CAMG
G
1
CA = Specific Device Code
A
= Assembly Location
M = Date Code
Y
= Year
G
= Pb−Free Package
W = Work Week
(Note: Microdot may be in either location)
G
= Pb−Free Package
(Note: Microdot may be in either location)
CCA = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Micro8
CASE 846A
SOIC−8
CASE 751
8
ULLGA8
CASE 613AG
8
V393
AYWG
G
1
1
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
A
L
Y
W
G
1
V393
ALYW G
G
XXMG
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
SOIC−14
CASE 751A
TSSOP−14
CASE 948G
14
14
LMV
339
ALYWG
G
LMV339
AWLYWWG
1
1
A
WL
Y
WW
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PACKAGE PINOUTS
SC−70/TSOP−5
+IN
1
GND
2
−IN
Micro8 / SOIC−8 / UDFN8
5
VCC
Output A
+
−
3
4
Inputs A
OUTPUT
IN−
1
IN+
2
VCC−/GND
3
8
4
NC
(Top Views)
8
2
7
−
+
3
GND
ULLGA8
NC
(Top Views)
1
−
+
4
VCC
Output 2
1
14
Output 3
Output B
Output 1
2
13
Output 4
VCC
3
12
GND
− Input 1
4
11
+ Input 4
10
− Input 4
9
+ Input 3
8
− Input 3
6
5
Inputs B
(Top Views)
7
OUT
6
NC
5
SOIC−14 / TSSOP−14
+ Input 1
5
− Input 2
6
+ Input 2
VCC+
7
*
1
)
4
*2
)
3
(Top Views)
NC − No Internal Connection
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2
)
*
)
*
LMV331, LMV393, LMV339
MAXIMUM RATINGS
Symbol
VS
Rating
Voltage on any Pin (referred to V− pin)
Value
Unit
5.5
V
VIDR
Input Differential Voltage Range
±Supply Voltage
V
TJ
Maximum Junction Temperature
150
°C
Tstg
Storage Temperature Range
−65 to 150
°C
TL
Mounting Temperature (Infrared or Convection (1/16″ From Case for 30 Seconds))
260
°C
ESD Tolerance (Note 1)
Machine Model
Human Body Model
100
1000
VESD
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage Temperature Range (Note 2)
qJA
Thermal Resistance
SC−70
TSOP−5
ULLGA8
Micro8
SOIC−8
UDFN8
SOIC−14
TSSOP−14
Value
Unit
2.7 to 5.0
V
280
333
340
238
212
350
156
190
°C/W
1. Human Body Model, applicable std. MIL−STD−883, Method 3015.7. Machine Model, applicable std. JESD22−A115−A (ESD MM std. of
JEDEC) Field−Induced Charge−Device Model, applicable std. JESD22−C101−C (ESD FICDM std. of JEDEC).
2. The maximum power dissipation is a function of TJ(MAX), qJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) − TA)/qJA. All numbers apply for packages soldered directly onto a PC board.
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LMV331, LMV393, LMV339
2.7 V DC ELECTRICAL CHARACTERISTICS (All limits are guaranteed for TA = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 1.35 V unless
otherwise noted.)
Parameter
Symbol
Input Offset Voltage
Input Offset Voltage Average Drift
Input Bias Current (Note 3)
Input Offset Current (Note 3)
Condition
Min
Typ
Max
Unit
VIO
1.7
9
mV
TC VIO
5
mV/°C
IB
<1
nA
IIO
<1
nA
Input Voltage Range
VCM
0 to 2
V
Saturation Voltage
VSAT
ISINK ≤ 1 mA
120
mV
IO
VO ≤ 1.5 V
23
mA
Output Sink Current
Supply Current
LMV331
LMV393
LMV339
5
ICC
40
70
140
100
140
200
mA
2.7 V AC ELECTRICAL CHARACTERISTICS (TA = 25°C, V+ = 2.7 V, RL = 5.1 kW, V− = 0 V unless otherwise noted.)
Parameter
Symbol
Condition
Propagation Delay − High to Low
tPHL
Input Overdrive = 10 mV
Input Overdrive = 100 mV
1000
500
ns
Propagation Delay − Low to High
tPLH
Input Overdrive = 10 mV
Input Overdrive = 100 mV
800
200
ns
3. Guaranteed by design and/or characterization.
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4
Min
Typ
Max
Unit
LMV331, LMV393, LMV339
5.0 V DC ELECTRICAL CHARACTERISTICS (All limits are guaranteed for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = 2.5 V unless
otherwise noted.)
Parameter
Input Offset Voltage
Symbol
Condition
VIO
Typ
Max
Unit
TA = −40°C to +85°C
1.7
9
mV
TA = −40°C to +85°C
5
mV/°C
IB
TA = −40°C to +85°C
<1
nA
IIO
TA = −40°C to +85°C
Input Offset Voltage Average Drift
Input Bias Current (Note 4)
Input Offset Current (Note 4)
Input Voltage Range
VCM
Voltage Gain (Note 4)
AV
Saturation Voltage
Output Sink Current
20
VSAT
ISINK ≤ 4 mA
TA = −40°C to +85°C
IO
VO ≤ 1.5 V
Supply Current
LMV331
ICC
Supply Current
LMV393
ICC
Supply Current
LMV339
ICC
Output Leakage Current (Note 4)
10
TA = −40°C to +85°C
TA = −40°C to +85°C
TA = −40°C to +85°C
V+
= 5 V, RL = 5.1 kW,
<1
nA
0 to 4.2
V
50
V/mV
200
TA = −40°C to +85°C
5.0 V AC ELECTRICAL CHARACTERISTICS (TA = 25°C,
Parameter
Min
V−
400
700
84
mV
mA
60
120
150
mA
100
200
250
mA
170
300
350
mA
0.003
1
mA
= 0 V unless otherwise noted.)
Symbol
Condition
Propagation Delay − High to Low
tPHL
Input Overdrive = 10 mV
Input Overdrive = 100 mV
1500
900
ns
Propagation Delay − Low to High
tPLH
Input Overdrive = 10 mV
Input Overdrive = 100 mV
800
200
ns
4. Guaranteed by design and/or characterization.
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5
Min
Typ
Max
Unit
LMV331, LMV393, LMV339
TYPICAL CHARACTERISTICS
(VCC = 5.0 V, TA = 25°C, RL = 5 kW unless otherwise specified)
50
40
−40°C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
30
−40°C
45
25°C
35
85°C
30
25
20
15
10
25°C
20
85°C
10
5
0
0
1
2
3
SUPPLY VOLTAGE (V)
4
0
0
5
Figure 3. LMV331Supply Current vs. Supply
Voltage (Output High)
4
5
600
160
500
140
25°C
85°C
100
400
VSAT (mV)
120
VSAT (mV)
2
3
SUPPLY VOLTAGE (V)
Figure 4. LMV331Supply Current vs. Supply
Voltage (Output Low)
180
−40°C
80
60
85°C
300
25°C
−40°C
200
40
100
20
0
1
0
1
2
3
4
5
6
7
8
9
0
0
10
OUTPUT CURRENT (mA)
20
30
OUTPUT CURRENT (mA)
Figure 5. VSAT vs. Output Current at
VCC = 2.7 V
Figure 6. VSAT vs. Output Current at
VCC = 5.0 V
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10
40
50
LMV331, LMV393, LMV339
NEGATIVE TRANSITION INPUT − VCC = 2.7 V
Timebase
5.00 kS
−600
500 ns/div
1.0 GS/s
Trigger
Stop
Edge
28 mV
Negative
Figure 7. 10 mV Overdrive
Timebase
2.00 kS
−200
200 ns/div
1.0 GS/s
Trigger
Stop
Edge
11.5 mV
Negative
Figure 8. 20 mV Overdrive
Timebase
5.00 kS
−600
500 ns/div
1.0 GS/s
Trigger
Stop
Edge
Figure 9. 100 mV Overdrive
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7
18 mV
Negative
LMV331, LMV393, LMV339
POSITIVE TRANSITION INPUT − VCC = 2.7 V
Timebase
2.00 kS
−400
200 ns/div
1.0 GS/s
Trigger
Stop
Edge
=11.5 mV
Positive
Figure 10. 10 mV Overdrive
Timebase
1.00 kS
−300
100 ns/div
1.0 GS/s
Trigger
Stop
Edge
−49.5 mV
Positive
Figure 11. 20 mV Overdrive
Timebase
1.00 kS
−150
100 ns/div
1.0 GS/s
Trigger
Stop
Edge
18 mV
Positive
Figure 12. 100 mV Overdrive
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LMV331, LMV393, LMV339
NEGATIVE TRANSITION INPUT − VCC = 5.0 V
Timebase
5.00 kS
−600
500 ns/div
1.0 GS/s
Trigger
Stop
Edge
28 mV
Negative
Figure 13. 10 mV Overdrive
Timebase
2.00 kS
−200
200 ns/div
1.0 GS/s
Trigger
Stop
Edge
11.5 mV
Negative
Figure 14. 20 mV Overdrive
Timebase
5.00 kS
−600
500 ns/div
1.0 GS/s
Trigger
Stop
Edge
18 mV
Negative
Figure 15. 100 mV Overdrive
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LMV331, LMV393, LMV339
POSITIVE TRANSITION INPUT − VCC = 5.0 V
Timebase
2.00 kS
−400
200 ns/div
1.0 GS/s
Trigger
Stop
Edge
−11.5 mV
Positive
Figure 16. 10 mV Overdrive
Timebase
1.00 kS
−300
100 ns/div
1.0 GS/s
Trigger
Stop
Edge
−49.5 mV
Positive
Figure 17. 20 mV Overdrive
Timebase
1.00 kS
−150
100 ns/div
1.0 GS/s
Trigger
Stop
Edge
18 mV
Positive
Figure 18. 100 mV Overdrive
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LMV331, LMV393, LMV339
APPLICATION CIRCUITS
Basic Comparator Operation
+VCC
The basic operation of a comparator is to compare two
input voltage signals, and produce a digital output signal by
determining which input signal is higher. If the voltage on
the non−inverting input is higher, then the internal output
transistor is off and the output will be high. If the voltage on
the inverting input is higher, then the output transistor will
be on and the output will be low. The LMV331/393/339 has
an open−drain output stage, so a pull−up resistor to a positive
supply voltage is required for the output to switch properly.
The size of the pull−up resistor is recommended to be
between 1 kW and 10 kW. This range of values will balance
two key factors; i.e., power dissipation and drive capability
for interface circuitry.
Figure 19 illustrates the basic operation of a comparator
and assumes dual supplies. The comparator compares the
input voltage (VIN) on the non−inverting input to the
reference voltage (VREF) on the inverting input. If VIN is less
than VREF, the output voltage (VO) will be low. If VIN is
greater than VREF, then VO will be high.
R1
RPULL−UP
−
VIN
VO
RLOAD
+
V+
R3
R2
Figure 20. Inverting
Comparator with
Hysteresis
When VIN is less than the voltage at the non−inverting
node, V+, the output voltage will be high. When VIN is
greater than the voltage at V+, then the output will be low.
The hysteresis band (Figure 21) created from the resistor
network is defined as:
VOUT
V+
VREF
DV ) + V T1 * V T2
0V
where VT1 and VT2 are the lower and upper trip points,
respectively.
Time
VIN
V+
+VIN
VCC
+
3.0 k
VO
VO
+VREF
VT2
VT1
0
−
VIN
Figure 19.
Figure 21.
VT1 is calculated by assuming that the output of the
comparator is pulled up to supply when high. The
resistances R1 and R3 can be viewed as being in parallel
which is in series with R2 (Figure 22). Therefore VT1 is:
Comparators and Stability
A common problem with comparators is oscillation due to
their high gain. The basic comparator configuration in
Figure 19 may oscillate if the differential voltage between
the input pins is close to the device’s offset voltage. This can
happen if the input signal is moving slowly through the
comparator’s switching threshold or if unused channels are
connected to the same potential for termination of unused
channels. One way to eliminate output oscillations or
‘chatter’ is to include external hysteresis in the circuit
design.
V T1 +
V CC R 2
ǒR 1 ø R 3Ǔ ) R 2
VT2 is calculated by assuming that the output of the
comparator is at ground potential when low. The resistances
R2 and R3 can be viewed as being in parallel which is in
series with R1 (Figure 23). Therefore VT2 is:
Inverting Configuration with Hysteresis
V T2 +
An inverting comparator with hysteresis is shown in
Figure 20.
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V CCǒR 2 ø R 3Ǔ
R 1 ) ǒR 2 ø R 3Ǔ
LMV331, LMV393, LMV339
VO LOW
VO HIGH
+VCC
When VIN is much less than the voltage at the inverting
input (VREF), then the output is low. R2 can then be viewed
as being connected to ground (Figure 26). To calculate the
voltage required at VIN to trip the comparator high, the
following equation is used:
+VCC
R1
R1
R3
V in1 +
VT2
VT1
R2
When the output is high, VIN must less than or equal to
VREF (VIN ≤ VREF) before the output will be low again
(Figure 27). The following equation is used to calculate the
voltage at VIN to switch the output back to the low state:
R3
R2
V in2 +
Figure 23.
Figure 22.
Non−inverting Configuration with Hysteresis
A non−inverting comparator is shown in Figure 24.
+VCC
VREF
RPULL−UP
−
V ref (R 1 ) R 2)
R2
V ref (R 1 ) R 2) * V CCR 1
R2
VO LOW
VIN1
VO HIGH
+VCC
R1
R2
VA = VREF
VA = VREF
R2
R1
VO
VIN2
VA
VIN
Figure 26.
RLOAD
+
R1
Figure 27.
Termination of Unused Inputs
Proper termination of unused inputs is a good practice to
keep the output from ‘chattering.’ For example, if one
channel of a dual or quad package is not being used, then the
inputs must be connected to a defined state. The
recommended connections would be to tie one input to VCC
and the other input to ground.
R2
Figure 24.
The hysteresis band (Figure 25) of the non−inverting
configuration is defined as follows:
DV in + V CCR 1ńR 2
VCC
VO
VIN2
VIN1
0
VIN
Figure 25.
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12
LMV331, LMV393, LMV339
ORDERING INFORMATION
Number of Channels
Specific Device Marking
Package Type
Shipping†
LMV331SQ3T2G
Single
CCA
SC−70
(Pb−Free)
3000 / Tape & Reel
LMV331SN3T1G
Single
3CA
TSOP−5
(Pb−Free)
3000 / Tape & Reel
LMV331MU3TBG*
Single
3C
ULLGA8
(Pb−Free)
3000 / Tape & Reel
LMV393DMR2G
Dual
V393
Micro8
(Pb−Free)
4000 / Tape & Reel
LMV393DR2G
Dual
V393
SOIC−8
(Pb−Free)
2500 / Tape & Reel
LMV393MUTAG
Dual
CA
UDFN8
(Pb−Free)
3000 / Tape & Reel
LMV339DR2G
Quad
LMV339
SOIC−14
(Pb−Free)
2500 / Tape & Reel
LMV339DTBR2G
Quad
LMV
339
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Contact factory.
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LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
J
C
H
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
K
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14
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
D 5X
NOTE 5
2X
0.10 T
2X
0.20 T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
0.20 C A B
M
5
1
4
2
L
3
B
S
K
DETAIL Z
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
J
C
0.05
SEATING
PLANE
H
T
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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15
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
UDFN8 1.8x1.2, 0.4P
CASE 517AJ−01
ISSUE O
PIN ONE
REFERENCE
ÉÉÉ
ÉÉÉ
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH MAY
NOT EXCEED 0.03 ONTO BOTTOM
SURFACE OF TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
A B
D
0.10 C
L1
E
DETAIL A
NOTE 5
TOP VIEW
(A3)
0.05 C
DIM
A
A1
A3
b
b2
D
E
e
L
L1
L2
A
0.05 C
SIDE VIEW
e/2
(b2)
A1
e
1
C
SEATING
PLANE
DETAIL A
8X
L
4
MOUNTING FOOTPRINT*
SOLDERMASK DEFINED
(L2)
8
5
BOTTOM VIEW
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
0.30 REF
1.80 BSC
1.20 BSC
0.40 BSC
0.45
0.55
0.00
0.03
0.40 REF
8X b
8X
0.10
M
C A B
0.05
M
C
0.66
7X
0.22
NOTE 3
1.50
1
0.32
0.40 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
16
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE H
D
HE
PIN 1 ID
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
E
e
b 8 PL
0.08 (0.003)
T B
M
S
A
DIM
A
A1
b
c
D
E
e
L
HE
S
SEATING
−T− PLANE
0.038 (0.0015)
A
A1
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
L
c
SOLDERING FOOTPRINT*
8X
1.04
0.041
0.38
0.015
3.20
0.126
6X
8X
4.24
0.167
0.65
0.0256
5.28
0.208
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
S
M
J
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
18
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
ULLGA8, 1.5x1.5, 0.5P
CASE 613AG−01
ISSUE O
A
B
D
PIN ONE
REFERENCE
0.10 C
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
E
DIM
A
A1
b
b1
D
E
e
L
L1
L3
TOP VIEW
0.05 C
MILLIMETERS
MIN
MAX
−−−
0.40
0.00
0.05
0.20
0.30
0.30
0.40
1.50 BSC
1.50 BSC
0.50 BSC
0.25
0.35
0.05 REF
0.15 REF
A
8X
0.05 C
A1 C
SIDE VIEW
MOUNTING FOOTPRINT*
SEATING
PLANE
7X
b1
e
8X
3
1
0.32
8X
0.51
PACKAGE
OUTLINE
L
1.65
L3
1
7
5
L1
0.42
8X
b
DIMENSIONS: MILLIMETERS
0.10 C A B
BOTTOM VIEW
0.50
PITCH
0.05 C
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
19
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
D 14 PL
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
20
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
Micro8 is a trademark of International Rectifier.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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21
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LMV331/D