MC74HCT4051A, MC74HCT4052A, MC74HCT4053A Analog Multiplexers / Demultiplexers with LSTTL Compatible Inputs http://onsemi.com MARKING DIAGRAMS High−Performance Silicon−Gate CMOS The MC74HCT4051A, MC74HCT4052A and MC74HCT4053A utilize silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The HCT4051A, HCT4052A and HCT4053A are identical in pinout to the metal−gate MC14051AB, MC14052AB and MC14053AB. The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel−Select and Enable inputs are compatible with standard CMOS and LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal−gate CMOS analog switches. For a multiplexer/demultiplexer with injection current protection, see HC4851A and HCT4851A. Features • • • • • • • • • • Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance Than Metal−Gate Counterparts Low Noise In Compliance with the Requirements of JEDEC Standard No. 7 A Chip Complexity: HCT4051A − 184 FETs or 46 Equivalent Gates HCT4052A − 168 FETs or 42 Equivalent Gates HCT4053A − 156 FETs or 39 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2011 June, 2011 − Rev. 2 1 16 SOIC−16 WIDE DW SUFFIX CASE 751G 16 1 1 SOIC−16 D SUFFIX CASE 751B 16 1 HCT405xA AWLYWWG 16 HCT405xAG AWLYWW 1 16 HCT40 5xA ALYWG G TSSOP−16 DT SUFFIX CASE 948F 16 1 1 x A WL, L YY, Y WW, W G or G = 1, 2, 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. Publication Order Number: MC74HCT4051A/D MC74HCT4051A, MC74HCT4052A, MC74HCT4053A FUNCTION TABLE − MC74HCT4051A Control Inputs 13 X0 14 X1 15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS X4 1 5 X5 2 X6 4 X7 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 3 Enable C L L L L L L L L H L L L L H H H H X COMMON X OUTPUT/ INPUT Select B A L L H H L L H H X ON Channels X0 X1 X2 X3 X4 X5 X6 X7 NONE L H L H L H L H X X = Don’t Care VCC X2 X1 X0 X3 A B C 16 15 14 13 12 11 10 9 6 7 8 GND Figure 1. Logic Diagram − MC74HCT4051A Single−Pole, 8−Position Plus Common Off 1 2 3 4 5 X4 X6 X X7 X5 Enable VEE Figure 2. Pinout: MC74HCT4051A (Top View) FUNCTION TABLE − MC74HCT4052A Control Inputs Enable B L L L L H L L H H X 12 ANALOG INPUTS/OUTPUTS CHANNEL‐SELECT INPUTS X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B ENABLE X SWITCH 13 X COMMON OUTPUTS/INPUTS 1 5 2 Y SWITCH 3 Y 4 Select A ON Channels L H L H X Y0 Y1 Y2 Y3 X0 X1 X2 X3 NONE X = Don’t Care VCC X2 X1 X X0 X3 A B 16 15 14 13 12 11 10 9 6 7 8 GND 10 9 6 PIN 16 = VCC PIN 7 = VEE PIN 8 = GND Figure 3. Logic Diagram − MC74HCT4052A Double−Pole, 4−Position Plus Common Off 1 2 3 4 5 Y0 Y2 Y Y3 Y1 Enable VEE Figure 4. Pinout: MC74HCT4052A (Top View) http://onsemi.com 2 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A FUNCTION TABLE − MC74HCT4053A Control Inputs 12 X0 13 X1 14 X SWITCH 2 ANALOG INPUTS/OUTPUTS Y0 1 Y1 15 Y SWITCH 5 Z0 3 Z1 4 Z SWITCH Enable C L L L L L L L L H L L L L H H H H X X Y COMMON OUTPUTS/INPUTS Select B A L L H H L L H H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 L H L H L H L H X Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X = Don’t Care Z 11 A 10 B 9 C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND CHANNEL‐SELECT INPUTS VCC Y X X1 X0 A B C 16 15 14 13 12 11 10 9 6 7 8 GND NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch Figure 5. Logic Diagram − MC74HCT4053A Triple Single−Pole, Double−Position Plus Common Off 1 2 3 4 5 Y1 Y0 Z1 Z Z0 Enable VEE Figure 6. Pinout: MC74HCT4053A (Top View) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Unit −0.5 to +7.0 −0.5 to +14.0 V VCC Positive DC Supply Voltage VEE Negative DC Supply Voltage (Referenced to GND) −7.0 to +5.0 V VIS Analog Input Voltage VEE − 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) I (Referenced to GND) (Referenced to VEE) Value −0.5 to VCC + 0.5 V ±25 mA 500 450 mW −65 to +150 °C DC Current, Into or Out of Any Pin PD Power Dissipation in Still Air, Tstg Storage Temperature Range SOIC Package† TSSOP Package† Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating − SOIC Package: − 7 mW/°C from 65°C to 125°C TSSOP Package: − 6.1 mW/°C from 65°C to 125°C http://onsemi.com 3 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HCT4051A, MC74HCT4052A, MC74HCT4053A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 2.0 6.0 12.0 V Negative DC Supply Voltage, Output (Referenced to GND) −6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V −55 +125 °C 0 0 0 0 1000 600 500 400 ns VCC Positive DC Supply Voltage VEE (Referenced to GND) (Referenced to VEE) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V *For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Symbol Parameter VCC V Condition Guaranteed Limit −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 4.5 to 5.5 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 4.5 to 5.5 0.8 0.8 0.8 V Iin Maximum Input Leakage Current, Channel−Select or Enable Inputs Vin = VCC or GND, VEE = − 6.0 V 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VIS = VCC or GND; VEE = GND VEE = − 6.0 VIO = 0 V 6.0 6.0 1 4 10 40 20 80 mA DC CHARACTERISTICS − Analog Section Guaranteed Limit Symbol Ron Parameter Maximum “ON” Resistance VCC VEE −55 to 25°C ≤85°C ≤125°C Unit Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA (Figures 7, 8) 4.5 4.5 6.0 0.0 −4.5 −6.0 190 120 100 240 150 125 280 170 140 W Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS ≤ 2.0 mA (Figures 7, 8) 4.5 4.5 6.0 0.0 −4.5 −6.0 150 100 80 190 125 100 230 140 115 Condition DRon Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA 4.5 4.5 6.0 0.0 −4.5 −6.0 30 12 10 35 15 12 40 18 14 Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 9) 5.0 −5.0 0.1 0.5 1.0 Maximum Off−Channel HCT4051A Vin = VIL or VIH; Leakage Current, HCT4052A VIO = VCC − VEE; Common Channel HCT4053A Switch Off (Figure 10) 5.0 5.0 5.0 −5.0 −5.0 −5.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Maximum On−Channel HCT4051A Vin = VIL or VIH; Leakage Current, HCT4052A Switch−to−Switch = Channel−to−Channel HCT4053A VCC − VEE; (Figure 11) 5.0 5.0 5.0 −5.0 −5.0 −5.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion http://onsemi.com 4 W mA mA MC74HCT4051A, MC74HCT4052A, MC74HCT4053A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Parameter Symbol Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Channel−Select to Analog Output (Figure 15) 2.0 3.0 4.5 6.0 270 90 59 45 320 110 79 65 350 125 85 75 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 16) 2.0 3.0 4.5 6.0 40 25 12 10 60 30 15 13 70 32 18 15 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 17) 2.0 3.0 4.5 6.0 160 70 48 39 200 95 63 55 220 110 76 63 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 17) 2.0 3.0 4.5 6.0 245 115 49 39 315 145 69 58 345 155 83 67 ns Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF Common O/I: HCT4051A HCT4052A HCT4053A 130 80 50 130 80 50 130 80 50 Feed−through 1.0 1.0 1.0 (All Switches Off) Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 19)* HCT4051A HCT4052A HCT4053A *Used to determine the no−load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . http://onsemi.com 5 45 80 45 pF MC74HCT4051A, MC74HCT4052A, MC74HCT4053A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Parameter Symbol BW − − Condition Maximum On−Channel Bandwidth or Minimum Frequency Response (Figure 12) fin = 1 MHz Sine Wave; Adjust fin Voltage to Obtain 0 dBm at VOS; Increase fin Frequency Until dB Meter Reads −3 dB; RL = 50 W, CL = 10 pF Off−Channel Feed−through Isolation (Figure 13) Feedthrough Noise. Channel−Select Input to Common I/O (Figure 14) − Crosstalk Between Any Two Switches (Figure 18) (Test does not apply to HCT4051A) THD VCC V Total Harmonic Distortion (Figure 20) Limit* VEE V 25°C ‘52 ‘53 80 80 80 95 95 95 120 120 120 2.25 4.50 6.00 −2.25 −4.50 −6.00 fin = Sine Wave; Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −50 −50 −50 fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −40 −40 −40 Vin ≤ 1 MHz Square Wave (tr = tf = 6 ns); Adjust RL at Setup so that IS = 0 A; Enable = GND RL = 600 W, CL = 50 pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 25 105 135 RL = 10 kW, CL = 10 pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 35 145 190 fin = Sine Wave; Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −50 −50 −50 fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −60 −60 −60 fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDmeasured − THDsource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave Unit ‘51 MHz dB mVPP dB % 2.25 4.50 6.00 −2.25 −4.50 −6.00 0.10 0.08 0.05 *Limits not tested. Determined by design and verified by qualification. 180 160 250 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 300 200 125°C 150 25°C -55°C 100 50 140 120 125°C 100 80 25°C 60 -55°C 40 20 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 0 2.25 0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 7. Figure 7a. Typical On Resistance, VCC − VEE = 2.0 V 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 Figure 7b. Typical On Resistance, VCC − VEE = 3.0 V http://onsemi.com 6 120 105 100 90 80 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) MC74HCT4051A, MC74HCT4052A, MC74HCT4053A 125°C 60 25°C 40 -55°C 20 0 75 125°C 60 25°C 45 -55°C 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.5 0 0.5 Figure 7c. Typical On Resistance, VCC − VEE = 4.5 V 3.0 3.5 4.0 4.5 5.0 5.5 6.0 60 70 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 2.0 2.5 Figure 7d. Typical On Resistance, VCC − VEE = 6.0 V 80 60 50 125°C 40 30 25°C 20 -55°C 10 0 1.0 1.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 0 1 2 3 4 5 6 7 8 50 125°C 40 25°C 30 -55°C 20 10 0 0 9 1 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 2 3 4 5 8 9 10 11 12 Figure 7f. Typical On Resistance, VCC − VEE = 12.0 V PLOTTER - 7 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 7e. Typical On Resistance, VCC − VEE = 9.0 V PROGRAMMABLE POWER SUPPLY 6 MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT VEE GND Figure 8. On Resistance Test Set−Up http://onsemi.com 7 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A VCC VCC VCC 16 VEE ANALOG I/O OFF A VCC VIH OFF VCC COMMON O/I OFF NC OFF VIH 6 7 8 VEE COMMON O/I 6 7 8 VEE Figure 9. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up Figure 10. Maximum Off Channel Leakage Current, Common Channel, Test Set−Up VCC VCC VCC 16 A VEE fin COMMON O/I OFF VOS 16 0.1mF ON VCC VCC 16 VEE dB METER ON N/C RL CL* ANALOG I/O VIL 6 7 8 6 7 8 VEE VEE Figure 11. Maximum On Channel Leakage Current, Channel to Channel, Test Set−Up VCC VIS fin VCC dB METER OFF RL Figure 12. Maximum On Channel Bandwidth, Test Set−Up VOS 16 0.1mF *Includes all probe and jig capacitance CL* 16 RL ON/OFF COMMON O/I ANALOG I/O RL OFF/ON RL RL 6 7 8 VEE VIL or VIH 3.0 V GND CHANNEL SELECT Vin ≤ 1 MHz tr = tf = 6 ns *Includes all probe and jig capacitance 6 7 8 VEE TEST POINT CL* VCC 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 13. Off Channel Feedthrough Isolation, Test Set−Up Figure 14. Feedthrough Noise, Channel Select to Common Out, Test Set−Up http://onsemi.com 8 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A VCC VCC 16 VCC CHANNEL SELECT (VI) ON/OFF Vm COMMON O/I ANALOG I/O OFF/ON GND tPLH TEST POINT CL* tPHL ANALOG OUT 6 7 8 50% VI = GND to 3.0 V Vm = 1.3 V CHANNEL SELECT *Includes all probe and jig capacitance Figure 15a. Propagation Delays, Channel Select to Analog Out Figure 15b. Propagation Delay, Test Set−Up Channel Select to Analog Out Figure 15. VCC 16 VCC ANALOG IN COMMON O/I ANALOG I/O ON 50% TEST POINT CL* GND tPHL tPLH ANALOG OUT 6 7 8 50% *Includes all probe and jig capacitance Figure 16a. Propagation Delays, Analog In to Analog Out Figure 16b. Propagation Delay, Test Set−Up Analog In to Analog Out Figure 16. tf ENABLE (VI) tr 90% VM VM 10% tPZL ANALOG OUT 1 VCC 2 GND tPLZ CL* VOL VOH 50% Figure 17a. Propagation Delays, Enable to Analog Out TEST POINT ON/OFF ENABLE VI = GND to 3.0 V Vm = 1.3 V 1kW ANALOG I/O 2 tPHZ 90% ANALOG OUT 16 1 50% tPZH VCC VCC HIGH IMPEDANCE 10% POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL 6 7 8 HIGH IMPEDANCE Figure 17. Figure 17b. Propagation Delay, Test Set−Up Enable to Analog Out http://onsemi.com 9 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A VCC VIS A VCC 16 RL fin 16 VOS ON/OFF ON COMMON O/I NC ANALOG I/O 0.1mF OFF/ON OFF VEE RL RL CL* RL CL* 6 7 8 VEE VCC 6 7 8 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 18. Crosstalk Between Any Two Switches, Test Set−Up Figure 19. Power Dissipation Capacitance, Test Set−Up 0 VIS VCC 0.1mF fin ON CL* -20 TO DISTORTION METER -30 -40 dB RL FUNDAMENTAL FREQUENCY -10 VOS 16 -50 DEVICE -60 6 7 8 VEE SOURCE -70 -80 *Includes all probe and jig capacitance -90 - 100 Figure 20. Figure 20a. Total Harmonic Distortion, Test Set−Up 1.0 2.0 3.125 FREQUENCY (kHz) Figure 20b. Plot, Harmonic Distortion APPLICATIONS INFORMATION The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 21, a maximum analog signal of ten volts peak−to−peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feed−through noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC − GND = 2 to 6 V VEE − GND = 0 to −6 V VCC − VEE = 2 to 12 V and VEE ≤ GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 22. These diodes should be able to absorb the maximum anticipated current surges during clipping. http://onsemi.com 10 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A VCC +5V 16 +5V ANALOG SIGNAL -5V ON 6 7 8 Dx +5V ANALOG SIGNAL VCC 16 Dx Dx VEE VEE 7 8 -5V VEE Figure 21. Application Example Figure 22. External Germanium or Schottky Clipping Diodes +5V +5V 16 +5V ANALOG SIGNAL VEE ON/OFF HC405x 6 7 8 VEE Dx ON/OFF -5V TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS 11 10 9 VCC ANALOG SIGNAL +5V * R R 11 10 9 +5V +5V VEE VEE 16 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL VEE HCT405x R +5V 6 7 8 LSTTL/NMOS CIRCUITRY 11 10 9 LSTTL/NMOS CIRCUITRY VEE * 2K ≤ R ≤ 10K a. Using Pull−Up Resistors with a HC Device b. Using HCT Interface Figure 23. Interfacing LSTTL/NMOS to CMOS Inputs A 11 13 LEVEL SHIFTER 14 B 10 15 LEVEL SHIFTER 12 C 9 1 LEVEL SHIFTER 5 ENABLE 6 2 LEVEL SHIFTER 4 3 Figure 24. Function Diagram, HCT4051A http://onsemi.com 11 X0 X1 X2 X3 X4 X5 X6 X7 X MC74HCT4051A, MC74HCT4052A, MC74HCT4053A A 10 12 LEVEL SHIFTER 14 B 9 15 LEVEL SHIFTER 11 13 ENABLE 6 1 LEVEL SHIFTER 5 2 4 3 X0 X1 X2 X3 X Y0 Y1 Y2 Y3 Y Figure 26. Function Diagram, HCT4052A A 11 13 LEVEL SHIFTER 12 14 B 10 1 LEVEL SHIFTER 2 15 C 9 3 LEVEL SHIFTER 5 4 ENABLE 6 LEVEL SHIFTER Figure 25. Function Diagram, HCT4053A http://onsemi.com 12 X1 X0 X Y1 Y0 Y Z1 Z0 Z MC74HCT4051A, MC74HCT4052A, MC74HCT4053A ORDERING INFORMATION Package Shipping† MC74HCT4051ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HCT4051ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74HCT4051ADTG TSSOP−16* 96 Units / Rail M74HCT4051ADTR2G TSSOP−16* 2500 / Tape & Reel MC74HCT4052ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HCT4052ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74HCT4052ADTG TSSOP−16* 96 Units / Rail M74HCT4052ADTR2G TSSOP−16* 2500 / Tape & Reel MC74HCT4052ADWG SOIC−16 WIDE (Pb−Free) 48 Units / Rail M74HCT4052ADWR2G SOIC−16 WIDE (Pb−Free) 1000 / Tape & Reel MC74HCT4053ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HCT4053ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74HCT4053ADTG TSSOP−16* 96 Units / Rail M74HCT4053ADTR2G TSSOP−16* 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 13 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S K S ÇÇÇ ÉÉ ÇÇÇ ÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HCT4051A, MC74HCT4052A, MC74HCT4053A PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 B M S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A PACKAGE DIMENSIONS SOIC−16 WIDE DW SUFFIX CASE 751G−03 ISSUE C A D 9 h X 45 _ E 0.25 H 8X M B M 16 q 1 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ 8 16X M 14X e T A S B S A1 L A 0.25 B B SEATING PLANE T C ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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