AD AD7302BRUZ 2.7 v to 5.5 v, parallel input dual voltage output 8-bit dac Datasheet

a
FEATURES
Two 8-Bit DACs In One Package
20-Lead DIP/SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer
Rail-to-Rail Operation
Low Power Operation 3 mA max @ 3.3 V
Power-Down to 1 mA max @ 258C
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
2.7 V to 5.5 V, Parallel Input
Dual Voltage Output 8-Bit DAC
AD7302
FUNCTIONAL BLOCK DIAGRAM
AD7302
D7
D0
INPUT
REGISTER
DAC
REGISTER
I DAC A
I/V
VOUTA
INPUT
REGISTER
DAC
REGISTER
I DAC B
I/V
VOUTB
A/B
WR
MUX
CONTROL
LOGIC
CS
POWER ON
RESET
÷2
PD
CLR
LDAC
REFIN
VDD
AGND
DGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7302 is a dual, 8-bit voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision
output buffers allow the DAC outputs to swing rail to rail. The
AD7302 has a parallel microprocessor and DSP-compatible
interface with high speed registers and double buffered interface
logic. Data is loaded to the registers on the rising edge of CS or
WR and the A/B pin selects either DAC A or DAC B.
1.␣ Low Power, Single Supply Operation. This part operates
from a single +2.7 V to +5.5 V supply and typically consumes
15 mW at 5 V, making it ideal for battery powered applications.
Reference selection for AD7302 can be either an internal
reference derived from the VDD or an external reference applied
at the REFIN pin. Both DACs can be simultaneously updated
using the asynchronous LDAC input and can be cleared by
using the asynchronous CLR input.
4.␣ High speed parallel interface.
2.␣ The on-chip output buffer amplifiers allow the outputs of the
DACs to swing rail to rail with a settling time of typically 1.2 µs.
3.␣ Internal or external reference capability.
5. Power-Down Capability. When powered down the DAC
consumes less than 1 µA at 25°C.
6. Packaged in 20-lead DIP, SOIC and TSSOP packages.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consumption is less than 10 mW at 3.3 V, reducing to 3 µW in powerdown mode.
The AD7302 is available in a 20-pin plastic dual-in-line package,
20-lead SOIC and a 20-lead TSSOP package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
(VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 kV to VDD and GND;
MAX unless otherwise noted)
AD7302–SPECIFICATIONS to T
Parameter
B Versions1
Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Zero Code Error @ 25°C
Gain Error3
Zero Code Temperature Coefficient
8
±1
±1
–0.75
3
±1
100
Bits
LSB max
LSB max
LSB typ
LSB typ
% FSR typ
µV/°C typ
DAC REFERENCE INPUT
REFIN Input Range
REFIN Input Impedance
1.0 to VDD/2
10
V min to max
MΩ typ
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Digital to Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DC Output Impedance
Short Circuit Current
Power Supply Rejection Ratio4
0 to VDD
2
7.5
1
0.2
0.2
± 0.2
40
14
0.0003
V min to max
µs max
V/µs typ
nV-s typ
nV-s typ
nV-s typ
LSB typ
Ω typ
mA typ
%/% max
LOGIC INPUTS
Input Current
VINL, Input Low Voltage
VINL, Input Low Voltage
VINH, Input High Voltage
VINH, Input High Voltage
Pin Capacitance
± 10
0.8
0.6
2.4
2.1
7
µA max
V max
V max
V min
V min
pF max
2.7/5.5
V min/max
POWER REQUIREMENTS
VDD
IDD
VDD = 3.3 V
@ 25°C
@ TMIN to TMAX
VDD = 5.5 V
@ 25°C
@ TMIN to TMAX
IDD (Full Power-Down)
@ 25°C
TMIN to TMAX
Conditions/Comments
Note 2
Guaranteed Monotonic
All Zeroes Loaded to DAC Register
Typically 1.2 µs
1 LSB Change Around Major Carry
∆VDD = ± 10%
VDD = +5 V
VDD = +3␣ V
VDD = +5 V
VDD = +3 V
2.8
3
mA max
mA max
4.5
5
mA max
mA max
Both DACs Active and Excluding Load Currents
VIH = VDD and VIL = GND
Typically 2.3 mA
See Figures 6 and 7
VIH = VDD and VIL = GND
Typically 2.8 mA
See Figures 6 and 7
1
2
µA max
µA max
VIH = VDD and VIL = GND
See Figure 18
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +105°C.
2
Relative Accuracy is calculated using a reduced code range of 15 to 245.
3
Gain error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4
Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
–2–
REV. 0
AD7302
(VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference;
MIN to T MAX unless otherwise noted)
TIMING CHARACTERISTICS1, 2 all specifications T
Parameter
Limit at TMIN, T MAX
(B Version)
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
0
0
0
0
20
15
4.5
20
20
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Address to Write Setup Time
Address Valid to Write Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
Data Setup Time
Data Hold Time
Write to LDAC Setup Time
LDAC Pulse Width
CLR Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of
(VIL + V IH )/2. tr and tf should not exceed 1 µs on any digital input.
2
See Figure 1.
t1
t2
A/B
CS
t4
t3
t5
WR
t6
t7
D7–D0
t8
t9
LDAC
t10
CLR
Figure 1. Timing Diagram for Parallel Data Write
REV. 0
–3–
AD7302
ABSOLUTE MAXIMUM RATINGS*
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 700 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature, Soldering
␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering
␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Reference Input Voltage to AGND . . . .–0.3 V to V DD + 0.3␣ V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 0.3 V
VOUTA, VOUTB to AGND . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 900 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 102°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7302 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature
Range
Package
Options*
AD7302BN
AD7302BR
AD7302BRU
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
N-20
R-20
RU-20
*N = Plastic DIP; R = Small Outline; RU =Thin Shrink Small Outline.
–4–
REV. 0
AD7302
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic Function
1-8
D7–D0
9
10
CS
WR
11
12
13
A/B
PD
LDAC
14
CLR
15
16
VDD
REFIN
17
18
19
20
AGND
VOUTB
VOUTA
DGND
Parallel Data Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of CS
and WR.
Chip Select. Active low logic input.
Write Input. WR is an active low logic input used in conjunction with CS and A/B to write data to the selected
DAC register.
DAC Select. Address pin used to select writing to either DAC A or DAC B.
Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with
the contents of their DAC registers. If LDAC is permanently tied low, the DACs are updated on the rising
edge of WR.
Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all
zeroes and the DAC outputs are cleared to zero volts.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND.
External Reference Input. This can used as the reference for both DACs. The range on this reference input is
1 V to VDD /2. If REFIN is directly tied to VDD the internal VDD /2 reference is selected.
Analog Ground reference point and return point for all analog current on the part.
Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output.
Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output.
Digital Ground reference point and return point for all digital current on the part.
PIN CONFIGURATION
(MSB) DB7 1
20 DGND
DB6 2
19 VOUTA
DB5 3
18 VOUTB
17 AGND
DB4 4
DB3 5
AD7302
16 REFIN
TOP VIEW 15 V
DD
(Not to Scale)
DB1 7
14 CLR
DB2 6
13 LDAC
(LSB) DB0 8
REV. 0
CS 9
12 PD
WR 10
11 A/B
–5–
AD7302
TERMINOLOGY
DIGITAL FEEDTHROUGH
INTEGRAL NONLINEARITY
Digital Feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital inputs of the same
DAC, but is measured when the DAC is not updated. It is
specified in nV-s and measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa.
For the DACs, relative accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A graphical representation of the transfer curve is shown in
Figure 14.
DIGITAL CROSSTALK
Digital Crosstalk is the glitch impulse transferred to the output
of one converter due to a digital code change to another DAC.
It is specified in nV-s.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maximum
ensures monotonicity.
ANALOG CROSSTALK
Analog Crosstalk is a change in output of any DAC in response
to a change in the output of the other DAC. It is measured in
LSBs.
ZERO CODE ERROR
Zero Code Error is the measured output voltage from VOUT of
either DAC when zero code (all zeros) is loaded to the DAC
latch. It is due to a combination of the offset errors in the DAC
and output amplifier. Zero scale error is expressed in LSBs.
POWER SUPPLY REJECTION RATIO (PSRR)
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
rejection ratio is quoted in terms of % change in output per %
change in VDD for full-scale output of the DAC. VDD is varied
± 10%.
GAIN ERROR
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from ideal, expressed
as a percent of the full-scale value. It includes full-scale errors
but not offset errors.
DIGITAL-TO-ANALOG GLITCH IMPULSE
Digital-to-Analog Glitch Impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected and the LDAC used to update the DAC. It is
normally specified as the area of the glitch in nV-s and is
measured when the digital input code is changed by 1 LSB at
the major carry transition.
–6–
REV. 0
Typical Performance Characteristics–AD7302
5
3.5
4.92
3.25
800
480
VOUT – Volts
VOUT – mV
560
400
320
240
3.0
4.76
2.75
4.68
4.6
4.52
4.36
80
4.28
2
4
6
SINK CURRENT – mA
4.2
8
␣ Figure 2. Output Sink Current Capa␣ bility with VDD = 3 V and VDD = 5 V
0
2.5
2.25
2.0
1.5
1.25
2
4
6
SOURCE CURRENT – mA
1.0
8
0
4.0
3.5
0.3
3.0
IDD – mA
INL ERROR
0.25
0.2
VDD = 5.5V
VDD = 3.3V
0.1
1.0
0.05
0.5
0
–50
0
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE – Volts
8
LOGIC INPUTS = VIH OR VIL
4.0
3.0
INTERNAL REFERENCE
LOGIC INPUTS = VDD OR GND
BOTH DACS ACTIVE
DNL ERROR
␣ ␣ ␣ ␣ Figure 5. Relative Accuracy vs.
␣ ␣ ␣ ␣ External Reference
5.0
2.5
2.0
1.5
0.15
7
BOTH DACS ACTIVE
INTERNAL REFERENCE USED
TA = +25°C
6.0
0.4
2
3
4
5
6
SOURCE CURRENT – mA
7.0
4.5
0.35
1
Figure 4. Output Source Current
Capability with VDD = 3 V
5.0
VDD = 5V
TA = +258C
VDD = 3V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHex
TA = +25°C
1.75
Figure 3. Output Source Current
Capability with V DD = 5 V
0.5
0.45
VDD = 5V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHEX
TA = +25°C
4.44
160
0
0
ERROR – LSBs
4.84
VOUT – Volts
640
IDD – mA
720
VDD = 5V AND 3V
INTERNAL REFERENCE
TA = +25 C
DAC LOADED WITH 00HEX
–25
0
25
50
75
TEMPERATURE – C
2.0
LOGIC INPUTS = VDD OR GND
100
125
Figure 6. Typical Supply Current
vs. Temperature
1.0
2.5
3.0
3.5
4.0
4.5
VDD – Volts
5.0
5.5
Figure 7. Typical Supply Current
vs. Supply Voltage
10
5
WR
ATTENUATION – dB
0
T
1←
–5
PD
2
–10
2←
–15
VOUT
VOUT
–20
–25
VDD = 5V
EXTERNAL SINEWAVE REFERENCE
DAC REGISTER LOADED WITH FFHEX
TA = +25°C
–30
–35
–40
1
10
100
1k
FREQUENCY – Hz
␣ ␣ ␣ ␣ ␣ ␣ Figure 8. Large Scale Signal
␣ ␣ ␣ ␣ ␣ ␣ Frequency Response
REV. 0
3←
10k
←
VDD = 3V
INTERNAL VOLTAGE
REFERENCE
FULL SCALE CODE
CHANGE 00H-FFH
TA = +25°C
CH1 5V, CH2 1V, CH3 20mV
TIME BASE = 200 ns/Div
Figure 9. Full-Scale Settling Time
–7–
1
VOUT
AD7302 POWER-UP TIME
VDD = 5V
INTERNAL REFERENCE
DAC IN POWER-DOWN INITIALLY
CH1 = 2V/div, CH2 = 5V/Div,
TIME BASE = 2 µs/Div
␣ Figure 10. Exiting Power-Down (Full
␣ Power-Down)
AD7302
10
9
T
VDD
8
ZERO CODE ERROR – LSB
1
T
2
VOA
T
3
VOB
VDD = 2.7 TO 5.5V
DAC LOADED WITH ALL ZEROES
INTERNAL REFERENCE
6
5
VOUT
4
DAC B
3
2
DAC A
0
–50
2←
5.00V M20.0ms CH1
VDD = 5V
INTERNAL REFERENCE
5kΩ 100pf. LOAD
LIMITED CODE RANGE (10–245)
TA = +25°C
INL ERROR – LSB
0
–0.1
50
75
100
CH1 5.00V, CH2 50.0mV, M 250ns
125
Figure 13. Small-Scale Settling Time
0.5
0.5
0.4
0.4
0.3
DAC A
0.1
DAC B
–0.2
0.2
0.1
0.3
VDD = 5V
INTERNAL REFERENCE
0
–0.1
–0.2
0.2
0.1
0
–0.2
–0.3
–0.3
–0.4
–0.4
–0.4
0
32
64 96 128 160 192 224 256
INPUT CODE (10 to 245)
Figure 14. Integral Linearity Plot
–0.5
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 15. Typical INL vs. Temperature
–0.5
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 16. Typical DNL vs. Temperature
1000
1.0
VDD = 5V
LOGIC INPUTS = VDD OR GND
900
VDD = 5V
POWER-DOWN CURRENT – nA
–0.5
VDD = 5V
INTERNAL REFERENCE
–0.1
–0.3
INT REFERENCE ERROR – 6%
INL ERROR – LSB
0.2
25
Figure 12. Zero Code Error vs.
Temperature
0.5
0.3
0
TEMPERATURE – C
Figure 11. Power-On—RESET
0.4
–25
DNL ERROR – LSB
5.00V CH2
5.00V
VDD = 5V
INTERNAL VOLTAGE
REFERENCE
10 LSB STEP CHANGE
TA = +258C
7
1
CH1
CH3
WR
1←
0.8
0.6
0.4
0.2
800
700
600
500
400
300
200
100
0
–60 –40 –20
0
–50
0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 17. Typical Internal Reference
Error vs. Temperature
–25
25
50
75
0
TEMPERATURE – C
100
125
Figure 18. Power-Down Current vs.
Temperature
–8–
REV. 0
AD7302
GENERAL DESCRIPTION
D/A Section
The AD7302 is a dual 8-bit voltage output digital-to-analog
converter. The architecture consists of a reference amplifier, a
current source DAC followed by a current-to-voltage converter
capable of generating rail-to-rail voltages on the output of the
DAC. Figure 19 shows a block diagram of the basic DAC
architecture.
AD7302
VDD
REFERENCE
AMPLIFIER
30kΩ
+
REFIN
11.7kΩ
CURRENT
DAC
-
I/V
VO A/B
11.7kΩ
30kΩ
The internal reference is selected by tying the REFIN pin to
VDD. If an external reference is to be used, this can be directly
applied to the REFIN pin; if this is 1 V below VDD , the internal
circuitry will select this externally applied reference as the
reference source for the DAC.
Digital Interface
The AD7302 contains a fast parallel interface allowing this dual
DAC to interface to industry standard microprocessors, microcontrollers and DSP machines. There are two modes in which
this parallel interface can be configured to update the DAC
outputs. The simultaneous update mode allows simultaneous
updating of both DAC outputs. The automatic update mode
allows each DAC to be individually updated following a write
cycle. Figure 21 shows the internal logic associated with the
digital interface. The PON STRB signal is internally generated
from the power on reset circuitry and is low during the poweron reset phase of the power-up procedure.
Figure 19. DAC Architecture
Both DAC A and DAC B outputs are internally buffered and
these output buffer amplifiers have rail-to-rail output characteristics. The output amplifier is capable driving a load of 10 kΩ to
both VDD and ground in parallel with a 100 pF to ground. The
reference selection for the DAC can either be internally generated
from VDD or externally applied through the REFIN pin. A
comparator on the REFIN pin detects whether the required
reference is the internally generated reference or the externally
applied voltage to the REFIN pin. If REFIN is connected to
VDD, the reference selected is the internally generated VDD/2
reference. When an externally applied voltage is more than one
volt below VDD, the comparator selection switches to the
externally applied voltage to the REFIN pin. The range on the
external reference input is from 1.0 V to VDD/2. The output
voltage from either DAC is given by:
VO A/B = 2 × VREF × (N/256)
where:
VREF is the voltage applied to the external REFIN pin or
VDD/2 when the internal reference is selected.
␣␣ N
CLR
CLR
PON STRB
CLEAR
SET SLE
LDAC
DAC A
CONTROL
LOGIC
LDAC
SLE A
DAC A SEL
ENABLE
A/B
CLEAR
SET SLE
DAC B
CONTROL
LOGIC
LDAC
WR
Figure 21. Logic Interface
The AD7302 has a double buffered interface, which allows
for simultaneous updating of the DAC outputs. Figure 22 shows
a block diagram of the register arrangement within the AD7302.
DB7–DB0
is the decimal equivalent of the code loaded to the DAC
register and ranges from 0 to 255.
INPUT
REGISTER
8
Reference
4
The AD7302 has the facility to use either an external reference
applied through the REFIN pin or an internal reference
generated from VDD . Figure 20 shows the reference input
arrangement where either the internal VDD /2 reference or the
externally applied reference can be selected.
4 TO 15
DECODER
4
4 TO 15
DECODER
15
MLE
A/B
CS
WR
LDAC
CLR
VDD
VTH
PMOS
SLE
CONTROL
LOGIC
DAC
REGISTER
15
DAC
REGISTER
15
DRIVERS
15
DRIVERS
30
30
COMPARATOR
INT REF
LOWER
NIBBLE
REFIN
MUX
SELECTED
REFERENCE OUTPUT
Figure 20. Reference Selection Circuitry
REV. 0
UPPER
NIBBLE
Figure 22. Register Arrangement
EXT REF
INT
REF
MLE B
SLE B
DAC B SEL
ENABLE
CS
MLE A
–9–
AD7302
Automatic Update Mode
POWER-ON RESET
In this mode of operation the LDAC signal is permanently tied
low. The state of the LDAC is sampled on the rising edge of
WR. LDAC being low allows the selected DAC register to be
automatically updated on the rising edge of WR. The output
update occurs on the rising edge of WR. Figure 23 shows the
timing associated with the automatic update mode of operation
and also the status of the various registers during this frame.
The AD7302 has a power-on reset circuit designed to allow
output stability during power-up. This circuit holds the DACs
in a reset state until a write takes place to the DAC. In the reset
state all zeros are latched into the input registers of each DAC
and the DAC registers are in transparent mode, thus the output
of both DACs is held at ground potential until a write takes
place to the DAC. The power-on reset circuitry generates a
PON STRB signal, which is a gating signal used within the logic
to identify a power-on condition.
A/B
POWER-DOWN FEATURES
CS
The AD7302 has a power-down feature. This is implemented
by exercising the external PD pin; an active low signal puts the
complete DAC into power-down mode. When in power-down
the current consumption of the device is reduced to 1 µA max at
25°C and 2 µA max over temperature, making the device
suitable for use in portable battery powered equipment. When
power-down is activated, the reference bias servo loop and the
output amplifiers with their associated linear circuitry are
powered down, the reference resistors are open circuited to
further reduce the power consumption. The output sees a load
of approximately 23 kΩ to GND when in power-down mode as
shown in Figure 25. The contents of the data registers are
unaffected when in power-down mode. The device comes out
of power-down in typically 13 µs (see Figure 10).
WR
D7–D0
LDAC = 0
I/P REG (MLE)
DAC REG (SLE)
HOLD
TRACK
HOLD
TRACK
HOLD
TRACK
VOUT
Figure 23. Timing and Register Arrangement for Automatic Update Mode
Simultaneous Update Mode
11.7kΩ
In this mode of operation the LDAC signal is used to update both
DAC outputs simultaneously. The state of the LDAC is sampled
on the rising edge of WR. If LDAC is high, the automatic update
mode is disabled and both DAC latches are updated at any time
after the write by taking LDAC low. The output update occurs
on the falling edge of LDAC. LDAC must be taken back high
again before the next data transfer takes place. Figure 24
shows the timing associated with the simultaneous update mode
of operation and also the status of the various registers during
this frame.
VDD
IDAC
11.7kΩ
VREF
Figure 25. Output Stage During Power-Down
Analog Outputs
The AD7302 contains two independent voltage output DACs
with 8-bit resolution and rail-to-rail operation. The output buffer
provides a gain of two at the output. Figures 2 to 4 show the
source and sink capabilities of the output amplifier. The slew
rate of the output amplifier is typically 7.5 V/µs and has a fullscale settling to 8 bits with a 100 pF capacitive load in typically
1.2 µs.
A/B
CS
WR
D7–D0
LDAC
I/P REG (MLE)
DAC REG (SLE)
HOLD
TRACK
HOLD
The input coding to the DAC is straight binary. Table I shows
the binary transfer function for the AD7302. Figure 26 shows
the DAC transfer function for binary coding. Any DAC output
voltage can be expressed as:
HOLD
TRACK
VOUT = 2 × VREF (N/256)
HOLD
VOUT
Figure 24. Timing and Register Arrangement for Simultaneous Update Mode
where:
␣␣N
–10–
is the decimal equivalent of the binary input code.
N ranges from 0 to 255.
REV. 0
AD7302
␣ ␣ VREF
is the voltage applied to the external REFIN pin when
the external reference is selected and is VDD/2 if the
internal reference is used.
VDD = 3 TO 5V
0.1µF 10µF
Table I. Output Voltage for Selected Input Codes
VDD
Digital Input
MSB . . . LSB
Analog Output
1111 1111
1111 1110
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
2 × 255/256 × VREF V
2 × 254/256 × VREF V
2 × 129/256 × VREF V
VREF V
2 × 127/256 × VREF V
2 × VREF/256␣ V
0V
VOUTA
AD7302
CLR
VOUTB
PD
D7–D0
A/B CS
VOUTB
WR LDAC
VDD
DATA BUS
CONTROL INPUTS
Figure 27. Typical Configuration Selecting the Internal
Reference
Figure 28 shows a typical setup for the AD7302 when using an
external reference. The reference range for the AD7302 is from
1 V to VDD /2 V. Higher values of reference can be incorporated,
but will saturate the output at both the top and bottom end of
the transfer function. There is a gain of two from input to output
on the AD7302. Suitable references for 5 V operation are the
AD780 and REF192. For 3 V operation a suitable external
reference would be the AD589 a 1.23 V bandgap reference.
2.VREF
DAC OUTPUT VOLTAGE
AGND DGND
VOUTA
REF IN
VREF
VDD = 3 TO 5V
0.1µF 10µF
0
DAC INPUT
CODE
VIN
00
01
7F
80
81
FE
VDD
FF
EXT REF
VOUT
0.1µF
CLR
REV. 0
VOUTB
PD
Figure 27 shows a typical setup for the AD7302 when using its
internal reference. The internal reference is selected by tying the
REFIN pin to VDD . Internally in the reference section there is a
reference detect circuit that will select the internal VDD /2 based
on the voltage connected to the REFIN pin. If REFIN is within
a threshold voltage of a PMOS device (approximately 1 V) of
VDD the internal reference is selected. When the REFIN voltage
is more than 1 V below VDD , the externally applied voltage at
this pin is used as the reference for the DAC. The internal
reference on the AD7302 is VDD/2, the output current to voltage
converter within the AD7302 provides a gain of two. Thus the
output range of the DAC is from 0 V to VDD, based on Table I.
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
VOUTA
AD7302
GND
Figure 26. DAC Transfer Function
AGND DGND
VOUTA
REF IN
D7–D0
A/B CS
VOUTB
WR LDAC
VDD
DATA BUS
CONTROL INPUTS
Figure 28. Typical Configuration Using An External
Reference
–11–
AD7302
MICROPROCESSOR INTERFACING
AD7302–ADSP-2101/ADSP-2103 Interface
A15
ADDRESS BUS
Figure 29 shows an interface between the AD7302 and the
ADSP-2101/ADSP-2103. The fast interface timing associated
with the AD7302 allows easy interface to the ADSP-2101/
ADSP-2103.
A0
A**
IS
A/B
ADDR
EN
DECODE
TMS32020
CS
A+1**
STRB
DMA14
WR
R/W
ADDRESS BUS
DB7
DMA0
A**
DMS
EN
ADDR
DECODE
ADSP-2101*/
ADSP-2103*
WR
DB0
A/B
CS
A+1**
AD7302*
LDAC
DMD15
AD7302*
DATA BUS
LDAC
DMD0
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
WR
DB7
DB0
DMD15
DATA BUS
DMD0
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
Figure 29. AD7302–ADSP-2101/ADSP-2103 Interface
Two addresses are decoded to select loading data to either
DAC A or DAC B. LDAC is permanently tied low in this
circuit, so the selected DAC output is updated on the rising
edge of the WR signal.
Data is loaded to the AD7302 input register using the following
ADSP-21xx instruction:
DM (DAC) = MR0
MR0 = ADSP-21xx MR0 Register.
Figure 30. AD7302–TMS32020 Interface
In the circuit shown the LDAC is hardwired low, thus the
selected DAC output is updated on the rising edge of WR.
Some applications may require simultaneous updating of both
DACs in the AD7302. In this case the LDAC signal can be
driven from an external timer or can be controlled by the
microprocessor. One option for simultaneous updating is to
decode the LDAC from the address bus so that a write operation at this address will simultaneously update both DAC
outputs. A simple OR gate with one input driven from the
decoded address and the second input from the WR signal will
implement this function.
AD7302–8051/8088 Interface
Figure 31 shows a serial interface between the AD7302 and the
8051/8088 processors. The address decoder is used to decode
the addresses for DAC A and DAC B.
DAC = Decoded DAC Address.
A15
ADDRESS BUS
AD7302–TMS32020 Interface
A8
Figure 30 shows an interface between the AD7302 and the
TMS32020. The address decoder is used to decode the
addresses for DAC A and DAC B. Data is loaded to the
AD7302 using the following instruction:
A**
/B
ADDR
DECODE
OR
AD7302*
A+1**
OUT DAC, D
8051/8088
DAC = Decoded DAC Address.
ALE
D = Data Memory Address.
OCTAL
LATCH
DB7
DB0
AD7
ADDRESS/DATA BUS
AD0
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
Figure 31. AD7302–8051//8088 Interface
–12–
REV. 0
AD7302
APPLICATIONS
Bipolar Operation Using the AD7302
AD7302
DATA BUS
The AD7302 has been designed for single supply operation,
but bipolar operation is achievable using the circuit shown in
Figure 32. The circuit shown has been configured to achieve an
output voltage range of –5 V < VO < +5 V. Rail-to-rail operation
at the amplifier output is achievable using an AD820 or OP295
as the output amplifier.
VOUTA
D0
D8
VDD
ENABLE
VCC
1
CODED
ADDRESS
The output voltage for any input code can be calculated as
follows:
AD7302
1Y0
1A
1B
VOUTA
1Y1
1Y2
74HC139
D0
D8
1Y3
DGND
VO = [(1+R4/R3) × (R2/(R1+R2) × (2 × VREF × D/256)] – R4 × VREF/R3
VOUTA
D0
D8
With VREF = 2.5 V, R1 = R3 = 10␣ kΩ and R2 = R4 = 20 kΩ and
VDD = 5␣ V.
VOUT = (10 × D/256) – 5 V
VOUTA
D0
D8
0.1µF 10µF
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
±5V
–5V
REF IN
0.1µF
Figure 33. Decoding Multiple AD7302 DACs in a System
+5V
AD820/
OP295
VDD
GND
AD7302
AGND
VOUTA
DGND
R1
10kΩ
AD7302 As a Digitally Programmable Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD7302 is shown in Figure 34. The upper
and lower limits for the test are loaded to DACs A and B, which
in turn set the limits on the CMP04. If a signal at the VIN input
is not within the programmed window an LED will indicate the
fail condition.
R2
20kΩ
+5V
0.1µF
VIN
10µF
Figure 32. Bipolar Operation Using the AD7302
VDD
PD
Decoding Multiple AD7302 in a System
The CS pin on the AD7302 can be used in applications to
decode a number of DACs. In this application all DACs in the
system receive the same input data, but only the CS to one of
the DACs will be active at any one time allowing access to two
channels in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the enable input should
be brought to its inactive state while the coded address inputs are
changing state. Figure 33 shows a diagram of a typical setup for
decoding multiple AD7302 devices in a system. The built-in
power-on reset circuit on the AD7302 ensures that the outputs
of all DACs in the system power up with zero volts on their
outputs.
REV. 0
VOUTB
R4
20kΩ
R3
10kΩ
VOUT
VOUTB
AD7302
VDD = 5V
EXT REF
VOUTB
AD7302
where
␣ ␣ D is the decimal equivalent of the code loaded to the DAC
and
␣ ␣ VREF is the reference voltage input.
VIN
VOUTB
1k
1k
FAIL
PASS
REFIN
AD7302
D7
VOUTA
D0
PASS/FAIL
A/B
VOUTB
CS
1/6 74HC05
WR
DVDD
CLR
LDAC
1/2 CMP04
DGND
AGND
Figure 34. Programmable Window Detector
–13–
AD7302
Programmable Current Source
VDD = 5V
Figure 35 shows the AD7302 used as the control element of a
programmable current source. In this circuit the full-scale
current is set to 1 mA. The output voltage from the DAC is
applied across the current setting resistor of 4.7 kΩ in series
with the full-scale setting resistor of 470 Ω. Transistors suitable
to place in the feedback loop of the amplifier include the BC107
or the 2N3904, which enable the current source to operate from
a min VSOURCE of 6 V. The operating range is determined by
the operating characteristics of the of the transistor. Suitable
amplifiers include the AD820 and the OP295 both having railto-rail operation on their outputs. The current for any digital
input code can be calculated as follows:
0.1µF 10µF
R4
390Ω
R3
51.2kΩ
+5V
VIN
EXT REF
AD820/
OP295
VDD
VOUTA
REF IN
VOUT
R1
390Ω
0.1µF
AD7302
GND
VOUT
VOUTB
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
I = 2 × VREF × D/(5E +3 × 256) mA
AGND
DGND
R2
51.2kΩ
Figure 36. Coarse/Fine Adjust Circuit
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7302 is mounted should be designed so the analog and
digital sections are separated and confined to certain areas of the
board. If the AD7302 is in a system where multiple devices
require an AGND to DGND connection, the connection should
be made at one point only, a star ground point that should be
established as closely as possible to the AD7302. The AD7302
should have ample supply bypassing of 10 µF in parallel with
0.1 µF on the supply located as close to the package as possible,
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. The 0.1 µF capacitor should have low
Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types, which provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
VDD = 5V
0.1µF 10µF
VIN
VSOURCE
VDD
EXT REF
+5V
REF IN
VOUT
0.1µF
GND
AD780/REF192
WITH VDD = 5V
AD7302
LOAD
VOUTA
AD820/
OP295
AGND DGND
4.7kΩ
470Ω
Figure 35. Programmable Current Source
Coarse and Fine Adjustment Using the AD7302
The DACs on the AD7302 can be paired together to form a
coarse and fine adjustment function as shown in Figure 36. In
this circuit DAC A is used to provide the coarse function while
DAC B is used to provide the fine adjustment. Varying the ratio
of R1 and R2 will vary the relative effect of the coarse and fine
tune elements in the circuit. For the resistor values shown
DAC B has a resolution of 148 µV giving a fine tune range of
approximately 2 LSBs for operation with a VDD of 5 V and a
reference of 2.5 V. The amplifiers shown allow a rail-to-rail
output voltage to be achieved on the output. A typical application for such a circuit would be in a setpoint controller.
The power supply lines of the AD7302 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid
radiating noise to other parts of the board and should never be
run near the reference inputs. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board should run
at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the
best, but not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to
ground plane while signal traces are placed on the solder side.
–14–
REV. 0
AD7302
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Plastic DIP
(N-20)
1.060 (26.90)
0.925 (23.50)
20
11
1
10
PIN 1
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.045 (1.15) PLANE
20-Lead SO
(R-20)
11
1
10
PIN 1
0.4193 (10.65)
0.3937 (10.00)
20
0.2992 (7.60)
0.2914 (7.40)
0.5118 (13.00)
0.4961 (12.60)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0500 0.0192 (0.49)
0°
(1.27) 0.0138 (0.35) SEATING 0.0125 (0.32)
PLANE
BSC
0.0091 (0.23)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
20-Lead TSSOP
(RU-20)
0.260 (6.60)
0.252 (6.40)
11
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
20
1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. 0
10
PIN 1
0.0433
(1.10)
MAX
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–15–
8°
0°
0.028 (0.70)
0.020 (0.50)
–16–
PRINTED IN U.S.A.
C2990–12–4/97