AVAGO HCPL-0302-500E 0.4 amp output current igbt gate drive optocoupler Datasheet

HCPL-3020/HCPL-0302
0.4 Amp Output Current IGBT Gate Drive Optocoupler
Data Sheet
Description
Features
The HCPL-3020 and HCPL-0302 consist of a GaAsP LED
optically coupled to an integrated circuit with a power
output stage. These optocouplers are ideally suited for
driving power IGBTs and MOSFETs used in motor control
inverter applications. The high operating voltage range of
the output stage provides the drive voltages required by
gate-controlled devices. The voltage and current supplied
by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. For IGBTs with higher
ratings, the HCPL-0314/3140 (0.6 A), HCPL‑3150 (0.6 A) or
HCPL-3120 (2.5 A) gate drive opto-couplers can be used.
• 0.4 A maximum peak output current
• 0.2 A minimum peak output current
• High speed response: 0.7 µs maximum propagation
delay over temperature range
• Ultra high CMR: minimum 10 kV/µs at VCM = 1000 V
• Bootstrappable supply current: maximum 3 mA
• Wide operating temperature range: –40°C to 100°C
• Wide VCC operating range: 10 V to 30 V over temperature range
• Available in DIP 8 and SO-8 packages
• Safety approvals: UL approval, 3750 VRMS for 1 minute
• CSA approval
• IEC/EN/DIN EN 60747-5-2 approval
VIORM = 630 VPEAK (HCPL-3020),
VIORM = 566 VPEAK (HCPL-0302)
Functional Diagram
N/C
1
8
VCC
ANODE
2
7
N/C
CATHODE
3
6
VO
N/C
4
5
VEE
SHIELD
Truth Table
LED
VO
OFF
LOW
ON
HIGH
Applications
•
•
•
•
•
•
•
Isolated IGBT/power MOSFET gate drive
AC and brushless DC motor drives
Industrial inverters
Air conditioner
Washing machine
Induction heater for cooker
Switching power supplies (SPS)
Note:
A 0.1 uF bypass capacitor must be connected between pins VCC and VEE.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and /or degradation which may be induced by ESD.
Ordering Information
Specify part number followed by option number (if desired).
Example:
HCPL-3020-XXXX
No option = Standard DIP package, 50 per tube
300 = Gull Wing Surface Mount Option, 50 per tube
500 = Tape and Reel Packaging Option
060 = IEC/EN/DIN EN 60747-5-2, VIORM = 630 VPEAK
XXXE = Lead Free Option
HCPL-0302-XXXX
No option = Standard SO-8 package, 100 per tube
500 = Tape and Reel Packaging Option
060 = IEC/EN/DIN EN 60747-5-2, VIORM = 566 VPEAK
XXXE = Lead Free Option
Package Outline Drawings
HCPL-3020 Standard DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
5
OPTION CODE*
6.35 ± 0.25
(0.250 ± 0.010)
DATE CODE
A XXXXZ
YYWW
1
1.19 (0.047) MAX.
2
3
4
1.78 (0.070) MAX.
5 TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
+ 0.076
- 0.051
+ 0.003)
(0.010 - 0.002)
0.254
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE:
FLOATING LEAD PROTUSION IS 0.25 mm (10 mils) MAX.
HCPL-3020 Gull Wing Surface Mount Option 300
Land Pattern Recommendation
9.65 ± 0.25
(0.380 ± 0.010)
6
7
8
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
3
2
10.9 (0.430)
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
12 NOM.
NOTE: FLOATING LEAD PROTUSION IS 0.25 mm (10 mils) MAX.
HCPL-0302 Small Outline SO-8 Package
Land Pattern Recommendation
8
7
6
5
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
PIN ONE
1
2
3
0.406 ± 0.076
(0.016 ± 0.003)
4
1.9 (0.075)
1.270 BSC
(0.050)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
*
7
1.524
(0.060)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
45 X
0.432
(0.017)
0~7
0.228 ± 0.025
(0.009 ± 0.001)
0.203 ± 0.102
(0.008 ± 0.004)
0.305 MIN.
(0.012)
NOTE: FLOATING LEAD PROTUSION IS 0.15 mm (6 mils) MAX.
Solder Reflow Temperature Profile
300
PREHEATING RATE 3˚C + 1˚C/–0.5˚C/SEC.
REFLOW HEATING RATE 2.5˚C ± 0.5˚C/SEC.
TEMPERATURE (˚C)
200
PEAK
TEMP.
245˚C
PEAK
TEMP.
240˚C
2.5˚C ± 0.5˚C/SEC.
SOLDERING
TIME
200˚C
30
SEC.
160˚C
150˚C
140˚C
PEAK
TEMP.
230˚C
30
SEC.
3˚C + 1˚C/–0.5˚C
100
PREHEATING TIME
150˚C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
0
0
50
ROOM TEMPERATURE
100
150
TIME (SECONDS)
Note: Use of non-chlorine-activated fluxes is highly recommended
Recommended Solder Reflow Temperature Profile (Lead free)
TEMPERATURE (˚C)
tp
Tp
217 ˚C
TL
Tsmax
Tsmin
260 +0/-5 ˚C
RAMP-UP
3 ˚C/SEC. MAX.
150 - 200 ˚C
ts
PREHEAT
60 to 180 SEC.
TIME WITHIN 5 ˚C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
RAMP-DOWN
6 ˚C/SEC. MAX.
tL
60 to 150 SEC.
25
t 25 ˚C to PEAK
TIME (SECONDS)
NOTES:
THE TIME FROM 25 ˚C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 ˚C, Tsmin = 150 ˚C
Note: Use of non-chlorine-activated fluxes is highly recommended
200
250
Regulatory Information
The HCPL-0302/3020 has been approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
(Option 060 only)
UL
Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (HCPL-3020 and HCPL-0302 Option 060)
Description
Symbol
HCPL-3020 HCPL-0302 Unit
Installation Classification per DIN VDE 0110/1.89, Table 1
for Rated Mains Voltage ­ 150 Vrms
I – IV
I – IV
for Rated Mains Voltage ­ 300 Vrms
I – III
I – III
for Rated Mains Voltage ­ 600 Vrms
I – II
Climatic Classification
55/100/21
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
2
Maximum Working Insulation Voltage
VIORM
630
566
Vpeak
VPR
1181
1050
Vpeak
VPR
945
840
Vpeak
VIOTM
6000
4000
Vpeak
Input to Output Test Voltage, Method b [1]
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a [1]
VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec,
Partial Discharge < 5 pC
Highest Allowable Overvoltage
(Transient Overvoltage tini = 10 sec)
Safety-Limiting Values – Maximum Values Allowed in the Event of a
Failure.
Case Temperature
TS
175
150
°C
Input Current [2]
IS, INPUT
230
150
mA
Output Power [2]
PS, OUTPUT
600
600
mW
RS
>109
>109
Ω
Insulation Resistance at TS, VIO = 500 V
800
OUTPUT POWER – PS, INPUT CURRENT – IS
1. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section,
(IEC/EN/DIN EN 60747-5-2), for a detailed description of Method a
and Method b partial discharge test profiles.
2. Refer to the following figure for dependence of PS and IS on ambient
temperature.
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0
25
50
75
100 125 150 175 200
TS – CASE TEMPERATURE – C
Insulation and Safety Related Specifications
Parameter
Symbol HCPL-3020 HCPL-0302 Units Conditions
Minimum External Air Gap
L(101) 7.1
4.9
mm
(Clearance)
Minimum External Tracking L(102) 7.4
4.8
mm
(Creepage)
Minimum Internal Plastic Gap
0.08
0.08
mm
(Internal Clearance)
Tracking Resistance
CTI
(Comparative Tracking
Index)
Isolation Group
>175
>175
IIIa
IIIa
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Input Current
Peak Transient Input Current (<1 µs pulse width, 300 pps)
Reverse Input Voltage
“High” Peak Output Current
“Low” Peak Output Current
Supply Voltage
Output Voltage
Output Power Dissipation
Input Power Dissipation
Lead Solder Temperature
Solder Reflow Temperature Profile
Recommended Operating Conditions
Parameter
Symbol
Power Supply
VCC - VEE
Input Current (ON)
IF(ON)
Input Voltage (OFF)
VF(OFF)
Operating Temperature
TA
Min.
10
7
–3.0
–40
V
Measured from input terminals to output
terminals, shortest distance through air.
Measured from input terminals to output
terminals, shortest distance path along
body.
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and
detector.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89,
Table 1)
Symbol
Min.
Max.
Units
Note
TS
–55
125
°C
TA
–40
100
°C
IF(AVG)
20
mA
1
IF(TRAN)
1.0
A
VR
5
V
IOH(PEAK)
0.4
A
2
IOL(PEAK)
0.4
A
2
VCC – VEE
–0.5
35
V
VO(PEAK)
–0.5
VCC
V
PO
250
mW
3
PI
45
mW
4
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings section
Max.
30
12
0.8
100
Units
Note
V
mA
V
°C
Electrical Specifications (DC)
Over recommended operating conditions unless otherwise specified.
Parameter
Note
Symbol Min.
Typ.
Max. Units Test Conditions Fig.
High Level Output Current
IOH
0.15
A
VO = VCC – 4
5
0.2
0.3
A
VO = VCC – 10
2
2
Low Level Output Current
IOL
0.15
A
VO = VEE + 2.5
5
0.2
0.3
A
VO = VEE + 10
4
2
High Level Output Voltage
VOH
VCC – 4 VCC – 1.8
V
IO = –100 mA
1
6, 7
Low Level Output Voltage
VOL
0.4
1
V
IO = 100 mA
3
High Level Supply Current
ICCH
0.7
3
mA
IO = 0 mA
5, 6
14
Low Level Supply Current
ICCL
1.2
3
mA
IO = 0 mA
Threshold Input Current Low to High
IFLH
6
mA
IO = 0 mA,
7, 13
VO > 5 V
Threshold Input Voltage High to Low
VFHL
0.8
V
Input Forward Voltage
VF
1.2
1.5
1.8 V
IF = 10 mA
14
Temperature Coefficient of Input
DVF/DTA
–1.6
mV/°C
Forward Voltage
Input Reverse Breakdown Voltage
BVR
5
V
IR = 10 µA
Input Capacitance
CIN
60
pF
f = 1 MHz,
VF = 0 V
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Parameter
Symbol Min. Typ. Max. Units Test Conditions
Fig.
Note
Propagation Delay Time to High
tPLH
0.1 0.2 0.7 µs
Rg=75Ω, Cg = 1.5 nF,
8, 9
14
Output Level
f = 10 kHz, Duty Cycle = 50%, 10, 11
IF = 7 mA, VCC = 30 V
12, 15
Propagation Delay Time to Low
tPHL
0.1 0.2 0.7 µs
Output Level
Propagation Delay Difference
PDD
–0.5
0.5 µs
10
Between Any Two Parts or Channels
Rise Time
tR
50
ns
Fall Time
tF
50
ns
Output High Level Common Mode
|CMH|
10
kV/µs TA = 25°C, VCM = 1000 V
16
11
Transient Immunity
Output Low Level Common Mode
|CML|
10
kV/µs
16
12
Transient Immunity
Package Characteristics
Parameter
Symbol
Input-Output Momentary
Withstand Voltage
Input-Output Resistance
Input-Output Capacitance
VISO
Min.
Typ. Max.
3750
RI-O
CI-O
1012
0.6
Units
Test Conditions
Fig. Note
Vrms
TA = 25°C, RH < 50%
8, 9
Ω
pF
VI-O = 500 V
Freq = 1 MHz
9
-0.5
-1.0
-1.5
-2.0
-2.5
-50
-25
0
25
50
75
TA – TEMPERATURE – C
100
125
0
0.44
VOL – OUTPUT LOW VOLTAGE – V
0
(VOH-VCC) – OUTPUT HIGH VOLTAGE DROP – V
(VOH-VCC) – HIGH OUTPUT VOLTAGE DROP – V
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 0.2 A. See Application section for additional details on limiting IOL peak.
3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C.
4. Input power dissipation does not require derating.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage >4500 Vrms for 1 second (leakage detection current limit II-O < 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN
60747-5-2 Insulation Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PDD is the difference between tPHL and tPLH between any two parts or channels under the same test conditions.
11. Common mode transient immunity in the high state is the maximum tolerable |dVCM/dt| of the common mode pulse VCM to assure that the
output will remain in the high state (i.e. VO > 6.0 V).
12. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e. VO < 1.0 V).
13. This load condition approximates the gate load of a 1200 V/20 A IGBT.
14. The power supply current increases when operating frequency and Cg of the driven IGBT increases.
-1
-2
-3
-4
0
0.2
IOH – OUTPUT HIGH CURRENT – A
Figure 1. VOH vs. temperature.
Figure 2. VOH vs. IOH.
0.4
0.43
0.42
0.41
0.40
0.39
-50
-25
0
25
50
75
TA – TEMPERATURE – C
Figure 3. VOL vs. temperature.
100
125
3
2
1
0
0.1
0.2
0.3
1.2
1.2
1.0
1.0
0.8
0.6
0.4
ICCL
ICCH
0.2
0
-50
0.4
IOL – OUTPUT LOW CURRENT – A
75
100
2.5
2.0
-25
0
25
50
75
100
300
TP – PROPAGATION DELAY – ns
300
200
TPLH
TPHL
25
50
75
100
125
200
100
TPLH
TPHL
15
20
25
TA – TEMPERATURE – C
Figure 10. Propagation delay vs. tempera-
25
30
200
100
0
30
6
9
12
15
18
IF – FORWARD LED CURRENT – mA
Figure 9. Propagation delay vs. IF.
400
350
TPLH
TPHL
300
250
200
20
300
VCC – SUPPLY VOLTAGE – V
400
15
Figure 6. ICC vs. VCC.
400
0
ICCL
ICCH
0.2
400
0
10
125
500
-25
0.4
VCC – SUPPLY VOLTAGE – V
Figure 8. Propagation delay vs. VCC.
100
0.6
0
10
125
TP – PROPAGATION DELAY – ns
TP – PROPAGATION DELAY – ns
IFLH – LOW TO HIGH CURRENT THRESHOLD – mA
3.0
Figure 7. IFLH vs. temperature.
TP – PROPAGATION DELAY – ns
50
400
TA – TEMPERATURE – C
25
Figure 5. ICC vs. temperature.
3.5
0
-50
0
0.8
TA – TEMPERATURE – C
Figure 4. VOL vs. IOL.
1.5
-50
-25
TP – PROPAGATION DELAY – ns
0
1.4
ICC – SUPPLY CURRENT – mA
4
ICC – SUPPLY CURRENT – mA
VOL – OUTPUT LOW VOLTAGE DROP – V
5
0
50
100
150
Rg – SERIES LOAD RESISTANCE – Ω
Figure 11. Propagation delay vs. Rg.
200
300
200
100
TPLH
TPHL
0
0
20
40
60
80
Cg – LOAD CAPACITANCE – nF
Figure 12. Propagation delay vs. Cg.
100
25
35
IF – FORWARD CURRENT – mA
VO – OUTPUT VOLTAGE – V
30
25
20
15
10
5
0
-5
0
1
2
3
4
5
20
15
10
5
0
1.2
6
IF – FORWARD LED CURRENT – mA
1
50% DUTY
CYCLE
1.8
8
0.1 µF
IF = 7 to 16 mA
500 Ω
1.6
Figure 14. Input current vs. forward voltage.
Figure 13. Transfer characteristics.
+
10 KHz –
1.4
VF – FORWARD VOLTAGE – V
2
IF
V
= 15
+ CC
– to 30 V
7
tr
tf
VO
3
6
90%
75 Ω
50%
VOUT
1.5 nF
4
10%
5
tPLH
tPHL
Figure 15. Propagation delay test circuits and waveforms.
VCM
IF
1
5V
δt
0.1 µF
A
B
δV
8
2
VO
3
6
4
5
+
–
VCC = 30 V
VO
–
Figure 16. CMR test circuits and waveforms.
10
VOH
SWITCH AT A: IF = 10 mA
SWITCH AT B: IF = 0 mA
+
∆t
∆t
VO
VCM = 1000 V
VCM
0V
7
+
–
=
VOL
Applications Information Eliminating Negative IGBT
Gate Drive
To keep the IGBT firmly off, the HCPL-3020 and HCPL0302 have a very low maximum VOL specification of
1.0 V. Minimizing Rg and the lead inductance from the
HCPL-3020 or HCPL-0302 to the IGBT gate and emitter
(possibly by mounting the HCPL-3020 or HCPL-0302 on a
small PC board directly above the IGBT) can eliminate the
need for negative IGBT gate drive in many applications as
shown in Figure 17. Care should be taken with such a PC
board design to avoid routing the IGBT collector or emitter traces close to the HCPL-3020 or HCPL-0302 input as
this can result in unwanted coupling of transient signals
into the input of HCPL-3020 or HCPL-0302 and degrade
performance. (If the IGBT drain must be routed near the
HCPL-3020 or HCPL-0302 input, then the LED should be
reverse biased when in the off state, to prevent the transient
signals coupled from the IGBT drain from turning on the
HCPL-3020 or HCPL-0302.
HCPL-3020/0302
+5 V
1
270 Ω
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
8
0.1 µF
2
7
3
6
4
5
+
–
VCC = 15 V
Rg
Figure 17. Recommended LED drive and application circuit for HCPL-3020 and HCPL-0302.
11
+ HVDC
Q1
3-PHASE
AC
Q2
- HVDC
Selecting the Gate Resistor (Rg) for HCPL-3020
Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure 17 can be analyzed as a
simple RC circuit with a voltage supplied by the HCPL-3020.
Rg
≤
VCC – VOL
IOLPEAK
=
24 - 1
0.4
=
57.5 Ω
The VOL value of 1 V in the previous equation is the VOL at the peak current of 0.4 A. (See Figure 4).
Step 2: Check the HCPL-3020 power dissipation and increase Rg if necessary. The HCPL-3020 total power dissipation
(PT ) is equal to the sum of the emitter power (PE) and the output power (PO).
PT = PE + PO
PE = IF • VF • Duty Cycle
PO = PO(BIAS) + PO(SWITCHING) = ICC • VCC + ESW (Rg;Qg) • f
= (ICCBIAS + KICC • Qg • f ) • VCC + ESW (Rg;Qg) • f
where KICC • Qg • f is the increase in ICC due to switching and KICC is a constant of 0.001 mA/(nC*kHz). For the circuit
in Figure 17 with IF (worst case) = 10 mA, Rg = 57.5 Ω, Max Duty Cycle = 80%, Qg = 100 nC, f = 20 kHz and TAMAX =
85°C:
PE = 10 mA • 1.8 V • 0.8 = 14 mW
PO = [3 mA + (0.001 mA/nC • kHz) • 20 kHz • 100 nC] • 24 V + 0.3mJ • 20 kHz
= 126 mW < 250 mW (PO(MAX)) @ 85°C
The value of 3 mA for ICC in the previous equation is the max. ICC over entire operating temperature range.
Since PO for this case is less than PO(MAX), Rg = 57.5 Ω is alright for the power dissipation.
Esw – ENERGY PER SWITCHING CYCLE – µJ
4.0
Qg = 50 nC
Qg = 100 nC
Qg = 200 nC
3.5
3.0
Qg = 400 nC
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
80
100
Rg – GATE RESISTANCE – Ω
Figure 18. Energy dissipated in the HCPL-3020 and HCPL-0302
and for each IGBT switching cycle.
12
LED Drive Circuit Considerations for Ultra High CMR
Performance
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side
of the optocoupler, through the package, to the detector
IC as shown in Figure 19. The HCPL-3020 and HCPL-0302
improve CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 20. This capacitive coupling causes
1
CLEDP
2
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or off ) during common mode transients. For example, the recommended application circuit
(Figure 17), can achieve 10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are discussed in the next two sections.
8
1
7
2
CLEDO1
8
CLEDP
7
CLEDO2
3
CLEDN
4
6
3
5
4
Figure 19. Optocoupler input to output capacitance model for
unshielded optocouplers.
+5 V
1
2
+
VSAT
–
1
0.1
µF
7
6
CLEDN
4
+
–
SHIELD
VCC = 18 V
Rg
5
2
•••
Q1
8
+5 V
3
4
CLEDN
SHIELD
CLEDN
7
6
SHIELD
5
Figure 22. Not recommended open collector drive circuit.
Figure 21. Equivalent circuit for figure 15 during common mode
transient.
CLEDP
CLEDP
ILEDN
4
+ –
2
3
•••
VCM
1
8
+5 V
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
7
6
5
Figure 23. Recommended LED drive circuit for ultra-high CMR IPM
dead time and propagation delay specifications.
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Figure 20. Optocoupler Input to output capacitance model for
shielded optocouplers.
ILEDP
3
5
SHIELD
8
CLEDP
6
CLEDN
CMR with the LED On (CMRH)
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving
the LED current beyond the input threshold so that it is not
pulled below the threshold during a transient. A minimum
LED current of 7 mA provides adequate margin over the
maximum IFLH of 6 mA to achieve 10 kV/µs CMR.
CMR with the LED Off (CMRL)
A high CMR LED drive circuit must keep the LED off (VF ­
VF(OFF)) during common mode transients. For example,
during a -dVCM/dt transient in Figure 21, the current flowing through CLEDP also flows through the RSAT and VSAT of
the logic gate. As long as the low state voltage developed
across the logic gate is less than VF(OFF) the LED will remain
off and no common mode failure will occur.
The open collector drive circuit, shown in Figure 22, cannot
keep the LED off during a +dVCM/dt transient, since all the
current flowing through CLEDN must be supplied by the
LED, and it is not recommended for applications requiring
ultra high CMR1 performance. The alternative drive circuit,
which likes the recommended application circuit (Figure
17), does achieve ultra high CMR performance by shunting
the LED in the off state.
Dead Time and Propagation Delay Specifications
The HCPL-3020 and HCPL-0302 include a Propagation
Delay Difference (PDD) specification intended to help
designers minimize “dead time” in their power inverter
designs. Dead time is the time high and low side power
transistors are off. Any overlap in Ql and Q2 conduction
will result in large currents flowing through the power
devices from the high voltage to the low-voltage motor
rails. To minimize dead time in a given design, the turn
on of LED2 should be delayed (relative to the turn off of
LED1) so that under worst-case conditions, transistor Q1
has just turned off when transistor Q2 turns on, as shown
in Figure 24. The amount of delay necessary to achieve
this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is
specified to be 500 ns over the operating temperature
range of –40° to 100°C.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propaga­tion delay difference specification as shown in
Figure 25. The maximum dead time for the HCPL-3020 and
HCPL-0302 is 1 ms (= 0.5 µs – (–0.5 µs)) over the operating
temperature range of –40°C to 100°C.
Note that the propagation delays used to calculate PDD and dead time are
taken at equal temperatures and test conditions since the optocouplers
under consideration are typically mounted in close proximity to each
other and are switching identical IGBTs.
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ILED1
ILED1
VOUT1
VOUT1
Q1 ON
Q1 ON
Q1 OFF
Q1 OFF
Q2 ON
VOUT2
Q2 OFF
Q2 ON
VOUT2
Q2 OFF
ILED2
ILED2
tPHL MIN
tPHL MAX
tPHL MAX
tPLH
tPLH MIN
MIN
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
tPLH MAX
(tPHL-tPLH) MAX
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX)
= PDD* MAX – PDD* MIN
Figure 24. Minimum LED skew for zero dead time.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 25. Waveforms for dead time.
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5989-2947EN
AV01-0367EN - August 2, 2006
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