Preliminary GS8662D08/09/18/36E-333/300/250/200/167 72Mb SigmaQuad-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array SigmaQuad™ Family Overview The GS8662D08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662D08/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS8662D08/09/18/36E SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O SigmaQuad-II B4 RAMs always transfer data in four packets, A0 and A1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. Because the LSBs are tied off internally, the address field of a SigmaQuad-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index). Parameter Synopsis Rev: 1.01a 2/2006 - 333 -300 -250 -200 -167 tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.50 ns 1/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 2M x 36 SigmaQuad-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ MCL/SA (288Mb) SA W BW2 K BW1 R SA MCL/SA (144Mb) CQ B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35 2. MCL = Must Connect Low Rev: 1.01a 2/2006 2/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 4M x 18 SigmaQuad-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ MCL/SA (144Mb) SA W BW1 K NC R SA SA CQ B NC Q9 D9 SA NC K BW0 SA NC NC Q8 C NC NC D10 VSS SA NC SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. MCL = Must Connect Low Rev: 1.01a 2/2006 3/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 8M x 9 SigmaQuad-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA W NC K NC R SA SA CQ B NC NC NC SA NC K BW0 SA NC NC Q4 C NC NC NC VSS SA NC SA VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1 M NC NC NC VSS VSS VSS VSS VSS NC NC D1 N NC D8 NC VSS SA SA SA VSS NC NC NC P NC NC Q8 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. 2. MCL = Must Connect Low Rev: 1.01a 2/2006 4/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 8M x 8 SigmaQuad-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA W NW1 K NC R SA SA CQ B NC NC NC SA NC K NW0 SA NC NC Q3 C NC NC NC VSS SA NC SA VSS NC NC D3 D NC D4 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS SA SA SA VSS NC NC NC P NC NC Q7 SA SA C SA SA NC NC NC R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. MCL = Must Connect Low Rev: 1.01a 2/2006 5/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Pin Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — NC No Connect — — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3 Synchronous Byte Writes Input Active Low x9/x18/x36 only NW0–NW1 Nybble Write Control Pin Input Active Low x8 only K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — Qn Synchronous Data Outputs Output Dn Synchronous Data Inputs Input Doff Disable DLL when low Input Active Low CQ Output Echo Clock Output — CQ Output Echo Clock Output — VDD Power Supply Supply 1.8 V Nominal VDDQ Isolated Output Buffer Supply Supply 1.5 or 1.8 V Nominal VSS Power Supply: Ground Supply — Note: NC = Not Connected to die or any other pin Rev: 1.01a 2/2006 6/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Background Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half. Alternating Read-Write Operations SigmaQuad-II SRAMs follow a few simple rules of operation. - Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port. - Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM. - All address, data, and control inputs are sampled on clock edges. In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details. SigmaQuad-II B4 SRAM DDR Read The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C, and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle. SigmaQuad-II B4 Double Data Rate SRAM Read First Read A NOP Read B Write C Read D Write E NOP K K Address A B C D E R W BWx C C+1 C+2 C+3 E E+1 D C C+1 C+2 C+3 E E+1 C C Q A A+1 A+2 A+3 B B+1 B+2 B+3 D D+1 D+2 CQ CQ Rev: 1.01a 2/2006 7/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 SigmaQuad-II B4 SRAM DDR Write The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K. and by the rising edge of the K that follows. SigmaQuad-II B4 Double Data Rate SRAM Write First Write A NOP Read B Write C Read D Write E NOP K K Address A B C D E R W BWx A A+1 A+2 A+3 C C+1 C+2 C+3 E E+1 E+ D A A+1 A+2 A+3 C C+1 C+2 C+3 E E+1 E+ C C B Q B+1 B+2 B+3 D D+1 D+2 CQ CQ Rev: 1.01a 2/2006 8/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Power-Up Sequence for SigmaQuad-II SRAMs SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations. Power-Up Sequence 1. Power-up and maintain Doff at low state. 1a. 1b. 1c. Apply VDD. Apply VDDQ. Apply VREF (may also be applied at the same time as VDDQ). 2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high. 3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled. Note: If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized. DLL Constraints • The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar on page 21). • The DLL cannot operate at a frequency lower than 119 MHz. • If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage. Power-Up Sequence (Doff controlled) Power UP Interval Unstable Clocking Interval DLL Locking Interval (1024 Cycles) Normal Operation K K VDD VDDQ VREF Doff Power-Up Sequence (Doff tied High) Power UP Interval Unstable Clocking Interval Stop Clock Interval 30ns Min DLL Locking Interval (1024 Cycles) Normal Operation K K VDD VDDQ VREF Doff Note: If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock. Rev: 1.01a 2/2006 9/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Special Functions Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above. Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time BW0 BW1 D0–D8 D9–D17 Beat 1 0 1 Data In Don’t Care Beat 2 1 0 Don’t Care Data In Beat 3 0 0 Data In Data In Beat 4 1 0 Don’t Care Data In Resulting Write Operation Byte 1 D0–D8 Byte 2 D9–D17 Byte 1 D0–D8 Byte 2 D9–D17 Byte 1 D0–D8 Byte 2 D9–D17 Byte 1 D0–D8 Byte 2 D9–D17 Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1 Beat 2 Beat 3 Beat 4 Output Register Control SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM. Rev: 1.01a 2/2006 10/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Example Four Bank Depth Expansion Schematic R3 W3 R2 W2 R1 W1 R0 W0 A0–An K D1–Dn Bank 0 Bank 1 Bank 2 Bank 3 A A A A W W W W R R R R K D CQ Q C K D CQ Q C K D CQ K CQ Q D Q C C C Q1–Qn CQ0 CQ1 CQ2 CQ3 Note: For simplicity BWn, NWn, K, and C are not shown. Rev: 1.01a 2/2006 11/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Rev: 1.01a 2/2006 A A+1 B+1 B D(2) Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 12/29 CQ[2] CQ[2] Q(2) C[2] C[2] CQ[1] CQ(1) Q(1) C[1] C[1] B+1 B BWx(2) A+2 A+3 B+3 B+2 B+3 C C+1 D+1 E D B+2 D Read E D(1) C Write D D+1 B Read C D A Write B BWx(1) W(2) W(1) R(2) R(1) Address K K Read A Σ2x2B4 SigmaQuad-II SRAM Depth Expansion C+2 D+2 D+2 F Write F C+3 D+3 D+3 E F F NOP E+1 F+1 F+1 E+2 F F Preliminary GS8662D08/09/18/36E-333/300/250/200/167 © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z. Separate I/O SigmaQuad-II B4 SRAM Truth Table Previous Operation A R W Current Operation D D D D Q Q Q Q K↑ (tn-1) K ↑ (tn) K ↑ (tn) K ↑ (tn) K↑ (tn) K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) Deselect X 1 1 Deselect X X — — Hi-Z Hi-Z — — Write X 1 X Deselect D2 D3 — — Hi-Z Hi-Z — — Read X X 1 Deselect X X — — Q2 Q3 — — Deselect V 1 0 Write D0 D1 D2 D3 Hi-Z Hi-Z — — Deselect V 0 X Read X X — — Q0 Q1 Q2 Q3 Read V X 0 Write D0 D1 D2 D3 Q2 Q3 — — Write V 0 X Read D2 D3 — — Q0 Q1 Q2 Q3 Notes: 1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care” 2. “—” indicates that the input requirement or output state is determined by the next operation. 3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations. 4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command. 6. Users should not clock in metastable addresses. Rev: 1.01a 2/2006 13/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Byte Write Clock Truth Table BW BW BW BW Current Operation D D D D K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) K↑ (tn) K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) T T T T Write Dx stored if BWn = 0 in all four data transfers D0 D2 D3 D4 T F F F Write Dx stored if BWn = 0 in 1st data transfer only D0 X X X F T F F Write Dx stored if BWn = 0 in 2nd data transfer only X D1 X X F F T F Write Dx stored if BWn = 0 in 3rd data transfer only X X D2 X F F F T Write Dx stored if BWn = 0 in 4th data transfer only X X X D3 F F F F Write Abort No Dx stored in any of the four data transfers X X X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”. Rev: 1.01a 2/2006 14/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 x36 Byte Write Enable (BWn) Truth Table BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35 1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care 0 1 1 1 Data In Don’t Care Don’t Care Don’t Care 1 0 1 1 Don’t Care Data In Don’t Care Don’t Care 0 0 1 1 Data In Data In Don’t Care Don’t Care 1 1 0 1 Don’t Care Don’t Care Data In Don’t Care 0 1 0 1 Data In Don’t Care Data In Don’t Care 1 0 0 1 Don’t Care Data In Data In Don’t Care 0 0 0 1 Data In Data In Data In Don’t Care 1 1 1 0 Don’t Care Don’t Care Don’t Care Data In 0 1 1 0 Data In Don’t Care Don’t Care Data In 1 0 1 0 Don’t Care Data In Don’t Care Data In 0 0 1 0 Data In Data In Don’t Care Data In 1 1 0 0 Don’t Care Don’t Care Data In Data In 0 1 0 0 Data In Don’t Care Data In Data In 1 0 0 0 Don’t Care Data In Data In Data In 0 0 0 0 Data In Data In Data In Data In x18 Byte Write Enable (BWn) Truth Table BW0 BW1 D0–D8 D9–D17 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In x09 Byte Write Enable (BWn) Truth Table BW0 D0–D8 1 Don’t Care 0 Data In 1 Don’t Care 0 Data In Rev: 1.01a 2/2006 15/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Nybble Write Clock Truth Table NW NW NW NW Current Operation D D D D K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) K↑ (tn) K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) T T T T Write Dx stored if NWn = 0 in all four data transfers D0 D2 D3 D4 T F F F Write Dx stored if NWn = 0 in 1st data transfer only D0 X X X F T F F Write Dx stored if NWn = 0 in 2nd data transfer only X D1 X X F F T F Write Dx stored if NWn = 0 in 3rd data transfer only X X D2 X F F F T Write Dx stored if NWn = 0 in 4th data transfer only X X X D3 F F F F Write Abort No Dx stored in any of the four data transfers X X X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more NWn = 0, then NW = “T”, else NW = “F”. x8 Nybble Write Enable (NWn) Truth Table NW0 NW1 D0–D3 D4–D7 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In Rev: 1.01a 2/2006 16/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 State Diagram Power-Up Read NOP READ WRITE READ READ D Count = 2 WRITE Load New Write Address D Count = 0 Load New Read Address D Count = 0 Always WRITE D Count = 2 READ D Count = 2 WRITE D Count = 2 Always DDR Write D Count = D Count + 1 DDR Read D Count = D Count + 1 READ D Count = 1 Write NOP Always Always Increment Read Address WRITE D Count = 1 Increment Write Address Notes: 1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1. 2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is true for “WRITE” and “WRITE”. 3. Read and write state machine can be active simultaneously. 4. State machine control timing sequence is controlled by K. Rev: 1.01a 2/2006 17/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 2.9 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VREF Voltage in VREF Pins –0.5 to VDDQ V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V VIN Voltage on Other Input Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V IIN Input Current on Any Pin +/–100 mA dc IOUT Output Current on Any I/O Pin +/–100 mA dc TJ Maximum Junction Temperature 125 o C TSTG Storage Temperature –55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 1.7 1.8 1.9 V I/O Supply Voltage VDDQ 1.4 1.5 VDD V Reference Voltage VREF 0.68 — 0.95 V Notes: 1. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. 2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Operating Temperature Parameter Symbol Min. Typ. Max. Unit Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C Rev: 1.01a 2/2006 18/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 HSTL I/O DC Input Characteristics Parameter Symbol Min Max Units Notes DC Input Logic High VIH (dc) VREF + 0.1 VDD + 0.3 V 1 DC Input Logic Low VIL (dc) –0.3 VREF – 0.1 V 1 Notes: 1. Compatible with both 1.8 V and 1.5 V I/O drivers 2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 3. VIL (Min)DC = –0.3 V, VIL(Min)AC = –1.5 V (pulse width ≤ 3 ns). 4. VIH (Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 0.85 V (pulse width ≤ 3 ns). HSTL I/O AC Input Characteristics Parameter Symbol Min Max Units Notes AC Input Logic High VIH (ac) VREF + 200 — mV 3,4 AC Input Logic Low VIL (ac) — VREF – 200 mV 3,4 VREF (ac) — 5% VREF (DC) mV 1 VREF Peak to Peak AC Voltage Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKHKH VDD + 1.0 V VSS 50% 50% VDD VSS – 1.0 V 20% tKHKH Rev: 1.01a 2/2006 VIL 19/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 1.8 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Output Capacitance COUT VOUT = 0 V 6 7 pF Clock Capacitance CCLK VIN = 0 V 5 6 pF Notes Note: This parameter is sample tested. AC Test Conditions Parameter Conditions Input high level 1.25 V Input low level 0.25 V Max. input slew rate 2 V/ns Input reference level 0.75 V Output reference level VDDQ/2 Note: Test conditions as specified with output loading as shown unless otherwise noted. AC Test Load Diagram DQ RQ = 250 Ω (HSTL I/O) VREF = 0.75 V 50Ω VT = VDDQ/2 Input and Output Leakage Characteristics Parameter Symbol Test Conditions Min. Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA Doff IINDOFF VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –2 uA –2 uA 2 uA 2 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDDQ –2 uA 2 uA Rev: 1.01a 2/2006 20/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Symbol Min. Max. Units Notes Output High Voltage VOH1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 1, 3 Output Low Voltage VOL1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 2, 3 Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5 Output Low Voltage VOL2 Vss 0.2 V 4, 6 Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = –1.0 mA 6. IOL = 1.0 mA Operating Currents -333 Parameter Symbol Test Conditions Operating Current (x36): DDR IDD Operating Current (x18): DDR -300 -250 -200 -167 Notes 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 Operating Current (x9): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 Operating Current (x8): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 Standby Current (NOP): DDR ISB1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4 Device deselected, IOUT = 0 mA, f = Max, All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V Notes: 1. 2. 3. 4. Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed. Rev: 1.01a 2/2006 21/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 AC Electrical Characteristics Parameter Symbol -333 -300 -250 -200 -167 Min Max Min Max Min Max Min Max Min Max Units Notes Clock K, K Clock Cycle Time C, C Clock Cycle Time tKHKH tCHCH 3.0 3.5 3.3 4.2 4.0 6.3 5.0 7.88 6.0 8.4 ns tKC Variable tKCVar — 0.2 — 0.2 — 0.2 — 0.2 — 0.2 ns K, K Clock High Pulse Width C, C Clock High Pulse Width tKHKL tCHCL 1.2 — 1.32 — 1.6 — 2.0 — 2.4 — ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width tKLKH tCLCH 1.2 — 1.32 — 1.6 — 2.0 — 2.4 — ns K to K High C to C High tKHKH 1.35 — 1.49 — 1.8 — 2.2 — 2.7 — ns K, K Clock High to C, C Clock High tKHCH 0 1.30 0 1.45 0 1.8 0 2.3 0 2.8 ns DLL Lock Time tKCLock 1024 — 1024 — 1024 — 1024 — 1024 — cycle K Static to DLL reset tKCReset 30 — 30 — 30 — 30 — 30 — ns K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid tKHQV tCHQV — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns 3 K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold tKHQX tCHQX –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns 3 K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid tKHCQV tCHCQV — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold tKHCQX tCHCQX –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns CQ, CQ High Output Valid tCQHQV — 0.25 — 0.27 — 0.30 — 0.35 — 0.40 ns 7 CQ, CQ High Output Hold tCQHQX –0.25 — –0.27 — –0.30 — –0.35 — –0.40 — ns 7 K Clock High to Data Output High-Z C Clock High to Data Output High-Z tKHQZ tCHQZ — 0.45 — 0.45 — 0.45 — 0.45 — 0.5 ns 3 K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z tKHQX1 tCHQX1 –0.45 — –0.45 — –0.45 — –0.45 — –0.5 — ns 3 Address Input Setup Time tAVKH 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns Control Input Setup Time tIVKH 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns Data Input Setup Time tDVKH 0.28 — 0.3 — 0.35 — 0.4 — 0.5 — ns 5 6 Output Times Setup Times Rev: 1.01a 2/2006 22/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 2 © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 AC Electrical Characteristics (Continued) Parameter Symbol -333 -300 -250 -200 -167 Min Max Min Max Min Max Min Max Min Max Units Notes Hold Times Address Input Hold Time tKHAX 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns Control Input Hold Time tKHIX 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns Data Input Hold Time tKHDX 0.28 — 0.3 — 0.35 — 0.4 — 0.5 — ns Notes: 1. 2. 3. 4. 5. 6. 7. All Address inputs must meet the specified setup and hold times for all latching clock edges. Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36). If C, C are tied high, K, K become the references for C, C timing parameters To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations. Rev: 1.01a 2/2006 23/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Rev: 1.01a 2/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 24/29 CQ CQ Q KHCQV KHCQV A KHQX1 B KHCQX B KLKH D KHCQX IVKH KHIX AVKH KHKL B A KHKH Write B BWx W R Address K K Read A KHIX CQHQX A+1 KHQV DVKH IVKH IVKH NOP B+1 B+1 C CQHQV A+2 B+2 KHDX A+3 KHQX Write C B+2 KHIX KHKHbar K and K Controlled Read-Write-Read Timing Diagram B+3 B+3 KHQZ C C D Read D C+1 C+1 C+2 C+2 E Write E C+3 C+3 D E E D+1 NOP E+1 E+1 D+2 Preliminary GS8662D08/09/18/36E-333/300/250/200/167 © 2005, GSI Technology Rev: 1.01a 2/2006 CHCQX B CHQV KHKHbar C A+3 KHIX IVKH Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 25/29 CQ CQ Q C C CHCQX CHCQX CQHQX CQHQV A+2 A A+1 CHQX CHQX1 B C KLKH Write C D KHIX IVKH KHAX KHKL Read B C CHCQV A AVKH KHKH NOP BWx W R Address K K Read A C and C Controlled Read-Write-Read Timing Diagram C+1 B+1 C+1 KHDX IVKH NOP B+2 C+2 C+2 D B+3 DVKH KHIX Write D C+3 C+3 CHQZ D D NOP D+1 D+1 D D Preliminary GS8662D08/09/18/36E-333/300/250/200/167 © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 14.0 17±0.05 1.0 A B C D E F G H J K L M N P R A 1.0 1.0 10.0 0.20 C B Rev: 1.01a 2/2006 SEATING PLANE 0.20(4x) 0.36~0.46 1.50 MAX. C 15±0.05 26/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Ordering Information—GSI SigmaQuad-II SRAM Org Part Number1 Type Package Speed (MHz) TA3 8M x 8 GS8662D08E-333 SigmaQuad-II SRAM 165-bump BGA 333 C 8M x 8 GS8662D08E-300 SigmaQuad-II SRAM 165-bump BGA 300 C 8M x 8 GS8662D08E-250 SigmaQuad-II SRAM 165-bump BGA 250 C 8M x 8 GS8662D08E-200 SigmaQuad-II SRAM 165-bump BGA 200 C 8M x 8 GS8662D08E-167 SigmaQuad-II SRAM 165-bump BGA 167 C 8M x 8 GS8662D08E-333I SigmaQuad-II SRAM 165-bump BGA 333 I 8M x 8 GS8662D08E-300I SigmaQuad-II SRAM 165-bump BGA 300 I 8M x 8 GS8662D08E-250I SigmaQuad-II SRAM 165-bump BGA 250 I 8M x 8 GS8662D08E-200I SigmaQuad-II SRAM 165-bump BGA 200 I 8M x 8 GS8662D08E-167I SigmaQuad-II SRAM 165-bump BGA 167 I 8M x 9 GS8662D09E-333 SigmaQuad-II SRAM 165-bump BGA 333 C 8M x 9 GS8662D09E-300 SigmaQuad-II SRAM 165-bump BGA 300 C 8M x 9 GS8662D09E-250 SigmaQuad-II SRAM 165-bump BGA 250 C 8M x 9 GS8662D09E-200 SigmaQuad-II SRAM 165-bump BGA 200 C 8M x 9 GS8662D09E-167 SigmaQuad-II SRAM 165-bump BGA 167 C 8M x 9 GS8662D09E-333I SigmaQuad-II SRAM 165-bump BGA 333 I 8M x 9 GS8662D09E-300I SigmaQuad-II SRAM 165-bump BGA 300 I 8M x 9 GS8662D09E-250I SigmaQuad-II SRAM 165-bump BGA 250 I 8M x 9 GS8662D09E-200I SigmaQuad-II SRAM 165-bump BGA 200 I 8M x 9 GS8662D09E-167I SigmaQuad-II SRAM 165-bump BGA 167 I 4M x 18 GS8662D18E-333 SigmaQuad-II SRAM 165-bump BGA 333 C 4M x 18 GS8662D18E-300 SigmaQuad-II SRAM 165-bump BGA 300 C 4M x 18 GS8662D18E-250 SigmaQuad-II SRAM 165-bump BGA 250 C 4M x 18 GS8662D18E-200 SigmaQuad-II SRAM 165-bump BGA 200 C 4M x 18 GS8662D18E-167 SigmaQuad-II SRAM 165-bump BGA 167 C 4M x 18 GS8662D18E-333I SigmaQuad-II SRAM 165-bump BGA 333 I 4M x 18 GS8662D18E-300I SigmaQuad-II SRAM 165-bump BGA 300 I 4M x 18 GS8662D18E-250I SigmaQuad-II SRAM 165-bump BGA 250 I 4M x 18 GS8662D18E-200I SigmaQuad-II SRAM 165-bump BGA 200 I 4M x 18 GS8662D18E-167I SigmaQuad-II SRAM 165-bump BGA 167 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.01a 2/2006 27/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Ordering Information—GSI SigmaQuad-II SRAM Org Part Number1 Type Package Speed (MHz) TA3 2M x 36 GS8662D36E-333 SigmaQuad-II SRAM 165-bump BGA 333 C 2M x 36 GS8662D36E-300 SigmaQuad-II SRAM 165-bump BGA 300 C 2M x 36 GS8662D36E-250 SigmaQuad-II SRAM 165-bump BGA 250 C 2M x 36 GS8662D36E-200 SigmaQuad-II SRAM 165-bump BGA 200 C 2M x 36 GS8662D36E-167 SigmaQuad-II SRAM 165-bump BGA 167 C 2M x 36 GS8662D36E-333I SigmaQuad-II SRAM 165-bump BGA 333 I 2M x 36 GS8662D36E-300I SigmaQuad-II SRAM 165-bump BGA 300 I 2M x 36 GS8662D36E-250I SigmaQuad-II SRAM 165-bump BGA 250 I 2M x 36 GS8662D36E-200I SigmaQuad-II SRAM 165-bump BGA 200 I 2M x 36 GS8662D36E-167I SigmaQuad-II SRAM 165-bump BGA 167 I 8M x 8 GS8662D08E-333 SigmaQuad-II SRAM 165-bump BGA 333 C 8M x 8 GS8662D08GE-300 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 C 8M x 8 GS8662D08GE-250 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 C 8M x 8 GS8662D08GE-200 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 200 C 8M x 8 GS8662D08GE-167 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 167 C 8M x 8 GS8662D08GE-333I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 I 8M x 8 GS8662D08GE-300I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 I 8M x 8 GS8662D08GE-250I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 I 8M x 8 GS8662D08GE-200I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 200 I 8M x 8 GS8662D08GE-167I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 167 I 8M x 9 GS8662D09GE-333 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 C 8M x 9 GS8662D09GE-300 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 C 8M x 9 GS8662D09GE-250 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 C 8M x 9 GS8662D09GE-200 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 200 C 8M x 9 GS8662D09GE-167 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 167 C 8M x 9 GS8662D09GE-333I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 I 8M x 9 GS8662D09GE-300I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 I 8M x 9 GS8662D09GE-250I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 I 8M x 9 GS8662D09GE-200I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 200 I 8M x 9 GS8662D09GE-167I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 167 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.01a 2/2006 28/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Ordering Information—GSI SigmaQuad-II SRAM Org Part Number1 Type Package Speed (MHz) TA3 4M x 18 GS8662D18GE-333 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 C 4M x 18 GS8662D18GE-300 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 C 4M x 18 GS8662D18GE-250 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 C 4M x 18 GS8662D18GE-200 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 200 C 4M x 18 GS8662D18GE-167 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 167 C 4M x 18 GS8662D18GE-333I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 I 4M x 18 GS8662D18GE-300I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 I 4M x 18 GS8662D18GE-250I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 I 4M x 18 GS8662D18GE-200I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 200 I 4M x 18 GS8662D18GE-167I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 167 I 2M x 36 GS8662D36GE-333 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 C 2M x 36 GS8662D36GE-300 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 C 2M x 36 GS8662D36GE-250 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 C 2M x 36 GS8662D36GE-200 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 200 C 2M x 36 GS8662D36GE-167 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 167 C 2M x 36 GS8662D36GE-333I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 I 2M x 36 GS8662D36GE-300I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 I 2M x 36 GS8662D36GE-250I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 I 2M x 36 GS8662D36GE-200I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 200 I 2M x 36 GS8662D36GE-167I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 167 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.01a 2/2006 29/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology