PHILIPS MB2821BB Dual 10-bit d-type flip-flop; positive-edge trigger 3-state Datasheet

Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
FEATURES
DESCRIPTION
•
The MB2821 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
•
•
•
•
•
•
•
20-bit positive-edge triggered register
Multiple VCC and GND pins minimize
switching noise
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
ESD protection exceeds 2000V per MIL
STD 883 Method 3015 and 200V per
Machine Model
the Low-to-High clock transition, is
transferred to the corresponding flip-flop’s Q
output.
The 3-State output buffers are designed to
drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors.
The MB2821 has two 10-bit, edge triggered
registers, with each register coupled to ten
3-State output buffers. The two sections of
each register are controlled independently by
the clock (nCP) and Output Enable (nOE)
control gates.
The active Low Output Enable (nOE) controls
all ten 3-State buffers independent of the
register operation. When nOE is Low, the
data in the register appears at the outputs.
When nOE is High, the outputs are in high
impedance “off” state, which means they will
neither drive nor load the bus.
Each register is fully edge triggered. The
state of each D input, one set-up time before
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
nCP to nQx
CL = 50pF; VCC = 5V
4.6
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
COUT
Output capacitance
VO = 0V or VCC; 3-State
7
pF
ICCZ
Total supply current
Outputs disabled; VCC = 5.5V
120
µA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
52-pin plastic Quad Flat Pack
-40°C to +85°C
MB2821BB
1418B
52 51
50 49 48 47
46 45 44 43 42
Vcc
1D3
1D2
GND
1D1
1D0
1CP
LOGIC SYMBOL
1OE
1Q0
1Q1
1Q2
1Q3
Vcc
PIN CONFIGURATION
45
41 40
1Q4
È
È
È
1
39 1D4
1Q5
2
38 1D5
1Q6
3
37 1D6
È
È
È
2Q0
8
32 2D1
2Q1
9
31 2D2
GND
4
36 1D7
1Q7
5
35 1D8
188
6
1Q9
7
MB2821
52–pin PQFP
46
1CP
47
1OE
33 2D0
3
5
6
7
33
32
31
29
28
27
25
24
23
22
2D0 2D1 2D2 2D3 2D4 2D5 2D6
2OE
2Q5 13
27 2D5
2D7 2D8
2D9
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
26
8
Vcc
2D6
2D7
2D8
2D9
21 22 23 24 25
2CP
2OE
1D9
2
2CP
2Q9
1D7 1D8
34
1
20
2Q8
35
51
21
GND
36
50
28 2D4
2Q7
37
49
29 2D3
Vcc
38
48
2Q4 12
2Q6
39
34 1D9
2Q3 11
August 24, 1993
41
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
30 GND
17 18 19 20
42
1D0 1D1 1D2 1D3 1D4 1D5 1D6
2Q2 10
14 15 16
44
1
9
10
11
12
13
15
16
18
19
853-1670 10620
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
45, 44, 42, 41, 39, 38, 37, 36, 35, 34,
33, 32, 31, 29, 28, 27, 25, 24, 23, 22
1D0 – 1D9
2D0 – 2D9
Data inputs
48, 49, 50, 51, 1, 2, 3, 5, 6, 7, 8, 9,
10, 11, 12, 13, 15, 16, 18, 19
1Q0 – 1Q9
2Q0 – 2Q9
Data outputs
47, 20
1OE, 2OE
Output enable inputs (active-Low)
Clock pulse inputs (active rising edge)
46, 21
1CP, 2CP
4, 17, 30, 43
GND
Ground (0V)
14, 26, 40, 52
VCC
Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
47
46
20
EN
21
C2
EN
C2
48
33
44
49
32
9
42
50
31
10
41
51
29
11
39
1
28
12
38
2
27
13
37
3
25
15
36
5
24
16
35
6
23
18
34
7
22
19
45
2D
1
2D
8
1
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
nOE
nCP
nDx
REGISTER
nQ0 – nQ9
L
L
↑
↑
l
h
L
H
L
H
L
↑
X
NC
NC
H =
h =
L =
l =
NC=
X =
Z =
↑ =
↑ =
H
↑
X
NC
Z
H
Dn
Dn
Z
↑
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low to High clock transition
Not a Low-to-High clock transition
August 24, 1993
2
OPERATING MODE
Load and read register
Hold
Disable outputs
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
SYMBOL
VCC
IIK
CONDITIONS
RATING
UNIT
–0.5 to +7.0
V
–18
mA
–1.2 to +7.0
V
VO < 0
–50
mA
output in Off or High state
–0.5 to +5.5
V
output in Low state
128
mA
–65 to 150
°C
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
voltage3
VOUT
DC output
IOUT
DC output current
Tstg
Storage temperature range
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
LIMITS
DC supply voltage
UNIT
MIN
MAX
4.5
5.5
V
0
VCC
V
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level Input voltage
0.8
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
0
5
ns/V
–40
+85
°C
∆t/∆v
Input transition rise or fall rate
Tamb
Operating free-air temperature range
August 24, 1993
2.0
3
V
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
VIK
VOH
Input clamp voltage
High-level output voltage
Tamb = –40°C
to +85°C
Tamb = +25°C
VCC = 4.5V; IIK = –18mA
Typ
Max
–0.9
–1.2
Min
UNIT
Max
–1.2
V
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
2.5
2.9
2.5
V
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
3.0
3.4
3.0
V
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
2.0
2.4
2.0
V
VOL
Low-level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
0.42
0.55
0.55
V
VRST
Power-up output
voltageNO TAG
VCC = 5.5V; IO = 1mA; VI = GND or VCC
0.13
0.55
0.55
V
Input leakage current
VCC = 5.5V; VI = GND or 5.5V
±0.01
±1.0
±1.0
µA
Power-off leakage current
VCC = 0.0V; VO or VI ≤ 4.5V
±5.0
±100
±100
µA
Power-up/down 3-State
output current4
VCC = 2.1V; VO = 0.5V; VI = GND or VCC;
VOE = Don’t care
±5.0
±50
±50
µA
IOZH
3-State output High current
VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
5.0
50
50
µA
IOZL
3-State output Low current
VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
–5.0
–50
–50
µA
ICEX
Output High leakage current
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
5.0
50
50
µA
Output current1
VCC = 5.5V; VO = 2.5V
–70
–180
–180
mA
VCC = 5.5V; Outputs High, VI = GND or VCC
120
250
250
µA
VCC = 5.5V; Outputs Low, VI = GND or VCC
54
76
76
mA
VCC = 5.5V; Outputs 3-State; VI = GND or VCC
120
250
250
µA
VCC = 5.5V; one input at 3.4V, other inputs at
VCC or GND
0.5
1.5
1.5
mA
II
IOFF
IPU/PD
IO
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current per
input pin2
–50
–50
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V a transition
time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = -40 to
+85oC
VCC = +5.0V ±0.5V
Tamb = +25oC
VCC = +5.0V
WAVEFORM
MIN
TYP
MAX
MIN
UNIT
MAX
fMAX
Maximum clock frequency
1
160
250
tPLH
tPHL
Propagation delay
nCP to nQx
1
2.5
2.7
4.4
4.6
5.6
6.0
2.5
2.7
6.4
6.7
ns
tPZH
tPZL
Output enable time
to High and Low level
3
4
1.2
2.2
3.3
3.8
4.2
5.1
1.2
2.2
5.0
5.8
ns
tPHZ
tPLZ
Output disable time
from High and Low level
3
4
1.3
1.5
3.2
3.0
4.6
4.2
1.3
1.5
5.0
4.7
ns
August 24, 1993
4
160
MHz
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = -40 to
+85oC
VCC = +5.0V ±0.5V
Tamb = +25oC
VCC = +5.0V
WAVEFORM
MIN
TYP
2
1.5
1.0
0.6
–0.2
1.5
1.0
ns
Hold time, High or Low
nDx to nCP
2
1.0
1.0
0.3
–0.4
1.0
1.0
ns
nCP pulse width
High or Low
1
3.5
3.0
2.2
1.6
3.5
3.0
ns
ts(H)
ts(L)
Setup time, High or Low
nDx to nCP
th(H)
th(L)
tw(H)
tw(L)
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
AC WAVEFORMS
1/fMAX
nCP
VM
VM
tw(H)
tPHL
VM
nDx
tw(L)
ts(H)
tPLH
VM
MAX
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
VM
VM
th(H)
VM
VM
ts(L)
VM
th(L)
VM
nOE
VM
tPZH
tPHZ
VM
VM
Waveform 2. Data Setup and Hold Times
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
nQx
VM
MIN
CP
nQx
nOE
MAX
UNIT
VM
VM
tPZL
VOH –0.3V
nQx
tPLZ
VM
VOL +0.3V
0V
Waveform 3. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
August 24, 1993
Waveform 4. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
5
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
TEST CIRCUIT AND WAVEFORM
VCC
7.0V
VOUT
VIN
PULSE
GENERATOR
tW
90%
VM
NEGATIVE
PULSE
10%
0V
tTHL (tF)
CL
tTLH (tR)
tTLH (tR)
RL
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs
AMP (V)
90%
VM
VM
10%
10%
tW
SWITCH POSITION
TEST
SWITCH
tPLZ
closed
tPZL
closed
All other
open
0V
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
MB
RT = Termination resistance should be equal to ZOUT of
pulse generators.
August 24, 1993
AMP (V)
VM
10%
RL
D.U.T
RT
90%
6
Amplitude
Rep. Rate
tW
tR
tF
3.0V
1MHz
500ns
2.5ns
2.5ns
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
tPLH vs Temperature (Tamb)
CL = 50pF, 1 Output Switching
nCP to nQx
8
Adjustment of tPLH for
Load Capacitance and # of Outputs Switching
nCP to nQx
6
5
7
6
20 switching
10 switching
4
MAX
1 switching
ns
4.5VCC
5.5VCC
4
3
Offset in ns
5
2
1
MIN
3
0
2
–1
1
–2
–55
–35
–15
5
25
45
65
85
105
125
0
50
°C
200
Adjustment of tPHL for
Load Capacitance and # of Outputs Switching
nCP to nQx
6
5
7
MAX
5
Offset in ns
6
ns
4.5VCC
5.5VCC
4
4
20 switching
10 switching
3
1 switching
2
1
MIN
3
0
2
–1
1
–2
–55
–35
–15
5
25
45
65
85
105
125
0
50
°C
100
150
200
pF
tPZH vs Temperature (Tamb)
CL = 50pF, 1 Output Switching
nOE to nQx
6
5
Adjustment of tPZH for
Load Capacitance and # of Outputs Switching
nOE to nQx
4
2
Offset in ns
4.5VCC
5.5VCC
3
20 switching
10 switching
1 switching
3
MAX
4
ns
150
pF
tPHL vs Temperature (Tamb)
CL = 50pF, 1 Output Switching
nCP to nQx
8
100
2
1
0
MIN
1
–1
0
–55
–2
–35
–15
5
25
45
65
85
105
125
0
°C
August 24, 1993
50
100
pF
7
150
200
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
tPZL vs Temperature (Tamb)
CL = 50pF, 1 Output Switching
nOE to nQx
7
Adjustment of tPZL for
Load Capacitance and # of Outputs Switching
nOE to nQx
5
4
6
MAX
20 switching
10 switching
1 switching
3
Offset in ns
ns
5
4.5VCC
4
5.5VCC
3
2
1
0
MIN
2
–1
1
–2
–55
–35
–15
5
25
45
65
85
105
0
125
50
°C
150
200
pF
tPHZ vs Temperature (Tamb)
CL = 50pF, 1 Output Switching
nOE to nQx
6
100
Adjustment of tPHZ for
Load Capacitance and # of Outputs Switching
nOE to nQx
10
5
8
MAX
20 switching
10 switching
1 switching
6
Offset in ns
ns
4
4.5VCC
3
5.5VCC
2
4
2
0
MIN
1
–2
0
–4
–55
–35
–15
5
25
45
65
85
105
0
125
50
°C
6
MAX
Adjustment of tPLZ for
Load Capacitance and # of Outputs Switching
nOE to nQx
Offset in ns
4.5VCC
3
20 switching
10 switching
1 switching
4
4
ns
200
5
5
5.5VCC
2
MIN
3
2
1
0
1
–1
0
–55
150
pF
tPLZ vs Temperature (Tamb)
CL = 50pF, 1 Output Switching
nOE to nQx
6
100
–2
–35
–15
5
25
45
65
85
105
125
0
°C
August 24, 1993
50
100
pF
8
150
200
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
MB2821
tTLH vs Temperature (Tamb)
CL = 50pF, 1 Output Switching
4
Adjustment of tTLH for
Load Capacitance/# of Outputs
9
20 switching
10 switching
1 switching
7
3
Offset in ns
ns
5
4.5VCC
5.5VCC
2
3
1
1
–1
0
–3
–55
–35
–15
5
25
45
65
85
105
125
0
50
°C
150
200
pF
tTHL vs Temperature (Tamb)
CL = 50pF, 1 Output Switching
4
100
Adjustment of tTHL for
Load Capacitance and # of Outputs Switching
5
4
3
2
1 switching
Offset in ns
4.5VCC
ns
20 switching
10 switching
3
5.5VCC
2
1
0
1
–1
0
–2
–55
–35
–15
5
25
45
65
85
105
0
125
50
°C
200
VOHP and VOLV vs Load Capacitance
VCC = 5V, VIN = 0 to 3V
6
5
3.5
125°C
25°C
–55°C
3.0
125°C
25°C
–55°C
4
3
Volts
2.5
Volts
150
pF
VOHV and VOLP vs Load Capacitance
VCC = 5V, VIN = 0 to 3V
4.0
100
2.0
1.5
2
1
0
1.0
125°C
25°C
–55°C
0.5
125°C
25°C
–55°C
–1
–2
0
–3
0
50
100
150
0
200
pF
August 24, 1993
50
100
pF
9
150
200
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