NB3N51032 3.3 V, Crystal to 25 MHz, 100 MHz, 125 MHz and 200 MHz Dual HCSL/LVDS Clock Generator The NB3N51032 is a precision, low phase noise clock generator that supports PCI Express and Ethernet requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal and generates a differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies. Outputs can interface with LVDS with proper termination (See Figure 10). The NB3N51032 provides selectable spread options of −0.5% and −0.75% for applications demanding low Electromagnetic Interference (EMI) as well as optimum performance with no spread option. Features • • • • • • • • • • • • • http://onsemi.com MARKING DIAGRAM 16 16 NB3N 1032 1 ALYWG TSSOP−16 G 1 DT SUFFIX CASE 948F A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) Uses 25 MHz Fundamental Mode Parallel Resonant Crystal External Loop Filter is Not Required HCSL Differential Output or LVDS with Proper Termination Four Selectable Multipliers of the Input Frequency Output Enable with Tri−State Outputs ORDERING INFORMATION PCIe Gen 1, Gen 2, Gen 3 Compliant See detailed ordering and shipping information on page 11 of this data sheet. Spread of −0.5%, −0.75% and No Spread Applications Phase Noise: @ 100 MHz • Networking Offset Noise Power 100 Hz −88 dBc/Hz • Consumer 1 kHz −118 dBc/Hz • Computing and Peripherals 10 kHz −131 dBc/Hz • Industrial Equipment 100 kHz −132 dBc/Hz • PCIe Clock Generation Gen 1, Gen 2 and Gen 3 1 MHz −144 dBc/Hz • Gigabit Ethernet 10 MHz −155 dBc/Hz • FB DIMM Typical Period Jitter RMS of 1.5 ps Operating Supply Voltage Range 3.3 V ±5% End Products Industrial Temperature Range −40°C to +85°C • Switch and Router Functionally Compatible with IDT557−03, • Set Top Box, LCD TV IDT5V41065, IDT5V41235 with enhanced performance • Servers, Desktop Computers These are Pb−Free Devices • Automated Test Equipment VDD Spread Spectrum Circuit X1/CLK 25 MHz Clock or Crystal SS0 SS1 Clock Buffer Crystal Oscillator Charge Pump Phase Detector VCO X2 BN VDD = VDDODA = VDDXD GND = GNDODA = GNDXD GND S1 OE CLK0 CLK0 HCSL Output CLK1 CLK1 IREF Figure 1. NB3N51032 Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 1 S0 HCSL Output 1 Publication Order Number: NB3N51032/D NB3N51032 S0 1 16 VDDXD S1 2 15 CLK0 SS0 3 14 CLK0 X1/CLK 4 13 GNDODA X2 5 12 VDDODA OE 6 11 CLK1 GNDXD 7 10 CLK1 SS1 8 9 IREF Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O Description 1 S0 Input LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDDXD. See output select table 2 for details. 2 S1 Input LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDDXD. See output select Table 2 for details. 3 SS0 Input LVTTL/LVCMOS Spread select input 0. Internal pullup resistor to VDDXD. See Spread selection Table 3 for details. 4 X1/CLK Input Crystal or Clock input. Connect to 25 MHz crystal source or single−ended clock. 5 X2 Input Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input. Output enable tri−states output when connected to GND. Internal pullup resistor to VDDXD. 6 OE Input 7 GNDXD Power Supply 8 SS1 Input LVTTL/LVCMOS Spread select input 1. Internal pullup resistor to VDDXD. See Spread selection Table 3 for details. 9 IREF Output Output current reference pin. Precision resistor (typ. 475 W) is connected to set the output current. 10 CLK1 HCSL or LVDS Output Inverted clock output. (For LVDS levels see Figure 10) 11 CLK1 HCSL or LVDS Output Noninverted clock output. (For LVDS levels see Figure 10) 12 VDDODA Power Supply Positive supply voltage pin connected to +3.3 V supply voltage. 13 GNDODA Power Supply Ground 0 V. These pins provide GND return path for the devices. 14 CLK0 HCSL or LVDS Output Inverted clock output. (For LVDS levels see Figure 10) 15 CLK0 HCSL or LVDS Output Noninverted clock output. (For LVDS levels see Figure 10) 16 VDDXD Power Supply Positive supply voltage pin connected to +3.3 V supply voltage. Ground 0 V. This pin provides GND return path for the device. http://onsemi.com 2 NB3N51032 Recommended Crystal Parameters Table 2. OUTPUT FREQUENCY SELECT TABLE WITH 25MHz CRYSTAL S1* S0* CLK Multiplier fCLKout (MHz) L L 1x 25 L H 4x 100 H L 5x 125 H H 8x 200 Crystal Frequency Load Capacitance Shunt Capacitance, C0 Equivalent Series Resistance Initial Accuracy at 25 °C Temperature Stability Aging Fundamental AT−Cut 25 MHz 16−20 pF 7 pF Max 50 W Max ±20 ppm ±30 ppm ±20 ppm *Pins S1 and S0 default high when left open. Table 3. SPREAD SELECTION TABLE SS1* SS0* Spread% Spread Type 0 0 No Spread N/A 0 1 −0.5 Down 1 0 −0.75 Down 1 1 No Spread N/A *Pins S1 and S0 default high when left open. Table 4. ATTRIBUTES Characteristic ESD Protection Value Human Body Model 2 kV Pull−up Resistor (Pins OE, S0, S1, SS0 and SS1) 50 kW Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 132000 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NB3N51032 Table 5. MAXIMUM RATINGS (Note 2) Symbol Parameter Rating Unit 4.6 V −0.5 V to VDD+0.5 V V Operating Temperature Range −40 to +85 °C Storage Temperature Range −65 to +150 °C 74 64 °C/W °C/W Thermal Resistance (Junction−to−Case) 50 °C/W Wave Solder 265 °C VDD Positive Power Supply with respect to GND (VDDXD and VDDODA) VI Input Voltage with respect to GND (VIN) TA Tstg qJA Thermal Resistance (Junction−to−Ambient) (Note 3) qJC Tsol 0 lfpm 500 lfpm Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). Table 6. DC CHARACTERISTICS (VDD = 3.3 V ±5%, GND = 0 V, TA = −40°C to +85°C, Note 4) Symbol Characteristic Min Typ Max Unit 3.135 3.3 3.465 V VDD Power Supply Voltage (VDDXD and VDDODA) GND Power Supply Ground (GNDXD and GNDODA) IDD IDDOE VIH Input HIGH Voltage (X1/CLK, S0, S1, SS0, SS1 and OE) 2000 VDD + 300 mV VIL Input LOW Voltage (X1/CLK, S0, S1, SS0, SS1 and OE) GND − 300 800 mV VOH Output HIGH Voltage for HCSL Output (Note 5) 660 850 mV VOL Output LOW Voltage for HCSL Output (Note 5) −150 Vcross Crossing Voltage Magnitude (Absolute) for HCSL Output (Notes 6 and 7) 250 DVcross Change in Magnitude of Vcross for HCSL Output (Notes 6 and 8) 0 V Power Supply Current, 200 MHz Output, −0.75% spread 100 mA Power Supply Current when OE is Set Low 55 mA 0 mV 550 mV 150 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. VDDXD and VDDODA power pins must be shorted to power supply voltage VDD and GNDXD and GNDODA ground pins must be shorted to power supply ground GND. Measurement taken with outputs terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 9. Guaranteed by characterization. 5. Measurement taken from single−ended waveform. 6. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx−. 7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 8. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx−. This is maximum allowed variance in the VCROSS for any particular system. http://onsemi.com 4 NB3N51032 Table 7. AC CHARACTERISTICS (VDD = 3.3 V ±5%, GND = 0 V, TA = −40°C to +85°C; Note 9) Symbol Characteristic Min fCLKIN Clock/Crystal Input Frequency fCLKOUT Output Clock Frequency FNOISE Phase−Noise Performance tJITTER Period Jitter Peak−to−Peak (Note 10) Period Jitter RMS (Note 10) Cycle−Cycle RMS Jitter (Note 11) Cycle−to−Cycle Peak to Peak Jitter (Note 11) tJIT(F) Phase RMS Jitter, Integration Range 12 kHz to 20 MHz fMOD Spread Spectrum Modulation Frequency Typ Max 25 25 fCLKOUT = 100 Mhz @ 100 Hz offset from carrier @ 1 kHz offset from carrier @ 10 kHz offset from carrier @ 100 kHz offset from carrier @ 1 MHz offset from carrier @ 10 MHz offset from carrier 200 MHz dBc/Hz −88 −118 −131 −132 −144 −155 fCLKOUT = 200 Mhz fCLKOUT = 200 MHz fCLKOUT = 200 MHz fCLKOUT = 200 MHz 10 1.5 2.0 20 20 3.0 5.0 35 0.5 30 3rd Unit MHz Harmonic 31.5 ps ps 33.33 −10 kHz SSCRED Spectral Reduction, fCLKOUT of 100 MHz with −0.5% spread, (Note 12) dB tSKEW Within Device Output to Output Skew Eppm Frequency Synthesis Error, All Outputs tSPREAD Spread Spectruction Transition Time (Stablization Time After Spread Spectrum Changes) tOE Output Enable/Disable Time (Note 13) tDUTY_CYCLE Output Clock Duty Cycle (Measured at cross point) 45 55 % tR Output Risetime (Measured from 175 mV to 525 mV, Figure 11) 175 700 ps tF Output Falltime (Measured from 525 mV to 175 mV, Figure 11) 175 700 ps DtR Output Risetime Variation (Single−Ended) 125 ps DtF Output Falltime Variation (Single−Ended) 125 ps Stabilization Time Stabilization Time From Powerup VDD = 3.3 V 40 0 7 50 3.0 ps ppm 30 ms 10 ms ms NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. VDDXD and VDDODA power pins must be shorted to power supply voltage VDD and GNDXD and GNDODA ground pins must be shorted to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 9. Guaranteed by characterization. 10. Sampled with 10000 cycles. 11. Sampled with 1000 cycles. 12. Spread spectrum clocking enabled. 13. Output pins are tri−stated when OE is asserted LOW. Output pins are driven differentially when OE is HIGH. http://onsemi.com 5 NB3N51032 Table 8. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS, VDD = 3.3 V ± 5%, TA = −40°C to 85°C Symbol tj (PCIe Gen 1) Parameter Typ Max PCIe Industry Spec SSOFF 10 20 86 pS SSON (−0.5%) 19 28 SSOFF 1.0 1.8 3.1 pS SSON (−0.5%) 1.1 1.9 SSOFF 0.1 0.15 3 pS SSON (−0.5%) 0.8 1.1 SSOFF 0.35 0.7 1 pS SSON (−0.5%) 0.55 0.8 Test Conditions Phase Jitter Peak−to−Peak (Notes 15 and 18) f = 100 MHz, 25 MHz Crystal Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) tREFCLK_HF_RMS (PCIe Gen 2) Phase Jitter RMS (Notes 16 and 18) f = 100 MHz, 25 MHz Crystal Input High Band: 1.5 MHz − Nyquist (clock frequency/2) tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS (Notes 16 and 18) f = 100 MHz, 25 MHz Crystal Input Low Band: 10 kHz − 1.5 MHz tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS (Notes 17 and 18) f = 100 MHz, 25 MHz Crystal Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) Min Unit 14. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. 15. Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps peak−to−peak for a sample size of 106 clock periods. 16. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band) and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band). 17. RMS jitter after applying system transfer function for the common clock architecture. 18. VDDXD and VDDODA power pins must be shorted to power supply voltage VDD and GNDXD and GNDODA ground pins must be shorted to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 50 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 11. This parameter is guaranteed by characterization. Not tested in production. http://onsemi.com 6 NB3N51032 NOISE POWEER (dBc/Hz) PHASE NOISE OFFSET FREQUENCY (Hz) NOISE POWEER (dBc/Hz) Figure 3. Typical Phase Noise Plot at 25 MHz; (fCLKIN = 25 MHz Crystal , fCLKOUT = 25 MHz SS OFF, RMS Phase Jitter for Integration Range 12 kHz to 20 MHz = 554 fs, Output Termination = HCSL type) OFFSET FREQUENCY (Hz) Figure 4. Typical Phase Noise Plot at 100 MHz; (fCLKIN = 25 MHz Crystal , fCLKOUT = 100 MHz SS OFF, RMS Phase Jitter for Integration Range 12 kHz to 20 MHz = 456 fs, Output Termination = HCSL type) http://onsemi.com 7 NB3N51032 NOISE POWEER (dBc/Hz) PHASE NOISE OFFSET FREQUENCY (Hz) NOISE POWEER (dBc/Hz) Figure 5. Typical Phase Noise Plot at 125 MHz; (fCLKIN = 25 MHz Crystal , fCLKOUT = 125 MHz SS OFF, RMS Phase Jitter for Integration Range 12 kHz to 20 MHz = 480 fs, Output Termination = HCSL type) OFFSET FREQUENCY (Hz) Figure 6. Typical Phase Noise Plot at 200 MHz; (fCLKIN = 25 MHz Crystal , fCLKOUT = 200 MHz SS OFF, RMS Phase Jitter for Integration Range 12 kHz to 20 MHz = 497 fs, Output Termination = HCSL type) http://onsemi.com 8 NB3N51032 APPLICATION INFORMATION Crystal Input Interface as nominal values, assuming approximately 2 pF of stray capacitance per trace and approximately 8 pF of internal capacitance. CL = (C1 + Cstray + Cin) / 2; C1 = C2 The frequency accuracy and duty cycle skew can be fine-tuned by adjusting the C1 and C2 values. For example, increasing the C1 and C2 values will reduce the operational frequency. Figure 7 shows the NB3N51032 device crystal oscillator interface using a typical parallel resonant crystal. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors, C1 and C2, need to consider the stray capacitances of the board and are used to match the nominally required crystal load capacitance CL. A parallel crystal with loading capacitance CL = 18 pF would use C1 = 26 pF and C2 = 26 pF C1 = 26 pF X1 Fundamental Mode Parallel Resonant Crystal 18 pF Load X2 C2 = 26 pF Figure 7. Crystal Interface Loading Power Supply Filter as close as possible to the device to minimize lead inductance. In order to isolate the NB3N51032 from system power supply, noise decoupling is required. The 10 mF and a 0.1 mF cap from supply pins to GND decoupling capacitor has to be connected between VDD (pins 12 and 16) and GND (pins 7 and 13). It is recommended to place decoupling capacitors Termination The output buffer structure is shown in the Figure 8. 2.6 mA 14 mA IREF RREF CLKx CLKx HCSL / LVDS termination 475 W Figure 8. Simplified Output Structure http://onsemi.com 9 NB3N51032 interface may not require the 100 W near the LVDS receiver if the receiver has internal 100 W termination. An optional series resistor RL may be connected to reduce the overshoots in case of impedance mismatch. The outputs can be terminated to drive HCSL receiver (see Figure 9) or LVDS receiver (see Figure 10). HCSL output interface requires 49.9 W termination resistors to GND for generating the output levels. LVDS output HCSL INTERFACE RL* = 33.2 W CLK0 Zo = 50 W RL* = 33.2 W Zo = 50 W CLK0 RL = 49.9 W NB3N51032 HCSL Driver RL = 49.9 W HCSL Receiver RL* = 33.2 W CLK1 Zo = 50 W RL* = 33.2 W Zo = 50 W CLK1 IREF RL = 49.9 W *Optional RL = 49.9 W RREF = 475 W Figure 9. Typical Termination for Output Driver and Device Evaluation LVDS COMPATIBLE INTERFACE CLK0 RL* = 33.2 W Zo = 50 W 100 W RL* = 33.2 W 100 W** Zo = 50 W CLK0 RL = 150 W RL = 150 W NB3N51032 CLK1 RL* = 33.2 W Zo = 50 W 100 W RL* = 33.2 W CLK1 IREF RREF = 475 W LVDS Receiver 100 W** Zo = 50 W *Optional **Not required if LVDS receiver has 100 Ohm internal termination RL = 150 W RL = 150 W LVDS Device Load Figure 10. Typical Termination for LVDS Device Load http://onsemi.com 10 NB3N51032 700 mV 525 mV 525 mV 175 mV 175 mV 0 mV tR tF Figure 11. HCSL Output Parameter Characteristics ORDERING INFORMATION Package Shipping† NB3N51032DTG TSSOP−16 (Pb−Free) 96 Units / Rail NB3N51032DTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 NB3N51032 PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NB3N51032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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