ICST ICS281PGILF Triple pll field prog. spread spectrum clock synthesizer Datasheet

PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Description
Features
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The ICS281 field programmable spread spectrum
clock synthesizer generates up to three high-quality,
high-frequency clock outputs including multiple
reference clocks from a low-frequency crystal input. It
is designed to replace crystals, crystal oscillators and
stand alone spread spectrum devices in most
electronic systems.
Using ICS’ VersaClockTM software to configure PLLs
and outputs, the ICS281 contains a One-Time
Programmable (OTP) ROM for field programmability.
Programming features include input/output
frequencies, spread spectrum amount and eight
selectable configuration registers.
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
Packaged as 16-pin TSSOP
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3 V
Configurable Spread Spectrum Modulation
Input crystal frequency of 5 to 27 MHz
Input clock frequency of 3 to 166 MHz
Up to three reference outputs
Operating voltages of 3.3 V
VDDO output control from 1.8 V to 3.3 V
Controllable output drive levels
Advanced, low-power CMOS process
Available in Pb (lead) free packaging
The ICS281 is also available in factory programmed
custom versions for high-volume applications.
Block Diagram
VDD
S2:S0
3
OTP
ROM
with PLL
Values
3
VDDO
PLL1 with
Spread
Spectrum
PLL2
Crystal or
clock input
CLK1
Divide
Logic
and
Output
Enable
Control
PLL3
CLK2
CLK3
X1/ICLK
Crystal
Oscillator
X2
GND
External capacitors
are required with a crystal input.
3
PDTS
1
MDS 281 C
Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
Revision 062205
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tel (408) 297-1201
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PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Pin Assignment
GND
16
S2
2
15
3
14
VDD
4
13
VDD
PDTS
GND
VDDO
CLK1
5
6
12
11
CLK2
GND
7
10
VDD
X1/ICLK
8
9
S0
S1
1
CLK3
X2
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
GND
Power
Connect to ground.
2
S0
Input
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
Pin Description
3
S1
Input
4
VDD
Power
5
VDDO
Power
Power supply for outputs.
6
CLK1
Output
Output clock 1. Weak internal pull-down when tri-state.
7
GND
Power
8
X1
XI
Crystal input. Connect this pin to a crystal or external input clock.
9
X2
XO
Connect to ground.
10
VDD
Power
Crystal Output. Connect this pin to a crystal. Float for clock input.
Connect to +3.3 V.
11
CLK2
Output
Output clock 2. Weak internal pull-down when tri-state.
12
CLK3
Output
Output clock 3. Weak internal pull-down when tri-state.
13
GND
Power
Connect to ground.
14
PDTS
Input
15
VDD
Power
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
Connect to +3.3 V.
16
S2
Input
Select pin 2. Internal pull-up resistor.
2
MDS 281 C
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
Revision 062205
●
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
External Components
set within the range of M = 1 to 1024 and N = 1 to
32,895.
The ICS281 requires a minimum number of external
components for proper operation.
The ICS281 also provides separate output divide
values, from 2 through 63, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Each output frequency can be represented as:
OutputFreq
=
REFFreq
----⋅M
N
Output Drive Control
The ICS281 has two output drive settings. For
VDDO=VDD, low drive should be selected when
outputs are less than 100 MHz. High drive should be
selected when outputs are greater than 100 MHz.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS281 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
For VDDO<2.8 V, high drive should be selected for all
output frequencies.
(Consult the AC Electrical Characteristics for output
rise and fall times for each drive option.)
ICS VersaClock Software
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(CL -6 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
ICS281 Configuration Capabilities
The architecture of the ICS281 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
Spread Spectrum Modulation
The ICS281 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By
modulating the output clock frequencies, the device
effectively lowers energy across a broader range of
frequencies; thus, lowering a system’s electromagnetic
interference (EMI). The modulation rate is the time from
transitioning from a minimum frequency to a maximum
frequency and then back to the minimum.
3
MDS 281 C
Integrated Circuit Systems, Inc.
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
●
525 Race Street, San Jose, CA 95126
Revision 062205
●
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is
equal in the positive and negative directions. The
effective average frequency is equal to the target
frequency. In applications where the clock is driving a
component with a maximum frequency rating, down
spread should be applied. In this case, the maximum
frequency, including modulation, is the target
frequency. The effective average frequency is less than
the target frequency.
The ICS281 operates in both center spread and down
spread modes. For center spread, the frequency can
be modulated between ±0.125% to ±2.0%. For down
spread, the frequency can be modulated between
-0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates,
if a common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to
the output clock frequency may occur at a variety of
rates. For applications requiring the driving of
“down-circuit” PLLs, Zero Delay Buffers, or those
adhering to PCI standards, the spread spectrum
modulation rate should be set to 30-33 kHz. For other
applications, a 120 kHz modulation option is available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS281. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Condition
Min.
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
Clock Outputs
Referenced to GND
Max.
Units
7
V
-0.5
VDD+0.5
V
-0.5
VDD+0.5
V
-65
150
°C
260
°C
125
°C
Storage Temperature
Soldering Temperature
Typ.
Max 10 seconds
Junction Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (ICS281PG/PGLF)
0
+70
°C
Ambient Operating Temperature (ICS281PGI/PGILF)
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+3.135
+3.465
V
4
ms
+3.3
Power Supply Ramp Time
4
MDS 281 C
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
Revision 062205
●
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Operating Voltage
Conditions
Min.
VDD
VDDO Voltage
Typ.
Max.
Units
3.135
3.465
V
1.80
VDD
V
Config. Dependent - See
VersaClockTM Estimates
Operating Supply Current
Input High Voltage
IDD
mA
Three 33.3333 MHz outs,
VDD=VDDO=3.3V;
PDTS = 1, no load, Note 1
20
mA
500
µA
V
Input High Voltage
VIH
PDTS = 0, no load, Note 1
S2:S0
Input Low Voltage
VIL
S2:S0
Input High Voltage, PDTS
VIH
Input Low Voltage, PDTS
VIL
Input High Voltage
VIH
ICLK
Input Low Voltage
VIL
ICLK
Output High Voltage
(CMOS High)
VOH
IOH = -4 mA
Output High Voltage
VOH
IOH = -8 mA (Low Drive);
IOH = -12 mA (High Drive)
Output Low Voltage
VOL
IOL = 8 mA (Low Drive);
IOL = 12 mA (High Drive)
Short Circuit Current
IOS
Low Drive
±40
High Drive
±70
mA
20
Ω
Nom. Output Impedance
VDD/2+1
0.4
VDD-0.5
V
0.4
VDD/2+1
V
V
VDD/2-1
V
VDD-0.4
V
2.4
VDDO-0.4
V
0.4
ZO
V
V
Internal pull-up resistor
RPUS
S2:S0, PDTS
190
kΩ
Internal pull-down
resistor
RPD
CLK outputs
120
kΩ
Input Capacitance
CIN
Inputs
4
pF
Note 1: Example with 25 MHz crystal input, three unloaded 33.3 MHz outputs and VDD = VDDO = 3.3 V.
5
MDS 281 C
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
Revision 062205
●
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Input Frequency
FIN
Output Frequency
Conditions
Min.
Typ.
Max. Units
Fundamental crystal
5
27
MHz
Clock input
3
166
MHz
VDDO=VDD
0.314
200
MHz
1.8 V<VDDO<2.8 V
0.314
150
MHz
Output Rise/Fall Time
tOF
80% to 20%, high drive,
Note 1
1.0
ns
Output Rise/Fall Time
tOF
80% to 20%, low drive,
Note 1
2.0
ns
Output Rise/Fall Time
tOF
80% to 20%, high drive,
1.8 V<VDDO<2.8
Note 2
2.0
ns
Duty Cycle
Note 2
Output Frequency Synthesis Error
Configuration Dependent
Power-up Time
PLL lock-time from
power-up
One Sigma Clock Period Jitter
Maximum Absolute Jitter
tja
40
49-51
60
TBD
%
ppm
4
10
ms
PDTS goes high until
stable CLK output,
Spread Spectrum Off
0.6
2
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On
4
7
ms
Configuration Dependent
50
ps
Deviation from Mean.
Configuration Dependent
+200
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Thermal Characteristics
Parameter
Symbol
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Min.
Typ.
Max. Units
θJA
Still air
78
°C/W
θJA
1 m/s air flow
70
°C/W
θJA
3 m/s air flow
68
°C/W
37
°C/W
θJC
6
MDS 281 C
Integrated Circuit Systems, Inc.
Conditions
●
525 Race Street, San Jose, CA 95126
Revision 062205
●
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Marking Diagrams
Marking Diagrams (Pb free)
16
16
9
9
281PGL
######
YYWW
281PG
######
YYWW
1
8
1
8
16
9
16
9
281PGIL
######
YYWW
281PGI
######
YYWW
1
1
8
8
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temperature range (if applicable).
4. “L” denotes Pb (lead) free package.
5. Bottom marking: country of origin.
7
MDS 281 C
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
Revision 062205
●
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
24
Millimeters
Symbol
E1
INDEX
AREA
Min
A
A1
A2
b
C
D
E
E1
e
L
α
E
1 2
D
Inches
Max
Min
—
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.10
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
Max
—
.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
.018
.030
0°
8°
A
A2
A1
c
- Ce
SEATING
PLANE
b
.10 (.004)
L
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
Tubes
16-pin TSSOP
0 to +70°C
ICS281PG
ICS281PGI
See page 7
Tubes
16-pin TSSOP
-40 to +85°C
ICS281PGLF
Tubes
16-pin TSSOP
0 to +70°C
ICS281PGILF
Tubes
16-pin TSSOP
-40 to +85°C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
VersaClockTM is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
8
MDS 281 C
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
Revision 062205
●
tel (408) 297-1201
●
www.icst.com