TI DAC5573IPW Quad, 8-bit, low-power, voltage output, interface digital-to-analog converter Datasheet

DAC5573
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SLAS401 – NOVEMBER 2003
QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT,
I C INTERFACE DIGITAL-TO-ANALOG CONVERTER
2
FEATURES
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DESCRIPTION
Micropower Operation: 500 µA at 3 V VDD
Fast Update Rate: 188 kSPS
Power-On Reset to Zero
2.7-V to 5.5-V Analog Power Supply
8-Bit Monotonic
I2C™ Interface up to 3.4 Mbps
Data Transmit Capability
Rail-to-Rail Output Buffer Amplifier
Double-Buffered Input Register
Address Support for up to Sixteen DAC5573s
Synchronous Update for up to 64 Channels
Voltage Translators for all Digital Inputs
Operation From –40°C to 105°C
Small 16 Lead TSSOP Package
Process Control
Data Acquisition Systems
Closed-Loop Servo Control
PC Peripherals
Portable Instrumentation
VDD
The DAC5573 requires an external reference voltage
to set the output range of the DAC. The DAC5573
incorporates a power-on-reset circuit that ensures
that the DAC output powers up at zero volts and
remains there until a valid write takes place in the
device. The DAC5573 contains a power-down feature, accessed via the internal control register, that
reduces the current consumption of the device to 200
nA at 5 V.
The low power consumption of this part in normal
operation makes it ideally suited to portable battery
operated equipment. The power consumption is less
than 3 mW at VDD = 5 V reducing to 1 µW in
power-down mode.
APPLICATIONS
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The DAC5573 is a low-power, quad channel, 8-bit
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing. The
DAC5573 utilizes an I2C-compatible two-wire serial
interface supporting high-speed interface mode with
address support of up to sixteen DAC5573s for a total
of 64 channels on the bus.
The DAC5573 is available in a 16-lead TSSOP
package.
IOVDD
VREFH
Data
Buffer A
DAC
Register A
DAC A
VOUTA
VOUTB
VOUTC
Data
Buffer D
DAC
Register D
Buffer
Control
Register
Control
DAC D
VOUTD
18
SCL
I2C Block
SDA
Power−Down
Control Logic
8
A0
A1
GND
Resistor
Network
A2
A3
LDAC
VREFL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003, Texas Instruments Incorporated
DAC5573
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SLAS401 – NOVEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC5573
16-TSSOP
PW
–40°C TO +105°C
D5573I
ORDERING
NUMBER
TRANSPORT MEDIA
DAC5573IPW
90 Piece Tube
DAC5573IPWR
2000 Piece Tape and Reel
PW PACKAGE
(TOPVIEW)
PIN DESCRIPTIONS
PIN
16 A3
NAME DESCRIPTION
1
VOUTA
Analog output voltage from DAC A
2
VOUTB
Analog output voltage from DAC B
Positive reference voltage input
VOUTA
1
VOUTB
2
15 A2
3
3
14 A1
VREFH
VREFH
4
VDD
VDD
4
13 A0
5
VREFL
Negative reference voltage input
VREFL
5
12 IOVDD
6
GND
GND
6
11 SDA
Ground reference point for all circuitry on the
part
VOUTC
7
10 SCL
VOUTD
8
9 LDAC
DAC5573
Analog voltage supply input
7
VOUTC Analog output voltage from DAC C
8
VOUTD Analog output voltage from DAC D
9
LDAC
10
SCL
H/W synchronous VOUT update
Serial clock input
11
SDA
Serial data input
12
IOVDD
13
A0
Device address select - I2C
14
A1
Device address select - I2C
15
A2
Device address select - Extended
16
A3
Device address select - Extended
I/O voltage supply input
ABSOLUTE MAXIMUM RATINGS (1)
VDD to GND
–0.3 V to +6 V
Digital input voltage to GND
–0.3 V to VDD + 0.3 V
VOUT to GND
–0.3 V to VDD + 0.3 V
Operating temperature range
–40°C to +105°C
Storage temperature range
–65°C to +150°C
Junction temperature range (TJ max)
Power dissipation:
Lead temperature, soldering:
(1)
2
+150°C
Thermal impedance (RΘJA)
161°C/W
Thermal impedance (RΘJC)
29°C/W
Vapor phase (60s)
215°C
Infrared (15s)
220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
DAC5573
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SLAS401 – NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (1) (2)
Resolution
8
Bits
±0.25
±0.5
LSB
±0.1
± 0.25
LSB
Zero-scale error
5
20
mV
Full-scale error
-0.15
±1.0
% of FSR
±1.0
% of FSR
Relative accuracy
Differential nonlinearity
Specified monotonic by design
Gain error
Zero code error drift
±7
µV/°C
Gain temperature coefficient
±3
ppm of FSR/°C
OUTPUT CHARACTERISTICS (3)
Output voltage range
Output voltage settling time (full scale)
0
Digital-to-analog glitch impulse
12
µs
1
V/µs
0.0025
LSB
1 kHz Sine Wave
-100
dB
RL= ∞
470
pF
RL= 2 kΩ
1000
pF
1 LSB change around major
carry
12
nV-s
0.3
nV-s
1
Ω
VDD= 5 V
50
mA
VDD= 3 V
20
mA
Coming out of power-down
mode, VDD= +5 V
2.5
µs
Coming out of power-down
mode, VDD= +3 V
5
µs
Digital feedthrough
dc output impedance
Short-circuit current
Power-up time
µs
RL = ∞ ; CL = 500 pF
dc crosstalk (channel-to-channel)
Capacitive load stability
V
8
6
Slew rate
ac crosstalk (channel-to-channel)
VREFH
RL = ∞; 0 pF < CL < 200 pF
REFERENCE INPUT
VREFH Input range
VREFL Input range
0
VREFL<VREFH
0
Reference input impedance
Reference current
LOGIC INPUTS
VDD
GND
VDD/2
25
V
V
kΩ
VREF=VDD = +5 V
185
260
VREF=VDD = +3 V
122
200
µA
(3)
Input current
VIN_L, Input low voltage
VIN_H, Input high voltage
±1
µA
0.3xIOVDD
V
3
pF
5.5
V
0.7xIOVDD
V
Pin Capacitance
POWER REQUIREMENTS
VDD, IOVDD
2.7
IDD(normal operation), including reference current
Excluding load current
IDD@ VDD=+3.6V to +5.5V
VIH= IOVDD and VIL=GND
600
900
µA
IDD@ VDD =+2.7V to +3.6V
VIH= IOVDD and VIL=GND
500
750
µA
IDD (all power-down modes)
(1)
(2)
(3)
Linearity tested using a reduced code range of 3 to 253; output unloaded.
VREFH = VDD - 0.1, VREFL = GND
Specified by design and characterization, not production tested.
3
DAC5573
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SLAS401 – NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
TYP
MAX
UNITS
IDD@ VDD=+3.6V to +5.5V
VIH= IOVDD and VIL=GND
MIN
0.2
1
µA
IDD@ VDD =+2.7V to +3.6V
VIH= IOVDD and VIL=GND
0.05
1
µA
ILOAD= 2 mA, VDD= +5 V
93%
+105
°C
POWER EFFICIENCY
IOUT/IDD
TEMPERATURE RANGE
Specified performance
-40
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to +105°C, unless otherwise specified.
SYMBOL
PARAMETER
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP and
START condition
tHD; tSTA
Hold time (repeated) START
condition
TEST CONDITIONS
MIN
MAX
UNITS
Standard mode
100
kHz
Fast mode
400
kHz
High-Speed mode, CB = 100 pF max
3.4
MHz
1.7
MHz
High-speed mode, CB = 400 pF max
tLOW
tHIGH
tSU; tSTA
tSU; tDAT
tHD; tDAT
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START
condition
Data setup time
Data hold time
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
4.0
µs
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
4.7
µs
Fast mode
1.3
µs
High-speed mode, CB = 100 pF max
160
ns
High-speed mode, CB = 400 pF max
320
ns
Standard mode
4.0
µs
Fast mode
600
ns
High-Speed Mode, CB = 100 pF max
60
ns
High-speed mode, CB = 400 pF max
120
ns
Standard mode
4.7
µs
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
High-speed mode
10
ns
Standard mode
0
3.45
µs
Fast mode
0
0.9
µs
High-speed mode, CB = 100 pF max
0
70
ns
High-speed mode, CB = 400 pF max
0
150
ns
1000
ns
20 + 0.1CB
300
ns
High-speed mode, CB = 100 pF max
10
40
ns
High-speed mode, CB = 400 pF max
20
Standard mode
tRCL
Rise time of SCL signal
Fast mode
Standard mode
tRCL1
4
Rise time of SCL signal after a
repeated START condition and after
an acknowledge BIT
TYP
Fast mode
20 + 0.1CB
80
ns
1000
ns
300
ns
High-speed mode, CB = 100 pF max
10
80
ns
High-speed mode, CB = 400 pF max
20
160
ns
DAC5573
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SLAS401 – NOVEMBER 2003
TIMING CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to +105°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
300
ns
20 + 0.1CB
300
ns
High-speed mode, CB = 100 pF max
10
40
ns
High-speed mode, CB = 400 pF max
20
80
ns
1000
ns
Standard mode
tFCL
Fall time of SCL signal
Fast mode
Standard mode
tRDA
Rise time of SDA signal
Fast mode
20 + 0.1CB
300
ns
High-speed mode, CB = 100 pF max
10
80
ns
High-speed mode, CB = 400 pF max
20
160
ns
300
ns
Standard mode
tFDA
tSU; tSTO
Fall time of SDA signal
Setup time for STOP
condition
CB
Capacitive load for SDA and SCL
tSP
Pulse width of spike
suppressed
VNH
VNL
Noise margin at the HIGH level for
each connected device
(including hysteresis)
Noise margin at the LOW level for
each connected device
(including hysteresis)
TYP
20 + 0.1CB
300
ns
High-speed mode, CB = 100 pF max
Fast mode
10
80
ns
High-speed mode, CB = 400 pF max
20
160
ns
Standard mode
4.0
µs
Fast mode
600
ns
High-speed mode
160
ns
400
pF
Fast mode
50
ns
High-speed mode
10
ns
Standard mode
Fast mode
0.2 VDD
V
0.1 VDD
V
High-speed mode
Standard mode
Fast mode
High-speed mode
5
DAC5573
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SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
1
1
VDD = 5 V
Channel B
LE − LSB
LE − LSB
Channel A
0.5
0
−0.5
0.5
0.5
0.25
0
−0.25
32
64
96
128
160
Digital Input Code
192
224
0
255
96
128
160
192
224
255
Figure 2.
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
1
Channel D
VDD = 5 V
0.5
LE − LSB
LE − LSB
64
Figure 1.
Channel C
0
−0.5
VDD = 5 V
0.5
0
−0.5
−1
−1
0.5
0.5
0.25
0.25
DLE − LSB
DLE − LSB
32
Digital Input Code
1
0
−0.25
0
−0.25
−0.5
−0.5
0
32
64
96
128
160
Digital Input Code
192
224
0
255
32
64
96
128
160
Digital Input Code
192
224
255
Figure 3.
Figure 4.
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
1
1
Channel A
Channel B
VDD = 2.7 V
LE − LSB
0.5
0
−0.5
0
−0.5
−1
0.5
0.5
0.25
0.25
0
−0.25
−0.5
VDD = 2.7 V
0.5
−1
DLE − LSB
LE − LSB
0
−0.25
−0.5
0
DLE − LSB
−0.5
0.25
−0.5
0
−0.25
−0.5
0
32
64
96
128
160
Digital Input Code
Figure 5.
6
0
−1
DLE − LSB
DLE − LSB
−1
VDD = 5 V
0.5
192
224
255
0
32
64
96
128
160
Digital Input Code
Figure 6.
192
224
255
DAC5573
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SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
1
1
VDD = 2.7 V
−0.5
−0.5
−1
0.5
0.5
0.25
0.25
−0.25
0
−0.25
−0.5
−0.5
0
32
Digital Input Code
96
128
160
Digital Input Code
Figure 7.
Figure 8.
ZERO-SCALE ERROR
vs TEMPERATURE
ZERO-SCALE ERROR
vs TEMPERATURE
64
96
128
160
192
224
0
255
32
64
192
224
255
4
9
VDD = 5 V
VDD = 2.7 V
CH A
6
CH D
CH C
3
CH B
Zero-Scale Error − mV
Zero-Scale Error − mV
VDD = 2.7 V
0
−1
0
Channel D
0.5
LE − LSB
0
DLE − LSB
DLE − LSB
LE − LSB
Channel C
0.5
2
CH A
CH D
0
CH C
CH B
−2
0
−40
−10
20
50
80
−40
−10
FULL-SCALE ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
−1
VDD = 2.7 V
CH B
CH A
Full-Scale Error − mV
Full-Scale Error − mV
CH D
CH C
−4
−40
80
Figure 10.
VDD = 5 V
−3
50
Figure 9.
−1
−2
20
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
−1.25
CH D
CH C
−1.5
CH A
CH B
−1.75
−2
−10
20
50
TA − Free-Air Temperature − °C
Figure 11.
80
−40
−10
20
50
80
TA − Free-Air Temperature − °C
Figure 12.
7
DAC5573
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SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
SINK CURRENT CAPABILITY
AT NEGATIVE RAIL
SOURCE CURRENT CAPABILITY
AT POSITIVE RAIL
0.150
5.50
Typical For All Channels
0.125
0.100
VOUT − Output Voltage − V
VOUT − Output Voltage − V
Typical For All Channels
VDD = 2.7 V
VDD = 5.5 V
0.075
0.050
0.025
5.45
5.40
5.35
DAC Loaded With FFH
VDD = 5.5 V
DAC Loaded With 00H
0.000
5.30
0
1
2
3
4
5
0
1
ISINK − Sink Current − mA
SOURCE CURRENT CAPABILITY
AT POSITIVE RAIL
SUPPLY CURRENT
vs DIGITAL INPUT CODE
5
800
IDD − Supply Current − µA
700
2.6
2.5
2.4
DAC Loaded With FFH
VDD = 2.7 V
VDD = 5.5 V
600
500
400
VDD = 2.7 V
300
200
100
2.3
All Channels Powered, No Load
0
0
1
2
3
4
5
0
32
64
96
ISOURCE − Source Current − mA
128
160
192
224
255
5.1
5.5
Digital Input Code
Figure 15.
Figure 16.
SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT
vs SUPPLY VOLTAGE
700
700
650
600
IDD - Supply Current - µA
IDD - Supply Current - µA
4
Figure 14.
Typical For All Channels
VDD = 5.5 V
500
400
VDD = 2.7 V
300
200
100
600
550
500
450
400
350
300
250
All Channels Powered, No Load
0
All DACs Powered, No Load
200
- 40
- 10
20
50
TA - Free - Air Temperature - °C
Figure 17.
8
3
Figure 13.
2.7
VOUT − Output Voltage − V
2
ISOURCE − Source Current − mA
80
110
2.7
3.1
3.5
3.9
4.3
4.7
VDD - Supply Voltage - V
Figure 18.
DAC5573
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SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
2000
TA = 25°C
A0 Input (All Other Inputs = GND)
VDD = 5 V
1000
1500
Frequency
IDD − Supply Current − µA
1200
HISTOGRAM
OF CURRENT CONSUMPTION
800
VDD = 5.5 V
600
1000
500
400
VDD = 2.7 V
200
0
0
1
2
3
4
500 520 540 560 580 600 620 640 660 680 700 720 740
5
IDD - Current Consumption - µA
VLogic − Logic Input Voltage − V
Figure 19.
Figure 20.
HISTOGRAM
OF CURRENT CONSUMPTION
EXITING
POWER-DOWN MODE
2000
6
VOUT − Output Voltage − V
VDD = 2.7 V
Frequency
1500
1000
500
0
5
VDD = 5 V
Powerup to Code 250
4
3
2
1
0
−1
400 420 440 460 480 500 520 540 560 580 600 620
Time (2 µs/div)
IDD - Current Consumption - µA
Figure 21.
Figure 22.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
3.0
4
3
VDD = 5 V
Output Loaded with
200 pF to GND
10% to 90% FSR
2
1
0
VOUT - Output Voltage - V
VOUT - Output Voltage - V
5
2.5
2.0
1.5
VDD = 2.7 V
Output Loaded with
200 pF to GND
10% to 90% FSR
1.0
0.5
0.0
Time (25 µs/div)
Time (25 µs/div)
Figure 23.
Figure 24.
9
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SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
ABSOLUTE ERROR†
ABSOLUTE ERROR†
18
24
VDD = 5 V, TA = 25°C
VDD = 2.7 V, TA = 25°C
14
Channel A Output
Channel D Output
16
Output Error (mV)
Output Error (mV)
20
12
8
Channel C Output
Channel B Output
4
6
2
Channel B Output
−2
Channel D Output
Channel C Output
−6
0
0
32
64
96
128
160
Digital Input Code
Figure 25.
†
Channel A Output
10
192
224
255
0
32
64
96
128
160
Digital Input Code
192
224
255
Figure 26.
Absolute error is the deviation from ideal DAC characteristics. It includes affects of offset, gain, and integral
linearity.
10
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SLAS401 – NOVEMBER 2003
THEORY OF OPERATION
D/A SECTION
The architecture of the DAC5573 consists of a string DAC followed by an output buffer amplifier. Figure 27
shows a generalized block diagram of the DAC architecture.
VREFH
50 k
50 k
70 k
_
Ref+
Resistor String
Ref−
DAC Register
+
VOUT
VREFL
Figure 27. R-String DAC Architecture
The input coding to the DAC5573 is unsigned binary, which gives the ideal output voltage as:
V OUT 2VREFL (VREFH VREFL) D
256
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255.
RESISTOR STRING
The resistor string section is shown in Figure 28. It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
To Output
Amplifier
VREFH
VREFL
R
R
R
R
Figure 28. Typical Resistor String
Output Amplifier
The output buffer is a gain-of-2 noninverting amplifier, capable of generating rail-to-rail voltages on its output,
which gives an output range of 0V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND.
The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs
with a half-scale settling time of 8 µs with the output unloaded.
I2C Interface
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
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SLAS401 – NOVEMBER 2003
THEORY OF OPERATION (continued)
The DAC5573 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data
transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in
this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
H/S-mode. The DAC5573 supports 7-bit addressing; 10-bit addressing and general call address are not
supported.
F/S-Mode Protocol
•
•
•
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 29. All I2C-compatible devices
recognize a start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 30). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 31) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 29). This releases the bus and stops the communication link
with the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
H/S-Mode Protocol
•
•
•
When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
The master generates a start condition followed by a valid serial byte containing H/S master code
00001XXX. This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to
acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to
support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated
start conditions must be used to secure the bus in H/S-mode.
SDA
SDA
SCL
SCL
S
P
Start
Condition
Stop
Condition
Figure 29. START and STOP Conditions
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DAC5573
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SLAS401 – NOVEMBER 2003
THEORY OF OPERATION (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 30. Bit Transfer on the I2C Bus
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
Figure 31. Acknowledge on the I2C Bus
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
MSB
Acknowledgement
Signal From Slave
Sr
Address
R/W
SCL
S
or
Sr
START or
Repeated START
Condition
1
2
7
8
9
ACK
1
2
3-8
9
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
STOP or
Repeated START
Condition
Figure 32. Bus Protocol
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SLAS401 – NOVEMBER 2003
DAC5573 I2C Update Sequence
The DAC5573 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC5573 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I2C address selects the DAC5573. The control byte sets the operational
mode of the selected DAC5573. Once the operational mode is selected by the control byte, DAC5573 expects an
MSB byte followed by an LSB byte for data update to occur. DAC5573 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
The control byte needs not to be resent until a change in operational mode is required. The bits of the control
byte continuously determine the type of update performed. Thus, for the first update, DAC5573 requires a start
condition, a valid I2C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC5573 needs an MSB byte, and an LSB byte as long as the control command remains the same. MSB byte
contains DAC data LSB byte contains 8 don't care bits.
Using the I2C high-speed mode (fscl= 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other than
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 kSPS. Using the fast mode (fscl= 400 kHz), clock running at 400 kHz, maximum DAC update
rate is limited to 22.22 kSPS. Once a stop condition is received, DAC5573 releases the I2C bus and awaits a
new start condition.
Address Byte
MSB
1
LSB
0
0
1
1
A1
A0
R/W
The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to VDD or digital GND, or can be actively driven by
TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC5573. Up to 16 devices (DAC5573) can still be connected to the same I2C-bus.
Broadcast Address Byte
MSB
1
LSB
0
0
1
0
0
0
0
Broadcast addressing is also supported by DAC5573. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC5573 devices. DAC5573 is designed to work with other members of the
DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address,
DAC5573 responds regardless of the states of the address pins. Broadcast is supported only in write mode
(master writes to DAC5573).
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SLAS401 – NOVEMBER 2003
Control Byte
MSB
LSB
A3
A2
L1
L0
X
Sel1
Sel0
PD0
Table 1. Control Register Bit Descriptions
Bit Name
Bit Number/Description
A3
Extended address bit
A2
Extended address bit
L1
Load1 (mode select) bit
L2
Load0 (mode select) bit
Are used for selecting the update mode.
00
Store I2C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the
temporary register of a selected channel. This mode does not change the DAC output of the selected
channel.
01
Update selected DAC with I2C data. Most commonly utilized mode. The contents of MS-BYTE and
LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of
the selected channel. This mode changes the DAC output of the selected channel with the new data.
10
4-channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information)
are stored in the temporary register and in the DAC register of the selected channel. Simultaneously,
the other three channels get updated with previously stored data from the temporary register. This
mode updates all four channels together.
11
Broadcast update mode. This mode has two functions. In broadcast mode, DAC5573 responds
regardless of local address matching, and channel selection becomes irrelevant as all channels update.
This mode is intended to enable up to 64 channels simultaneous update, if used with the I2C broadcast
address (1001 0000).
Sel1
Buff Sel1 Bit
Sel0
Buff Sel0 Bit
PD0
The state of these bits must match the state of pins A3 and A2 in order for a proper
DAC5573 data update, except in broadcast update mode.
If Sel1=0
All four channels are updated with the contents of their temporary register data.
If Sel1=1
All four channels are updated with the MS-BYTE and LS-BYTE data or powerdown.
Channel select bits
00
Channel A
01
Channel B
10
Channel C
11
Channel D
Power Down Flag
0
Normal operation
1
Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2).
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SLAS401 – NOVEMBER 2003
Table 2. Control Byte
C7
C6
C5
C4
C3
C2
C1
C0
MSB7
MSB6
MSB5...
A3
A2
Load1
Load0
Don't
Care
Ch Sel 1
Ch Sel 0
PD0
MSB
(PD1)
MSB-1
MSB-2 ...LSB
(PD2)
0
0
X
0
0
0
Data
0
0
X
0
1
0
Data
Write to temporary
register B (TRB) with
data
0
0
X
1
0
0
Data
Write to temporary
register C (TRC) with
data
0
0
X
1
1
0
Data
Write to temporary
register D (TRD) with
data
0
0
X
0
1
X
0
1
X
1
0
X
1
0
X
DESCRIPTION
(Address
Select)
(A3 and A2
should correspond to the
package address, set via
pins A3 and
A2)
Write to temporary
register A (TRA) with
data
(00, 01, 10, or 11)
1
See Table 8
0
(00, 01, 10, or 11)
0
(00, 01, 10, or 11)
1
Write to TRx (selected
by C2 &C1 and load
DACx w/data
Data
See Table 8
0
(00, 01, 10, or 11)
0
See Table 8
Power-down DACx
(selected by C2 and C1)
Write to TRx (selected
by C2 &C1 w/ data and
load all DACs
Data
(00, 01, 10, or 11)
1
Write to TRx (selected
by C2 &C1
w/Powerdown Command
0
Power-down DACx
(selected by C2 and C1)
& load all DACs
Broadcast Modes (controls up to 4 devices on a single serial bus)
X
X
1
1
X
0
X
X
X
Update all DACs, all
devices with previously
stored TRx data
X
X
1
1
X
1
X
0
Data
Update all DACs, all
devices with MSB[7:0]
and LSB[7:0] data
X
X
1
1
X
1
X
1
See Table 8
0
Power-down all DACs,
all devices
Most Significant Byte
Most significant byte MSB[7:0] consists of eight most significant bits of 8-bit unsigned binary D/A conversion
data. C0=1, MSB[7], MSB[6] indicate a power-down operation as shown in Table 8.
Least Significant Byte
Least significant byte LSB[7:0] consists of the 8 don't care bits. DAC5573 updates at the falling edge of the
acknowledge signal that follows the LSB[0] bit. Therefore, the LS byte is needed for the update to occur.
Default Readback Condition
If the user initiates a readback of a specified channel without first writing data to that specified channel, the
default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.
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DAC5573
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SLAS401 – NOVEMBER 2003
LDAC Functionality
Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal
that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the
channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four
DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only
be used after the buffer's temporary registers are properly updated through software.
DAC5573 Registers
Table 3. DAC5573 Architecture Register Descriptions
REGISTER
DESCRIPTION
CTRL[7:0]
Stores 8-bit wide control byte sent by the master
MSB[7:0]
Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit power-down data.
TRA[9:0], TRB[9:0],
TRC[9:0], TRD[9:0]
10-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 8 LSBs
store data.
DRA[9:0], DRB[9:0],
DRC[9:0], DRD[9:0]
10-bit DAC registers for each channel. Two MSBs store power-down information, 8 LSBs store DAC data. An
update of this register means a DAC update with data or power down.
DAC5573 as a Slave Receiver—Standard and Fast Mode
Figure 33 shows the standard and fast mode master transmitter addressing a DAC5573 Slave Receiver with a
7-bit address.
S SLAVE ADDRESS R/W A Ctrl-Byte A MS-Byte A LS-Byte
0 (write)
A/A
P
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
From Master to DAC5573
DAC5573 I2C-SLAVE ADDRESS:
From DAC5573 to Master
MSB
A =
A =
S =
Sr =
P =
Acknowledge (SDA LOW)
Not Acknowledge (SDA HIGH)
START Condition
Repeated START Condition
STOP Condition
1
LSB
0
0
1
1
A1
A0
R/W
0 = Write to DAC5573
1 = Read from DAC5573
Factory Preset
A0 = I2C Address Pin
A1 = I2C Address Pin
Figure 33. Standard and Fast Mode: Slave Receiver
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DAC5573 as a Slave Receiver—High-Speed Mode
Figure 34 shows the high-speed mode master transmitter addressing a DAC5573 Slave Receiver with a 7-bit
address.
F/S-Mode
S
HS-Mode
HS-Master Code
A Sr Slave Address
F/S-Mode
R/W A Ctrl-Byte A MS-Byte A LS-Byte
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
0 (write)
HS-Mode Master Code:
0
0
0
1
X
X
R/W
Control Byte:
A3
LSB
A2
L1
L0
X
Sel1 Sel2 PD0
MS-Byte:
MSB
LSB
D6
D5
D4
D3
D2
D1
X
X
X
X
X
D0
LS-Byte:
MSB
X
LSB
X
D11 − D0 = Data Bits
X
A3
A2
L1
L0
Sel1
Sel0
PD0
=
=
=
=
=
=
=
Extended Address Bit
Extended Address Bit
Load1 (Mode Select) Bit
Load0 (Mode Select) Bit
Buff Sel1 (Channel) Select Bit
Buff Sel0 (Channel) Select Bit
Power Down Flag
X = Don’t Care
Figure 34. High-Speed Mode: Slave Receiver
18
HS-Mode Continues
LSB
MSB
D7
P
Sr Slave Address
MSB
0
A/A
DAC5573
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SLAS401 – NOVEMBER 2003
Master Transmitter Writing to a Slave Receiver (DAC5573) in Standard/Fast Modes
All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This
control byte specifies the operation mode of DAC5573 and determines which channel of DAC5573 is being
accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines whether the
following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC5573 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE –
HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I2C bus is
recognized (refer to the DATA INPUT MODE section of Table 4).
With (PD0-Bit = 1) the DAC5573 expects to receive 2 bytes of power-down data (refer to the POWER DOWN
MODE section of Table 4).
Table 4. Write Sequence in F/S Mode
DATA INPUT MODE
Transmitter
MSB
6
5
4
Master
Master
1
0
0
1
DAC5573
Master
A3
A2
Load 1
1
LSB
1
Comment
A1
A0
R/W
Write addressing (R/W=0)
Buff Sel 0
PD0
Control byte (PD0=0)
D1
D0
Writing data word, high byte
x
x
Writing data word, low byte
Begin sequence
Load 0
x
Buff Sel 1
DAC5573 Acknowledges
D7
D6
D5
x
x
x
D4
DAC5573
Master
2
DAC5573 Acknowledges
DAC5573
Master
3
Start
D3
D2
DAC5573 Acknowledges
x
DAC5573
x
x
DAC5573 Acknowledges
Data or Stop or Repeated Start (1)
Master
Data or done (2)
POWER DOWN MODE
Transmitter
MSB
6
5
4
Master
Master
1
0
0
DAC5573
Master
A3
A2
Load 1
PD1
PD2
0
LSB
1
1
Comment
Begin sequence
A1
Load 0
x
A0
R/W
Write addressing (R/W=0)
Buff Sel 0
PD0
Control byte (PD0 = 1)
0
0
0
Writing data word, high byte
x
x
x
Writing data word, low byte
Buff Sel 1
0
0
DAC5573 Acknowledges
x
x
x
x
x
DAC5573
DAC5573 Acknowledges
Master
Stop or Repeated Start (1)
(1)
(2)
1
DAC5573 Acknowledges
DAC5573
Master
2
DAC5573 Acknowledges
DAC5573
Master
3
Start
Done
Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.
Once DAC5573 is properly addressed and control byte is sent, HIGH-BYTE-LOW-BYTE sequences can repeat until a STOP condition
or repeated START condition is received.
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Master Transmitter Writing to a Slave Receiver (DAC5573) in HS Mode
When writing data to the DAC5573 in HS-mode, the master begins to transmit what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with
R/W = 0) after which the DAC5573 acknowledges by pulling SDA low. This address byte is usually followed by
the control byte, which is also acknowledged by the DAC5573. The LSB of the control byte (PD0-Bit) determines
if the following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC5573 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE –
HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I2C bus is recognized
(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).
With (PD0-Bit = 1) the DAC5573 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE
WRITE SEQUENCE - POWER DOWN).
Table 5. Master Transmitter Writes to Slave Receiver (DAC5573) in HS-Mode
HS MODE WRITE SEQUENCE - DATA
Transmitter
MSB
6
5
4
0
0
0
0
Master
Master
0
0
1
X
X
X
Comment
Begin sequence
1
HS mode master code
No device may acknowledge HS master code
1
A1
A0
R/W
Write addressing (R/W=0)
Buff Sel 0
PD0
Control byte (PD0=0)
D1
D0
Writing data word, MSB
x
x
Writing data word, LSB
DAC5573 acknowledges
0
0
Load 1
DAC5573
Load 0
0
Buff Sel 1
DAC5573 acknowledges
D7
D6
D5
x
x
x
D4
DAC5573
Master
LSB
Repeated start
1
DAC5573
Master
1
Not acknowledge
Master
Master
2
Start
NONE
Master
3
D3
D2
DAC5573 acknowledges
x
DAC5573
x
x
DAC5573 acknowledges
Data or stop or repeated start (1)
Master
Data or done
(2)
HS MODE WRITE SEQUENCE - POWER DOWN
Transmitter
MSB
6
5
4
Master
Master
3
0
0
0
0
Not acknowledge
Master
Repeated start
1
0
0
DAC5573
Master
0
0
Load 1
PD1
PD2
0
1
X
1
A1
Load 2
0
X
HS mode master code
A0
R/W
Write addressing (R/W = 0)
Buff Sel 0
PD0
Control byte (PD0=1)
0
0
0
Writing data word, high byte
x
x
x
Writing data word, low byte
Buff Sel 1
0
0
DAC5573 acknowledges
x
x
x
x
x
DAC5573 acknowledges
Master
Stop or repeated start (1)
20
X
No device may acknowledge HS master code
DAC5573
(1)
(2)
Comment
DAC5573 acknowledges
DAC5573
Master
LSB
DAC5573 acknowledges
DAC5573
Master
1
Begin sequence
1
NONE
Master
2
Start
Done
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
Once DAC5573 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start
condition is received.
DAC5573
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SLAS401 – NOVEMBER 2003
DAC5573 as a Slave Transmitter—Standard and Fast Mode
Figure 35 shows the standard and fast mode master receiver addressing a DAC5573 Slave Transmitter with a
7-bit address.
(DAC5573)
(DAC5573)
(MASTER)
(DAC5573)
S SLAVE ADDRESS R/W A Ctrl <7:1> PD0 A Sr Slave Address
R/W A MS-Byte A LS-Byte A P
1 (read)
0 (write)
0 = (Normal Mode)
Data Transferred
(2 Bytes + Acknowledge)
(DAC5573)
PD0 A Sr Slave Address
1 = (Power Down Flag)
(MASTER)
R/W A PDN-Byte A
(MASTER)
(MASTER)
MS-Byte A LS-Byte A P
Data Transferred
(3 Bytes + Acknowledge)
1 (read)
PDN-Byte:
MSB
(MASTER)
LSB
PD1 PD2
1
1
1
1
1
1
PD1 = Power Down Bit
PD2 = Power Down Bit
Figure 35. Standard and Fast Mode: Slave Transmitter
DAC5573 as a Slave Transmitter—High-Speed Mode
Figure 36 shows an I2C-Master addressing DAC5573 in high-speed mode (with a 7-bit address), as a Slave
Transmitter.
F/S-Mode
HS-Master Code
S
A
HS-Mode
(DAC5573)
Sr
Slave Address
(DAC5573)
R/W A Ctrl <7:1> PD0 A
Sr
(DAC5573)
Slave Address
0 = (Normal Mode)
Data Transferred
(2 Bytes + Acknowledge)
(DAC5573)
PD0 A Sr Slave Address
1 = (Power Down Flag)
(MASTER)
R/W A MS-Byte A LS-Byte A P
1 (read)
0 (write)
(MASTER)
(MASTER)
R/W A PDN-Byte A
1 (read)
(MASTER)
(MASTER)
MS-Byte A LS-Byte A P
Data Transferred
(3 Bytes + Acknowledge)
Figure 36. High-Speed Mode: Slave Transmitter
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Master Receiver Reading From a Slave Transmitter (DAC5573) in Standard/Fast Modes
When reading data back from the DAC5573, the user begins with an address byte (with R/W = 0) after which the
DAC5573 acknowledges by pulling SDA low. This address byte is usually followed by the control byte, which is
also acknowledged by the DAC5573. Following this there is a REPEATED START condition by the master and
the address is resent with (R/W = 1). This is acknowledged by the DAC5573, indicating that it is prepared to
transmit data. Two or three bytes of data are then read back from the DAC5573, depending on the (PD0-Bit).
The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP condition follows.
With the (PD0-Bit = 0) the DAC5573 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to
Table 6. Data Readback Mode - 2 bytes).
With the (PD0-Bit = 1) the DAC5573 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 6. Data Readback Mode - 3 bytes).
Table 6. Read Sequence in F/S Mode
DATA READBACK MODE - 2 BYTES
Transmitter
MSB
6
5
4
1
0
0
1
3
Master
Master
A3
A2
Load 1
Comment
A0
R/W
Write addressing (R/W=0)
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=0)
A1
A0
R/W
Read addressing (R/W = 1)
D2
D1
D0
Reading data word, high byte
x
x
x
Reading data word, low byte
Begin sequence
x
DAC5573 acknowledges
Repeated start
1
0
0
D7
D6
D5
DAC5573
1
1
DAC5573 acknowledges
Master
DAC5573
A1
1
Load 0
Master
DAC5573
LSB
DAC5573 acknowledges
DAC5573
Master
1
Start
DAC5573
Master
2
D4
D3
Master acknowledges
x
x
x
x
x
Master
Master not acknowledges
Master
Stop or repeated start (1)
Master signal end of read
Done
DATA READBACK MODE - 3 BYTES
Transmitter
MSB
6
5
4
3
Master
Master
1
0
0
1
A3
A2
Load 1
Load 0
DAC5573
Master
0
0
A1
A0
R/W
Write addressing (R/W=0)
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=1)
A1
A0
R/W
Read addressing (R/W = 1)
1
1
1
D2
D1
D0
Reading data word, high byte
x
x
x
Reading data word, low byte
Begin sequence
1
x
1
1
DAC5573 acknowledges
PD1
PD2
1
D7
D6
D5
Master
1
1
D4
D3
Master acknowledges
x
x
x
x
x
Master
Master not acknowledges
Master
Stop or repeated start (1)
(1)
22
Read power down byte
Master acknowledges
Master
DAC5573
Comment
Repeated start
1
DAC5573
DAC5573
LSB
DAC5573 acknowledges
Master
DAC5573
1
DAC5573 acknowledges
DAC5573
Master
2
Start
Master signal end of read
Done
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
DAC5573
www.ti.com
SLAS401 – NOVEMBER 2003
Master Receiver Reading From a Slave Transmitter (DAC5573) in HS-Mode
When reading data to the DAC5573 in HS-MODE, the master begins to transmit, what is called the HS-Master
Code (0000 1XXX) in F/S mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The master then switches to HS mode and issues a REPEATED START condition, followed by the address byte
(with R/W = 0) after which the DAC5573 acknowledges by pulling SDA low. This address byte is usually followed
by the control byte, which is also acknowledged by the DAC5573.
Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1).
This is acknowledged by the DAC5573, indicating that it is prepared to transmit data. Two or three bytes of data
are then read back from the DAC5573, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0
determines, which channel data is read back. A STOP condition follows.
With the (PD0-Bit = 0) the DAC5573 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to
Table 7 HS-Mode Readback Sequence).
With the (PD0-Bit = 1) the DAC5573 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence).
Table 7. Master Receiver Reading Slave Transmitter (DAC5573) in HS-Mode
HS MODE READBACK SEQUENCE
Transmitter
MSB
6
5
4
0
0
0
0
3
Master
Master
LSB
Comment
X
X
X
HS mode master code
Begin sequence
1
No device may acknowledge HS
master code
Not acknowledge
Master
Repeated start
1
0
0
DAC5573
Master
1
Start
NONE
Master
2
1
1
A1
A3
A2
Load 1
Load 0
X
Buff Sel 1
DAC5573
DAC5573 acknowledges
Master
Repeated start
Master
1
0
0
DAC5573
DAC5573
PD1
PD2
1
Write addressing (R/W=0)
Buff Sel 0
PD0
Control byte (PD0 = 1)
1
1
A1
A0
R/W
Read addressing (R/W=1)
1
1
1
1
1
Power-down byte
D1
D0
Reading data word, high byte
x
x
Reading data word, low byte
Master acknowledges
D7
D6
D5
Master
DAC5573
R/W
DAC5573 acknowledges
Master
DAC5573
A0
DAC5573 acknowledges
D4
D3
D2
Master acknowledges
x
x
x
x
x
x
Master
Master not acknowledges
Master signal end of read
Master
Stop or repeated start
Done
Power-On Reset
The DAC5573 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC
while it is in the process of powering up. Device pins must not be brought high before supply is applied.
Power-Down Modes
The DAC5573 contains four separate power-down modes of operation. The modes are programmable via two
most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits
corresponds to the mode of operation of the device.
23
DAC5573
www.ti.com
SLAS401 – NOVEMBER 2003
Table 8. Power-Down Modes of Operation for the DAC5573
CTRL[0]
MSB[7]
MSB[6]
OPERATING MODE
1
0
0
PWD, high impedance DAC output
1
0
1
PWD, 1 kΩ to GND DAC ouptut
1
1
0
PWD, 100 kΩ to GND DAC output
1
1
1
PWD, high impedance DAC output
When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per
channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only
does the supply current fall but also the output stage is also internally switched from the output of the amplifier to
a resistor network of known values. This has the advantage that the output impedance of the device is known
while in power-down mode. There are three different options: The output is connected internally to GND through
a 1 kΩ resistor, a 100 kΩ resistor or left open-circuit (high impedance). The output stage is illustrated in
Figure 37.
Amplifier
Resistor
String DAC
VOUT
Powerdown
Circuitry
Resistor
Network
Figure 37. Output Stage During Power Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power down is typically 2.5 µs for VDD = 5 V and 5
µs for VDD = 3 V. (See the Typical Curves section for additional information.)
The DAC5573 offers a flexible power-down interface based on channel register operation. A channel consists of
a single 8-bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR and
DR are both 10 bits wide. Two MSBs represent the power-down condition and the 8 LSBs represent data for TR
and DR. By using bits 9 and 8 of TR and DR, a power-down condition can be temporarily stored and used just
like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[9] and TR[8] (DR[9] and DR[8])
when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC5573 treats power-down conditions like data
and all the operational modes are still valid for power down. It is possible to broadcast a power-down condition to
all the DAC5573s in the system, or it is possible to simultaneously power down a channel while updating data on
other channels.
CURRENT CONSUMPTION
The DAC5573 typically consumes 150 µA at VDD = 5 V and 125 µA at VDD = 3 V for each active channel,
including reference current consumption. Additional current consumption can occur at the digital inputs if VIH <<
VDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In
power-down mode, typical current consumption is 200 nA.
24
DAC5573
www.ti.com
SLAS401 – NOVEMBER 2003
IOVDD AND VOLTAGE TRANSLATORS
IOVDD pin powers the digital input structures of the DAC5573. For single-supply operation, IOVDD can be tied to
VDD. For dual-supply operation, the IOVDD pin provides interface flexibility with various CMOS logic families—connect it to the logic supply of the system. Analog circuits and internal logic of the DAC5573 use VDD as
the supply voltage. The external logic high inputs get translated to VDD by level shifters. These level shifters use
the IOVDD voltage as a reference to shift the incoming logic HIGH levels to VDD. IOVDD operates from 2.7 V to 5.5
V regardless of the VDD voltage, ensuring compatibility with various logic families. Although specified down to 2.7
V, IOVDD operates as low as 1.8 V with degraded timing and temperature performance. For lowest power
consumption, ensure that logic VIH levels are as close as possible to IOVDD, and logic VIL levels as close as
possible to GND voltages.
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC5573 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC5573 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2
kΩ can be driven by the DAC5573 while achieving a good load regulation. When the outputs of the DAC are
driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter
into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the
DAC. This only occurs within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer
characteristic. The reference voltage applied to the DAC5573 may be reduced below the supply voltage applied
to VDD in order to eliminate this condition if good linearity is a requirement at full scale (under resistive loading
conditions).
CROSSTALK
The DAC5573 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.0025 LSBs. The ac crosstalk measured (for a full-scale, 1-kHz sine wave output generated
at one channel, and measured at the remaining output channel) is typically under –100 dB.
OUTPUT VOLTAGE STABILITY
The DAC5573 exhibits excellent temperature stability of ±3 ppm/°C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a ±25-µV window
for a ±1°C ambient temperature change. Combined with good dc noise performance and true 8-Bit differential
linearity, the DAC5573 becomes a perfect choice for closed-loop control applications.
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
Settling time to within the 8-bit accurate range of the DAC5573 is achievable within 6 µs for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The
high-speed serial interface of the DAC5573 is designed in order to support up to 188-ksps update rate. For
full-scale output swings, the output stage of each DAC5573 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 µV) given that the code-to-code transition does not cross an Nx16 code boundary. Due to internal
segmentation of the DAC5573, code-to-code glitches occur at each crossing of an Nx16 code boundary. These
glitches can approach 100 mVs for N = 15, but settle out within ~2 µs.
25
DAC5573
www.ti.com
SLAS401 – NOVEMBER 2003
APPLICATION INFORMATION
The following sections give example circuits and tips for using the DAC5573 in various applications. For more
information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com.
BASIC CONNNECTIONS
For many applications, connecting the DAC5573 is extremely simple. A basic connection diagram for the
DAC5573 is shown in Figure 38. The 0.1 µF bypass capacitors provide the momentary bursts of extra current
needed from the supplies.
DAC5573
I2C Pullup Resistors
1 kΩ to 10 kΩ (typical)
Microcontroller or
Microprocessor With
I2C Port
IOVDD
1 VOUTA
A3 16
2 VOUTB
A2 15
3 VREFH
A1 14
4 VDD
A0 13
5 VREFL
IOVDD 12
6 GND
SDA 11
7 VOUTC
SCL 10
8 VOUTD
LDAC 9
SCL
SDA
NOTE: DAC5573 power and input/output connections are omitted for clarity, except IC Inputs.
Figure 38. Typical DAC5573 Connections
The DAC5573 interfaces directly to standard mode, fast mode and high-speed mode I2C controllers. Any
microcontroller's I2C peripheral, including master-only and non-multiple-master I2C peripherals, work with the
DAC5573. The DAC5573 does not perform clock-stretching (i.e., it never pulls the clock line low), so it is not
necessary to provide for this unless other devices are on the same I2C bus.
Pullup resistors are necessary on both the SDA and SCL lines because I2C bus drivers are open-drain. The size
of the these resistors depend on the bus operating speed and capacitance on the bus lines. Higher-value
resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value
resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher
capacitance and require smaller pullup resistors to compensate. If the pullup resistors are too small the bus
drivers may not be able to pull the bus line low.
USING GPIO PORTS FOR I2C
Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or
outputs. If an I2C controller is not available, the DAC5573 can be connected to GPIO pins, and the I2C bus
protocol simulated, or bit-banged, in software. An example of this for a single DAC5573 is shown in Figure 39.
26
DAC5573
www.ti.com
SLAS401 – NOVEMBER 2003
APPLICATION INFORMATION (continued)
DAC5573
IOVDD
1 VOUTA
A3 16
2 VOUTB
A2 15
3 VREFH
A1 14
4 VDD
A0 13
5 VREFL
Microcontroller or
Microprocessor
IOVDD 12
6 GND
SDA 11
7 VOUTC
SCL 10
8 VOUTD
LDAC 9
GPIO-1
GPIO-2
NOTE: DAC5573 power and input/output connections are omitted for clarity, except IC Inputs.
Figure 39. Using GPIO With a Single DAC5573
Bit-banging I2C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and
output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line
go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is
pulling the line low, this reads as a zero in the port's input register.
Note that no pullup resistor is shown on the SCL line. In this simple case the resistor is not needed. The
microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this
because the DAC5573 never drives its clock line low. This technique can also be used with multiple devices, and
has the advantage of lower current consumption due to the absence of a resistive pullup.
If there are any devices on the bus that may drive their clock lines low, do not use the above method. The SCL
line must be high-Z or zero, and a pullup resistor must be provided as usual. Note also that this cannot be done
on the SDA line in any case, because the DAC5573 drives the SDA line low from time to time, as all I2C devices
do.
Some microcontrollers have selectable strong pullup circuits built in to their GPIO ports. In some cases, these
can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some
microcontrollers, but usually these are too weak for I2C communication. Test any circuit before committing it to
production.
USING REF02 AS A POWER SUPPLY FOR DAC5573
Due to the extremely low supply current required by the DAC5573, a possible configuration is to use a REF02
+5-V precision voltage reference to supply the required voltage to the DAC5573 supply input as well as the
reference input, as shown in Figure 40. This is especially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC5573.
If the REF02 is used, the current it needs to supply to the DAC5573 is 600 µA typical and 900 µA max for
27
DAC5573
www.ti.com
SLAS401 – NOVEMBER 2003
APPLICATION INFORMATION (continued)
VDD = 5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total
typical current required (with a 5-kΩ load on a single DAC output) is:
600 µA + (5 V / 5 kΩ) = 1.6 mA
The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 400 µV for 1.6 mA of
current drawn from it. This corresponds to a 0.02 LSB error for a 0 V to 5 V output range.
15 V
REF02
5V
1.6 mA
I2C
Interface
SCL
SDA
VDD
DAC5573
VOUT = 0 V to 5 V
Figure 40. REF02 Power Supply
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
For best performance, the power applied to VDD must be well-regulated and low noise. Switching power supplies
and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, VDD must be connected to a positive power-supply plane or trace that is separate
from the connection for digital logic until they are connected at the power-entry point. In addition, a 1-µF to 10-µF
capacitor in parallel with a 0.1-µF bypass capacitor is strongly recommended. In some situations, additional
bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and
capacitors—all designed to essentially low-pass filter the –5-V supply, removing the high-frequency noise.
28
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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