EL5421 ® Data Sheet Quad 12MHz Rail-to-Rail Input-Output Buffer The EL5421 is a quad, low power, high voltage rail-to-rail input-output buffer. Operating on supplies ranging from 5V to 15V, while consuming only 500µA per channel, the EL5421 has a bandwidth of 12MHz (-3dB). The EL5421 also provides rail-to-rail input and output ability, giving the maximum dynamic range at any supply voltage. August 2, 2007 FN7198.2 Features • 12MHz -3dB bandwidth • Unity gain buffer • Supply voltage = 4.5V to 16.5V • Low supply current (per buffer) = 500µA • High slew rate = 10V/µs • Rail-to-rail operation The EL5421 also features fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). These features make the EL5421 ideal for use as voltage reference buffers in Thin Film Transistor Liquid Crystal Displays (TFT-LCD). Other applications include battery power, portable devices and anywhere low power consumption is important. • “Mini” SO package (MSOP) The EL5421 is available in a space saving 10 Ld MSOP package and operates over a temperature range of -40°C to +85°C. • Electronics games • Pb-free plus anneal available (RoHS compliant) Applications • TFT-LCD drive circuits • Electronics notebooks • Personal communication devices • Personal digital assistants (PDA) Pinout • Portable instrumentation EL5421 (10 LD MSOP) TOP VIEW VOUTA 1 VINA 2 VS+ 3 VINB 4 • Wireless LANs • Office automation 10 VOUTD • Active filters 9 VIND • ADC/DAC buffers 8 VS- Ordering Information 7 VINC VOUTB 5 6 VOUTC PART NUMBER PART MARKING PACKAGE PKG. DWG. # EL5421CY F 10 Ld MSOP MDP0043 EL5421CY-T7* F 10 Ld MSOP MDP0043 EL5421CY-T13* F 10 Ld MSOP MDP0043 EL5421CYZ (Note) BCAAA 10 Ld MSOP (Pb-Free) MDP0043 EL5421CYZ-T7* (Note) BCAAA 10 Ld MSOP (Pb-Free) MDP0043 EL5421CYZ-T13* BCAAA (Note) 10 Ld MSOP (Pb-Free) MDP0043 *Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Elantec is a registered trademark of Elantec Semiconductor, Inc. Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5421 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS+ +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C unless otherwise specified. DESCRIPTION CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT 12 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 2 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 0V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF AV Voltage Gain -4.5V ≤ VOUT ≤ 4.5V 0.995 µV/°C 50 nA 1.005 V/V -4.85 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = 5mA 4.85 4.92 V ISC Short Circuit Current Short to GND (Note 2) ±80 ±120 mA 60 80 dB -4.92 POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V IS Supply Current (Per Buffer) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% tS Settling to +0.1% BW CS 10 V/µs VO = 2V step 500 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz Channel Separation f = 5MHz 75 dB 2 7 FN7198.2 August 2, 2007 EL5421 Electrical Specifications PARAMETER VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = +25°C unless otherwise specified. DESCRIPTION CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT 10 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 2 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 2.5V 2 RIN Input Impedance 1 GW CIN Input Capacitance 1.35 pF AV Voltage Gain 0.5 ≤ VOUT ≤ 4.5V 0.995 µV/°C 50 nA 1.005 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = 5mA 4.85 4.92 V ISC Short Circuit Current Short to GND (Note 2) ±80 ±120 mA 60 80 dB 80 POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current (Per Buffer) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) 1V ≤ VOUT ≤ 4V, 20% to 80% tS Settling to +0.1% BW CS 10 V/µs VO = 2V step 500 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz Channel Separation f = 5MHz 75 dB 3 7 FN7198.2 August 2, 2007 EL5421 Electrical Specifications PARAMETER VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = +25°C unless otherwise specified. DESCRIPTION CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT 14 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V 2 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 7.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF AV Voltage Gain 0.5 ≤ VOUT ≤ 14.5V 0.995 µV/°C 50 nA 1.005 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = 5mA ISC Short Circuit Current 80 14.85 14.92 V Short to GND (Note 2) ±80 ±120 mA 60 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current (Per Buffer) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) 1V ≤ VOUT ≤14V, 20% to 80% tS Settling to +0.1% BW CS 7 10 V/µs VO = 2V step 500 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz Channel Separation f = 5MHz 75 dB NOTES: 1. Measured over the operating temperature range 2. Limits established by characterization and are not production tested. 3. Slew rate is measured on rising and falling edges 4. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested 4 FN7198.2 August 2, 2007 EL5421 Typical Performance Curves 70 1800 VS=±5V TA=25°C TYPICAL PRODUCTION DISTRIBUTION 1400 1200 1000 800 600 400 VS=±5V 50 40 30 20 10 200 0 21 19 17 15 13 11 9 INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C) FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. INPUT OFFSET VOLTAGE DRIFT 2.0 10 VS=±5V INPUT BIAS CURRENT (nA) VS=±5V 5 0 0.0 -2.0 -5 -50 0 50 100 -50 150 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 4.97 -4.91 OUTPUT LOW VOLTAGE (V) OUTPUT HIGH VOLTAGE (V) 7 5 3 1 12 8 10 6 4 2 -0 -2 -4 -6 -8 -10 -12 0 INPUT OFFSET VOLTAGE (mV) INPUT OFFSET VOLTAGE (mV) TYPICAL PRODUCTION DISTRIBUTION 60 QUANTITY (BUFFERS) QUANTITY (BUFFERS) 1600 4.96 4.95 4.94 VS=±5V IOUT=5mA VS=±5V IOUT=-5mA -4.93 -4.94 -4.95 -4.96 -4.97 4.93 -50 -4.92 0 50 100 150 TEMPERATURE (°C) FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE 5 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE FN7198.2 August 2, 2007 EL5421 Typical Performance Curves 10.40 VS=±5V VS=±5V SLEW RATE (V/µs) VOLTAGE GAIN (V/V) 1.0005 1.0000 0.9995 10.35 10.30 10.25 -50 0 50 100 -50 150 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. VOLTAGE GAIN vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE 700 TA=25°C 0.55 SUPPLY CURRENT (µA) SUPPLY CURRENT (mA) VS=±5V 0.5 600 500 400 0.45 300 -50 0 50 100 0 150 5 5 10kΩ 1kΩ 560Ω 150Ω -10 CL=10pF VS=±5V -15 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS RL 6 20 FIGURE 10. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE MAGNITUDE (NORMALIZED) (dB) MAGNITUDE (NORMALIZED) (dB) FIGURE 9. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE -5 15 SUPPLY VOLTAGE (V) TEMPERATURE (°C) 0 10 20 RL=10kΩ VS=±5V 10 12pF 0 50pF -10 -20 -30 100K 100pF 1000pF 1M 10M 100M FREQUENCY (Hz) FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS CL FN7198.2 August 2, 2007 EL5421 Typical Performance Curves 160 MAXIMUM OUTPUT SWING (VP-P) OUTPUT IMPEDANCE (Ω) 200 TA=25°C VS=±5V 120 80 40 0 10K 100K 1M 12 10 8 6 4 2 VS=±5V TA=25°C RL=10kΩ CL=12pF DISTORTION <1% 0 10K 10M 100K 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 13. OUT PUT IMPEDANCE vs FREQUENCY FIGURE 14. MAXIMUM OUTPUT SWING vs FREQUENCY 600 80 PSRR- 60 PSRR (dB) VOLTAGE NOISE (nV/√Hz) PSRR+ 40 20 TA=25°C VS=±5V 0 100 1K 10K 100K 1M 100 10 1 100 10M 1K 10K FIGURE 15. PSRR vs FREQUENCY 100M -60 VS=±5V RL=10kΩ VIN=1VRMS -80 0.007 X-TALK (dB) THD+ N (%) 10M FIGURE 16. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 0.010 0.008 1M FREQUENCY (Hz) FREQUENCY (Hz) 0.009 100K 0.006 0.005 0.004 DUAL MEASURED CH A TO B QUAD MEASURED CH A TO D OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION -100 -120 0.003 VS=±5V RL=10kΩ VIN=220mVRMS 0.002 0.001 1K 10K 100K FREQUENCY (Hz) FIGURE 17. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 7 -140 1K 10K 100K 1M 6M FREQUENCY (Hz) FIGURE 18. CHANNEL SEPARATION vs FREQUENCY RESPONSE FN7198.2 August 2, 2007 EL5421 Typical Performance Curves 5 VS=±5V RL=10kΩ VIN=±50mV TA=25°C 70 VS=±5V RL=10kΩ CL=12pF TA=25°C 3 STEP SIZE (V) OVERSHOOT (%) 90 50 30 0.1% 1 -1 -3 0.1% 10 -5 10 100 1K 0 1V 1µs VS=±5V TA=25°C RL=10kΩ CL=12pF 400 600 800 SETTLING TIME (ns) LOAD CAPACITANCE (pF) FIGURE 19. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE 200 FIGURE 20. SETTLING TIME vs STEP SIZE 50mV 200ns VS=±5V TA=25°C RL=10kΩ CL=12pF FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE 8 FIGURE 22. SMALL SIGNAL TRANSIENT REPOSNE FN7198.2 August 2, 2007 EL5421 Pin Descriptions PIN NUMBER PIN NAME 1 VOUTA FUNCTION EQUIVALENT CIRCUIT Buffer A Output VS+ VS- GND CIRCUIT 1 2 VINA Buffer A Input VS+ VSCIRCUIT 2 3 VS+ Positive Power Supply 4 VINB Buffer B Input (Reference Circuit 1) 5 VOUTB Buffer B Output (Reference Circuit 2) 6 VOUTC Buffer C Output (Reference Circuit 2) 7 VINC Buffer C Input (Reference Circuit 1) 8 VS- 9 VIND 10 VOUTD Negative Power Supply Buffer D Input (Reference Circuit 2) Buffer D Output (Reference Circuit 1) The EL5421 unity gain buffer is fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability, and has low power consumption (500µA per buffer). These features make the EL5421 ideal for a wide range of general-purpose applications. When driving a load of 10kΩ and 12pF, the EL5421 has a -3dB bandwidth of 12MHz and exhibits 10V/µs slew rate. 5V 10µs INPUT Product Description voltage range even closer to the supply rails. Figure 23 shows the input and output waveforms for the device. Operation is from ±5V supply with a 10kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. Operating Voltage, Input, and Output The EL5421 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5421 specifications are stable over both the full supply range and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL5421 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output 9 5V VS=±5V TA=25°C VIN=10VP-P OUTPUT Applications Information FIGURE 23. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Short Circuit Current Limit The EL5421 will limit the short circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power FN7198.2 August 2, 2007 EL5421 dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±30mA. This limit is set by the design of the internal metal interconnects. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ] Output Phase Reversal The EL5421 is immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 24 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. when sourcing, and: P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ] (EQ. 3) when sinking. Where: i = 1 to 4 for quad VS = Total supply voltage 10µs 1V (EQ. 2) ISMAX = Maximum supply current per channel VOUTi = Maximum output voltage of the application ILOADi = Load current 1V FIGURE 24. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL5421 buffer, it is possible to exceed the +125°C 'absolute-maximum junction temperature' under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX P DMAX = --------------------------------------------Θ JA (EQ. 1) If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figures 25 and 26 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves shown in Figures 25 and 26. JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 0.9 POWER DISSIPATION (W) VS=±2.5V TA=25°C VIN=6VP-P 870mW 0.8 0.7 M θ JA = 0.6 11 0.5 0.4 SO 5° P1 C/ 0 W 0.3 0.2 0.1 where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE PDMAX = Maximum power dissipation in the package 10 FN7198.2 August 2, 2007 EL5421 Power Supply Bypassing and Printed Circuit Board Layout JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 0.6 486mW 0.5 0.4 θ M JA = 0.3 SO P1 20 0 6° C/ W 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE The EL5421 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the buffer. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. Unused Buffers It is recommended that any unused buffer have the input tied to the ground plane. Driving Capacitive Loads The EL5421 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. 11 FN7198.2 August 2, 2007 EL5421 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X 12 FN7198.2 August 2, 2007