Catalyst CAT28C257NA-15T 256k-bit cmos parallel eeprom Datasheet

H
EE
GEN FR
ALO
CAT28C257
256K-Bit CMOS PARALLEL EEPROM
LE
A D F R E ETM
FEATURES
■ Automatic page write operation:
■ Fast read access times: 120/150 ns
–1 to 128 Bytes in 5ms
–Page load timer
■ Low power CMOS dissipation:
–Active: 25 mA max.
–Standby: 150 µA max.
■ End of write detection:
–Toggle bit
DATA polling
–DATA
■ Simple write operation:
–On-chip address and data latches
–Self-timed write cycle with auto-clear
■ Hardware and software write protection
■ 100,000 Program/erase cycles
■ Fast write cycle time:
–5ms max
■ 100 Year data retention
■ CMOS and TTL compatible I/O
■ Commercial, industrial and automotive
temperature ranges
DESCRIPTION
The CAT28C257 is a fast, low power, 5V-only CMOS
Parallel EEPROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with autoclear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the selftimed write cycle. Additionally, the CAT28C257 features
hardware and software write protection.
The CAT28C257 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP or 32-pin PLCC packages.
BLOCK DIAGRAM
A7–A14
ADDR. BUFFER
& LATCHES
ROW
DECODER
VCC
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
128 BYTE PAGE
REGISTER
I/O BUFFERS
TIMER
A0–A6
32,768 x 8
EEPROM
ARRAY
ADDR. BUFFER
& LATCHES
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
DATA POLLING
AND
TOGGLE BIT
I/O0–I/O7
COLUMN
DECODER
1
Doc. No. 1015, Rev. D
CAT28C257
PIN CONFIGURATION
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A13
NC
VCC
WE
VCC
WE
A13
A8
A9
A11
OE
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
TOP VIEW
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O3
I/O4
I/O5
28
27
26
25
24
23
22
21
20
19
18
17
VSS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O1
I/O2
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
PLCC Package (N, G)
A7
A12
A14
DIP Package (P, L)
PIN FUNCTIONS
Pin Name
Function
Pin Name
Function
A0–A14
Address Inputs
WE
Write Enable
I/O0–I/O7
Data Inputs/Outputs
VCC
5V Supply
CE
Chip Enable
VSS
Ground
OE
Output Enable
NC
No Connect
Doc. No. 1015, Rev. D
2
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
CAT28C257
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Storage Temperature ........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ............ -2.0V to +VCC + 2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
NEND
(1)
TDR(1)
VZAP(1)
ILTH(1)(4)
Parameter
Test Method
Min
104
Max
Units
Endurance
MIL-STD-883, Test Method 1033
Data Retention
MIL-STD-883, Test Method 1008
100
Years
ESD Susceptibility MIL-STD-883, Test Method 3015
2000
Volts
100
mA
Latch-Up
JEDEC Standard 17
or
Typ
105
Cycles/Byte
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC
VCC Current (Operating, TTL)
ICCC(5)
Min
Typ
Max
CE = OE = VIL, f=6MHz
All I/O’s Open
30
mA
VCC Current (Operating, CMOS) CE = OE = VILC, f=6MHz
All I/O’s Open
25
mA
Units
ISB
VCC Current (Standby, TTL)
CE = VIH, All I/O’s Open
1
mA
ISBC(6)
VCC Current (Standby, CMOS)
CE = VIHC,
All I/O’s Open
150
µA
ILI
Input Leakage Current
VIN = GND to VCC
–10
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC,
CE = VIH
–10
10
µA
VIH(6)
High Level Input Voltage
2
VCC +0.3
V
VIL(5)
Low Level Input Voltage
–0.3
0.8
V
VOH
High Level Output Voltage
IOH = –400µA
VOL
Low Level Output Voltage
IOL = 2.1mA
VWI
Write Inhibit Voltage
2.4
V
0.4
3.5
V
V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(5) VILC = –0.3V to +0.3V.
(6) VIHC = VCC –0.3V to VCC +0.3V.
3
Doc. No. 1015, Rev. D
CAT28C257
MODE SELECTION
Mode
CE
WE
OE
Read
L
H
Byte Write (WE Controlled)
L
Byte Write (CE Controlled)
I/O
Power
L
DOUT
ACTIVE
H
DIN
ACTIVE
L
H
DIN
ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Conditions
CI/O(1)
Input/Output Capacitance
Input Capacitance
CIN
(1)
Min
Typ
Max
Units
VI/O = 0V
10
pF
VIN = 0V
6
pF
A.C. CHARACTERISTICS, Read Cycle
VCC=5V + 10%, Unless otherwise specified
28C257-12
Symbol
Parameter
Min
tRC
Read Cycle Time
120
tCE
CE Access Time
120
150
ns
tAA
Address Access Time
120
150
ns
tOE
OE Access Time
50
70
ns
(1)
Typ
28C257-15
Max
Min
Typ
Max
150
Units
ns
CE Low to Active Output
0
0
ns
tOLZ(1)
OE Low to Active Output
0
0
ns
tHZ(1)(2)
CE High to High-Z Output
50
50
ns
tOHZ(1)(2)
OE High to High-Z Output
50
50
ns
tLZ
tOH
(1)
Output Hold from Address Change
0
0
ns
Power-Up Timing
Symbol
Parameter
tPUR
Power-Up to Read
tPUW
Power-Up to Write
Min
Typ
Max
Units
100
µs
10
ms
5
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 1015, Rev. D
4
CAT28C257
A.C. CHARACTERISTICS, Write Cycle
VCC=5V±10%, unless otherwise specified
28C257-12
Symbol
Parameter
Min
Typ
28C257-15
Max
Min
Typ
Units
5
ms
tWC
Write Cycle Time
tAS
Address Setup Time
0
0
ns
tAH
Address Hold Time
50
50
ns
tCS
CE Setup Time
0
0
ns
tCH
CE Hold Time
0
0
ns
tCW(3)
CE Pulse Time
100
100
ns
tOES
OE Setup Time
0
0
ns
tOEH
OE Hold Time
0
0
ns
tWP(3)
WE Pulse Width
100
100
ns
tDS
Data Setup Time
50
50
ns
tDH
Data Hold Time
0
0
Write Inhibit Period After Power-up
5
10
5
10
ms
0.1
100
0.1
100
µs
tINIT(1)
tBLC(1)(4)
5
Max
Byte Load Cycle Time
ns
Figure 1. A.C. Testing Input/Output Waveform(2)
VCC - 0.3V
2.0 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.8 V
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
5
Doc. No. 1015, Rev. D
CAT28C257
Byte Write
DEVICE OPERATION
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Read
Data stored in the CAT28C257 is transferred to the data
bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Figure 3. Read Cycle
tRC
ADDRESS
tCE
CE
tOE
OE
VIH
tLZ
WE
tOHZ
DATA OUT
tHZ
tOH
tOLZ
HIGH-Z
DATA VALID
DATA VALID
tAA
28C256 F06
Figure 4. Byte Write Cycle [WE Controlled]
tWC
ADDRESS
tAS
tAH
tCH
tCS
CE
OE
tOES
tWP
tOEH
WE
tBLC
DATA OUT
DATA IN
HIGH-Z
DATA VALID
tDS
Doc. No. 1015, Rev. D
tDH
6
CAT28C257
Page Write
to A6 (which can be loaded in any order) during the first
and subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the falling edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within tBLC MAX.
The page write mode of the CAT28C257 (essentially an
extended BYTE WRITE mode) allows from 1 to 128
bytes of data to be programmed within a single EEPROM
write cycle. This effectively reduces the byte-write time
by a factor of 128.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that
existed in each addressed cell, and a write cycle, which
writes new data back into the cell. A page write will only
write data to the locations that were addressed and will
not rewrite the entire page.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a128 byte temporary buffer. The
page address where data is to be written, specified by
bits A7 to A14, is latched on the last falling edge of WE.
Each byte within the page is defined by address bits A0
CE Controlled]
Figure 5. Byte Write Cycle [CE
tWC
ADDRESS
tAS
tAH
tBLC
tCW
CE
tOEH
OE
tCS
tOES
tCH
WE
HIGH-Z
DATA OUT
DATA IN
DATA VALID
tDS
tDH
Figure 6. Page Mode Write Cycle
OE
CE
t BLC
t WP
WE
ADDRESS
t WC
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
7
BYTE n
BYTE n+1
BYTE n+2
Doc. No. 1015, Rev. D
CAT28C257
DATA Polling
Toggle Bit
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is
complete. Upon completion of the self-timed write cycle,
all I/O’s will output true data during a read cycle.
In addition to the DATA Polling feature of the CAT28C257,
the device offers an additional method for determining
the completion of a write cycle. While a write cycle is in
progress, reading data from the device will result in I/O6
toggling between one and zero. However, once the write
is complete, I/O6 stops toggling and valid data can be
read from the device.
Figure 7. DATA Polling
ADDRESS
CE
WE
tOEH
tOES
tOE
OE
tWC
I/O7
DIN = X
DOUT = X
DOUT = X
Figure 8. Toggle Bit
WE
CE
tOEH
tOES
tOE
OE
I/O6
(1)
(1)
tWC
Note:
(1) Beginning and ending state of I/O6 is indeterminate.
Doc. No. 1015, Rev. D
8
CAT28C257
HARDWARE DATA PROTECTION
The following is a list of hardware data protection features
that are incorporated into the CAT28C257.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
(1) VCC sense provides for write protection when VCC
falls below 3.5V min.
SOFTWARE DATA PROTECTION
The CAT28C257 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28C257 is
in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
WRITE DATA:
ADDRESS:
WRITE DATA:
ADDRESS:
WRITE DATA:
ADDRESS:
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
AA
ADDRESS:
5555
WRITE DATA:
55
ADDRESS:
2AAA
WRITE DATA:
A0
ADDRESS:
5555
SOFTWARE DATA
(12)
(1)
PROTECTION ACTIVATED
WRITE DATA:
WRITE DATA:
XX
WRITE DATA:
TO ANY ADDRESS
ADDRESS:
ADDRESS:
WRITE LAST BYTE
TO
LAST ADDRESS
W R I T E DATA :
ADDRESS:
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC
Max., after SDP activation.
9
Doc. No. 1015, Rev. D
CAT28C257
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection
on power-up in addition to the hardware protection
provided.
To allow the user the ability to program the device with
an EEPROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
DATA
ADDRESS
AA
5555
55
2AAA
tWC
A0
5555
CE
tWP
tBLC
BYTE OR
PAGE
WRITES
ENABLED
WE
Figure 12. Resetting Software Data Protection Timing
DATA
ADDRESS
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
tWC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Doc. No. 1015, Rev. D
10
CAT28C257
ORDERING INFORMATION
Prefix
Device #
CAT
28C257
Optional
Company
ID
Product
Number
Suffix
N
I
-90
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)*
Package
P: PDIP
N: PLCC
L: PDIP (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
T
Tape & Reel
Speed
12: 120ns
15: 150ns
* -40°C to +125°C is available upon request
Notes:
(1) The device used in the above example is a CAT28C257NI-90T (100,000 Cycle Endurance, PLCC, Industrial temperature, 200 ns
Access Time, Tape & Reel).
11
Doc. No. 1015, Rev. D
REVISION HISTORY
Date
Revision Comments
3/29/2004
D
04/19/04
D
Added Green packages in all areas.
Delete data sheet designation
Update Block Diagram
Update Ordering Information
Update Revision History
Update Rev Number
Copyrights, Trademarks and Patents
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
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situation where personal injury or death may occur.
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
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Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
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Publication #:
Revison:
Issue date:
1015
D
4/19/04
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