5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck Controller ADP3181 FEATURES Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±14.5 mV worst-case mV differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly VID code changes Digitally programmable output can be switched between VRM 9 (5-bit) and VRD 10 (6-bit) VID codes for ADP3181JRU. (VRD10 (6-bit) only for ADP3181JRQ) Programmable short circuit protection with programmable latch-off delay APPLICATIONS Desktop PC power supplies for next-generation Intel processors VRM modules FUNCTIONAL BLOCK DIAGRAM VCC RAMPADJ RT 28 14 13 ADP3181 UVLO SHUTDOWN AND BIAS EN 11 OSCILLATOR GND 19 CMP SET RESET EN 27 PWM1 DAC + 300mV CMP CURRENTBALANCING CIRCUIT CSREF CMP RESET 2-/3-/4-PHASE DRIVER LOGIC RESET 26 PWM2 RESET 24 PWM4 25 PWM3 DAC – 250mV CMP PWRGD 10 DELAY CROWBAR CURRENT LIMIT 23 SW1 22 SW2 21 SW3 ILIMIT 15 20 SW4 EN CURRENTLIMITING CIRCUIT DELAY 12 17 CSSUM 16 CSREF 18 CSCOMP SOFT START 8 FB COMP 9 PRECISION REFERENCE 6 1 2 3 4 5 VID4 VID3 VID2 VID1 VID0 04796-0-001 7 FBRTN CPUID VID DAC Figure 1. GENERAL DESCRIPTION The ADP3181 is a highly efficient multiphase synchronous buck-switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage. The CPUID input selects whether the DAC codes match the VRM 9 or VRD 10 specifications. It uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck-switching stages. The ADP3181 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3181 provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU. The device is specified over the commercial temperature range of 0°C to +85°C and is available in 28-lead QSOP (only VRD10 option) and TSSOP packages. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. ADP3181 TABLE OF CONTENTS Specifications..................................................................................... 3 Applications..................................................................................... 15 Test Circuits....................................................................................... 5 Setting the Clock Frequency..................................................... 15 Absolute Maximum Ratings............................................................ 6 Soft Start and Current Limit Latch-Off Delay Times............ 15 Pin Configuration and Function Descriptions............................. 7 Inductor Selection ...................................................................... 15 Typical Performance Characteristics ............................................. 8 Designing an Inductor............................................................... 16 Theory of Operation ........................................................................ 9 Output Droop Resistance.......................................................... 16 Start-Up Sequence........................................................................ 9 Inductor DCR Temperature Correction ................................. 17 Master Clock Frequency............................................................ 10 Output Offset .............................................................................. 17 Output Voltage Differential Sensing ........................................ 10 Cout Selection ............................................................................... 17 Output Current Sensing ............................................................ 10 Power MOSFETS........................................................................ 18 Active Impedance Control Mode............................................. 10 Ramp Resistor Selection............................................................ 19 Current Control Mode and Thermal Balance ........................ 10 Current Limit Setpoint .............................................................. 20 Voltage Control Mode................................................................ 11 Feedback Loop Compensation Design.................................... 20 Soft Start ...................................................................................... 12 CIN Selection and Input Current DI/DT Reduction .............. 21 Current Limit, Short Circuit, and Latch-Off Protection....... 12 Building a Switchable VR9/VR10 Design ............................... 22 Dynamic VID.............................................................................. 12 Layout and Component Placement.............................................. 23 Power Good Monitoring ........................................................... 13 General Recommendations....................................................... 23 Output Crowbar ......................................................................... 13 Outline Dimensions ....................................................................... 24 Output Enable and UVLO ........................................................ 13 Ordering Guide .......................................................................... 24 REVISION HISTORY 7/05—Rev. 0 to Rev. A Added QSOP Package................................................................ 25 Change to Ordering Guide........................................................ 25 4/04—Revision 0: Initial Version Rev. A | Page 2 of 24 ADP3181 SPECIFICATIONS VCC = 12 V, FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted. 1 Table 1. Parameter ERROR AMPLIFIER Output Voltage Range 2 Accuracy Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate Symbol VCOMP VFB ΔVFB IFB IFBRTN IO(ERR) GBW(ERR) VID INPUTS Input Low Voltage VIL(VID) Input High Voltage VIH(VID) Input Current IVID Pull-up Resistance Internal Pull-Up Voltage RVID VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 CPUID INPUT Input Low Voltage Input High Voltage VR 9 Detection Threshold Voltage Input Current Pull-Up Resistance OSCILLATOR Frequency Range2 Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common Mode Range Positioning Accuracy Output Voltage Range Output Current Conditions Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP. See Figure 3. VCC = 10 V to 14 V. FB forced to VOUT − 3%. COMP = FB. CCOMP = 10 pF. CPUID > 4.5 V. CPUID < 4.0 V. CPUID > 4.5 V. CPUID < 4.0 V. VID(X) = 0 V, CPUID > 4.5 V. VID(X) = 0 V, CPUID < 4.0 V. VIL(CPUID) VIH(CPUID) fOSC fPHASE VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA) ΔVFB Typ 0.7 −14.5 14 CPUID > 4.5 V. CPUID < 4.0 V. VID code change to FB change. VID code change to 11111 to PWM going low. ICPUID RCPUID Min 0.05 15.5 100 500 20 25 40 2.25 1.1 400 400 CPUID = 0 V. 4.0 CSSUM − CSREF. See Figure 2. CCSCOMP = 10 pF. CSSUM and CSREF. See Figure 4. ICSCOMP 40 20 60 2.5 1.25 0.25 155 1.9 −50 0 20 60 200 400 600 2.0 −3 −50 3.1 +14.5 V mV 17 140 μA μA μA MHz V/μs 0.8 0.4 V V V V μA μA kΩ V V ns ns % 70 35 2.75 1.4 0.4 4.0 4.5 3.5 V V V μA kΩ 4 245 MHz kHz kHz kHz V mV μA 2.1 +50 100 +3 +50 10 10 0 −77 0.05 −80 500 Rev. A | Page 3 of 24 Unit 2.0 0.8 0.8 4.0 TA = +25°C, RT = 250 kΩ, 4-phase. TA = +25°C, RT = 115 kΩ, 4-phase. TA = +25°C, RT = 75 kΩ, 4-phase. RT = 100 kΩ to GND. RAMPADJ − FB. Max 2.7 −83 2.7 mV nA MHz V/μs V mV V μA ADP3181 Parameter CURRENT BALANCE CIRCUIT Common Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR Output Voltage Normal Mode In Shutdown Output Current, Normal Mode Maximum Output Current2 Current Limit Threshold Voltage Current Limit Setting Ratio Delay Normal Mode Voltage Delay Overcurrent Threshold Latch-Off Delay Time Min Typ Max Unit −600 20 4 −5 30 7 ΔISW(X) SW(X) = 0 V. SW(X) = 0 V. SW(X) = 0 V. +200 40 10 +5 mV kΩ μA % VILIMIT(NM) VILIMIT(SD) IILIMIT(NM) EN > 0.8 V, RILIMIT = 250 kΩ. EN < 0.4 V, IILIMIT = −100 μA. EN > 0.8 V, RILIMIT = 250 kΩ. 2.9 3 3.1 400 V mV 125 10.4 3 1.8 1.5 145 μA μA mV 20 1 25 μA ms 0.4 VSW(X)CM RSW(X) ISW(X) 12 60 105 VCSREF – VCSCOMP, RILIMIT = 250 kΩ. VCL/IILIMIT. VDELAY(NM) VDELAY(OC) tDELAY RDELAY = 250 kΩ. RDELAY = 250 kΩ. RDELAY = 250 kΩ, CDELAY = 12 nF. 2.9 1.7 SOFT START Output Current, Soft Start Mode Soft Start Delay Time IDELAY(SS) tDELAY(SS) During start-up, delay < 2.4 V. 15 ENABLE INPUT Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High VIL(EN) VIH(EN) IIL(EN) IIH(EN) EN = 0 V. EN = 1.25 V. VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) Relative to nominal DAC output. Relative to nominal DAC output. IPWRGD(SINK) = 4 mA. −180 230 RDELAY = 250 kΩ, CDELAY = 12 nF, VID code = 011111. 1 100 SUPPLY DC Supply Current UVLO Threshold Voltage UVLO Hysteresis 2 Conditions VCL POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage 1 Symbol VCROWBAR tCROWBAR RDELAY = 250 kΩ, CDELAY = 12 nF, VID code = 011111. Relative to nominal DAC output. Relative to FBRTN. Overvoltage to PWM going low. 100 VOL(PWM) VOH(PWM) IPWM(SINK) = −400 μA. IPWM(SOURCE) = 400 μA. VUVLO VCC rising. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design, not tested in production. Rev. A | Page 4 of 24 mV/μA V V ms 10 1 25 V V μA μA −250 300 225 −320 370 400 mV mV mV 0.8 −1 230 630 3.1 1.9 ms 250 200 300 700 370 770 μs ns mV mV μs ns 250 400 500 4.0 160 5 mV V 6.5 0.7 5 6.9 0.9 10 7.3 1.1 mA V V ADP3181 TEST CIRCUITS ADP3181 12V 28 18 39kΩ ADP3181 VCC 12V CSCOMP 8 100nF 17 28 VCC FB 10kΩ CSSUM COMP 9 1kΩ CSREF 18 1.0V 19 200kΩ GND VOS = CSCOMP–1V 40 200kΩ 04796-0-005 16 CSCOMP 100nF CSSUM 17 ΔV CSREF 16 1.0V GND ΔVFB = FBΔV = 80mV – FBΔV = 0mV Figure 2. Current Sense Amplifier VOS Figure 4. Positioning Voltage ADP3181 5-BIT CODE VCC 28 2 VID3 PWM1 27 3 VID2 PWM2 26 4 VID1 PWM3 25 5 VID0 PWM4 24 6 CPUID SW1 23 7 FBRTN SW2 22 8 FB SW3 21 9 COMP SW4 20 10 PWRGD 11 EN 12 DELAY 1kΩ 1.25V VID4 + 1μF GND 19 CSCOMP 18 20kΩ 12nF 250kΩ 13 RT 14 RAMPADJ 12V 100nF 100nF CSSUM 17 CSREF 16 ILIMIT 15 250kΩ 04796-0-004 1 Figure 3. Closed-Loop Output Voltage Accuracy Rev. A | Page 5 of 24 04796-0-006 19 ADP3181 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN VID0 to VID4, CPUID, EN, DELAY, ILIMIT, CSCOMP, RT, PWM1 to PWM4, COMP SW1 to SW4 All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (θJA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating −0.3 V to 15 V −0.3 V to +0.3 V −0.3 V to 5.5 V −5 V to +25 V −0.3 V to VCC +0.3 V −65°C to +150°C 0°C to +85°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to GND. 125°C 100°C/W 300°C 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 24 ADP3181 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VID4 1 28 VCC VID3 2 27 PWM1 VID2 3 26 PWM2 VID1 4 25 PWM3 VID0 5 24 PWM4 CPUID 6 23 SW1 FBRTN 7 ADP3181 SW2 TOP VIEW 21 SW3 (Not to Scale) 20 SW4 COMP 9 22 PWRGD 10 19 GND EN 11 18 CSCOMP DELAY 12 17 CSSUM RT 13 16 CSREF RAMPADJ 14 15 ILIMIT 04796-0-011 FB 8 Figure 5. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 to 5 Mnemonic VID4 to VID0 6 CPUID 7 8 FBRTN FB 9 10 COMP PWRGD 11 12 EN DELAY 13 RT 14 RAMPADJ 15 ILIMIT 16 CSREF 17 CSSUM 18 CSCOMP 19 20 to 23 GND SW4 to SW1 24 to 27 PWM4 to PMW1 28 VCC Description Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a Logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage based on the condition of the CPUID pin (see Table 4 and Table 5). Leaving VID4 through VID0 open results in ADP3181 going into a no CPU mode, shutting off its PWM outputs. CPU DAC Code Selection Input. When this pin is pulled > 4.25 V, the internal DAC reads its inputs based on the VRM 9 VID table (see Table 4). When this pin is <4 V, the DAC reads its inputs based on the VRD 10 VID table (see Table 5) and treats CPUID as the VID5 input. (ADP3181JRQ, VRD10 only) Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no-load offset point. Error Amplifier Output and Compensation Point. Power Good Output. Open drain output that signals when the output voltage is outside of the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs. Soft Start Delay and Current Limit Latch-off Delay Setting Input. An external resistor and capacitor connected between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3181 EN input is low, or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the slope of the load line and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic-level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3110. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the ADP3181 to operate as a 2-, 3-, or 4-phase controller. Supply Voltage for the Device. Rev. A | Page 7 of 24 ADP3181 TYPICAL PERFORMANCE CHARACTERISTICS 5.3 4 5.2 SUPPLY CURRENT (mA) 3 2 1 0 50 100 150 200 RT VALUE (kΩ) 250 5.0 4.9 4.8 04796-0-003 0 5.1 4.7 04796-0-002 MASTER CLOCK FREQUENCY (MHz) TA = 25°C 4-PHASE OPERATION 4.6 300 0 0.5 1.0 1.5 2.0 2.5 3.0 OSCILLATOR FREQUENCY (MHz) 3.5 Figure 7. Supply Current vs. Oscillator Frequency Figure 6. Master Clock Frequency vs. RT Rev. A | Page 8 of 24 4.0 ADP3181 THEORY OF OPERATION The ADP3181 combines a multimode, fixed-frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC can be used in Intel’s 5-bit VRM 9 or 6-bit VRD/VRM 10 designs, depending on the setting of the CPUID pin. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system such as the inductors and MOSFETs. The multimode control of the ADP3181 ensures a stable, high performance topology for • Balancing currents and thermals between phases. • High speed response at the lowest possible switching frequency and output decoupling. • Minimizing thermal switching losses due to lower frequency operation. • Tight load line regulation and accuracy. • High current output from 4-phase operational design. • Reduced output ripple due to multiphase cancellation. • PC board layout noise immunity. • Ease of use and design due to independent component selection. • Flexibility in operation for tailoring design to low cost or high performance. The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3110. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at a time for overlapping phases. The VID DAC configuration is determined by the voltage present at the CPUID pin. If this pin is pulled up to >4.5 V, the VID DAC operates with five inputs and generates the VR 9 output voltage range, as shown in Table 4. If CPUID is <4 V, the VID DAC treats CPUID as the VID5 input of VR 10 and operates as a 6-bit DAC using the output voltage range given in Table 5. Table 4. VR 9 VID Codes for ADP3181JRU Only, CPUID >4.25 START-UP SEQUENCE Two functions are set during the start-up sequence: the number of active phases and the VID DAC configuration. The number of operational phases and their phase relationship is determined by internal circuitry that monitors the PWM outputs. Normally, the ADP3181 operates as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase operation and grounding the PWM3 and PWM4 pins programs 2-phase operation. When the ADP3181 is enabled, the controller outputs a voltage on PWM3 and PWM4 that is approximately 675 mV. An internal comparator checks each pin’s voltage versus a threshold of 300 mV. If the pin is grounded, then it is below the threshold and the phase is disabled. The output resistance of the PWM pin is approximately 5 kΩ during this detection time. Any external pull-down resistance connected to the PWM pin should not be less than 25 kΩ to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded the 5 kΩ resistance is removed and it switches between 0 V and 5 V. If the PWM output is grounded then it remains off. VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. A | Page 9 of 24 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output No CPU 1.100 V 1.125 V 1.150 V 1.175 V 1.200 V 1.225 V 1.250 V 1.275 V 1.300 V 1.325 V 1.350 V 1.375 V 1.400 V 1.425 V 1.450 V 1.475 V 1.500 V 1.525 V 1.550 V 1.575 V 1.600 V 1.625 V 1.650 V 1.675 V 1.700 V 1.725 V 1.750 V 1.775 V 1.800 V 1.825 V 1.850 V ADP3181 MASTER CLOCK FREQUENCY The clock frequency of the ADP3181 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, then divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and 4 are grounded, then divide by 2. If all phases are in use, divide by 4. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3181 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier to maintain a worst-case specification of ±14.5 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 μA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3181 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning versus load current and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method then peak current detection or sampling the current across a sense element such as the low side MOSFET. This amplifier can be configured several ways depending on the objectives of the system: • • • Output inductor ESR sensing without a thermistor for lowest cost. Output inductor ESR sensing with a thermistor for improved accuracy with tracking of inductor temperature. Sense resistors for highest accuracy measurements. The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF – CSCOMP. This difference signal is used internally to offset the VID DAC for voltage positioning and as a differential input for the current limit comparator. To provide the best accuracy for the sensing of current, the CSA has been designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors so that it can be made extremely accurate. ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the CSCOMP pin can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous implementations and allows enhanced feed-forward response. CURRENT CONTROL MODE AND THERMAL BALANCE The ADP3181 has individual inputs for each phase, which are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning described previously. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Applications section. External resistors can be placed in series with individual phases to create an intentional current imbalance, such as when one phase may have better cooling and can support higher currents. Resistors RSW1 through RSW4 (see the typical application circuit in Figure 10) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, so make sure placeholders are provided in the layout. To increase the current in any phase, make RSW for that phase larger (make RSW = 0 for the hottest phase; do not change during balancing). Increasing RSW to only 500 Ω makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first. Rev. A | Page 10 of 24 ADP3181 VOLTAGE CONTROL MODE A high gain-bandwidth voltage mode error amplifier is used for the voltage-mode control loop. The control input voltage to the positive input is set via the VID logic. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor RB and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through RB is used for setting the no-load offset voltage from the VID voltage. The no-load voltage is negative with respect to the VID DAC. The main loop compensation is incorporated in the feedback network between FB and COMP. Table 5. VR 10 VID Codes for the ADP3181, CPUID Used As a VID5 Input VID4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID2 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 VID1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 VID0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 CPUID 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output No CPU No CPU 0.8375 V 0.8500 V 0.8625 V 0.8750 V 0.8875 V 0.9000 V 0.9125 V 0.9250 V 0.9375 V 0.9500 V 0.9625 V 0.9750 V 0.9875 V 1.0000 V 1.0125 V 1.0250 V 1.0375 V 1.0500 V 1.0625 V 1.0750 V 1.0875 V 1.1000 V 1.1125 V 1.1250 V 1.1375 V 1.1500 V 1.1625 V 1.1750 V 1.1875 V 1.2000 V VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Rev. A | Page 11 of 24 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 CPUID 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output 1.2125 V 1.2250 V 1.2375 V 1.2500 V 1.2625 V 1.2750 V 1.2875 V 1.3000 V 1.3125 V 1.3250 V 1.3375 V 1.3500 V 1.3625 V 1.3750 V 1.3875 V 1.4000 V 1.4125 V 1.4250 V 1.4375 V 1.4500 V 1.4625 V 1.4750 V 1.4875 V 1.5000 V 1.5125 V 1.5250 V 1.5375 V 1.5500 V 1.5625 V 1.5750 V 1.5875 V 1.6000 V ADP3181 SOFT START The power-on ramp up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current limit latch-off time as explained in the following section. In UVLO or when EN is a logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is a logic high, the DELAY capacitor is charged up with an internal 20 μA current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft start time depends on the value of VID DAC and CDLY, with a secondary effect from RDLY. Refer to the Applications section for detailed information on setting CDLY. If either EN is taken low or VCC drops below UVLO, the delay capacitor is reset to ground to be ready for another soft start cycle. Figure 8 shows the typical start-up waveforms for the ADP3181. Figure 8. Typical Start-up Waveforms, Channel 1: PWRGD, Channel 2: CSREF, Channel 3: DELAY, Channel 4: COMP CURRENT LIMIT, SHORT CIRCUIT, AND LATCH-OFF PROTECTION The ADP3181 compares a programmable current limit setpoint to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3 V. The current through the external resistor is internally scaled to give a current limit threshold of 10.4 mV/μA. If the difference in voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. After the limit is reached, the 3 V pull-up on the DELAY pin is disconnected, and the external DELAY capacitor is discharged through the external resistor. A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1.8 V. The current limit latch-off delay time is thus set by the RC time constant discharging from 3 V to 1.8 V. The Applications section discusses the selection of CDLY and RDLY. Since the controller continues to cycle the phases during the latch-off delay time, the controller returns to normal operation if the short is removed before the 1.8 V threshold is reached. The recovery characteristic depends on the state of PWRGD. If the output voltage is within the PWRGD window, the controller resumes normal operation. However, if a short circuit has caused the output voltage to drop below the PWRGD threshold, then a soft start cycle is initiated. The latch-off function can be reset by removing and reapplying VCC to the ADP3181, or by pulling the EN pin low for a short time. To disable the short circuit latch-off function, the external resistor to ground should be left open and a high value (>1 MΩ) resistor should be connected from DELAY to VCC. This prevents the DELAY capacitor from discharging so the 1.8 V threshold is never reached. The resistor has an impact on the soft start time because the current through it adds to the internal 20 μA current source. Figure 9. Overcurrent Latch-off Waveforms. Channel 1: CSREF, Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node During start-up when the output voltage is below 200 mV, a secondary current limit is active because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 2 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. There is also an inherent per phase current limit that protects individual phases when one or more phases may stop functioning because of a faulty component. This limit is based on the maximum normal-mode COMP voltage. DYNAMIC VID The ADP3181 incorporates the ability to dynamically change the VID input while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID-on-the-fly (VID-OTF). A VID-OTF can occur under light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. Rev. A | Page 12 of 24 ADP3181 When a VID input changes state, the ADP3181 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time is to prevent a false code due to logic skew while the 5 VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 250 μs to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. OUTPUT CROWBAR POWER GOOD MONITORING Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short of the high-side MOSFET, this action current limits the input supply or blows its fuse, protecting the microprocessor from destruction. The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in the specifications above based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if all of the VID DAC inputs are high, or whenever the EN pin is pulled low. PWRGD is blanked during a VID-OTF event for a period of 250 μs to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time based on the delay ramp. The PWRGD pin is held low until the DELAY pin has reached 2.8 V. The time between when the PWRGD undervoltage threshold is reached and when the DELAY pin reaches 2.8 V provides the turn-on delay time. This time is incorporated into the soft start ramp. To ensure a 1 ms delay time on PWRGD, the soft start ramp must also be >1 ms. Refer to the Applications section for detailed information on setting CDLY. As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage has fallen below the release threshold of about 700 mV. OUTPUT ENABLE AND UVLO The VCC to the controller must be higher than the UVLO threshold and the EN pin must be higher then its logic threshold for the ADP3181 to begin switching. IF UVLO is less than the threshold or the EN pin is a logic low, the device is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3110 drivers. Because ILIMIT is grounded, this disables the drivers such that both DRVH and DRVL are grounded. This feature is important to prevent discharging of the output capacitors when the controller is shut off. If the driver outputs were not disabled, then a negative voltage could be generated on the output due to the high current discharge of the output capacitors through the inductors. Rev. A | Page 13 of 24 ADP3181 L1 470μF/16V × 6 1.6μH NICHICON PW SERIES VIN 12V + + R1 2.2Ω VIN RTN C1 C8 10nF U2 ADP3110 C6 D1 1N4148WS C9 4.7μF C10 18nF D2 1N4148WS 1 BST 2 IN 3 OD PGND 6 4 VCC DRVL 5 820μF/2.5V × 8 L2 FUJITSU RE SERIES 600nH/1.6mΩ 8mΩ ESR (EACH) Q1 IPD12N03L DRVH 8 SW 7 + + C21 C28 VCC(CORE) 0.8375V – 1.6V 65A AVG, 74A PK VCC(CORE) RTN C7 4.7μF Q3 IPD06N03L Q2 IPD06N03L R2 2.2Ω C14 18nF D3 1N4148WS C13 4.7μF C12 10nF U3 ADP3110 1 BST 2 IN 3 OD PGND 6 4 VCC DRVL 5 10μF × 23 MLCC IN SOCKET Q4 IPD12N03L DRVH 8 L3 600nH/1.6mΩ SW 7 C11 4.7μF Q6 IPD06N03L Q5 IPD06N03L R3 2.2Ω C18 18nF D4 1N4148WS C17 4.7μF C16 10nF U4 ADP3110 1 BST 2 IN 3 OD PGND 6 4 VCC DRVL 5 Q7 IPD12N03L DRVH 8 L4 600nH/1.6mΩ SW 7 C15 4.7μF Q9 IPD06N03L Q8 IPD06N03L FROM CPU CB 1.5nF CFB 33pF POWER GOOD RB 1.33kΩ CA RA 390pF 16.9kΩ ENABLE CDLY 12nF *FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION. RDLY 330kΩ RT 249kΩ RR 383kΩ U1 ADP3181 1 VID4 VCC 28 2 VID3 PWM1 27 3 VID2 PWM2 26 4 VID1 PWM3 25 5 VID0 PWM4 24 6 CPUID SW1 23 7 FBRTN SW2 22 8 FB SW3 21 9 COMP SW4 10 PWRGD GND 19 11 EN 12 DELAY CSSUM 17 13 RT CSREF 16 14 RAMPADJ RSW1 * RSW2 * RSW3 * 20 CCS2 RCS1 1.5nF 35.7kΩ RPH1 124kΩ RPH3 124kΩ RCS2 73.2kΩ RPH2 124kΩ CSCOMP 18 ILIMIT 15 CCS1 2.2nF RLIM 200kΩ Figure 10. Typical VR 10 Application Circuit Rev. A | Page 14 of 24 04796-0-008 + C20 33μF C19 1μF R4 10Ω RTH 100kΩ, 5% ADP3181 APPLICATIONS The design parameters for a typical ADP3181 CPU application are as follows: • Input voltage (VIN) = 12 V • VID setting voltage (VVID) = 1.500 V • Duty cycle (D) = 0.125 • Nominal output voltage at no load (VONL) = 1.480 V • Nominal output voltage at 65 A load (VOFL) = 1.3825 V • Static output voltage drop based on a 1.5 mΩ load line (RO) from no load to full load: (VΔ) = VONL − VOFL VΔ = 1.480 V − 1.3825 V = 97.5 mV • Maximum output current (IO) = 65 A • Number of phases (n) = 3 • Switching frequency per phase (fSW) = 330 kHz t ss = SETTING THE CLOCK FREQUENCY The ADP3181 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. With n = 3 for three phases, a clock frequency of 990 kHz sets the switching frequency of each phase, fSW, to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 6 shows that to achieve a 990 kHz oscillator frequency, the correct value for RT is 200 kΩ. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. SOFT START AND CURRENT LIMIT LATCH-OFF DELAY TIMES Because the soft start, PWRGD delay, and current limit latchoff delay functions all share the DELAY pin, these three parameters must be considered together. The first step is to set CDLY for the PWRGD delay ramp. This ramp is generated by a 20 μA internal current source. The value of RDLY has a secondorder impact on the soft start time because it sinks part of the current source to ground. However, as long as RDLY is greater than 200 kΩ, this effect is minor. The value for CDLY can be approximated using C DLY Assuming an RDLY of 250 kΩ and a desired PWRGD delay time of 1 μs, CDLY is 12 nF. The soft start delay time can then be calculated using 2.8 V − VVID − VPWRGD (UV ) ⎞ ⎛ t PWRGD ⎟× = ⎜⎜ 20 μA − ⎟ 2.8 V − V − V 2 × R DLY VID ⎝ ⎠ PWRGD (UV ) (1) where tPWRGD is the desired PWRGD delay time and VPWRGD(UV) is the undervoltage threshold for the PWRGD comparator. C DLY × VVID VVID 20 μA − 2 × RDLY (2) Once CDLY has been chosen, RDLY can be calculated for the current limit latch-off time using RDLY = 2 × t DELAY (3) C DLY If the result for RDLY is less than 200 kΩ, then a smaller soft start time should be considered by recalculating the equation for CDLY or a longer latch-off time should be used. In no case should RDLY be less than 200 kΩ. In this example, a delay time of 2 ms gives RDLY = 333 kΩ. The closest standard 5% value is 330 kΩ. Substituting 330 kΩ back into Equations 1 and 2 shows that the PWRGD delay and soft start times do not change significantly. INDUCTOR SELECTION The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs, but allows using smaller size inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger size inductors and more output capacitance for the same peak-to-peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 80% of the maximum DC current in the same inductor. Equation 3 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. Equation 4 determines the minimum inductance based on a given output ripple voltage: I RIPPLE = L= VVID (1 − D) (4) f SW × L VVID × RO × (1 − D ) × (1 − (n × D )) (5) f SW × VRIPPLE Intel recommends that the ripple voltage should not exceed 10 mV peak-to-peak at the socket. Solving Equation 4 for a 12 mV peak-to-peak output ripple voltage at the regulator’s output to allow for drops through the PCB traces yields L≥ Rev. A | Page 15 of 24 1.5 V × 1.5 mΩ × 0.875 × (1 − 0.375) 330 kHz × 12 mV = 310 nH (6) ADP3181 If the ripple voltage is less than that designed for, the inductor can be made smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling. • Coiltronics (561) 752-5000 www.coiltronics.com The smallest possible inductor should be used to minimize the number of output capacitors. A 300 nH inductor is a good choice to start, and it gives a calculated ripple current of 13.3 A, which is 61% of the full load current of 21.7 A. The inductor should not saturate at the peak current of 29 A, and should be able to handle the sum of the power dissipation caused by the average current of 22 A in the winding and the core loss. • Sumida Corporation (510) 668-0660 www.sumida.com • Vishay (402) 563-6866 www.vishay.com Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR causes excessive power losses, while too small a value leads to increased measurement error. A good rule is to have the DCR be about 1 to 1½ times the droop resistance or DC output resistance (RO). OUTPUT DROOP RESISTANCE DESIGNING AN INDUCTOR Once the inductance and DCR are known, the next step is to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to keep the accuracy of the system controlled. Using 15% for the inductance and 8% for the DCR (at room temperature) are reasonable tolerances that most manufacturers can meet. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (Kool-Mμ® from Magnetics, Inc., or Micrometals) and the gapped soft ferrite cores (3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry are closed-loop types, such as pot cores, PQ, U, and E cores, or toroids. A good compromise between price and performance are cores with a toroidal shape. There are many useful references for quickly designing a power inductor, such as • Magnetic Designer Software Intusoft (http://www.intusoft.com) • Designing Magnetic Components for High Frequency DC-DC Converters, McLyman, Kg Magnetics, ISBN 1-883107-00-08 The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request: Coilcraft (847) 639-6400 www.coilcraft.com The output current is measured by summing together the voltage across each inductor and then passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with resistors RPH(X) (summers), and RCS and CCS (filter). The output resistance of the regulator is set by these equations, where RL is the DCR of the output inductors: RO = RCS × RL RPH ( X ) (7) CCS = L RL × RCS (8) One has the flexibility of choosing either RCS or RPH(X). It is best to start with RPH(X) in the range of 100 kΩ to 200 kΩ, then solve for RCS by rearranging Equation 7. Using 100 kΩ for RPH(X) RCS = RO × RPH ( X ) RL RCS = 1.5 mΩ 1.6 mΩ × 100 kΩ = 93.8 kΩ Next, use equation 8 to solve for CCS: CCS = Selecting a Standard Inductor • The design requires that the regulator output voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to RO. 300 nH 1.6 mΩ × 93.8 kΩ = 2.0 nF The closest standard value for CCS is 1.8 nF. If the calculated value does not happen to be a standard value, then recalculate for the closest 1% resistor values for RCS and RPH(X) using the final selected value for CCS. This can be quickly calculated by multiplying the original values of RCS and RPH(X) by the ratio of the calculated CCS to the actual value used. For best accuracy, CCS should be a 5% or 10% NPO capacitor. For this example, the actual values used for RCS and RPH(X) are 104.2 kΩ and 111.1 kΩ. The closest standard 1% value for RPH(X) is 110 kΩ. RCS is used later and should not be rounded yet. Rev. A | Page 16 of 24 ADP3181 INDUCTOR DCR TEMPERATURE CORRECTION RTH = With the inductor’s DCR being used as the sense element, and copper wire being the source of the DCR, it is necessary to compensate for temperature changes of the inductor’s winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/°C. Calculate RTH = rTH × RCS, then select the closest value of thermistor available. Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 are needed (see Figure 11) to linearize the NTC and produce the desired temperature tracking. TO SWITCH NODES PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET 1 1 1 − 1 − rCS2 rCS1 k= RTH ( ACTUAL ) (10) RTH (CALCULATED ) Calculate values for RCS1 and RCS2 using the following: RCS1 = RCS × k × rCS1 TO VOUT SENSE (11) RCS2 = RCS × ((1 − k) + (k × rCS2 )) RTH RPH1 ADP3181 CSCOMP RCS1 RPH2 RPH3 RCS2 18 CCS 1.8nF CSSUM 17 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES 04796-0-009 CSREF 16 Figure 11. Temperature Compensation Circuit Values The following procedure yields values to use for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS value. 1. 2. 3. Select an NTC to be used based on type and value. Because there is no value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. OUTPUT OFFSET Intel’s specification requires that at no load the nominal output voltage of the regulator be offset to a lower value than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 12. The closest standard 1% resistor value is 1.33 kΩ. B Based on the type of NTC, find its relative resistance value at two temperatures. Temperatures that work well are 50°C and 90°C. We call these resistance values A (A is RTH(50°C)/ RTH(25°C)) and B (B is RTH(90°C)/RTH(25°C)). The NTC's relative value is always 1 at 25°C. Find the relative value of RCS required for each of these temperatures. This is based on the percentage change needed, which can be 0.39%/°C, initially. These are r1 (r1 is 1/(1+ TC × (T1 − 25))) and r2 (r2 is 1/(1 + TC × (T2 − 25))) where TC = 0.0039, T1 = 50°C, and T2 = 90°C. 4. For this example, RCS has already been calculated in the previous section to be 104.2 kΩ, so start with a thermistor value of 100 kΩ. Looking through available 0603 size thermistors, find a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these values compute rCS1 = 0.3796, rCS2 = 0.7195, and rTH = 1.0751. Solving for RTH yields 112.05 kΩ, so choose 100 kΩ, making k = 0.8925. Finally, find RCS1 and RCS2 to be 35.30 kΩ and 78.11 kΩ. Choosing the closest 1% resistor values yields 35.7 kΩ and 78.7 kΩ. Compute the relative values for RCS1, RCS2, and RTH: RCS2 = ( A − B ) × r1 × r2 − A × (1 − B ) × r2 + B × (1 − A ) × r1 (9) A × (1 − B ) × r1 − B × (1 − A ) × r2 − ( A − B ) RCS1 = (1 − A ) 1 A − 1 − rCS2 r1 − rCS2 RB = RB = B VVID − VONL I FB 1.5 V − 1.480 V 15 μA (12) = 1.33 kΩ COUT SELECTION The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Using some simple design guidelines determines what is required. These guidelines are based on having both bulk and ceramic capacitors in the system. First, select the total amount of ceramic capacitance based on the number and type of capacitor to be used. The best location for ceramics is inside the socket, with 12 to 18 of size 1,206 being the physical limit. Others can be also placed along the outer edge of the socket. Rev. A | Page 17 of 24 ADP3181 L X ≤ CZ × RO 2 Combined ceramic values of 200 μF to 300 μF made up of multiple 10 μF or 22 μF capacitors are recommended. Select the number of ceramics and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID-OTF voltage stepping of the output (voltage step VV in time tV) and a lower limit based on meeting the critical capacitance for load release for a given maximum load step IMAX: ⎛ L × I STEP ⎞ C X ( MIN ) ≥ ⎜ − CZ ⎟ ⎜ n× R ×V ⎟ VID O ⎝ ⎠ (13) ⎛ ⎛ V nKRO ⎜ × ⎜ 1 + ⎜⎜ t v VID × V L ⎜ V ⎝ ⎝ ⎛V where K = 1n ⎜⎜ ERR ⎝ VV ⎞ ⎟ ⎟ ⎠ 2 ⎞ ⎟ − 1 ⎟ − CZ ⎟ ⎠ ⎞ ⎟ ⎟ ⎠ (14) where RX is the ESR of the bulk capacitor bank. To meet the transient specification, RX cannot be greater than 3 × RO. If the CX(MIN) is larger than CX(MAX), the system does not meet the VID-OTF specification and may require the use of a smaller inductor or more phases (the switching frequency may need to be increased to keep the output ripple the same). This example uses twelve 22 μF 1206 MLC capacitors (CZ=264 μF). The VID on-the-fly step change is 12.5 mV in 5 μs. Solving for the bulk capacitance, assuming that RX = RO, and where k = 4.6, yields ⎛ 600 nH × 60 A ⎞ C X ( MIN ) ≥ ⎜ − 230 μF ⎟ = 5.92 mF ⎜ 3 × 1.3 mΩ × 1.5 V ⎟ ⎝ ⎠ C X ( MAX ) ≤ 600 nH × 250 mV 3 × 4.62 × 1.3 mΩ2 × 1.5 V In this example, LX is 400 pH for the 10 OSCSON capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of MLC capacitors must be increased. Note that for this multimode control technique, all ceramic designs can be used as long as the conditions of Equations 11, 12, and 13 are satisfied. POWER MOSFETS C X ( MAX ) ≤ V L × V nK 2 RO2 VVID (15) L X ≤ 230 μF × 1.3 mΩ2 = 389 pH × 2 ⎛ ⎞ ⎛ 150 μs × 1.5 V × 3 × 4.6 × 1.3 mΩ ⎞ ⎜ ⎟ ⎟ ⎜ − 1 ⎟ − 230 μ F ⎜ 1+ ⎜ ⎟ 450 mV × 320 nH ⎜ ⎟ ⎠ ⎝ ⎝ ⎠ = 23.9 mF Using ten 560 μF OSCONs with an ESR of 12 mΩ each yields CX = 5.6 mF with an RX = 1.2 mΩ (making the new limits on CX 2.4 mF to 8.8 mF, which is still within the acceptable range). One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the initial high frequency transient spike. This can be tested using For this example, the N channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3110) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current IO determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. In the ADP3181, currents are balanced between phases, so the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO). ⎡⎛ I PSF = (1 − D ) × ⎢⎜⎜ O ⎢⎣⎝ nSF 2 ⎞ 1 ⎛ n × IR ⎞ ⎟ ⎟ + ×⎜ ⎟ 12 ⎜ n ⎟ ⎝ SF ⎠ ⎠ 2 ⎤ ⎥ × RDS (SF ) ⎥⎦ (16) Knowing the maximum output current being designed for and the maximum allowed power dissipation, the required RDS(ON) for the MOSFET can be found. For D pak MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W (assuming 2 D paks) at 120°C junction temperature. Thus, for this example (65 A maximum), RDS(SF) (per MOSFET) < 8.7 mW. This RDS(SF) is also at a junction temperature of about 120°C, so it is important to account for this when making this selection. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3110). The output impedance of the driver is about 2 Ω and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω, so a total gate capacitance of less than 6,000 pF should be adhered to. Since there are two Rev. A | Page 18 of 24 ADP3181 ⎤ ⎡ f PDRV = ⎢ SW × (nMF × QGMF + nSF × QGSF ) + ICC ⎥ × VCC (19) ⎥⎦ ⎢⎣ 2 × n MOSFETs in parallel, limit the input capacitance for each synchronous MOSFET to 3,000 pF. The high-side (main) MOSFET must be able to handle two main power dissipation components; conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs: PS ( MF ) = 2 × f SW × VCC × IO nMF × RO × nMF × CISS n (17) Here, RG is the total gate resistance (2 Ω for the ADP3110 and about 1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω) and CISS is the input capacitance of the main MOSFET. It is interesting to note that adding more main MOSFETs (nMF) does not improve the switching loss per MOSFET because the additional gate capacitance slows down switching. The best method to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on-resistance of the MOSFET: ⎡⎛ I PC ( MF ) = D × ⎢⎜⎜ O ⎢⎣⎝ nMF 2 ⎞ 1 ⎛ n × IR ⎞ ⎟ + ×⎜ ⎟ ⎟ 12 ⎜ n ⎟ ⎠ ⎝ MF ⎠ 2 ⎤ ⎥ × RDS ( MF ) ⎥⎦ (18) Typically, for main MOSFETs, the highest speed (low CISS) device is desirable, but these usually have higher on-resistance. A device that meets the total power dissipation (about 1.5 W for a single D pak) when combining the switching and conduction losses should be selected. For this example, an Infineon IPD12N03L was selected as the main MOSFET (three total; nMF = 3), with a CISS = 1460 pF (max) and RDS(MF) = 14 mΩ (max at TJ = 120ºC), and an Infineon IPD06N03L was selected as the synchronous MOSFET (six total; nSF = 6), with CISS = 2,370 pF (max), and RDS(SF) = 8.3 mΩ (max at TJ = 120°C). The synchronous MOSFET CISS is less than 3,000°pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 65 A and IR = 13 A yields 900 mW for each synchronous MOSFET and 1.6 W for each main MOSFET. These numbers work well considering there is usually more PCB area available for each main MOSFET versus each synchronous MOSFET. Also shown is the standby dissipation factor (ICC × VCC) for the driver. For the ADP3110, the maximum dissipation should be less than 400 mW. For our example, with ICC = 7 mA, QGMF = 22.8 nC and QGSF = 34.3 nC, there is 260 mW in each driver, which is below the 400 mW dissipation limit. RAMP RESISTOR SELECTION The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value: RR = AR × L 3 × AD × RDS × CR (20) RR = 0.2 × 600 nH 3 × 5 × 4.2 mΩ × 5 pF = 381 kΩ where AR is the internal ramp amplifier gain AD is the current balancing amplifier gain RDS is the total low-side MOSFET on-resistance CR is the internal ramp capacitor value The closest standard 1% resistor value is 226 kΩ. The internal ramp voltage magnitude can be calculated using VR = AR × (1 − D ) × VVID RR × C R × f SW (21) VR = 0.2 × (1 − 0.125) × 1.5 V 383 kΩ × 5 pF × 267 kHz = 0.51 mV The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves at the sacrifice of transient response and stability. The factor of three in the denominator of equation 20 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. One last thing to consider is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following, where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET: Rev. A | Page 19 of 24 ADP3181 CURRENT LIMIT SETPOINT FEEDBACK LOOP COMPENSATION DESIGN To select the current limit setpoint, we need to find the resistor value for RLIM. The current limit threshold for the ADP3181 is set with a 3 V source (VLIM) across RLIM with a gain of 10 mV/μA (ALIM). RLIM can be found using the following: Optimized compensation of the ADP3181 allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including DC, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output decoupling. RLIM = ALIM × VLIM (22) I LIM × RO Here, ILIM is the average current limit for the output of the supply. For our example, using 90 A for ILIM, we find RLIM to be 222.2 kΩ, for which we chose 221 kΩ as the nearest 1% value. The per phase current limit described earlier has its limit determined by the following: I PHLIM ≅ VCOMP ( MAX ) − VR − VBIAS AD × RDS ( MAX ) + IR 2 (23) With the multimode feedback structure of the ADP3181, one needs to set the feedback compensation to make the converter’s output impedance working in parallel with the output decoupling meet this goal. There are several poles and zeros created by the output inductor and decoupling capacitors (output filter) that need to be compensated for. For the ADP3181, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the current balancing amplifier gain (AD) is 5. Using a VR of 0.7 V and a RDS(MAX) of 5.3 mΩ (low-side on-resistance at 150°C), the per-phase limit is 52 A. A type three compensator on the voltage feedback is adequate for proper compensation of the output filter. The expressions given below are intended to yield an optimal starting point for the design; some minor adjustments may be necessary to account for PCB and component parasitic effects. This limit can be adjusted by changing the ramp voltage, VR. Make sure not to set the per-phase limit lower than the average per-phase current (ILIM/n). Using Equations 24 to 28, compute the time constants for all of the poles and zeros in the system, where, for the ADP3181, R is the PCB resistance from the bulk capacitors to the ceramics and RDS is approximately the total low-side MOSFET on-resistance per phase at 25°C. For this example, AD is 5, VR equals 1 V, R´ is approximately 0.6 mΩ (assuming a 4-layer motherboard), and LX is 400 pH for the 10 OSCSON capacitors. R E = n × RO + AD × RDS + RL × VRT VVID RE = 3 × 1.3 mΩ+ 5 × 4.2 mΩ+ TA = C X × (RO − R' ) + + 2 × L × (1 − n × D ) × VRT (24) n × C X × RO × VVID 1.6 mΩ × 0.63 V 1.5 V + 2 × 600 nH × (1 − 0.375) × 0.63 V 3 × 6.56 mF × 1.3 mΩ × 1.5 V = 37.9 mΩ 375 pH 1.3 mΩ− 0.6 mΩ LX RO − R' × = 6.56 mF × (1.3 mΩ− 0.6 mΩ ) + × = 4.79 μs RO RX 1.3 mΩ 1.0 mΩ TB = (RX + R'− RO ) × C X = (1.0 mΩ + 0.6 mΩ − 1.3 mΩ ) × 6.56 mF = 1.97 ns (26) ⎛ ⎛ A × RDS ⎞ 5 × 4.2 mΩ ⎞ ⎟ ⎟ 0.63 V × ⎜ 600 nH − VRT × ⎜ L − D ⎜ ⎜ ⎟ f 2 2 × 267 kHz ⎟⎠ × SW ⎠ ⎝ ⎝ TC = = 6.2 μs = VVID × RE 1.5 V × 37.9 mΩ TD = C X × CZ × RO2 C X × (RO − R' ) + C Z × RO = 6.56 mF × 230 μF × 1.3 mΩ2 6.56 mF × (1.3 mΩ− 0.6 mΩ ) + 230 μF × 1.3 mΩ The compensation values can be solved using the following: Rev. A | Page 20 of 24 (25) (27) = 521 ns (28) ADP3181 CA = n × RO × TA CIN SELECTION AND INPUT CURRENT DI/DT REDUCTION RE × R B (29) CA = 3 × 1.3 mΩ × 4.79 μs 3.79 mΩ × 1.33 kΩ = 371 pF RA = 6.2 μs TC = = 16.7 kΩ C A 371 pF (30) CB = TB 1.97μs = = 1.48 nF RB 1.33 kΩ (31) CFB T 521 ns = D = = 31.2 pF RA 16.7 kΩ I CRMS = D × IO × 1 N×D (33) (32) Choosing the closest standard values for these components yields CA = 820 pF, RA = 7.87 kΩ, CB = 1.2 nF, and CFB = 100 pF. These make a good starting point. Using the design spreadsheet yields more optimal compensation values; from the spreadsheet, CA = 680 pF, RA = 5.49 kΩ, CB = 1.2 nF, and CFB = 68 pF. B In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n × VOUT/VIN and an amplitude of one-nth of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by I CRMS = 0.125 × 65 A × 1 − 1 = 10.5 A 3 × 0.125 Note that the capacitor manufacturer’s ripple current ratings are often based on only 2,000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by three 2,200 μF, 16 V Nichicon capacitors with a ripple current rating of 3.5 A each. To reduce the input-current di/dt to below the recommended maximum of 0.1 A/μs, an additional small inductor (L > 1 μH @ 15 A) should be inserted between the converter and the supply bus. That inductor also acts as a filter between the converter and the primary power source. Rev. A | Page 21 of 24 ADP3181 BUILDING A SWITCHABLE VR9/VR10 DESIGN To determine the values of x and y, start with the two load lines, ROL (smaller slope) and ROH (larger slope). First, follow the standard design procedure, which gives the values for RCS1, RCS2, and CCS for ROL. Tune RPH and CCS. Next, compute the values for RCS3 and CCS3 using the following: Some designs may require the ability to work with either a VR9or a VR10-based CPU, because both processors are available in the same package/pin count. To accomplish this, the voltage regulator must detect which processor is present and set the VID DAC and load line accordingly. This can be accomplished using the BOOTSELECT output from the CPU. Figure 12 shows how this signal is used to modify the load line and set the CPUID pin of the ADP3181 appropriately. ⎞ ⎛R RCS 3 = ⎜⎜ OH − 1⎟⎟ × RCS ⎠ ⎝ ROL CCS 3 = (34) CCS ⎞ ⎛ ROH ⎟ ⎜ ⎜ R − 1⎟ ⎠ ⎝ OL (35) In this case, ROL is 1.5 mΩ and ROH is 3 mΩ. TO PHASE INDUCTORS RTH 100kΩ, 5% SW1 23 SW2 22 SW3 21 ADP3181 RPH1 124kΩ RPH3 124kΩ SW4 20 GND 19 CCS2 RCS1 1.5nF 35.7kΩ RCS2 73.2kΩ RPH2 124kΩ CSCOMP 18 RCS3 CSSUM 17 CSREF 16 CCS1 2.2nF ILIMIT 15 CCS3 5VSB 100nF 2N7001 2.7kΩ 2N3905 10kΩ CPU NWD HI 100nF CPU PSC HI BOOTSELECT 10kΩ 100nF BSS84 51Ω 2N3904 TO APD3181 CPUID (PIN 6) Figure 12. Connections to Allow Automatic Switching between VR9 and VR10 Operation Rev. A | Page 22 of 24 04796-0-010 10kΩ ADP3181 LAYOUT AND COMPONENT PLACEMENT Power Circuitry The following guidelines are recommended for optimal performance of a switching regulator in a PC system. GENERAL RECOMMENDATIONS For good results, at least a 4-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input, and output power, and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 mW at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths are minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3181) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3181 for referencing the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not tie to any other power circuitry to prevent power currents from flowing in it. The components around the ADP3181 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins. See Figure 6 for details on layout for the CSSUM node. The output capacitors should be connected as closely as possible to the load (or connector) that receives the power (for example, a microprocessor core). If the load is distributed, the capacitors should also be distributed and generally in proportion to where the load is more dynamic. Avoid crossing any signal lines over the switching power path loop as described in the following section. The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path because it minimizes the inductance in the switching loop, which can cause high energy ringing. These traces also accommodate the high current demand with minimal voltage loss. Whenever a power-dissipating component (for example, a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry The output voltage is sensed and regulated between the FB pin and the FBRTN pin (which connects to the signal ground at the load). In order to avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus the FB and FBRTN traces should be routed adjacent to each other atop the power ground plane back to the controller. Connect the feedback traces from the switch nodes as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. Rev. A | Page 23 of 24 ADP3181 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 SEATING PLANE 8° 0° 0.20 0.09 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 13. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 0.390 BSC 28 15 0.154 BSC 1 14 0.236 BSC PIN 1 0.069 0.053 0.065 0.049 0.010 0.004 0.025 BSC 0.012 0.008 SEATING PLANE COPLANARITY 0.004 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137-AF Figure 14. 28-Lead Shrink Small Outline Package [QSOP] (RQ-28) Dimensions shown in inches ORDERING GUIDE Part Number ADP3181JRUZ-REEL 1 ADP3181JRQZ-RL1, 2 1 2 Temperature Package 0°C to +85°C 0°C to +85°C Package Description TSSOP—13” Reel QSOP—13” Reel Z = PB-free part. VRD10 only. ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04796–0–7/05(A) Rev. A | Page 24 of 24 Package Outline RU-28 RQ-28 Quantity per Reel 2500 2500