LM75 2-Wire Serial Temperature Sensor and Monitor The LM75 is a serially programmable temperature sensor that notifies the host controller when ambient temperature exceeds a user–programmed setpoint. Hysteresis is also programmable. The INT/CMPTR output is programmable as either a simple comparator for thermostat operation or as a temperature event interrupt. Communication with the LM75 is accomplished via a two–wire bus that is compatible with industry standard protocols. This permits reading the current temperature, programming the setpoint and hysteresis, and configuring the device. The LM75 powers up in Comparator Mode with a default setpoint of 80°C with 5°C hysteresis. Defaults allow independent operation as a stand–alone thermostat. A shutdown command may be sent via the 2–wire bus to activate the low–power standby mode. Address selection inputs allow up to eight LM75’s to share the same 2–wire bus for multi–zone monitoring. All registers can be read by the host and the INT/CMPTR output’s polarity is user programmable. Both polled and interrupt driven systems are easily accommodated. Small physical size, low installed cost, and ease of use make the LM75 an ideal choice for implementing sophisticated system management schemes. Features • Temperature Sensing: 0.5°C Accuracy (Typ.) • Operates from: 55°C to +125°C • Operating Range: 2.7V – 5.5V • Programmable Trip Point and Hysteresis with Power–up Defaults • Standard 2–Wire Serial Interface • Thermal Event Alarm Output Functions as Interrupt or Comparator / Thermostat Output • Up to 8 LM75’s May Share the Same Bus • Shutdown Mode for Low Standby Power Consumption • 5V Tolerant I/O at VDD = 3V • Low Power 250µA (Typ.) Operating, 1µA (Typ.) Shutdown Mode Typical Applications • Thermal Protection for High Performance CPUs • Solid–State Thermometer • Fire/Heat Alarms • Thermal Management in Electronic Systems: Computers Telecom Racks Power Supplies / UPS • Copiers / Office Electronics • Consumer Electronics / Amplifiers • Process Control Semiconductor Components Industries, LLC, 1999 February, 2000 – Rev. 0 1 http://onsemi.com Micro8 DM SUFFIX CASE TBD PRELIMINARY INFORMATION PIN CONFIGURATION (Top View) SDA 1 SCL 2 INT/CMPTR 3 LM75 GND 4 8 V DD 7 A0 6 A1 5 A2 ORDERING INFORMATION Device Package Shipping LM75DM–33R2 Micro–8 2500 Tape/Reel LM75DM–50R2 Micro–8 2500 Tape/Reel Publication Order Number: LM75/D LM75 FUNCTIONAL BLOCK DIAGRAM INT/ CMPTR 9 Bit DS V Temp Sensor DD Control Logic A/D Converter Register Set Configuration T SET Temperature T HYST SDA SCL A A A Two Wire Serial Port Interface 0 LM75 1 2 TIMING DIAGRAM t SC SCL t t H (START) SU (STOP) SDA Data In t DSU SDA Data Out t DH PIN DESCRIPTION ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin No. Symbol Description 1 SDA Bidirectional Serial Data 2 SCL Serial Data Clock Input 3 INT/CMPTR 4 GND 5 A2 Address Select Pin (MSB) 6 A1 Address Select Pin 7 A0 Address Select Pin (LSB) 8 VDD Interrupt or Comparator Output System Ground Power Supply Input http://onsemi.com 2 LM75 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage (VDD) ESD Susceptibility Input Voltage, On Pins: A0, A1, A2 SDA, SCL, INT/CMPTR Value Unit 6.0 V 1000 V V (GND – 0.3) to (VCC + 0.3) (GND – 0.3) to 5.5 Operating Temperature Range (TJ) –55 to +125 °C Storage Temperature Range (TSTG) –65 to +150 °C Lead Temperature Range (Soldering, 10 sec) +300 °C Thermal Resistance (Junction to Ambient) 250 °C/W * Maximum Ratings are those values beyond which damage to the device may occur. ELECTRICAL CHARACTERISTICS (Specifications Measured Over Operating Temperature Range, V+ = 5V, COSC = 0, Test Circuit (Figure 1), unless otherwise noted. Symbol Min Typ Max Supply Voltage Range, High (–40°C ≤ TA ≤ +85°C, RL = 10 kW, LV Open) 3.0 — 10 Supply Voltage Range, Low (–40°C ≤ TA ≤ +85°C, RL = 10 kW, LV to GND) 1.5 — 3.5 I+ Supply Current (RL = — 80 180 ROUT Output Source Resistance IOUT = 20mA, TA = 25°C IOUT = 20mA, 0°C ≤ TA ≤ +70°C IOUT = 20mA, –40°C ≤ TA ≤ +85°C V+ =2V, IOUT = 3 mA, LV to GND, 0°C ≤ TA ≤ +70°C — — — — 70 — — 150 100 120 130 300 Oscillator Frequency (Pin 7 Open) — 10 — kHz PEFF Power Efficiency (RL = 5kW) 95 98 — % VOUT EFF Voltage Conversion Efficiency 97 99.9 — % ZOSC Oscillator Impedance V+ = 2V V+ = 5V — — 1000 100 — — V+H V+L FOSC Characteristic Unit V V R) http://onsemi.com 3 µA W kW LM75 DETAILED OPERATING DESCRIPTION Slave Address A typical LM75 hardware connection is shown in Figure 1. The four most significant bits of the Address Byte (A6, A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the LM75 to respond with an Acknowledge (indicating the LM75 is on the bus and ready to accept data). The Slave Address is represented by: +V DD C Bypass 8 A0 Address (Set as Desired) A 1 A2 Two Wire Interface SDA SCL 7 6 5 0.1mF Recommended Unless Device is Mounted Close to CPU LM75 Slave Address 3 TCN75 1 INT/CMPTR 1 2 0 0 1 MSB A2 A1 A0 LSB 4 Comparator/Interrupt Modes INT/CMPTR behaves differently depending on whether the LM75 is in Comparator Mode or Interrupt Mode. Comparator Mode is designed for simple thermostatic operation. INT/CMPTR will go active anytime TEMP exceeds TSET. When in Comparator Mode, INT/CMPTR will remain active until TEMP falls below THYST, whereupon it will reset to its inactive state. The state of INT/CMPTR is maintained in shutdown mode when the LM75 is in comparator mode. In Interrupt Mode, INT/CMPTR will remain active indefinitely, even if TEMP falls below THYST, until any register is read via the 2–wire bus. Interrupt Mode is better suited to interrupt driven microprocessor–based systems. The INT/CMPTR output may be wire–OR’ed with other interrupt sources in such systems. Note that a pull–up resistor is necessary on this pin since it is an open–drain output. Entering Shutdown Mode will unconditionally reset INT/CMPTR when in Interrupt Mode. Figure 1. Typical Application Serial Data (SDA) Bidirectional. Serial data is transferred in both directions using this pin. Serial Clock (SCL) Input. Clocks data into and out of the LM75. INT/CMPTR Open Collector, Programmable Polarity. In Comparator Mode, unconditionally driven active any time temperature exceeds the value programmed into the TSET register. INT/CMPTR will become inactive when temperature subsequently falls below the THYST setting. (See Register Set and Programmer’s Model.) In Interrupt Mode, INT/CMPTR is made active by TEMP exceeding TSET; it is unconditionally reset to its inactive state by reading any register via the 2–wire bus. If and when temperature falls below THYST, INT/CMPTR is again driven active. Reading any register will clear the THYST interrupt. In Interrupt Mode, the INT/CMPTR output is unconditionally reset upon entering Shutdown Mode. If programmed as an active–low output, it can be wire–ORed with any number of other open collector devices. Most systems will require a pull–up resistor for this configuration. Note that current sourced from the pull–up resistor causes power dissipation and may cause internal heating of the LM75. To avoid affecting the accuracy of ambient temperature readings, the pull–up resistor should be made as large as possible. INT/CMPTR’s output polarity may be programmed by writing to the INT/CMPTR POLARITY bit in the CONFIG register. The default is active low. SHUTDOWN MODE When the appropriate bit is set in the configuration register (CONFIG) the LM75 enters its low–power shutdown mode (IDD = 1µA, typical) and the temperature–to–digital conversion process is halted. The LM75’s bus interface remains active and TEMP, TSET, and THYST may be read from and written to. Transitions on SDA or SCL due to external bus activity may increase the standby power consumption. If the LM75 is in Interrupt Mode, the state of INT/CMPTR will be RESET upon entering shutdown mode. Fault Queue To lessen the probability of spurious activation of INT/CMPTR the LM75 may be programmed to filter out transient events. This is done by programming the desired value into the Fault Queue. Logic inside the LM75 will prevent the device from triggering INT/CMPTR unless the programmed number of sequential temperature–to–digital conversions yield the same qualitative result. In other words, the value reported in TEMP must remain above TSET or below THYST for the consecutive number of cycles Address (A2, A1, A0) Inputs. Sets the three least significant bits of the LM75 8–bit address. A match between the LM75’s address and the address specified in the serial bit stream must be made to initiate communication with the LM75. Many protocol–compatible devices with other addresses may share the same 2–wire bus. http://onsemi.com 4 LM75 programmed in the Fault Queue. Up to a six–cycle ”filter” may be selected. See Register Set and Programmer’s Model. (SDA changes while SCL is HIGH are reserved for Start and Stop Conditions). Serial Port Operation Start Condition (START) The Serial Clock input (SCL) and bidirectional data port (SDA) form a 2–wire bidirectional serial port for programming and interrogating the LM75. The following conventions are used in this bus scheme: The LM75 continuously monitors the SDA and SCL lines for a start condition (a HIGH to LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met. (See Timing Diagram) LM75 Serial Bus Conventions Address Byte Term Immediately following the Start Condition, the host must next transmit the address byte to the LM75. The four most significant bits of the Address Byte (A6, A5, A4, A3) are fixed to 1001(B). The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the LM75 to respond with an Acknowledge (indicating the LM75 is on the bus and ready to accept data). The eighth bit in the Address Byte is a Read–Write Bit. This bit is a 1 for a read operation or 0 for a write operation. Explanation Transmitter The device sending data to the bus. Receiver The device receiving data from the bus. Master The device which controls the bus: initiating transfers (START), generating the clock, and terminating transfers (STOP). Slave The device addressed by the master. Start A unique condition signaling the beginning of a transfer indicated by SDA falling (High–Low) while SCL is high. Stop A unique condition signaling the end of a transfer indicated by SDA rising (Low – High) while SCL is high. ACK A Receiver acknowledges the receipt of each byte with this unique condition. The Receiver drives SDA low during SCL high of the ACK clock–pulse. The Master provides the clock pulse for the ACK cycle. NOT Busy When the bus is idle, both SDA & SCL will remain high. Data Valid The state of SDA must remain stable during the High period of SCL in order for a data bit to be considered valid. SDA only changes state while SCL is low during normal data transfers. (See Start and Stop conditions) Acknowledge (ACK) Acknowledge (ACK) provides a positive handshake between the host and the LM75. The host releases SDA after transmitting eight bits then generates a ninth clock cycle to allow the LM75 to pull the SDA line LOW to acknowledge that it successfully received the previous eight bits of data or address. Data Byte After a successful ACK of the address byte, the host must next transmit the data byte to be written or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data byte into the LM75. Stop Condition (STOP) Communications must be terminated by a stop condition (a LOW to HIGH transition of SDA while SCL is HIGH). The Stop Condition must be communicated by the transmitter to the LM75. (See Timing Diagram) All transfers take place under control of a host, usually a CPU or microcontroller, acting as the Master, which provides the clock signal for all transfers. The LM75 always operates as a Slave. This serial protocol is illustrated in Figure 2. All data transfers have two phases; and all bytes are transferred MSB first. Accesses are initiated by a start condition (START), followed by a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a Stop Condition (STOP). A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW Power Supply To minimize temperature measurement error, the LM75DM–33 is factory calibrated at a supply voltage of 3.3V ±5% and the LM75DM–50 is factory calibrated at a supply voltage of 5V ±5%. Either device is fully operational over the power supply voltage range of 2.7V to 5.5V, but with a lower measurement accuracy. The typical value of this power supply–related error is ±2°C. http://onsemi.com 5 LM75 1 1 9 0 Start by Master 0 1 1 A2 A1 A0 R/W 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack Most Significant Data Byte by LM75 Address Byte 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack by Master Stop No Ack Cond by by Master Master Least Significant Data Byte (a) Typical 2–Byte Read From Preset Pointer Location Such as Temp, TOS, THYST 9 1 1 9 ..... 1 0 Start by Master 0 1 A2 A1 A0 R/W 0 0 0 Ack by LM75 Address Byte 1 9 0 0 1 0 ..... 0 D1 D0 Ack by LM75 Pointer Byte 1 Repeat Start by Master 0 1 9 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 R/W Ack by Most Significant Data Byte LM75 Address Byte 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack by Master Least Significant Data Byte Stop No Ack Cond by by Master Master (b) Typical Pointer Set Followed by Immediate Read for 2–Byte Register Such as Temp, TOS, THYST 1 1 9 0 Start by Master 0 1 A2 A1 A0 R/W Address Byte 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack by LM75 Stop No Ack Cond by by Master Master Data Byte (c) Typical 1–Byte Read From Configuration Register With Preset Pointer 1 1 9 0 Start by Master 0 1 0 A2 A1 A0 R/W Address Byte 1 9 0 Ack by LM75 0 0 0 Pointer Byte 0 0 1 D0 1 Ack Repeat by Start LM75 by Master 9 0 0 1 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 Ack by LM75 Address Byte 9 Stop No Ack Cond by by Master Master Data Byte (d) Typical Pointer Set Followed by Immediate Read from Configuration Register 1 1 9 0 Start by Master 0 1 A2 A1 A0 R/W Address Byte 1 0 9 0 Ack by LM75 0 0 0 1 0 D1 D0 0 Ack by LM75 Pointer Byte 9 0 0 D4 D3 D2 D1 D0 Stop Ack Cond by by LM75 Master Configuration Byte (e) Configuration Register Write 1 1 Start by Master 9 0 0 1 A2 A1 A0 R/W Address Byte Ack by LM75 1 0 9 0 0 0 0 Pointer Byte 0 D1 D0 1 9 1 D7 D6 D5 D4 D3 D2 D1 D0 Ack by LM75 Most Significant Data Byte (f) TOS and THYST Write Figure 2. Serial Port Operation http://onsemi.com 6 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack by LM75 Least Significant Data Byte Stop Ack Cond by by LM75 Master LM75 REGISTER SET AND PROGRAMMER’S MODEL Register (POINT), 8–bits, Write–only Pointer Register (POINT) D[7] D[6] D[5] D[4] D[3] D[2] D[1] Must Be Set To Zero D[0] Pointer Register Selection via the Pointer Register: D1 D0 0 0 Register Selection TEMP 0 1 CONFIG 1 0 THYST 1 1 TSET Configuration Register (CONFIG), 8–bits, Read/Write Configuration Register (CONFIG) D[7] D[6] D[5] Must Be Set To Zero D0: Shutdown: D[4] D[3] Fault Queue D[2] D[1] D[0] INT/ CMPTR. POLARITY COMP/ INT. Shut– Down 0 = Normal Operation 1 = Shutdown Mode D1: CMPTR/INT: 0 = Comparator Mode 1 = Interrupt Mode D2: INT/CMPTR POLARITY: 0 = Active Low 1 = Active High D3 – D4: Fault Queue: Number of sequential temperature–to–digital conversions with the same result before the INT/CMPTR output is updated: D4 D3 Number of Conversions 0 0 1 (Power–up–default) 0 1 2 1 0 4 1 1 6 http://onsemi.com 7 LM75 Temperature (TEMP) Register, 16–bits, Read–only The binary value in this register represents ambient temperature following a conversion cycle. Temperature Register (TEMP) D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X Temperature Setpoint (TSET) and Hysteresis (THYST) Register, 16–bits, Read–Write: Temperature Setpoint Register (TSET) D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X Hysteresis Register (THYST) D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X In the TEMP, TSET, and THYST registers, each unit value represents one–half degree (Celsius). The value is in 2’s – complement binary format such that a reading of 000000000b corresponds to 0°C. Examples of this temperature to binary value relationship are shown in the following table. Temperature to Digital Value Conversion Temperature Binary Value HEX Value +125°C 0 11111010 0FA +25°C 0 00110010 032 +0.5°C 0 00000001 001 0°C 0 00000000 00 — 0.5°C 1 11111111 1FF — 25°C 1 11001110 1CE — 40°C 1 10110000 1B0 — 55°C 1 10010010 192 The LM75’s register set is summarized below Name Description Width Read TEMP Ambient Temperature 16 X TSET Write Notes 2’s Complement Format Temperature Setpoint 16 X X 2’s Complement Format THYST Temperature Hysteresis 16 X X 2’s Complement Format POINT Register Pointer 8 X X Configuration Register 8 X X CONFIG http://onsemi.com 8 LM75 TAPE AND REEL INFORMATION Component Taping Orientation for Micro–8 Devices USER DIRECTION OF FEED PIN 1 Standard Reel Component Orientation for R2 Suffix Device (Mark Right Side Up) Tape & Reel Specifications Table Package Tape Width (W) Pitch (P) Part Per Full Reel Diameter Micro–8 12 mm 4 mm 2500 13 inches MARKING LM75DM–33 LM75DM–50 LM75 33 LM75 50 http://onsemi.com 9 LM75 PACKAGE DIMENSIONS Micro8 PLASTIC PACKAGE CASE TBD ISSUE TBD PIN 1 .122 (3.10) .197 (5.00) .114 (2.90) .187 (4.80) .026 (0.65) TYP. .122 (3.10) .114 (2.90) .043 (1.10) MAX. .008 (0.20) .005 (0.13) 6 ° MAX. .006 (0.15) .016 (0.40) .002 (0.05) .010 (0.25) .028 (0.70) .016 (0.40) Dimensions: inches (mm) http://onsemi.com 10 LM75 Notes http://onsemi.com 11 LM75 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time) Email: ONlit–[email protected] French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time) Email: ONlit–[email protected] English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: [email protected] EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–[email protected] ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–[email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5740–2745 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 LM75/D