TI1 LM49251 Stereo audio subsystem with class g headphone amplifier and class d speaker amplifier with speaker protection Datasheet

LM49251
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SNAS498A – FEBRUARY 2011 – REVISED APRIL 2013
LM49251
Stereo Audio Subsystem with Class G
Headphone Amplifier and Class D Speaker Amplifier with Speaker Protection
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FEATURES
DESCRIPTION
•
The LM49251 is a fully integrated audio subsystem
designed for portable handheld applications such as
cellular phones. Part of TI’s PowerWise family of
products, the LM49251 utilizes a high efficiency class
G headphone amplifier topology as well as a high
efficiency class D loudspeaker.
1
2
•
•
•
•
•
•
Class G Ground Referenced Headphone
Outputs
E2S Class D Amplifier
No Clip Function
Power Limiter Speaker Protection
I2C Volume and Mode Control
Advanced Click-and-Pop Suppression
Micro-Power Shutdown
APPLICATIONS
•
•
Feature Phones
Smart Phones
KEY SPECIFICATIONS
•
•
Class G Headphone Amplifier, HPVDD = 1.8V,
RL = 32Ω
– IDDQHP: 1.15 mA (Typ)
– Output Power, THD+N ≤ 1%: 20 mW (Typ)
Stereo Class D Speaker Amplifier RL = 8Ω
– Output Power, THD+N ≤ 1%, LSVDD = 5.0V:
1.37 W (Typ)
– Output Power, THD+N ≤ 1%, LSVDD = 3.6V:
680 mW (Typ)
– Efficiency: 90% (Typ)
The headphone amplifiers feature TI’s class G ground
referenced architecture that creates a groundreferenced output with dynamic supply rails for
optimum efficiency. The stereo class D speaker
amplifier provides both a no-clip feature and speaker
protection. The Enhanced Emission Suppression
(E2S) outputs feature a patented, ultra low EMI PWM
architecture that significantly reduces RF emissions.
The LM49251 features separate volume controls for
the mono and stereo inputs. Mode selection,
shutdown control, and volume are controlled through
an I2C compatible interface.
Click and pop suppression eliminates audible
transients on power-up/down and during shutdown.
The LM49251 is available in an ultra-small 30-bump
DSBGA package (2.55mmx3.02mm)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LM49251
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Simplified Block Diagram
D
Mono Input and
Volume Control
Stereo Input
and Volume
Control
STEREO
ALC
MIXER
AND
OUTPUT
MODE
SELECT
D
Charge
Pump
+
Class G
2
I C
INTERFACE
Figure 1. LM49251 Simplified Block Diagram
2
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Typical Application
VDD
4.7 µF
4.7 µF
4.7 µF
0.22 µF
INM+
INM-
VDD
VDD
VDD
B1
F4
A4
A3
VOLUME
-86 dB to +12 dB
B3
ALC
POWER
LIMITER
AND
NO
CLIP
0.22 µF
LIN1
D3
CLASS D
+12 dB,
+18 dB
MIXER
AND
OUTPUT
MODE
SELECT
0.22 µF
RIN1
CLASS D
+12 dB,
+18 dB
C3
F5
LSOUTL+
E5
LSOUTL-
A5
LSOUTR+
B5
LSOUTR-
E4 SET
100 nF
INL1/INL2
0.22 µF
MUX
LIN2
INR1/INR2
C4
VOLUME
-80 dB to
+18 dB
0.22 µF
RIN2
E1
-18 dB
to 0 dB
D1
HPL
B4
0.22 µF
BYPASS
-18 dB
to 0 dB
D4
HPR
BIAS
E3
HP GND Sense
2.2 µF
2
I CVDD
A1
SDA
B2
LEVEL DETECT
AND
CLASS G
CONTROL
2
I C INTERFACE
SCL C2
A2
C5
GND
D5
GND
HPVDD
C1
CPVDD
2.2 µF
2.2 µF
CHARGE
PUMP
F3
GND
F2
CPVSS
2.2 µF
D2
E2
C1-
F1
C1+
CPGND
2.2 µF
Figure 2. Typical Audio Amplifier Application Circuit
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Connection Diagram
Top View
Figure 3. DSBGA Package
See Package Number YZR0030
Table 1. Bump Description
Bump
4
Name
Description
A1
2
2
I CVDD
I C Power Supply
A2
GND
Ground
A3
INM+
Mono Channel Non-Inverting Input
A4
VDD
A5
LSOUTR+
B1
VDD
Loudspeaker Power Supply
B2
SDA
I2C Serial Data Input
B3
INM-
Mono Channel Inverting Input
B4
RIN2
Right Channel Input 2
B5
LSOUTR-
C1
CPVDD
C2
SCL
I2C Serial Clock Input
C3
RIN1
Right Channel Input 1
C4
LIN2
Left Channel Input 2
C5
GND
Ground
D1
HPR
Right Channel Headphone Output
D2
C1-
Charge Pump Flying Capacitor Negative Terminal
D3
LIN1
Left Channel Input 1
D4
BYPASS
D5
GND
Ground
E1
HPL
Left Channel Headphone Output
E2
C1+
Charge Pump Flying Capacitor Positive Terminal
E3
HP SENSE GND
E4
SET
Loudspeaker Power Supply
Right Loudspeaker Non-Inverting Output
Right Loudspeaker Inverting Output
Charge Pump Supply (internally generated)
Mid-Rail Bias Bypass Node
Headphone Ground Sense
ALC Timing Set
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Table 1. Bump Description (continued)
Bump
Name
E5
LSOUTL-
F1
CPGND
Charge Pump Ground
F2
HPVDD
Headphone Power Supply
F3
CPVSS
Charge Pump Output
F4
VDD
F5
LSOUTL+
Description
Left Loudspeaker Inverting Output
Loudspeaker Power Supply
Left Loudspeaker Non-Inverting Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage (1)
VDD, I2CVDD
6V
HPVDD
3V
−65°C to +150°C
Storage Temperature
−0.3V to VDD +0.3V
Input Voltage
Power Dissipation (4)
Internally Limited
ESD HBM (5)
2000V
ESD MM (6)
150V
ESD CDM
(7)
750V
Junction Temperature
Thermal Resistance
150°C
θJA (TLA30B1A)
90°C/W
Soldering Information: See AN-1112 (Literature Number SNVA009)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
Human body model, applicable std. JESD22-A114C.
Machine model, applicable std. JESD22-A115-A.
Charge device model, applicable std. JESD22–C101D.
Operating Ratings
Temperature Range (TMIN ≤ TA ≤ TMAX)
−40°C ≤ TA ≤ +85°C
2.7V ≤ VDD ≤ 5.5V
VDD
Supply Voltage
HPVDD
1.6V ≤ HPVDD ≤ 2.0V
I2CDD
1.7V ≤ I2CVDD ≤ 5.5V
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Electrical Characteristics (1) (2) (3)
The following specifications apply for AV = 0dB, RL = 15μH+8Ω+15μH (Loudspeaker), RL = 32Ω (Headphone), CSET = 100nF, f
= 1kHz, ALC off, unless otherwise specified. Limits apply for TA = 25°C.
Parameter
LM49251
Typ (4)
Limit (5)
Units
(Limits)
LS Mode (stereo input), mode 2
5.6
6.25
mA (max)
LS Mode (mono input), mode 3
5.3
6.0
mA (max)
HP Mode (stereo input), mode 6
2.1
2.4
mA (max)
HP Mode (mono input), mode 4
1.8
2.0
mA (max)
LS+HP Mode (stereo input), mode 8
6.1
6.8
mA (max)
LS+HP Mode (mono input), mode 5
5.8
6.5
mA (max)
LS Mode (stereo input, ALC on), mode 2
5.9
VIN = 0, No Load, Mode 6
1.15
1.45
mA (max)
POUT = 0.5mW, GAMP_SD = 0,
RL = 32Ω, Mode 6
4.3
4.6
mA (max)
POUT = 1mW, GAMP_SD = 0,
RL = 32Ω, Mode 6
5.8
6.15
mA (max)
0.02
1
μA (max)
Test Conditions
VIN = 0, No Load
Quiescent Power Supply Current
(LSVDD + VDD)
IDD
Quiescent Power Supply Current
(HPVDD)
IDD(HP)
ISD
Operating Power Supply Current
(HPVDD)
Shutdown Current
VOS
Output Offset Voltage
VIN = 0
Mode 3, mono input, AV = 6dB
Mode 4, mono input
Mode 2, stereo input, AV = 6dB
Mode 6, stereo input
12
1.1
12
1.1
mV
mV
mV
mV
(max)
(max)
(max)
(max)
HP mode, CBYPASS = 2.2μF
TWU
Wake Up Time
AVOL
Volume Control
Normal turn on time
31
Fast turn on time
16
ms
Minimum Gain Setting (mono input),
Mode 3
–86
dB (max)
dB (min)
Maximum Gain Setting (mono input),
Mode 3
12
Minimum Gain Setting (stereo input),
Mode 6
–80
Maximum Gain Setting (stereo input),
Mode 6
18
Volume Control Step Error
(1)
(2)
(3)
(4)
(5)
6
±0.2
ms
13
11.5
dB (max)
dB (min)
dB (max)
dB (min)
19
17.5
dB (max)
dB (min)
dB
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Loudspeaker RL is a resistive load in series with two inductors to simulate an actual speaker load. For RL = 8Ω, the load is 15μH + 8Ω
+15μH. For RL = 4Ω, the load is 15μH + 4Ω + 15μH.
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
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Electrical Characteristics(1)(2)(3) (continued)
The following specifications apply for AV = 0dB, RL = 15μH+8Ω+15μH (Loudspeaker), RL = 32Ω (Headphone), CSET = 100nF, f
= 1kHz, ALC off, unless otherwise specified. Limits apply for TA = 25°C.
LM49251
Typ (4)
Limit (5)
Units
(Limits)
Gain 0
12
11.5
12.5
dB (min)
dB (max)
Gain 1
18
17.5
19
dB (min)
dB (max)
Gain 0
0
–0.5
0.5
dB (min)
dB (max)
Gain 1
–1.7
dB
Gain 2
–3
dB
Gain 3
–6
dB
Gain 4
–9
dB
Gain 5
–12
dB
Gain 6
–15
dB
Gain 7
–18
LS Output
HP Output
–93
–98
Parameter
Test Conditions
LS Mode
HP Mode
AV
AV(MUTE)
Gain
Mute Attenuation
–18.5
–17.5
dB (min)
dB (max)
dB
dB
MONO, RIN, LIN inputs
RIN
Input Resistance
Maximum Gain Setting
13
9.5
15.5
kΩ min)
kΩ (max)
Minimum Gain Setting
110
97
122
kΩ (min)
kΩ (max)
Mode 3, AV = 18dB, RL = 8Ω
PO
Output Power
LSVDD = 3.3V
570
mW
LSVDD = 3.6V
680
LSVDD = 4.2V
955
mW
LSVDD = 5.0V
1370
mW
600
mW (min)
Mode 6
THD+N
Total Harmonic Distortion + Noise
RL = 16Ω
20
RL= 32Ω
20
mW
16
mW (min)
f = 1kHz, Mode 3
Mono Input, PO = 250mW
0.02
%
f = 1kHz, Mode 6
Stereo Input, PO = 12mW
0.02
%
f = 217Hz, VRIPPLE = 200mVP-P, Inputs AC GND, CB = 2.2μF
Mode 3, mono input, AV = 6dB
77
dB
65
dB
Mode 4, ripple on VDD, mono input
93
dB
Mode 4, ripple on HPVDD, mono input
83
dB
Mode 6, ripple on VDD, stereo input
80
dB
80
dB
52
63
dB
dB
Mode 2, stereo input, AV = 6dB
PSRR
Power Supply Rejection Ratio
Mode 6, ripple on HPVDD, stereo input
VRIPPLE = 1VP-P, fRIPPLE = 217Hz, mono input
CMRR
Common Mode Rejection Ratio
η
Efficiency
LS Mode, PO = 680mW
90
%
XTALK
Crosstalk
PO = 12mW, f = 1kHz, Mode 6
84
dB
Mode 3
Mode 4
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Electrical Characteristics(1)(2)(3) (continued)
The following specifications apply for AV = 0dB, RL = 15μH+8Ω+15μH (Loudspeaker), RL = 32Ω (Headphone), CSET = 100nF, f
= 1kHz, ALC off, unless otherwise specified. Limits apply for TA = 25°C.
Parameter
Test Conditions
∈OS
Output Noise
A-weighted, Inputs AC GND
Mode 3, mono input
Mode 2, stereo input
Mode 4, mono input
Mode 6, stereo input
SNR
Signal-To-Noise-Ratio
Mode 3, PO = 680mW
Mode 6, PO = 20mW
tA
Attack Time
tR
Release Time
LM49251
Typ (4)
Limit (5)
Units
(Limits)
44
45
8
10.2
μV
μV
μV
μV
94
98
dB
dB
Step 1, Mode 1
0.75
ms
Step 1, Mode 1
1
s
3.9
4.7
5.4
6.2
7.0
7.8
VP-P
VP-P
VP-P
VP-P
VP-P
VP-P
Mode 3, THD+N ≤ 1% (6)
VLIMIT
(6)
Output Voltage Limit
Voltage Level
Step 1 001
Step 2 010
Step 3 011
Step 4 100
Step 5 101
Step 6 110
The LM49251 ALC limits the output power to which ever is lower, the supply voltage or output power limit.
I2C Interface Characteristics VDD = 5V, 2.2V ≤ I2CVDD ≤ 5.5V (1) (2)
The following specifications apply for AV = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
Parameter
Test Conditions
LM49251
Typ (3)
Limit (4)
Units
(Limits)
t1
SCL Period
2.5
μs (min)
t2
SDA Set-up Time
100
ns (min)
t3
SDA Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
t6
SDA Hold time
100
ns (min)
VIH
Input High Voltage
0.7*I2CVDD
V (min)
VIL
Input Low Voltage
0.3*I2CVDD
V (max)
(1)
(2)
(3)
(4)
8
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
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I2C Interface Characteristics VDD = 5V, 1.8V ≤ I2CVDD ≤ 2.2V (1) (2)
The following specifications apply for AV = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
Parameter
Test Conditions
LM49251
Typ
(3)
Limit (4)
Units
(Limits)
t1
SCL Period
2.5
μs (min)
t2
SDA Set-up Time
250
ns (min)
t3
SDA Stable Time
0
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition Time
250
ns (min)
t6
SDA Hold Time
250
ns (min)
2
VIH
Digital Input High Voltage
0.7*I CVDD
V (min)
VIL
Digital Input Low Voltage
0.3*I2CVDD
V (max)
(1)
(2)
(3)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 3.6V, RL = 15μH+8Ω+15μH
POUT = 450mW, Mode 3
10
5
10
5
2
1
2
1
0.5
0.5
THD+N (%)
THD+N (%)
THD+N vs Frequency
VDD = 3.6V, RL = 15μH+8Ω+15μH
POUT = 450mW, Mode 2
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.005
0.02
0.01
0.005
0.002
0.001
20
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
Figure 5.
THD+N vs Frequency
VDD = 3.6V, RL = 15μH+4Ω+15μH
POUT = 650mW, Mode 2
THD+N vs Frequency
VDD = 3.6V, RL = 15μH+4Ω+15μH
POUT = 650mW, Mode 3
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.005
0.02
0.01
0.005
0.002
0.001
20
0.002
0.001
20
10
5
50 100 200 500 1k 2k
5k 10k 20k
5k 10k 20k
Figure 6.
Figure 7.
THD+N vs Frequency
VDD = 5V, RL = 15μH+4Ω+15μH
POUT = 1.2W, Mode 2
THD+N vs Frequency
VDD = 5V, RL = 15μH+4Ω+15μH
POUT = 1.2W, Mode 3
10
5
2
1
0.2
0.1
0.05
THD+N (%)
0.5
0.02
0.01
0.005
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.0005
0.0002
0.0001
20
50 100 200 500 1k 2k
FREQUENCY (Hz)
2
1
0.5
THD+N (%)
5k 10k 20k
Figure 4.
FREQUENCY (Hz)
50 100 200 500 1k 2k
5k 10k 20k
0.002
0.001
20
FREQUENCY (Hz)
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 8.
10
50 100 200 500 1k 2k
FREQUENCY (Hz)
THD+N (%)
THD+N (%)
FREQUENCY (Hz)
Figure 9.
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Typical Performance Characteristics (continued)
THD+N vs Frequency
VDD = 5V, RL = 5μH+8Ω+15μH
POUT = 750mW, Mode 2
10
5
10
5
2
1
2
1
0.5
0.5
THD+N (%)
THD+N (%)
THD+N vs Frequency
VDD = 5V, RL = 15μH+8Ω+15μH
POUT = 50mW, Mode 3
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.005
0.02
0.01
0.005
0.002
0.001
20
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
5k 10k 20k
Figure 10.
Figure 11.
THD+N vs Frequency
RL = 32Ω
POUT = 14mW, Mode 4
THD+N vs Frequency
RL = 16Ω
POUT = 14mW, Mode 4
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.005
0.02
0.01
0.005
0.002
0.001
20
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 12.
Figure 13.
THD+N vs Frequency
RL = 32Ω
POUT = 14mW, Mode 6
THD+N vs Output Power
VDD = 3.6V, RL = 15μH+4Ω+15μH
f = 1kHz, Mode 2
10
5
10
5
2
1
2
1
0.5
THD+N (%)
0.5
THD+N (%)
50 100 200 500 1k 2k
FREQUENCY (Hz)
THD+N (%)
THD+N (%)
FREQUENCY (Hz)
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.005
0.02
0.01
0.005
0.002
0.001
20
0.002
0.001
10m 20m 50m 100m 200m 500m 1
50 100 200 500 1k 2k
5k 10k 20k
2
5
OUTPUT POWER (W)
FREQUENCY (Hz)
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 3.6V, RL = 15μH+8Ω+15μH
f = 1kHz, Mode 2
THD+N vs Output Power
VDD = 3.6V, RL = 15μH+8Ω+15μH
f = 1kHz, Mode 3
10
5
10
5
2
1
2
1
0.5
THD+N (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.005
0.02
0.01
0.005
0.002
0.001
10m 20m 50m 100m 200m 500m 1
0.002
0.001
10m 20m 50m 100m 200m 500m 1
2
5
OUTPUT POWER (W)
Figure 16.
Figure 17.
THD+N vs Output Power
VDD = 3.6V, RL = 15μH+4Ω+15μH
f = 1kHz, Mode 3
THD+N vs Output Power
VDD = 5V, RL = 15μH+4Ω+15μH
f = 1kHz, Mode 2
10
5
10
5
2
1
2
1
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.005
0.02
0.01
0.005
0.002
0.001
10m 20m 50m 100m 200m 500m 1
0.002
0.001
10m 20m 50m 100m 200m 500m 1
2
5
OUTPUT POWER (W)
2
5
OUTPUT POWER (W)
Figure 18.
Figure 19.
THD+N vs Output Power
VDD = 5V, RL = 15μH+8Ω+15μH
f = 1kHz, Mode 2
THD+N vs Output Power
VDD = 5V, RL = 15μH+4Ω+15μH
f = 1kHz, Mode 3
10
5
10
5
2
1
2
1
0.5
0.5
THD+N (%)
THD+N (%)
5
0.5
THD+N (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.005
0.02
0.01
0.005
0.002
0.001
10m 20m 50m 100m 200m 500m 1
0.002
0.001
10m 20m 50m 100m 200m 500m 1
2
5
OUTPUT POWER (W)
2
5
OUTPUT POWER (W)
Figure 20.
12
2
OUTPUT POWER (W)
Figure 21.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 5V, RL = 15μH+8Ω+15μH
f = 1kHz, Mode 3
THD+N vs Output Power
RL = 32Ω, f = 1kHz, Mode 4
10
5
2
1
2
0.5
1
THD+N (%)
THD+N (%)
10
5
0.2
0.1
0.05
0.5
0.2
0.1
0.02
0.01
0.005
0.05
0.002
0.001
10m 20m 50m 100m 200m 500m 1
0.02
2
0.01
1m
5
2m 3m 4m 5m 7m 10m 20m 30m 50m
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 22.
10
Figure 23.
THD+N vs Output Power
RL = 16Ω, f = 1kHz, Mode 4
5
2
2
1
1
THD+N (%)
THD+N (%)
5
0.5
0.2
0.5
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
1m
THD+N vs Output Power
RL = 16Ω, f = 1kHz, Mode 6
10
0.01
1m
2m 3m 4m 5m 7m 10m 20m 30m 50m
2m 3m 4m 5m 7m 10m 20m 30m 50m
OUTPUT POWER (W)
10
OUTPUT POWER (W)
Figure 24.
Figure 25.
THD+N vs Output Power
RL = 32Ω, f = 1kHz, Mode 6
Power Dissipation vs Output Power
RL = 15μH+4Ω+15μH, f = 1kHz, VDD = 3.6V
0.3
5
0.25
Power Dissipation (W)
2
THD+N (%)
1
0.5
0.2
0.1
0.05
0.2
0.15
0.1
0.05
0.02
0.01
1m
2m 3m 4m 5m 7m 10m 20m 30m 50m
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
OUTPUT POWER (W)
Output Power (W)
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
Power Dissipation vs Output Power
RL = 15μH+4Ω+15μH, f = 1kHz, VDD = 5V
Power Dissipation vs Output Power
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 3.6V
0.12
0.45
0.4
0.1
Power Dissipation (W)
Power Dissipation (W)
0.35
0.3
0.25
0.2
0.15
0.1
0.08
0.06
0.04
0.02
0.05
0
0
0
0.5
1
1.5
2
2.5
0
3
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Power (W)
Output Power (W)
Figure 28.
Figure 29.
Power Dissipation vs Output Power
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 5V
Power vs Output Power
RL = 16Ω, f = 1kHz, VDD = 1.8V
0.18
0.14
0.16
0.12
Power Dissipation (W)
Power Dissipation (W)
0.14
0.12
0.1
0.08
0.06
0.1
0.08
0.06
0.04
0.04
0.02
0.02
0
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
0
0.005 0.01 0.015 0.02 0.025 0.03 0.035
Output Power (W)
Output Power (W)
Figure 30.
Figure 31.
Power Dissipation vs Output Power
RL = 32Ω, f = 1kHz, VDD = 1.8V
Efficiency vs Output Power
RL = 15μH+4Ω+15μH, f = 1kHz, VDD = 3.6V
90
0.08
80
0.07
70
0.06
60
Efficiency (%)
Power Dissipation (W)
0.09
0.05
0.04
0.03
40
30
0.02
20
0.01
10
0
0
0.005 0.01 0.015 0.02
0.025 0.03 0.035
Output Power (W)
0
0
0.2
0.4 0.6
0.8
1
1.2
1.4 1.6
Output Power (W)
Figure 32.
14
50
Figure 33.
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Typical Performance Characteristics (continued)
Efficiency vs Output Power
RL = 15μH+4Ω+15μH, f = 1kHz, VDD = 5V
Efficiency vs Output Power
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 3.6V
100
100
90
90
80
80
70
Efficiency (%)
Efficiency (%)
70
60
50
40
60
50
40
30
30
20
20
10
10
0
0
0
0.5
1
1.5
2
2.5
3
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Power (W)
Output Power (W)
Figure 34.
Figure 35.
Efficiency vs Output Power
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 5V
PSRR vs Frequency
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 3.6V
AV = 6dB, Mode 2
100
0
-10
-20
70
-30
PSRR (dB)
Efficiency (%)
90
80
60
50
40
-40
-50
-60
30
-70
20
-80
10
-90
0
-100
20
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
5k 10k 20k
FREQUENCY (Hz)
Output Power (W)
Figure 36.
Figure 37.
PSRR vs Frequency
RL = 15μH+8Ω+15μH, VDD = 5V
AV = 6dB, Mode 2
PSRR vs Frequency
RL = 15μH+8Ω+15μH, VDD = 3.6V
AV = 6dB, Mode 3
0
0
-10
-10
-20
-20
-30
-30
PSRR (dB)
PSRR (dB)
50 100 200 500 1k 2k
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 38.
Figure 39.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
RL = 32Ω, HPVDD = 1.8V, VDD = 5V
AV = 6dB, Mode 4
0
0
-10
-10
-20
-20
-30
-30
PSRR (dB)
PSRR (dB)
PSRR vs Frequency
RL = 15μH+8Ω+15μH, VDD = 5V
AV = 6dB, Mode 3
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
50 100 200 500 1k 2k
5k 10k 20k
50 100 200 500 1k 2k
FREQUENCY (Hz)
Figure 40.
Figure 41.
CMRR vs Frequency HP Mode
0
+0
-10
-10
-20
-20
-30
-30
CMRR (dB)
PSRR (dB)
PSRR vs Frequency
RL = 32Ω, HPVDD = 1.8V, VDD = 5V
AV = 6dB, Mode 6
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
50 100 200 500 1k 2k
-100
20
5k 10k 20k
50 100 200 500 1k 2k
FREQUENCY (Hz)
5k 10k 20k
FREQUENCY (Hz)
Figure 42.
Figure 43.
CMRR vs Frequency LS Mode
Supply Current vs Supply Voltage
Mode 2, Stereo Inputs
+0
8
-10
7
Supply Current (mA)
-20
-30
CMRR (dB)
5k 10k 20k
FREQUENCY (Hz)
-40
-50
-60
-70
6
5
4
3
2
-80
1
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
3.2
3.7
4.2
4.7
5.2
Supply Voltage (V)
Figure 44.
16
0
2.7
Figure 45.
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Typical Performance Characteristics (continued)
8
Supply Current vs Supply Voltage
Mode 8, Stereo Inputs
7
6
6
Supply Current (mA)
Supply Current (mA)
7
5
4
3
2
5
4
3
2
1
1
0
2.7
Supply Current vs Supply Voltage
Mode 3, Mono Inputs
3.2
3.7
4.2
4.7
0
2.7
5.2
3.2
3.7
4.2
4.7
Supply Voltage (V)
Supply Voltage (V)
Figure 46.
Figure 47.
5.2
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System Control
I2C SIGNALS
In I2C mode the LM49251 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal
SDA. Both of these signals need a pull-up resistor according to I2C specification. The 7-bits I2C slave address for
LM49251 is 1111100.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when SCL is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
change
allowed
data
valid
Figure 48. I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
START condition
STOP condition
Figure 49. I2C Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C
master sends a chip address. This address is seven bits long followed by an eight bit which is a data direction bit
(R/W). The LM49251 address is 11111000. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the data will be written. The third byte contains data to write
to the selected register.
MSB
ADR6
Bit7
LSB
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
R/W
bit0
2
I C SLAVE address (chip address)
Figure 50. I2C Chip Address
18
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ack from slave
ack from slave
start
MSB Chip Address LSB
w
ack MSB Register 0x02h LSB ack
start
slave address =
11111002
w
ack
ack from slave
MSB
Data
LSB
ack
stop
ack
stop
SCL
SDA
register address = 0x02h
ack
register 0x02h data
Figure 51. Example I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
ack from slave repeated start
ack from slave
start MSB Chip Address LSB w ack MSB Register 0x00h LSB ack rs
ack from slave data from slave ack from master
MSB Chip Address LSB r ack MSB
Data
LSB ack stop
SCL
SDA
slave address =
11111002
start
w ack register address = 0x00h ack
rs
slave address =
11111002
r ack
register 0x00h data
ack stop
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
Figure 52. Example I2C Read Cycle
Table 2. Device Address
Device Address
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
1
1
0
0
0
Table 3. I2C Control Registers
Register Name
B7
B6
B5
B4
B3
B2
SHUTDOWN
CONTROL
B1
B0
0
0
0
1
GAMP__ON
HPR_ SD
Class G _SD
MODE
CONTROL
0
0
1
HP_ST
HP_M
SPK_ L+R
SPK_ST
SPK_M
POWER
LIMITER
CONTROL
0
1
0
ATK1
ATK0
PLEV2
PLEV1
PLEV0
NO CLIP
CONTROL
0
1
1
RLT1
RLT0
OCP2
OCP1
OCP0
GAIN
CONTROL
1
0
0
LSGAINL
LSGAINR
HPGAIN2
HPGAIN1
HPGAIN0
MONO
VOLUME
CONTROL
1
0
1
MG4
MG3
MG2
MG1
MG0
STEREO
VOLUME
CONTROL
1
1
0
SG4
SG3
SG2
SG1
SG0
SD
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Table 3. I2C Control Registers (continued)
Register Name
B7
B6
B5
B4
B3
B2
B1
B0
CLASS D
CONTROL
1
1
1
0
0
0
ER_CNTRL
SS_EN
LS CONTROL
1
1
1
0
1
0
ST_SEL
LSR_SD
CLASS G
CONTROL
1
1
1
1
0
0
TLEV1
TLEV2
OTHER
CONTROL
1
1
1
1
1
I2CVDD SD
RAIL_SW
TURN_ON
TIME
Table 4. Shutdown Control
BIT
NAME
VALUE
B3
GAMP_ON
DESCRIPTION
This disables the gain amplifiers that are not in use to minimize IDD.
0
Normal Operation
1
Unused gain amplifiers disabled
This disables the right headphone output.
B2
HPR_SD
0
Normal operation
1
Right headphone amplifier disabled
This disables the Class G.
B1
Class G_SD
0
Class G enabled
1
Class G disabled
LM49251 Shutdown
B0
SD
0
LM49251 Disabled
1
LM49251 Enabled
Table 5. Output Mode Selection
HP (ST)
HP (M)
SPK
(L+R)
SPK
(ST)
SPK
(M)
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
20
SPK(L)
SPK(R)
HP(L)
HP(R)
Datasheet
SD
SD
SD
SD
Mode 0
GST X (L + R)
GST X (L + R)
SD
SD
Mode 1
GST X L
GST X R
SD
SD
Mode 2
1
GM X M
GM X M
SD
SD
Mode 3
0
SD
SD
GM X M
GM X M
Mode 4
0
1
GM X M
GM X M
GM X M
GM X M
Mode 5
0
0
0
SD
SD
GSTX L
GST X R
Mode 6
1
1
0
GST X (L + R)
GST X (L + R)
GSTX L
GST X R
Mode 7
0
1
0
GST X L
GST X R
GSTX L
GST X R
Mode 8
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Table 6. Voltage Limit Control Register
BIT
B4:B3
B2:B0
NAME
VALUE
ATK1
ATK2
DESCRIPTION
B4
B3
Sets Attack Time based on CSET and RSET
0
0
tATK
0
1
1.3 x tATK
1
0
2 x tATK
1
1
2.7 x tATK
B2
B1
B0
Sets output power limit level
0
0
0
Voltage Limit disabled
0
0
1
VTH(VLIM) = 3.9VP-P
0
1
0
VTH(VLIM)) = 4.7VP-P
0
1
1
VTH(VLIM)= 5.4VP-P
1
0
0
VTH(VLIM) = 6.2VP-P
1
0
1
VTH(VLIM) = 7.0VP-P
1
1
0
VTH(VLIM) = 7.8VP-P
1
1
1
Voltage Limit disabled
PLEV2
PLEV1
PLEV0
Table 7. No Clip Control Register
BIT
B2:B0
B4:B3
NAME
VALUE
DESCRIPTION
B2
B1
B0
0
0
0
0
0
1
0
1
0
0
1
1
low
1
0
0
medium
1
0
1
medium high
1
1
0
high
1
1
1
maximum
B1
B0
0
0
1s
0
1
0.8s
1
0
0.65s
1
1
0.4s
OCP2
OCP1
OCP0
RLT1
RTL0
This sets the output clip limit level
NO_CLIP = disabled, OUTPUT_CLIP = disabled
Test Mode
NO_CLIP = enabled, OUTPUT_CLIP = disabled
This sets the release time of the automatic limiter
control circuit.
Table 8. Gain Control Register
BIT
B4
B3
NAME
LSGAINL
LSGAINR
VALUE
DESCRIPTION
0
6dB Loudspeaker gain
1
12dB Loudspeaker gain
0
6dB Loudspeaker gain
1
12dB Loudspeaker gain
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Table 8. Gain Control Register (continued)
BIT
B2:B0
NAME
HPGAIN2 (B2)
HPGAIN1 (B1)
HPGAIN0 (B0)
VALUE
DESCRIPTION
B2
B1
B0
Headphone Gain
0
0
0
0dB
0
0
1
-1.5db
0
1
0
-3dB
0
1
1
-6dB
1
0
0
-9dB
1
0
1
-12dB
1
1
0
-15dB
1
1
1
-18dB
General Amplifier Function
Table 9. Volume Control Table
VOLUME STEP
_G4
_G3
_G2
_G1
_G0
1
0
0
0
0
0
-80
2
0
0
0
0
1
-46.5
3
0
0
0
1
0
-40.5
4
0
0
0
1
1
-34.5
5
0
0
1
0
0
-30
6
0
0
1
0
1
-27
7
0
0
1
1
0
-24
8
0
0
1
1
1
-21
9
0
1
0
0
0
-18
10
0
1
0
0
1
-15
11
0
1
0
1
0
-13.5
12
0
1
0
1
1
-12
13
0
1
1
0
0
-10.5
14
0
1
1
0
1
-9
15
0
1
1
1
0
-7.5
16
0
1
1
1
1
-6
17
1
0
0
0
0
-4.5
18
1
0
0
0
1
-3
19
1
0
0
1
0
1.5
20
1
0
0
1
1
0
21
1
0
1
0
0
1.5
22
1
0
1
0
1
3
23
1
0
1
1
0
4.5
24
1
0
1
1
1
6
25
1
1
0
0
0
7.5
26
1
1
0
0
1
9
27
1
1
0
1
0
10.5
28
1
1
0
1
1
12
29
1
1
1
0
0
X
30
1
1
1
0
1
X
31
1
1
1
1
0
X
32
1
1
1
1
1
X
22
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Table 10. Class D Control
BIT
NAME
VALUE
DESCRIPTION
This enables edge rate control.
B1
ER_CNTRL
0
Edge Rate Control Disabled
1
Edge Rate Control Enabled
This enables Spread Spectrum.
B0
SS_EN
0
Spread Spectrum Disabled
1
Spread Spectrum Enabled
Table 11. Loudspeaker (LS) Control
BIT
NAME
VALUE
DESCRIPTION
This allows selection between two Stereo Inputs.
B1
ST_SEL
0
LIN1/RIN1
1
LIN2/RIN2
This disables the Left Loudspeaker.
B0
LSR_SD
0
Left Loudspeaker enabled
1
Left Loudspeaker disabled
Table 12. Class G Control
BIT
B1:B0
NAME
VALUE
TLEV1
TLEV0
DESCRIPTION
B1
B0
This sets the Trip Level.
0
0
High (default)
0
1
High-Medium
1
0
Low-Medium
1
1
Low
Table 13. Other Control
BIT
NAME
VALUE
DESCRIPTION
This switches between two HP voltage rails (1)
B1
RAIL_SW
0
High Rail
1
Low Rail
This allows fast turn on time
B0
(1)
TURN_ON_TIME
0
Normal Turn-On Time
1
Fast Turn-On Time
This option is only available when the Class G is disabled.
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APPLICATION INFORMATION
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM49251 features a differential input stage, which offers improved noise rejection compared to a singleended input amplifier. Because a differential input amplifier amplifies the difference between the two input
signals, any component common to both signals is cancelled. An additional benefit of the differential input
structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to
both inputs, and thus cancelled by the amplifier, the LM49251 can be used without input coupling capacitors
when configured with a differential input signal.
INPUT MIXER/MULTIPLEXER
The LM49251 includes a comprehensive mixer multiplexer controlled through the I2C interface. The
mixer/multiplexer allows any input combination to appear on any output of LM49251. Table 5 (MODE CONTROL)
shows how the input signals are routed together for each possible input selection.
SHUTDOWN FUNCTION
The LM49251 features the following shutdown controls: Bit B4 (GAMP_SD) of the SHUTDOWN CONTROL
register controls the gain amplifiers. When GAMP_SD = 1, it disables the gain amplifiers that are not in use. For
example, in Modes 1, 4 and 5, the Mono inputs are in use, so the Left and Right input gain amplifiers are
disabled, causing the IDD to be minimized. Bit B0 (PWR_ON) of the SHUTDOWN CONTROL register is the
global shutdown control for the entire device. Set PWR_ON = 0 for normal operation. PWR_ON = 1 overrides
any other shutdown control bit.
CLASS D AMPLIFIER
The LM49251 features a mono class D audio power amplifier with a filterless modulation scheme that reduces
external component count, conserving board space and reducing system cost. With no signal applied, the
outputs (LSOUT+ and LSOUT-) switch between VDD and GND with 50% duty cycle, in phase, causing the two
outputs to cancel. This cancellation results in no net voltage across the speaker, thus there is no current to the
load in the idle state.
With an input signal applied, the duty cycle (pulse width) of the class D output changes. For increasing output
voltage, the duty cycle of LSOUT+ increases, while the duty cycle of LSOUT- decreases. For decreasing output
voltages, the converse occurs. The difference between the two pulse widths yields the differential output voltage.
ENHANCED EMISSIONS SUPPRESSION (E2S)
The LM49251 class D amplifier features TI’s patent-pending E2S system that reduces EMI, while maintaining
high quality audio reproduction and efficiency. The E2S system features selectable spread spectrum and
advanced edge rate control (ERC). The LM49251 class D ERC greatly reduces the high frequency components
of the output square waves by controlling the output rise and fall times, slowing the transitions to reduces RF
emissions, while maximizing THD+N and efficiency performance.
FIXED FREQUENCY
The LM49251 class D amplifier features two modulation schemes, a fixed frequency mode and a spread
spectrum mode. Select the fixed frequency mode by setting bit B0 (SS_EN) of the SS Control register to 0. In
fixed frequency mode, the loudspeaker outputs switch at a constant 300kHz. The output spectrum consists of the
300kHz fundamental and its associated harmonics.
SPREAD SPECTRUM
The selectable spread spectrum mode minimizes the need for output filters, ferrite beads or chokes. In spread
spectrum mode, the switching frequency varies randomly by 30% about a 300kHz center frequency, reducing the
wideband spectral content, improving EMI emission radiated by the speaker and associated cables and traces.
Where a fixed frequency class D exhibits large amounts of spectral energy at multiples of the switching
frequency, the spread spectrum architecture spreads that energy over a larger bandwidth. The cycle-to-cycle
variation of the switching period does not affect the audio reproduction, efficiency, or PSRR. Set bit B0 (SS_EN)
of the SS Control register to 1 to enable spread spectrum mode.
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GROUND REFERENCED HEADPHONE AMPLIFIER
The LM49251 features a low noise inverting charge pump that generates an internal negative supply voltage.
This allows the headphone outputs to be biased about GND instead of a nominal DC voltage, like traditional
headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220μF) at
the headphone outputs are not necessary. The coupling capacitors are replaced by two small ceramic charge
pump capacitors, saving board space and cost. Eliminating the output coupling capacitors also improves low
frequency response. In traditional headphone amplifiers, the headphone impedance and the output capacitor
form a high-pass filter that not only blocks the DC component of the output, but also attenuates low frequencies,
impacting the bass response. Because the LM49251 does not require the output coupling capacitors, the low
frequency response of the device is not degraded by external components. In addition to eliminating the output
coupling capacitors, the ground referenced output nearly doubles the available dynamic range of the LM49251
headphone amplifiers when compared to a traditional headphone amplifier operating from the same supply
voltage.
CLASS G OPERATION
The LM49251 features a ground referenced class G headphone amplifier for increased efficiency and decreased
power dissipation. This particular architecture creates a ground-referenced output with dynamic supply rails for
optimum efficiency. Music and voice signals have a high peak-to-mean ratio with the majority of the signal
content at low levels, class G amplifiers take advantage of this behavior. Class G amplifiers have multiple voltage
supplies to decrease power dissipation. The LM49251 has two discrete supply rails: ±0.9V and ±1.8V. The
device switches from ±0.9V to ±1.8V when the output signal reaches the selectable threshold level to switch to
the higher voltage rails. When the output falls below the required voltage for a set period of time, it will switch
back to the lower rail until the next time the threshold is reached. The threshold level has 4 selectable levels that
can be set through the Class G Control I2C control register <B1:B2>. With this topology power dissipation is
reduced for typical music or voice sources. Figure 53 below shows how a music output may look.
HPVDD(+1.8V)
HPVDD(+0.9V)
0
HPVSS(-0.9v)
HPVSS(-1.8V)
Supply Rails
Power savings in Class G
+
Power dissipated in Class AB
Power dissipated in Class G
Figure 53. Class G Operation
Disabling the Class G
The Class G feature can be disabled via I2C Shutdown Control Register B1. When the Class G is disabled the
headphone supply rails are selectable. In the Other Control register B1 = 0 sets the headphone supply rails at
±1.8V (high) and B1 = 1 sets the supply to ±0.9V (low). Figure 54 below shows a curve of THD+N vs Output
Power for the two supply rails.
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10
5
2
Low Rail
High Rail
THD+N (%)
1
0.5
0.2
0.1
0.05
0.02
0.01
1m
2m 3m 4m 5m 7m10m
20m 30m 50m
OUTPUT POWER (W)
Figure 54. Class G Disabled (Low/High Supply Rails)
AUTOMATIC LIMITER CONTROL (ALC)
When enabled, the ALC continuously monitors and adjusts the gain of the loudspeaker amplifier signal path if
necessary. The ALC serves two functions: voltage limiter/speaker protection and output clip prevention (No-Clip)
with three clip controls levels. The voltage limiter/speaker protection prevents an output overload condition by
maintaining the loudspeaker output signal below a preset amplitude (See VOLTAGE LIMITER section). The No
Clip feature monitors the output signal and maintains audio quality by preventing the loudspeaker output from
exceeding the amplifier’s headroom (see NO CLIP/OUTPUT CLIP CONTROL section). The voltage limiter
thresholds, clip control levels, attack and release times are configured through the I2C interface.
VOLTAGE LIMITER
The voltage limiter function of the ALC monitors and prevents the audio signal from exceeding the voltage limit
threshold. The voltage limit threshold (VTH(VLIM)) is set by bits B2:B0 in the “Voltage Limit Threshold Register”
(see Table 6). Although the ALC reduces the gain of the speaker path to maintain the audio signal below the
voltage limit threshold, it is still possible to overdrive the speaker output in which case loudspeaker output will
exceed the voltage limit threshold and cause clipping on the output, and speaker damage is possible. Please see
the ALC HEADROOM section for further details.
4VP-P
4.8VP-P
5.6VP-P
6.4VP-P
7.2VP-P
8VP-P
OFF
Figure 55. Voltage Limit Output Level
NO CLIP/OUTPUT CLIP CONTROL
The LM49251 No Clip circuitry detects when the loudspeaker output is near clipping and reduces the signal gain
to prevent output clipping and preserve audio quality (Figure 54). Although the ALC reduces the gain of the
speaker path to prevent output clipping, it is still possible to overdrive the speaker output. Please see the ALC
HEADROOM section for further details.
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+VOUT(MAX)
+VOUT(MAX)
-VOUT(MAX)
-VOUT(MAX)
No Clip Enabled
No Clip Disabled
Figure 56. No Clip Function
The LM49251 also features an output clip control that allows a certain amount of clipping at the output in order to
increase the loudspeaker output power. The clip level is set by B2:B0 in the No Clip Control Register (see
Table 7). The clip control works by allowing the output to enter clipping before the ALC turns on and maintains
the output level. The clip control has three levels: low, medium, and high. The low and max clip level control
settings give the lowest distortion and highest distortion respectively on the output (see Figure 57). The actual
output level of the device will depend upon the supply voltage, and the output power will depend upon the load
impedance.
OUTPUT VOLTAGE (V)
4
2
0
-2
-4
0
1
2
3
4
TIME (ms)
Figure 57. Clip Control Levels
VDD = 3.3V, VIN = 8VPP Shaped Burst, 1kHz
Blue = No Clip Disabled, Gray = Low, Light Green = Medium
Green = High, Yellow = Max
ALC HEADROOM
When either voltage limiter or no clip is enabled, it is still possible to drive LM49251 into clipping by over driving
the input volume stage of the signal path beyond its output dynamic range. In this case, clipping occurs at the
input volume stage, and although ALC is active, the gain reduction will have no effect on the output clipping. The
maximum input that can safely pass through the input volume stage can be calculated by following formula:
VIN d
VDD
Av (volume gain)
(1)
So in the case of 0 dB volume gain, audio input has to be less than VDD for both voltage limiter or No clip
settings.
When voltage limiter is enabled, ALC can reach its max attenuation for lower voltage limit levels as shown in
Figure 58. Typically, after the ALC started working, with 6 dB of audio input change ALC is well within its
regulation. Voltage limiter Input headroom can be increased by switching to the LS_GAIN to 18dB in the Gain
Control Register (see Table 8).
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1
1.0
10
No Clip
Disabled
Voltage Limiter off
VIN > VDD
5.6VPP
0.6
4.8VPP
4VPP
0.4
1.0
100m
THD+N (%)
OUTPUT POWER (W)
OUTPUT POWER (W)
0.8
No Clip
Enabled
10m
0.1
0.2
ALC max attenuation
0
0
1
2
3
4
5
6
1m
7
0.01
2
1
4
6
8
INPUT VOLTAGE (VPP)
INPUT VOLTAGE (VPP)
Figure 58. Voltage Limiter Function
VDD = 3.3V, RL = 15μH+8Ω+15μH
fIN = 1kHz, LS_GAIN = 0
Figure 59. No Clip Function
VDD = 3.3V, RL = 15μH+8Ω+15μH
fIN = 1kHz, LS_GAIN = 0
Blue, Green = Output Power vs Input Voltage
Gray, Yellow = THD+N vs Input Voltage
When No Clip is enabled, class D speaker output reduces when it’s about to enter clipping region and power stay
constant as long as VIN is less than VDD for 0 dB volume gain (see Figure 58). For example, in the case of VDD =
3.3V, there is a 6 dB of headroom for the change in input. Please see the ALC typical performance curves for
additional plots relating to different supply voltages and LS_GAIN settings for specific application parameters.
ATTACK TIME
Attack time (tATK) is the time it takes for the gain to be reduced by 6dB (LS_GAIN=0) once the audio signal
exceeds the ALC threshold. Fast attack times allow the ALC to react quickly and prevent transients such as
symbol crashes from being distorted. However, fast attack times can lead to volume pumping, where the gain
reduction and release becomes noticeable, as the ALC cycles quickly. Slower attack times cause the ALC to
ignore the fast transients, and instead act upon longer, louder passages. Selecting an attack time that is too slow
can lead to increased distortion in the case of the No Clip function, and possible output overload conditions in the
case of the Voltage limiter. The attack time is set by a combination of the value of CSET and the attack time
coefficient as given by Equation 2:
tATK = 20kΩCSET / αATK(s)
(2)
Where αATK is the attack time coefficient (Table 14) set by bits B4:B3 in the Voltage Limit Control Register (see
Table 6). The attack time coefficient allows the user to set a nominal attack time. The internal 20kΩ resistor is
subject to temperature change, and it has tolerance between -11% to +20%.
Table 14. Attack Time Coefficient
B4
B3
αATK
0
0
2.667
0
1
2
1
0
1.333
1
1
1
RELEASE TIME
Release time (tRL) is the time it takes for the gain to return from 6dB (LS_GAIN=0) to its normal level once the
audio signal returns below the ALC threshold. A fast release time allows the ALC to react quickly to transients,
preserving the original dynamics of the audio source. However, similar to a fast attack time, a fast release time
contributes to volume pumping. A slow release time reduces the effect of volume pumping. The release time is
set by a combination of the value of CSET and release time coefficient as given by Equation 3:
tRL = 20MΩCSET / αRL(s)
(3)
where αRL is the release time coefficient (Table 15) set by bits B4:B3 in the No Clip Control Register. The release
time coefficient allows the user to set a nominal release time. The internal 20MΩ is subject to temperature
change, and it has tolerance between -11% to +20%.
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Table 15. Release Time Coefficient
B4
B3
αRL
0
0
2
0
1
2.5
1
0
3
1
1
5
A-WEIGHTED FILTER
The human ear is sensitive for acoustic signals within a frequency range from about 20Hz to 20kHz. Within this
range the sensitivity of the human ear is not equal for each frequency. To approach the hearing response,
weighting filters are introduced. One of those filters is the A-weighted filter.
The A-weighted filter is used in signal to noise measurements, where the wanted audio signal is compared to
device noise and distortion.
The use of this filter improves the correlation of the measured values to the way these ratios are perceived by
the human ear.
10
0
-10
dBV
-20
-30
-40
-50
-60
-70
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 60. A-Weighted Filter
PROPER SELECTION OF EXTERNAL COMPONENTS
ALC Timing (CSET) Capacitor Selection
The recommended range value of CSET is between .01μF to 1μF. Lowering the value below .01μF can increase
the attack time but LM49251 ALC ability to regulate its output can be disrupted and approaches the hard limiter
circuit. This in turn increases the THD+N and audio quality will be severely affected.
Charge Pump Capacitor Selection
Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.
Charge Pump Flying Capacitor (C1)
The flying capacitor (C1), see Figure 2, affects the load regulation and output impedance of the charge pump. A
C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued
C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2µF, the RDS(ON)
of the charge pump switches and the ESR of C1 and CPVSS dominate the output impedance. A lower value
capacitor can be used in systems with low maximum output power requirements.
Charge Pump Hold Capacitor (CPVSS)
The value and ESR of the hold capacitor (CPVSS) directly affects the ripple on CPVSS (see Figure 2). Increasing
the value of CPVSS reduces output ripple. Decreasing the ESR of CPVSS reduces both output ripple and charge
pump output impedance. A lower value capacitor can be used in systems with low maximum output power
requirements.
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Input Capacitor Selection
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM49251. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high-pass filter is found using Equation 4 below.
f = 1/ 2πRINCIN(Hz)
(4)
Where the value of RIN is given in the Electrical Characteristics Table.
High-pass filtering the audio signal helps protect the speakers. When the LM49251 is using a single-ended
source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the
power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not
amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance
matching and improved CMRR and PSRR.
Demo Board User Guide
Quick Start Guide:
1. Connect a shunt across pin 1 and pin 2 of JUI to provide 3.3V to I2CVDD.
2. Connect a shunt across JU3 to provide 1.8V to VDDHP from on board regulator.
3. Connect a 4Ω or 8Ω speaker across LSOUTL (left loudspeaker output) and LSOUTR (right loudspeaker
output).
4. Connect stereo headphones to the headphone jack J1.
5. Connect a 3.6V power supply to the VDD pin of J3 and the ground source to the GND pin.
6. Apply audio input signal to any of the stereo (IN1/IN2) or mono (MONO_IN) inputs.
7. Turn on power supply.
8. Connect the mini USB cable to J29 and the other end of the cable to a PC.
9. Open the LM49251 I2C control software.
10. Verify that the device has been acknowledged by looking at bottom left corner of GUI (see Figure 61 and
Figure 62).
11. On GUI:
a. Set POWER: on
b. Set MODE SELECT to desired position (see Table 16).
c. Set all VOLUME CONTROL to 0dB by clicking on Set 0dB button.
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Figure 61. Software Graphic user Interface (GUI)
Figure 62. Error Message displayed on GUI if device is NOT acknowledged (I2C Error)
or if there is an USB error (USB I/O error)
Table 16. Mode Table
SPK(L)
SPK(R)
HP(L)
HP(R)
Datasheet
SD
SD
SD
SD
Mode 0
GST X (L + R)
GST X (L + R)
SD
SD
Mode 1
GST X L
GST X R
SD
SD
Mode 2
GM X M
GM X M
SD
SD
Mode 3
SD
SD
GM X M
GM X M
Mode 4
GM X M
GM X M
GM X M
GM X M
Mode 5
SD
SD
GST X L
GST X R
Mode 6
GST X (L + R)
GST X (L + R)
GST X L
GST X R
Mode 7
GST X L
GST X R
GSTX L
GST X R
Mode 8
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Table 17. Board Connectors
Designator
Function
J1
(HPOUT)
Headphone Output
Comments
J3
(VDD/GND) Loudspeaker
Power Supply
J4
(VDDHP/GND) Headphone
Power Supply
J29
Mini USB
JU1
I2CVDD Select
JU2
(HPOUT)
Headphone Output
JU3
VDDHP = 1.8V
JU4
5V
Ring - Right Channel, Tip - Left Channel
Pin 1 = 3.3V, Pin 2 = I2CVDD, Pin 3 = GND Short Pin 1 and Pin 2 for I2CVDD = 3.3V
Left and Right Channel
Short JU3 for VDDHP = 1.8V from on board regulator
Access to 5V from USB
2
JU6
Apply voltage on J4 when JU3 is open. DO NOT apply voltage if JU3 is closed
I C Clock/Data
GND, SDA, SCL connections
JU7
To program USB controller
LSOUTL
Left Loudspeaker Out
LSOUTR
Right Loudspeaker Out
MONO_IN
Mono Input
IN1
Stereo Input 1
IN2
Stereo Input 2
Bill of Materials
Table 18. Bill of Materials
Ref Designator
Part Description
Manufacturer
Part Number
LM49251TL DEMO BOARD PCB, RevA
TI
U1
LM49251TL
TI
LM49251TL
U2
USB, 25 MIPS, 16 kB Flash, 10-Bit ADC, 32-Pin MixedSignal MCU
Silicon Labs
C8051F320-GQ
U3
Ultra Low Noise, 150mA Linear Regulator for RF/Analog
Circuits Requires No Bypass Capacitor
TI
LP5900TL-1.8/NOPB
C12, C13, C14,
C39, C40
CAP CER 4.7UF 10V X5R 0603 10%
Taiyo Yuden
LMK107BJ475KA-T
C10, C38, C41
CAP .1UF 25V CERAMIC X7R 0603 5%
Kemet
C0603C104J3RACTU
R3
NO LOAD
NO LOAD
NO LOAD
C11, C9, C15,
C8,C7
CAP CER 2.2UF 10V X7R 0603 10%
Murata
GRM188R71A225KE15D
L1, L2
FERRITE CHIP 30 OHM 2200MA 0402
Murata
BLM15PD300SN1D
C22, C37
CAP CERM .47UF 16V X7R 0603 10%
Kemet
C0603C474K4RACTU
C1,
C2,C3,C4,C5,C6
CAP CER .22UF 10V 10% X7R 0603
Murata
GRM188R71A224KA01D
R1, R2 R4, R5
RES 10.0K OHM 1/10W 1% 0603 SMD
Panasonic
ERJ-3EKF1002V
J29
CONN RECEPT MINI USB2.0 5POS
Hirose
UX60-MB-5ST
JU1, JU6, JU7
CONN HEADR BRKWAY .100 03POS STR
Tyco
9-146285-0-03
J3, J4, JU2,
LSOUTL,
LSOUTR, Jw
CONN HEADR BRKWAY .100 02POS STR
Tyco
9-146285-0-02
Mono_IN, In, In1
CONN HDR BRKWAY .100 04POS VERT
Tyco
9-146282-0-04
J1
CONN JACK STEREO 3.5MM HORIZONTAL
Switchcraft
35RAPC4BH3
JU3, JU7, JU1,
Jumper Shunt w/handle, 30μin gold plated, 0.100in pitch
Tyco/AMP
881545-2
32
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM49251
LM49251
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SNAS498A – FEBRUARY 2011 – REVISED APRIL 2013
Demo Board Schematic Diagram
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM49251
33
LM49251
SNAS498A – FEBRUARY 2011 – REVISED APRIL 2013
www.ti.com
Demo Board Layout
34
Figure 63. Top Layer
Figure 64. Layer 2
Figure 65. Layer 3
Figure 66. Bottom Layer
Figure 67. Top Silkscreen
Figure 68. Bottom Silkscreen
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM49251
LM49251
www.ti.com
SNAS498A – FEBRUARY 2011 – REVISED APRIL 2013
Figure 69. Paste Mask Top Layer
Figure 70. Past Mask Bottom Layer
Figure 71. Drill Drawing
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM49251
35
LM49251
SNAS498A – FEBRUARY 2011 – REVISED APRIL 2013
www.ti.com
Revision History
36
Rev
Date
Description
1.0
02/08/11
Initial Web released.
A
04/05/13
Changed layout of National Data Sheet to TI format
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM49251TL/NOPB
ACTIVE
DSBGA
YZR
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GN9
LM49251TLX/NOPB
ACTIVE
DSBGA
YZR
30
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GN9
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM49251TL/NOPB
DSBGA
YZR
30
250
178.0
8.4
LM49251TLX/NOPB
DSBGA
YZR
30
3000
178.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.74
3.15
0.76
4.0
8.0
Q1
2.74
3.15
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM49251TL/NOPB
DSBGA
YZR
LM49251TLX/NOPB
DSBGA
YZR
30
250
210.0
185.0
35.0
30
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0030xxx
0.600±0.075
D
E
TLA30XXX (Rev C)
D: Max = 3.011 mm, Min =2.951 mm
E: Max = 2.547 mm, Min =2.487 mm
4215057/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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