Anpec APW7142 3a, 12v, synchronous-rectified buck converter Datasheet

APW7142
3A, 12V, Synchronous-Rectified Buck Converter
Features
General Description
•
Wide Input Voltage from 4.3V to 14V
The APW7142 is a 3A synchronous-rectified Buck con-
•
Output Current up to 3A
•
Adjustable Output Voltage from 0.8V to VIN
verter with integrated 70mΩ power MOSFETs. The
APW7142, designed with a current-mode control scheme,
can convert wide input voltage of 4.3V to 14V to the output
voltage adjustable from 0.8V to VIN to provide excellent
- ±2% System Accuracy
•
70mΩ Integrated Power MOSFETs
•
High Efficiency up to 95%
output voltage regulation.
For high efficiency over all load current range, the
- Automatic Skip/PWM Mode Operation
•
APW7142 is equipped with an automatic Skip/PWM mode
operation. At light load, the IC operates in the Skip mode,
Current-Mode Operation
- Easy Feedback Compensation
which keeps a constant minimum inductor peak current,
to reduce switching losses. At heavy load, the IC works in
- Stable with Low ESR Output Capacitors
- Fast Load/Line Transient Response
•
PWM mode, which inductor peak current is programmed
by the COMP voltage, to provide high efficiency and excel-
Power-On-Reset Monitoring
•
Fixed 500kHz Switching Frequency in PWM Mode
•
Built-In Digital Soft-Start and Soft-Stop
•
Current-Limit Protection with Frequency Foldback
•
123% Over-Voltage Protection
•
Hiccup-Mode 50% Under-Voltage Protection
•
Over-Temperature Protection
•
<3µA Quiescent Current in Shutdown Mode
•
This device, available in a 8-pin SOP-8 package, provides a very compact system solution with minimal exter-
Small SOP-8 Package
•
nal components and PCB area.
Lead Free and Green Devices Available
lent output voltage regulation.
The APW7142 is also equipped with power-on-reset,
soft-start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature, and current-limit) into a
single package. In shutdown mode, the supply current
drops below 3µA.
(RoHS Compliant)
100
90
Applications
Notebook Computer
•
Handheld Portable Device
•
Step-Down Converters Requiring High Efficiency
Efficiency (%)
•
•
80
OLPC, UMPC
70
60
40
VIN=12V, VOUT=5V, L1=6.8µF
30
20
and 3A Output Current
VIN=5V, VOUT=3.3V, L1=2.2µF
50
10
VIN=12V, VOUT=3.3V, L1=4.7µF
0
0.001
0.01
0.1
1
10
Output Current, IOUT(A)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
1
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APW7142
Ordering and Marking Information
Package Code
K : SOP-8
Operating Junction Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7142
Assembly Material
Handling Code
Temperature Range
Package Code
APW7142 K :
APW7142
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
APW7142
PGND
VIN
AGND
FB
1
8
2
7
3
4
5
6
LX
LX
EN
COMP
SOP-8
Top View
Absolute Maximum Ratings
Symbol
VIN
VLX
(Note 1)
Parameter
VIN Supply Voltage (VIN to AGND)
LX to GND Voltage
- 5 ~ VIN+5
FB, COMP to AGND Voltage
Maximum Junction Temperature
Storage Temperature
Maximum Lead Soldering Temperature, 10 Seconds
V
< 100ns
Power Dissipation
TSTG
-0.3 ~ 15
-1 ~ VIN+1
EN to AGND Voltage
TSDR
Unit
> 100ns
PGND to AGND Voltage
PD
Rating
V
-0.3 ~ +0.3
V
-0.3 ~ VIN+0.3
V
-0.3 ~ 6
V
Internally Limited
W
150
o
-65 ~ 150
o
260
o
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Typical Value
Junction-to-Ambient Thermal Resistance in Free Air (Note 2)
SOP-8
Unit
o
80
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
2
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APW7142
Recommended Operating Conditions (Note 3)
Symbol
VIN
VOUT
Parameter
Range
Unit
VIN Supply Voltage
4.3 ~ 14
V
Converter Output Voltage
0.8 ~ VIN
V
IOUT
Converter Output Current
0~3
A
CIN
Converter Input Capacitor (MLCC)
8 ~ 50
µF
Converter Output Capacitor
20 ~ 1000
µF
COUT
LOUT
Effective Series Resistance
0 ~ 60
mΩ
Converter Output Inductor
1 ~ 22
µH
Resistance of the Feedback Resistor connected from FB to GND
1 ~ 20
kΩ
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
C
C
Note 3: Refer to the Typical Application Circuits
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW7142
Test Conditions
Unit
Min.
Typ.
Max.
SUPPLY CURRENT
IVIN
IVIN_SD
VIN Supply Current
VFB = VREF +50mV, VEN=3V, LX=NC
-
0.5
1.5
mA
VIN Shutdown Supply Current
VEN = 0V
-
-
3
µA
3.9
4.1
4.3
V
-
0.5
-
V
V
POWER-ON-RESET (POR) VOLTAGE THRESHOLD
VIN POR Voltage Threshold
VIN rising
VIN POR Hysteresis
REFERENCE VOLTAGE
VREF
Reference Voltage
Output Voltage Accuracy
-
0.8
-
TJ = 25oC, IOUT=10mA, VIN=12V
Regulated on FB pin
-1.0
-
+1.0
IOUT=10mA~3A, VIN=4.75~14V
-2.0
-
+2.0
%
Line Regulation
VIN = 4.75V to 14V
-
+0.02
-
%/V
Load Regulation
IOUT = 0.5A ~ 3A
-
-0.04
-
%/A
450
500
550
kHz
OSCILLATOR AND DUTY CYCLE
FOSC
TON_MIN
Oscillator Frequency
TJ = -40 ~ 125oC, VIN = 4.75 ~ 14V
Foldback Frequency
VOUT = 0V
-
80
-
kHz
Maximum Converter’s Duty
-
99
-
%
Minimum Pulse Width of LX
-
150
-
ns
Error Amplifier Transconductance VFB=VREF±50mV
-
200
-
µA/V
Error Amplifier DC Gain
-
80
-
dB
CURRENT-MODE PWM CONVERTER
Gm
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
COMP = NC
3
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APW7142
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C,
unless otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APW7142
Test Conditions
Unit
Min.
Typ.
Max.
-
0.048
-
VIN = 5V, TJ=25°C
-
90
110
VIN = 12V, TJ=25°C
-
70
90
VIN = 5V, TJ=25°C
-
90
110
VIN = 12V, TJ=25°C
-
70
90
CURRENT-MODE PWM CONVERTER (CONT.)
Current-Sense to COMP Voltage
Transresistance
High-side Switch Resistance
Low-side Switch Resistance
V/A
mΩ
mΩ
PROTECTIONS
High-Side Switch Current-Limit
Peak Current
4.0
5.5
7.0
A
VTH_UV
FB Under-Voltage Threshold
VFB falling
45
50
55
%
VTH_OV
FB Over-Voltage Threshold
VFB rising
ILIM
TOTP
118
123
128
%
FB Under-Voltage Debounce
-
1
-
µs
Over-Temperature Trip Point
-
150
-
o
Over-Temperature Hysteresis
TD
Dead-Time
VLX = -0.7V
C
-
40
-
o
-
20
-
ns
1.5
2
2.5
ms
C
SOFT-START, SOFT-STOP, ENABLE AND INPUT CURRENTS
TSS
Soft-Start / Soft-Stop Interval
EN Logic Low Voltage
VEN falling
-
-
0.5
V
EN Logic High Voltage
VEN rising
2.1
-
-
V
High-Side Switch Leakage Current
VEN = 0V, VLX = 0V
-
-
2
µA
-100
-
+100
nA
-100
-
+100
nA
IFB
FB Pin Input Current
IEN
EN Pin Input Current
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
VEN = 0V ~ VIN
4
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APW7142
Typical Operating Characteristics
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
Output Current vs. Efficiency
Output Voltage vs. Output Current
3.4
90
3.38
Output Voltage, VOUT (V)
100
Efficiency (%)
80
70
60
VIN=5V, VOUT=3.3V, L1=2.2µF
50
40
VIN=12V, VOUT=5V, L1=6.8µF
30
3.36
3.34
3.32
3.3
3.28
3.26
3.24
20
VIN=12V, VOUT=3.3V, L1=4.7µF
10
0
0.001
0.01
0.1
1
3.22
3.2
10
0
1
Current Limit Level (Peak Current)
3.4
IOUT=500mA
3.38
Output Voltage, VOUT (V)
Current Limit Level, ILIM(A)
3
Output Voltage vs. Supply Voltage
vs. Junction Temperature
7
2
Output Current, IOUT(A)
Output Current, IOUT(A)
6.5
6
5.5
3.36
3.34
3.32
3.3
3.28
3.26
3.24
5
3.22
4.5
-40 -20
3.2
0
20
40
60
80 100 120 140
4
6
o
Junction Temperature, TJ ( C)
VIN Input Current vs. Supply Voltage
12
14
0.816
VFB=0.85V
0.812
Reference Voltage, VREF (V)
VIN Input Current, I VIN(mA)
10
Reference Voltage vs. Junction Temperature
2.0
1.5
1.0
0.5
0.0
8
Supply Voltage, VIN (V)
0
2
4
6
8
10
12
0.804
0.800
0.796
0.792
0.788
0.784
-50
14
Supply Voltage, VIN (V)
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
0.808
-25
0
25
50
75 100 125 150
Junction Temperature, TJ (oC)
5
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APW7142
Typical Operating Characteristics (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
Oscillator Frequency, FOSC(kHz)
550
Oscillator Frequency vs.
Junction Temperature
540
530
520
510
500
490
480
470
460
450
-50 -25
0
25
50
75
100 125 150
o
Junction Temperature, TJ ( C)
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
6
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APW7142
Operating Waveforms
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
Power On
Power Off
IOUT=3A
IOUT=3A
VIN
VIN
1
1
VOUT
VOUT
2
2
IL1
IL1
3
3
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 2A/div
Time : 1ms/div
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 2A/div
Time : 10ms/div
Enable
Shutdown
IOUT=3A
IOUT=3A
VEN
VEN
1
1
VOUT
2
VOUT
2
IL1
IL1
3
3
CH1 : VEN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 2A/div
Time : 1ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
CH1 : VEN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IL1, 2A/div
Time : 100µs/div
7
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APW7142
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
Short Circuit
Short Circuit
IOUT =3~7A
VOUT is shorted to GND by a short wire
VLx
1
VLX
1
VOUT
VOUT
2
2
IL1
IL1
3
3
CH1 : VLX , 5V/div
CH2 : VOUT , 200mV/div
CH3 : IL1 , 5A/div
Time : 5ms/div
CH1 : VLX , 10V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 5A/div
Time : 20µs/div
Load Transient Response
Load Transient Response
IOUT= 0.5A-> 3A ->0.5A
IOUT rising/falling time=10µs
IOUT= 50mA-> 3A ->50mA
IOUT rising/falling time=10µs
VOUT
1
1
VOUT
IL1
IL1
2
2
CH1 : VOUT , 200mV/div
CH2 : IL1 , 2A/div
Time : 100µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
CH1 : VOUT , 100mV/div
CH2 : IL1 , 2A/div
Time : 100µs/div
8
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APW7142
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
Switching Waveform
Switching Waveform
VLX
VLX
IOUT=0.2A
IOUT=3A
1
1
IL1
IL1
2
2
CH1 : VLX , 5V/div
CH2 : IL1 , 2A/div
Time : 1µs/div
CH1 : VLX , 5V/div
CH2 : IL1 , 2A/div
Time : 1µs/div
Line Transient
VIN= 5~12V
Over-Voltage Protection
VIN
VIN rising/falling time=20µs
VIN
VOUT
1
1
VOUT
2
2
VLX
3
IL1
4
IL1
3
IOUT=-1A
CH1 : VIN , 5V/div
CH2 : VOUT , 50mV/div (Voffset=3.3V)
CH3 : IL1 , 2A/div
Time : 100µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH3 : VLX , 5V/div
CH4 : IL1 , 5A/div
Time : 20µs/div
9
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APW7142
Pin Description
PIN
FUNCTION
NO.
NAME
1
PGND
2
VIN
3
AGND
4
FB
Output feedback Input. The APW7142 senses the feedback voltage via FB and
regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s
output sets the output voltage from 0.8V to VIN.
5
COMP
Output of the error amplifier. Connect a series RC network from the COMP to the GND to
compensate the regulation control loop. In some cases, an additional capacitor from the
COMP to the GND is required.
6
EN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn
on the regulator, drive it low to turn it off. Connect this pin to the VIN if it is not used.
7, 8
LX
Power Switching Output. LX is the junction of the high-side and low-side power
MOSFETs to supply power to the output LC filter.
Power Ground of the APW7142, which is the source of the N-channel power MOSFET.
Connect this pin to system ground with lowest impedance.
Power Input. VIN supplies the power (4.3V to 14V) to the control circuitry, gate drivers
and step-down converter switches. Connecting a ceramic bypass capacitor and a
suitably large capacitor between VIN and both of AGND and PGND eliminates switching
noise and voltage ripple on the input to the IC.
Ground of MOSFET Gate Drivers and Control Circuitry.
Block Diagram
VIN
Current Sense
Amplifier
Power-OnReset
Zero-Crossing
Comparator
POR
OVP
123%VREF
50%VREF
UVP
UG
Soft-Start /
Soft-Stop
and
Fault Logic
Gate
Driver
Soft-Start /
Soft-Stop
FB
Inhibit
LX
Gate
Control
Gm
VREF
VIN
Current
Limit
Error
Amplifier
VIN
LG
Current
Compartor
COMP
Gate
Driver
PGND
Slope
Compensation
EN
Enable
1.5V
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
Over
Temperature
Protection
FB
10
Oscillator
500kHz
AGND
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APW7142
Typical Application Circuits
1. 4.3~14V Single Power Input Step-Down Converter (with a Ceramic Output Capacitor)
VIN
C1
2
VIN
L1
Enable
6
LX
8
7
PGND
1
EN
U1 LX
APW7142
Shutdown
5 COMP
R3
±5%
FB
AGND
3
C3
±
30%
VOUT
C2
R1
±
1%
4
R2
±1%
C4
±30%, Optional
a. Cost-effective Feedback Compensation (C4 is not connected)
VIN(V)
VOUT(V)
L1(µH)
C2(µF)
C2 ESR(mΩ)
R1(kΩ)
R2(kΩ)
R3(kΩ)
C3(pF)
12
5
6.8
22
5
63.0
12
10.0
1500
12
5
6.8
44
3
63.0
12
20.0
1500
12
3.3
4.7
22
5
46.9
15
10.0
1500
12
3.3
4.7
44
3
46.9
15
22.0
1500
12
2
3.3
22
5
30.0
20
10.0
1500
12
2
3.3
44
3
30.0
20
20.0
1500
12
1.2
2.2
22
5
7.5
15
8.2
1800
12
1.2
2.2
44
3
7.5
15
16.0
1800
5
3.3
2.2
22
5
46.9
15
8.2
680
5
3.3
2.2
44
3
46.9
15
20.0
680
5
1.2
2.2
22
5
7.5
15
3.0
1800
5
1.2
2.2
44
3
7.5
15
7.5
1800
b. Fast-Transient-Response Feedback Compensation (C4 is connected)
VIN(V)
VOUT(V)
L1(µH)
C2(µF)
C2 ESR(mΩ)
R1(kΩ)
R2(kΩ)
C4(pF)
R3(kΩ)
C3(pF)
12
5
6.8
22
5
63.0
12
47
33.0
470
12
5
6.8
44
3
63.0
12
47
68.0
470
12
3.3
4.7
22
5
46.9
15
47
22.0
680
12
3.3
4.7
44
3
46.9
15
47
47.0
680
12
2
3.3
22
5
30.0
20
47
13.0
1200
12
2
3.3
44
3
30.0
20
47
27.0
1200
12
1.2
2.2
22
5
7.5
15
150
7.5
2200
12
1.2
2.2
44
3
7.5
15
150
15.0
2200
5
3.3
2.2
22
5
46.9
15
56
20.0
220
5
3.3
2.2
44
3
46.9
15
56
43.0
220
5
1.2
2.2
22
5
7.5
15
330
3.3
1800
5
1.2
2.2
44
3
7.5
15
330
8.2
1500
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
11
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APW7142
Typical Application Circuits (Cont.)
2. +12V Single Power Input Step-Down Converter (with an Electrolytic Output Capacitor)
C1
2.2µF
2
C5
470µF
VIN
12V
VIN
L1
4.7µH /3A
Enable
6
Shutdown
LX
U1
LX
APW7142
PGND
5 COMP
8
7
FB
4
EN
R3
62K
±5%
C3
680pF
±30%
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
AGND
3
1
R1
46.9K
±1%
R2
15K
±1%
12
VOUT
3.3V/3A
C2
470µF
(ESR=30mΩ)
C4
47pF
±30%
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APW7142
Function Description
VIN Power-On-Reset (POR)
The APW7142 keeps monitoring the voltage on VIN pin to
prevent wrong logic operations which may occur when
The under-voltage threshold is 50% of the nominal output voltage. The under-voltage comparator has a built-in
2µs noise filter to prevent the chips from wrong UVP shut-
VIN voltage is not high enough for the internal control
circuitry to operate. The VIN POR has a rising threshold of
down being caused by noise. The under-voltage protection works in a hiccup mode without latched shutdown.
4.1V (typical) with 0.5V of hysteresis.
During startup, the VIN voltage must exceed the enable
The IC will initiate a new soft-start process at the end of
the preceding delay.
voltage threshold. Then, the IC starts a start-up process
and ramps up the output voltage to the voltage target.
Over-Voltage Protection (OVP)
Digital Soft-Start
The over-voltage function monitors the output voltage by
The APW7142 has a built-in digital soft-start to control the
rise rate of the output voltage and limit the input current
FB pin. When the FB voltage increases over 123% of the
reference voltage due to the high-side MOSFET failure or
surge during start-up. During soft-start, an internal voltage ramp (VRAMP), connected to one of the positive inputs
for other reasons, the over-voltage protection comparator
will force the low-side MOSFET gate driver high. This ac-
of the error amplifier, rises up from 0V to 0.95V to replace
the reference voltage (0.8V) until the voltage ramp reaches
tion actively pulls down the output voltage and eventually
attempts to blow the internal bonding wires. As soon as
the reference voltage.
During soft-start without output over-voltage, the APW7142
the output voltage is within regulation, the OVP comparator is disengaged. The chip will restore its normal
converter’s sinking capability is disabled until the output
voltage reaches the voltage target.
operation. This OVP scheme only clamps the voltage
overshoot, and does not invert the output voltage when
Digital Soft-Stop
otherwise activated with a continuously high output from
low-side MOSFET driver - a common problem for OVP
At the moment of shutdown controlled by EN signal, un-
schemes with a latch.
der-voltage event or over-temperature protection, the
APW7142 initiates a digital soft-stop process to discharge
Over-Temperature Protection (OTP)
the output voltage in the output capacitors. Certainly, the
load current also discharges the output voltage.
The over-temperature circuit limits the junction temperature of the APW7142. When the junction temperature ex-
During soft-stop, the internal voltage ramp (VRAMP) falls
down rises from 0.95V to 0V to replace the reference
ceeds TJ = +150oC, a thermal sensor turns off the both
power MOSFETs, allowing the devices to cool. The ther-
voltage. Therefore, the output voltage falls down slowly at
the light load. After the soft-stop interval elapses, the soft-
mal sensor allows the converters to start a start-up process and to regulate the output voltage again after the
stop process ends and the the IC turns on the low-side
power MOSFET.
junction temperature cools by 40oC. The OTP is designed
with a 40 oC hysteresis to lower the average TJ during
Output Under-Voltage Protection (UVP)
continuous thermal overload conditions, increasing lifetime of the APW7142.
In the operational process, if a short-circuit occurs, the
Enable/Shutdown
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the re-
Driving EN to the ground initiates a soft-stop process and
quired regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
then places the APW 7142 in shutdown. W hen in
shutdown, after the soft-stop process is completed, the
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC shuts down
internal power MOSFETs turn off, all internal circuitry shuts
down and the quiescent supply current reduces to less
converter’s output.
than 3µA.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
13
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APW7142
Function Description (Cont.)
Current-Limit Protection
The APW7142 monitors the output current, flows through
the high-side power MOSFET, and limits the current peak
at current-limit level to prevent loads and the IC from damaging during overload or short-circuit conditions.
Frequency Foldback
The foldback frequency is controlled by the FB voltage.
When the output is shortened to the ground, the frequency
of the oscillator will be reduced to 80kHz. This lower frequency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s frequency will gradually increase to its designed rate when
the feedback voltage on the FB again approaches 0.8V.
Copyright  ANPEC Electronics Corp.
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14
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APW7142
Application Information
T=1/FOSC
Setting Output Voltage
The regulated output voltage is determined by:
VOUT = 0.8 × (1 +
R1
)
R2
VLX
(V)
Suggested R2 is in the range from 1k to 20kΩ. For por-
DT
I
IOUT
IL
table applications, a 10k resistor is suggested for R2. To
prevent stray pickup, please locate resistors R1 and R2
IOUT
close to APW7142.
IQ1
I
Input Capacitor Selection
ICOUT
Use small ceramic capacitors for high frequency
VOUT
decoupling and bulk capacitors to supply the surge current needed each time the P-channel power MOSFET (Q1)
VOUT
turns on. Place the small ceramic capacitors physically
close to the VIN and between the VIN and the GND.
Figure 1 Converter Waveforms
The important parameters for the bulk input capacitor are
Output Capacitor Selection
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and cur-
An output capacitor is required to filter the output and sup-
rent ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor volt-
ply the load transient current. The filtering requirements
are the function of the switching frequency and the ripple
age rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times
current (∆I). The output ripple is the sum of the voltages,
having phase shift, across the ESR, and the ideal output
is a conservative guideline. The RMS current (IRMS) of the
bulk input capacitor is calculated as the following equation:
capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations:
D=
VOUT
VIN
........... (1)
where D is the duty cycle of the power MOSFET.
For a through hole design, several electrolytic capacitors
∆I =
........... (2)
may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exer-
VOUT ·(1 - D)
FOSC ·L
VESR = ∆I. ⋅ ESR
IRMS= IOUT× D×(1- D)
(A)
........... (3)
cised with regard to the capacitor surge current rating.
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equations:
VIN
VIN
IQ1
CIN
∆VCOUT =
Q1
IL
LX
Q2
VOUT
ICOUT
........... (4)
For the applications using bulk capacitors, the ∆VCOUT is
IOUT
L
∆I
(V)
8 ⋅ FOSC ⋅ COUT
much smaller than the VESR and can be ignored. Therefore,
the AC peak-to-peak output voltage (∆VOUT ) is shown as
ESR
below:
COUT
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
∆VOUT = ∆ I ⋅ ESR
15
(V)
........... (5)
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APW7142
Application Information (Cont.)
Output Capacitor Selection (Cont.)
where VIN = VIN(MAX)
For the applications using ceramic capacitors, the VESR is
much smaller than the ∆V COUT and can be ignored.
Layout Consideration
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
close to ∆VCOUT .
In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In
The load transient requirements are the function of the
slew rate (di/dt) and the magnitude of the transient load
general, interconnecting impedance should be minimized
by using short and wide printed circuit traces. Signal and
current. These requirements are generally met with a mix
of capacitors and careful layout. High frequency capaci-
power grounds are to be kept separating and finally combined using the ground plane construction or single point
tors initially supply the transient and slow the current load
rate seen by the bulk capacitors. The bulk filter capacitor
grounding. Figure 2 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
values are generally determined by the ESR (Effective
Series Resistance) and voltage rating requirements rather
lines should be placed close together. The following is a
checklist for your layout:
than actual capacitance requirements.
High frequency decoupling capacitors should be placed
1. Firstly, to initial the layout by placing the power
components. Orient the power circuitry to achieve a
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
clean power flow path. If possible, make all the connections on one side of the PCB with wide and copper
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
filled areas.
2
+
VIN
-
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the Equiva-
VIN
lent Series Inductance (ESL) of these capacitors increases
with case size and can reduce the usefulness of the ca-
6
pacitor to the high slew-rate transient loading.
EN
5 COMP PGND
related in that higher operating frequencies permit the
use of a smaller inductor for the same amount of inductor
FB
R3
C3
AGND
3
ripple current. However, this is at the expense of efficiency
due to an increase in MOSFET gate charge losses. The
equation (2) shows that the inductance value has a direct
effect on ripple current.
+
C2 Load
VOUT
-
1
4
R2
R1
C4
(Optional)
Feedback
Divider
2. In Figure 2, the loops with the same color bold lines
conduct high slew rate current. These interconnect-
Accepting larger values of ripple current allows the use of
low inductances, but results in higher output voltage ripple
ing impedances should be minimized by using wide
and short printed circuit traces.
and greater core losses. A reasonable starting point for
setting ripple current is ∆I ≤ 0.4x IOUT(MAX) . Remember, the
3. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB.
maximum ripple current occurs at the maximum input
voltage. The minimum inductance of the inductor is cal-
Therefore place the feedback divider and the feedback
compensation network close to the IC to avoid switch-
culated by using the following equation:
ing noise. Connect the ground of feedback divider directly to the AGND pin of the IC using a dedicated
VOUT ·(VIN - VOUT)
≤ 1.2
500000 ·L ·VIN
VOUT ·(VIN - VOUT )
600000 ·VIN
L1
LX
LX 7
U1
APW7142
Compensation
Network
Inductor Value Calculation
The operating frequency and inductor selection are inter-
L≥
C1
8
ground trace.
(H)
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
........... (6)
16
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APW7142
Application Information (Cont.)
Layout Consideration (Cont.)
4. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. Use a wide power ground
plane to connect the C1 and C2 to provide a low impedance path between the components for large and
high slew rate current.
C2
C1
VIN
1
Ground
SOP-8
2
3
8 V
LX
7
L1
VOUT
6
5
4
APW7142
Ground
Figure 3 Recommended Layout Diagram
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
17
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APW7142
Package Information
SOP-8
D
E
E1
SEE VIEW A
h X 45
°
c
A
0.25
b
GAUGE PLANE
SEATING PLANE
A1
A2
e
L
VIEW A
S
Y
M
B
O
L
SOP-8
MILLIMETERS
MIN.
INCHES
MAX.
A
MIN.
MAX.
1.75
0.069
0.004
0.25
0.010
A1
0.10
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
5.80
6.20
0.228
0.244
3.80
4.00
0.150
0.157
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
0°
8°
0°
E
E1
e
0.049
1.27 BSC
0.050 BSC
8°
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
18
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APW7142
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
SOP-8
4.0±0.10
8.0±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP-8
Tape & Reel
2500
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Rev. A.6 - Nov., 2010
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APW7142
Taping Direction Information
SOP-8
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
20
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APW7142
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
ESD
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD 78
21
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV, VMM≧200V
10ms, 1tr≧100mA
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APW7142
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
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