AD AD9235BCP-40 12-bit, 20/40/65 msps 3 v a/d converter Datasheet

a
FEATURES
Single 3 V Supply Operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low Power: 300 mW at 65 MSPS
Differential Input with 500 MHz Bandwidth
On-Chip Reference and SHA
DNL = 0.4 LSB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
IS-95, CDMA-One, IMT-2000
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
12-Bit, 20/40/65 MSPS
3 V A/D Converter
AD9235
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
VIN+
SHA
MDAC1
VIN–
8-STAGE
1 1/2-BIT PIPELINE
4
REFT
A/D
3
16
A/D
REFB
CORRECTION LOGIC
12
OTR
OUTPUT BUFFERS
D11
AD9235
D0
VREF
CLOCK
DUTY CYCLE
STABLIZER
SENSE
REF
SELECT
MODE
SELECT
0.5V
AGND
CLK
PDWN
MODE
DGND
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters. This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9235 uses a multistage differential
pipelined architecture with output error correction logic to provide
12-bit accuracy at 20/40/65 MSPS data rates and guarantee
no missing codes over the full operating temperature range.
1. The AD9235 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate
2.5 V and 3.3 V logic families.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
analog-to-digital converters, the AD9235 is suitable for applications in communications, imaging, and medical ultrasound.
2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
3. The patented SHA input maintains excellent performance
for input frequencies up to 100 MHz and can be configured
for single-ended or differential operation.
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulsewidths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance. The digital output data is presented
in straight binary or twos complement formats. An out-of-range
(OTR) signal indicates an overflow condition that can be used
with the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9235 is available
in a 28-lead thin shrink small outline package (TSSOP) and a
32-lead chip scale package (LFCSP) and is specified over the
industrial temperature range (–40°C to +85°C).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9235–SPECIFICATIONS
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input,
MIN to TMAX, unless otherwise noted.)
DC SPECIFICATIONS 1.0 V internal reference, T
Parameter
Temp
Test
Level
AD9235BRU-20
Min Typ
Max
AD9235BRU-40
Min Typ
Max
RESOLUTION
Full
VI
12
12
Full
Full
Full
Full
25°C
Full
25°C
VI
VI
VI
IV
I
IV
I
12
TEMPERATURE DRIFT
Offset Error
Gain Error1
Full
Full
V
V
±2
± 12
INTERNAL VOLTAGE
REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
Full
Full
Full
Full
VI
V
V
V
±5
0.8
± 2.5
0.1
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
25°C
25°C
V
V
0.54
0.27
0.54
0.27
0.54
0.27
LSB rms
LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance3
Full
Full
Full
IV
IV
V
1
2
7
1
2
7
1
2
7
V p-p
V p-p
pF
REFERENCE INPUT
RESISTANCE
Full
V
7
7
7
kΩ
Full
Full
IV
IV
Full
Full
Full
V
V
V
30
2
± 0.01
Full
Full
Full
V
VI
V
90
95
1.0
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL) 2
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input4
Sine Wave Input2
Standby Power5
12
12
± 0.30
± 0.30
± 0.35
± 0.35
± 0.45
± 0.40
2.7 3.0
2.25 3.0
± 1.20
± 2.40
± 0.65
± 0.80
3.6
3.6
± 1.20
± 2.50
± 0.75
± 0.90
±5
0.8
± 2.5
0.1
2.7 3.0
2.25 3.0
165
180
1.0
± 0.50
± 0.50
± 0.40
± 0.35
± 0.70
± 0.45
± 1.20
± 2.60
± 0.80
± 1.30
±3
± 12
± 35
3.6
3.6
55
5
± 0.01
110
Bits
12
± 0.50
± 0.50
± 0.35
± 0.35
± 0.50
± 0.40
±2
± 12
± 35
AD9235BRU/BCP-65
Min Typ
Max
Unit
±5
0.8
± 2.5
0.1
2.7 3.0
2.25 3.0
ppm/°C
ppm/°C
± 35
3.6
3.6
100
7
± 0.01
205
300
320
1.0
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
mV
mV
mV
mV
V
V
mA
mA
% FSR
350
mW
mW
mW
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate, f IN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
–2–
REV. B
AD9235
DIGITAL SPECIFICATIONS
Parameter
Temp
Test
Level
AD9235BRU-20
Min Typ
Max
AD9235BRU-40
AD9235BRU/BCP-65
Min
Typ
Max Min
Typ
Max Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
2.0
2.0
Full
IV
3.29
3.29
3.29
V
Full
IV
3.25
3.25
3.25
V
Full
IV
0.2
0.2
0.2
V
Full
IV
0.05
0.05
0.05
V
Full
IV
2.49
2.49
2.49
V
Full
IV
2.45
2.45
2.45
V
Full
IV
0.2
0.2
0.2
V
Full
IV
0.05
0.05
0.05
V
LOGIC OUTPUTS*
DRVDD = 3.3 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
DRVDD = 2.5 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
0.8
+10
+10
–10
–10
2.0
0.8
+10
+10
–10
–10
2
0.8
+10
+10
–10
–10
2
2
V
V
µA
µA
pF
*Output voltage levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameter
Temp
Test
Level
AD9235BRU-20
Min Typ
Max
AD9235BRU-40
Min
Typ
Max
AD9235BRU/BCP-65
Min
Typ
Max Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulsewidth High1
CLK Pulsewidth Low1
Full
Full
Full
Full
Full
VI
V
V
V
V
20
40
DATA OUTPUT PARAMETERS
Output Delay2 (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty Jitter (t J)
Wake-Up Time3
Full
Full
Full
Full
Full
V
V
V
V
V
3.5
7
1.0
0.5
3.0
3.5
7
1.0
0.5
3.0
3.5
7
1.0
0.5
3.0
ns
Cycles
ns
ps rms
ms
OUT-OF-RANGE RECOVERY
TIME
Full
V
1
1
2
Cycles
65
1
1
50.0
15.0
15.0
1
25.0
8.8
8.8
15.4
6.2
6.2
NOTES
1
For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
N
N+1
N+2
N–1
tA
ANALOG
INPUT
N+8
N+3
N+7
N+4
N+5
N+6
CLK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
tPD = 6.0ns MAX
2.0ns MIN
Figure 1. Timing Diagram
REV. B
–3–
N–1
N
MSPS
MSPS
ns
ns
ns
AD9235–SPECIFICATIONS
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input, AIN = –0.5 dBFS,
MIN to TMAX, unless otherwise noted.)
AC SPECIFICATIONS 1.0 V internal reference, T
Parameter
SIGNAL-TO-NOISE RATIO
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE RATIO
AND DISTORTION
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
TOTAL HARMONIC
DISTORTION
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
WORST HARMONIC
(Second or Third)
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
SPURIOUS FREE DYNAMIC
RANGE
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
Temp
Test
Level
AD9235BRU-20
Min Typ
Max
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
–88.0
–86.0
–87.4
Full
Full
Full
IV
IV
IV
–90.0
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
70.0
AD9235BRU-40
AD9235BRU/BCP-65
Min
Typ
Max Min
Typ
Max Unit
70.8
70.4
70.6
70.6
69.9
70.5
70.3
70.4
68.7
69.9
68.7
68.5
69.7
70.1
68.3
70.6
70.3
70.5
70.5
70.4
69.7
68.3
69.5
69.9
67.8
–89.0
–87.5
–79.0
–85.5
–86.0
–84.0
–79.0
–81.8
–82.0
–78.0
–82.5
–80.0
–83.5
92.0
88.5
91.0
92.0
80.0
92.0
89.0
90.0
74.0
84.0
–74.0
–80.0
–90.0
80.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
70.2
70.3
68.3
68.6
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
85.0
83.0
85.0
80.5
–74.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Specifications subject to change without notice.
–4–
REV. B
AD9235
ABSOLUTE MAXIMUM RATINGS 1
EXPLANATION OF TEST LEVELS
I
100% production tested.
Pin Name
With
Respect to Min
Max
Unit
ELECTRICAL
AVDD
DRVDD
AGND
AVDD
Digital Outputs
CLK, MODE
VIN+, VIN–
VREF
SENSE
REFB, REFT
PDWN
II 100% production tested at 25°C and sample tested at
specified temperatures.
AGND
DGND
DGND
DRVDD
DGND
AGND
AGND
AGND
AGND
AGND
AGND
–0.3
–0.3
–0.3
–3.9
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+3.9
+3.9
+0.3
+3.9
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
V
V
V
V
V
V
V
V
V
V
V
III Sample tested only.
–40
+85
150
300
+150
°C
°C
°C
°C
ENVIRONMENTAL2
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
–65
IV Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for military
devices.
NOTES
1
Absolute maximum ratings are limiting values to be applied individually and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (28-lead TSSOP), θJA = 67.7°C/W; (32-lead LFCSP),
θJA = 32.5°C/W, θJC = 32.71°C/W. These measurements were taken on a 4-layer
board in still air, in accordance with EIA/JESD51-1.
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option
AD9235BRU-20
AD9235BRU-40
AD9235BRU-65
AD9235BCP-20*
AD9235BCP-40*
AD9235BCP-65*
AD9235-20PCB
AD9235-40PCB
AD9235-65PCB
AD9235BCP-20EB
AD9235BCP-40EB
AD9235BCP-65EB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
RU-28
RU-28
RU-28
CP-32
CP-32
CP-32
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
32-Lead Lead Frame Chip Scale Package (LFCSP) (Contact Factory)
32-Lead Lead Frame Chip Scale Package (LFCSP) (Contact Factory)
32-Lead Lead Frame Chip Scale Package (LFCSP)
TSSOP Evaluation Board
TSSOP Evaluation Board
TSSOP Evaluation Board
LFCSP Evaluation Board (Contact Factory)
LFCSP Evaluation Board (Contact Factory)
LFCSP Evaluation Board
*It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of
the package is achieved with exposed paddle soldered to the customer board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9235 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
WARNING!
ESD SENSITIVE DEVICE
AD9235
PIN CONFIGURATION
28 D11 (MSB)
OTR 1
MODE 2
27 D10
SENSE 3
26 D9
VREF 4
25 D8
REFB 5
32-Lead LFCSP
32 AVDD
31 AGND
30 VIN–
29 VIN+
28 AGND
27 AVDD
26 REFT
25 REFB
28-Lead TSSOP
AD9235
DNC 1
CLK 2
DNC 3
PDWN 4
DNC 5
DNC 6
(LSB)D0 7
D1 8
24 DRVDD
AGND 8
21 D6
VIN+ 9
20 D5
VIN– 10
19 D4
AGND 11
18 D3
AVDD 12
17 D2
CLK 13
16 D1
PDWN 14
AD9235
TOP VIEW
(Not to Scale)
24 VREF
23 SENSE
22 MODE
21 OTR
20 D11(MSB)
19 D10
18 D9
17 D8
D2 9
D3 10
D4 11
D5 12
D6 13
D7 14
DGND 15
DRVDD 16
REFT 6
TOP VIEW 23 DGND
AVDD 7 (Not to Scale) 22 D7
PIN 1
INDICATOR
15 D0 (LSB)
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Description
28-Lead
TSSOP
32-Lead
LFCSP
1
2
3
4
5
6
7, 12
8, 11
9
10
13
14
15–22,
25–28
23
24
21
22
23
24
25
26
27, 32
28, 31
29
30
2
4
7-14,
17-20
15
16
OTR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
VIN–
CLK
PDWN
D0 (LSB)–D11(MSB)
Out-of-Range Indicator.
Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.
Reference Mode Selection.
Voltage Reference Input/Output.
Differential Reference (–).
Differential Reference (+).
Analog Power Supply.
Analog Ground.
Analog Input Pin (+).
Analog Input Pin (–).
Clock Input Pin.
Power-Down Function Selection (Active High).
Data Output Bits.
DGND
DRVDD
1, 3, 5, 6
DNC
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DGND with a minimum
0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.
Do Not Connect.
–6–
REV. B
AD9235
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Signal-to-Noise and Distortion (SINAD)*
The ratio of the rms signal amplitude (set 0.5 dB below full scale)
to the rms value of the sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
Effective Number of Bits (ENOB)
The effective number of bits for a device for sine wave inputs at
a given input frequency can be calculated directly from its measured SINAD using the following formula
N = (SINAD − 1.76) 6.02
Aperture Jitter (tJ)
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSBs beyond
the last code transition. The deviation is measured from the
middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096 codes
must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value 1/2 LSB
below VIN+ = VIN–. Offset error is defined as the deviation of
the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur
at an analog value 1 1/2 LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Signal-to-Noise Ratio (SNR)*
The ratio of the rms signal amplitude (set at 0.5 dB below
full scale) to the rms value of the sum of all other spectral
components below the Nyquist frequency, excluding the first six
harmonics and dc.
Spurious Free Dynamic Range (SFDR)*
The difference in dB between the rms amplitude of the input signal
and the peak spurious signal.
Two-Tone SFDR*
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulsewidth and Duty Cycle
Pulsewidth high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated performance. Pulsewidth low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Temperature Drift
Output Propagation Delay (tPD)
The temperature drift for offset error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Power Supply Rejection Ratio
The time it takes for the ADC to reacquire the analog input after
a transition from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum
limit.
Out-of-Range Recovery Time
Total Harmonic Distortion (THD)*
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
*AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
REV. B
–7–
AD9235
Equivalent Circuits
DRVDD
AVDD
D11–D0,
OTR
VIN+, VIN–
Figure 4. Equivalent Digital Output Circuit
Figure 2. Equivalent Analog Input Circuit
AVDD
AVDD
MODE
CLK,
PDWN
20k⍀
Figure 3. Equivalent MODE Input Circuit
Figure 5. Equivalent Digital Input Circuit
–8–
REV. B
AD9235
Typical Performance Characteristics
(AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS Disabled, TA = 25C, 2 V Differential Input, AIN = –0.5 dBFS, VREF = 1.0 V,
unless otherwise noted.)
0
100
SNR = 70.3dBc
SINAD = 70.2dBc
ENOB = 11.4 BITS
THD = –86.3dBc
SFDR = 89.9dBc
MAGNITUDE (dBFS)
–20
SFDR (2V DIFF)
95
90
85
SNR/SFDR (dBc)
–40
–60
–80
80
SNR (2V SE)
75
70
65
SNR (2V DIFF)
60
–100
55
–120
0.0
6.5
13.0
19.5
FREQUENCY (MHz)
32.5
26.0
SFDR (2V SE)
50
40
45
50
60
55
65
SAMPLE RATE (MSPS)
TPC 1. Single Tone 8K FFT with fIN = 10 MHz
TPC 4. AD9235-65: Single Tone SNR/SFDR vs. fCLK with
fIN = Nyquist (32.5 MHz)
100
0
SNR = 69.4dBc
SINAD = 69.1dBc
ENOB = 11.2 BITS
THD = –81.0dBc
SFDR = 83.8dBc
–20
95
90
SNR/SFDR (dBc)
MAGNITUDE (dBFS)
85
–40
–60
–80
SFDR (2V DIFF)
80
SNR (2V SE)
SNR (2V DIFF)
75
70
65
60
SFDR (2V SE)
–100
55
–120
65.0
71.5
78.0
84.5
FREQUENCY (MHz)
50
20
91.0
40
100
SFDR (2V DIFF)
95
90
85
–40
SNR/SFD (dBc)
MAGNITUDE (dBFS)
35
TPC 5. AD9235-40: Single Tone SNR/SFDR vs. fCLK with
fIN = Nyquist (20 MHz)
SNR = 68.5dBc
SINAD = 66.5dBc
ENOB = 10.8 BITS
THD = –71.0dBc
SFDR = 71.2dBc
–20
30
SAMPLE RATE (MSPS)
TPC 2. Single Tone 8K FFT with fIN = 70 MHz
0
25
–60
–80
SFDR (2V SE)
80
75
SNR (2V SE)
70
65
SNR (2V DIFF)
60
–100
55
–120
97.5
50
104.0
110.5
117.0
FREQUENCY (MHz)
123.5
130.0
0
10
15
SAMPLE RATE (MSPS)
20
TPC 6. AD9235-20: Single Tone SNR/SFDR vs. fCLK with
fIN = Nyquist (10 MHz)
TPC 3. Single Tone 8K FFT with fIN = 100 MHz
REV. B
5
–9–
AD9235
95
100
SFDR
SINGLE-ENDED (dBFS)
SFDR
DIFFERENTIAL (dBFS)
90
SFDR
SFDR
DIFFERENTIAL (dBc)
80
SNR
DIFFERENTIAL (dBFS)
SNR/SFDR (dBc)
SNR/SFDR (dBFS and dBc)
90
70
SNR
SINGLE-ENDED (dBFS)
60
85
80
75
SFDR
SINGLE-ENDED (dBc)
SNR
SNR
SINGLE-ENDED (dBc)
50
70
SNR
DIFFERENTIAL (dBc)
40
–30
–25
–20
–10
–15
A IN (dBFS)
65
0
20
–5
95
SFDR
DIFFERENTIAL (dBFS)
SFDR
90
SFDR
SINGLE-ENDED
(dBFS)
SFDR
DIFFERENTIAL
SNR
DIFFERENTIAL (dBc)
(dBFS)
SNR/SFDR (dBc)
SNR/SFDR (dBFS and dBc)
125
TPC 10. AD9235-65: SNR/SFDR vs. fIN
90
80
100
Input Frequency (MHz)
TPC 7. AD9235-65: Single Tone SNR/SFDR vs. AIN with
fIN = Nyquist (32.5 MHz)
100
75
50
25
70
SNR
SINGLE-ENDED
(dBFS)
60
SFDR
SINGLE-ENDED
(dBc)
SNR
DIFFERENTIAL (dBc)
–20
–15
–10
75
SNR
SNR
SINGLE-ENDED (dBc)
–25
80
70
50
40
–30
85
65
–5
0
0
25
50
75
100
125
Input Frequency (MHz)
AIN (dBFS)
TPC 11. AD9235-40: SNR/SFDR vs. fIN
TPC 8. AD9235-40: Single Tone SNR/SFDR vs. AIN with
fIN = Nyquist (20 MHz)
95
100
SFDR DIFFERENTIAL (dBFS)
SFDR
SINGLE-ENDED (dBFS)
80
SNR
DIFFERENTIAL (dBFS)
SFDR
SINGLE-ENDED
(dBc)
70
SNR
SINGLE-ENDED (dBFS)
60
50
SNR
DIFFERENTIAL
(dBc)
–25
–20
85
80
75
SNR
70
SNR
SINGLE-ENDED (dBc)
40
–30
SFDR
90
SFDR
DIFFERENTIAL (dBc)
SNR/SFDR (dBc)
SNR/SFDR (dBFS and dBc)
90
–15
–10
AIN (dBFS)
65
–5
0
0
25
50
75
100
125
Input Frequency (MHz)
TPC 12. AD9235-20: SNR/SFDR vs. fIN
TPC 9. AD9235-20: Single Tone SNR/SFDR vs. AIN with
fIN = Nyquist (10 MHz)
–10–
REV. B
AD9235
95
0
SNR = 64.6dBFS
SFDR = 81.6dBFS
1V SFDR
85
SNR/SFDR (dBFS)
MAGNITUDE (dBFS)
2V SFDR
90
–20
–40
–60
–80
80
75
2V SNR
70
1V SNR
–100
–120
32.5
65
39.0
45.5
52.0
FREQUENCY (MHz)
58.5
60
–24
65.0
–18
–15
AIN (dBFS)
–12
–9
–6
TPC 16. Dual Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz
and fIN2 = 46 MHz
TPC 13. Dual Tone 8K FFT with fIN1 = 45 MHz and
fIN2 = 46 MHz
95
0
2V SFDR
SNR = 64.3dBFS
SFDR = 81.1dBFS
90
–20
1V SFDR
85
SNR/SFDR (dBFS)
MAGNITUDE (dBFS)
–21
–40
–60
–80
80
75
2V SNR
70
1V SNR
–100
–120
65.0
65
71.5
78.0
84.5
FREQUENCY (MHz)
91.0
60
–24
97.5
–21
–18
–15
AIN (dBFS)
–12
–9
–6
TPC 17. Dual Tone SNR/SFDR vs. AIN with fIN1 = 69 MHz
and fIN2 = 70 MHz
TPC 14. Dual Tone 8K FFT with fIN1 = 69 MHz and
fIN2 = 70 MHz
0
95
SNR = 62.5dBFS
SFDR = 75.6dBFS
90
–20
2V SFDR
SNR/SFDR (dBFS)
MAGNITUDE (dBFS)
1V SFDR
85
–40
–60
–80
80
75
2V SNR
70
1V SNR
–100
–120
130.0
65
136.5
143.0
149.5
FREQUENCY (MHz)
156.0
60
–24
162.5
–18
–15
AIN (dBFS)
–12
–9
–6
TPC 18. Dual Tone SNR/SFDR vs. AIN with fIN1 = 144 MHz
and fIN2 = 145 MHz
TPC 15. Dual Tone 8K FFT with fIN1 = 144 MHz and
fIN2 = 145 MHz
REV. B
–21
–11–
AD9235
20
12.2
75
15
11.7
AD9235-65: 2V SINAD
11.2
69
AD9235-20: 1V SINAD
AD9235-40: 1V SINAD
10.7
66
GAIN DRIFT (ppm / C)
10
ENOB – BITS
SINAD (dBc)
AD9235-40:
2V SINAD
AD9235-20:
2V SINAD
72
AD9235-65: 1V SINAD
5
0
–5
–10
10.2
63
–15
60
0
10
20
30
40
SAMPLE RATE (MSPS)
50
9.7
60
–20
–40
TPC 19. SINAD vs. fCLK with fIN = Nyquist
–20
0
20
40
TEMPERATURE (C)
60
80
TPC 22. A/D Gain vs. Temperature Using an
External Reference
1.0
90
SFDR: DCS ON
0.8
80
0.6
SINAD: DCS ON
0.4
70
0.2
INL (LSB)
SINAD/SFDR (dBc)
SFDR: DCS OFF
SINAD: DCS OFF
60
50
0.0
–0.2
–0.4
–0.6
40
–0.8
–1.0
30
35
40
45
50
55
DUTY CYCLE (%)
60
0
65
500
TPC 20. SINAD/SFDR vs. Clock Duty Cycle
1500
2000
2500
CODE
3000
3500
4000
3000
3500
4000
TPC 23. Typical INL
90
85
1000
1.0
SFDR 2V DIFF
0.8
0.6
0.4
SFDR 1V DIFF
75
70
DNL (LSB)
SINAD/SFDR (dBc)
80
SINAD 2V DIFF
65
0.2
0.0
–0.2
–0.4
60
SINAD 1V DIFF
–0.6
55
50
–40 –30 –20 –10
–0.8
0
10 20 30 40 50
SAMPLE RATE (MSPS)
60
70
–1.0
80
0
TPC 21. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
–12–
500
1000
1500
2000 2500
CODE
TPC 24. Typical DNL
REV. B
AD9235
APPLYING THE AD9235
H
THEORY OF OPERATION
The AD9235 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections, consisting
of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit
flash. Each stage provides sufficient overlap to correct for flash
errors in the preceding stages. The quantized outputs from each
stage are combined into a final 12-bit result in the digital correction
logic. The pipelined architecture permits the first stage to operate
on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT
VIN+
CPAR
T
5pF
VIN–
CPAR
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors will be reduced by
the common-mode rejection of the ADC.
REV. B
T
H
Figure 6. Switched-Capacitor SHA Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as follows:
REFT = 1 2 ( AVDD + VREF )
REFB = 1 2 ( AVDD − VREF )
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
The analog input to the AD9235 is a differential switched
capacitor SHA that has been designed for optimum performance
while processing a differential input signal. The SHA input can
support a wide common-mode range and maintain excellent
performance, as shown in Figure 7. An input common-mode
voltage of midsupply will minimize signal-dependant errors and
provide optimum performance.
–90
90
THD 2.5MHz 2V DIFF
–85
85
–80
80
THD 35MHz 2V DIFF
SNR (dBc)
Referring to Figure 6, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half of
a clock cycle. A small resistor in series with each input can help
reduce the peak transient current required from the output stage
of the driving source. Also, a small shunt capacitor can be placed
across the inputs to provide dynamic charging currents. This
passive network will create a low-pass filter at the ADC’s input;
therefore, the precise values are dependant upon the application.
In IF undersampling applications, any shunt capacitors should
be removed. In combination with the driving source impedance,
they would limit the input bandwidth.
T
5pF
75
–75
SNR 2.5MHz 2V DIFF
–70
70
SNR 35MHz 2V DIFF
65
–65
60
–60
55
–55
50
0.0
0.5
1.0
1.5
2.0
COMMON-MODE LEVEL (V)
2.5
THD – dBc
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output and
the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash
errors. The last stage simply consists of a flash ADC.
T
–50
3.0
Figure 7. AD9235-65: SNR, THD vs. Common-Mode Level
The internal voltage reference can be pin-strapped to fixed values
of 0.5 V or 1.0 V, or adjusted within the same range as discussed
in the Internal Reference Connection section. Maximum SNR
performance will be achieved with the AD9235 set to the largest
input span of 2 V p-p. The relative SNR degradation will be 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
–13–
AD9235
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels
are defined as follows:
The signal characteristics must be considered when selecting a
transformer. Most RF transformers will saturate at frequencies
below a few MHz, and excessive signal power can also cause core
saturation, which leads to distortion.
VCM MIN = VREF / 2
Single-Ended Input Configuration
VCM MAX = ( AVDD + VREF )/ 2
The minimum common-mode input level allows the AD9235 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN–.
In this configuration, one input will accept the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9235 will then accept an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance may
degrade significantly as compared to the differential case. However,
the effect will be less noticeable at lower input frequencies and
in the lower speed grade models (AD9235-40 and AD9235-20).
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there will be a
degradation in SFDR and in distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little effect
on SNR performance. Figure 10 details a typical single-ended
input configuration.
1k⍀
2Vp-p
499⍀
AVDD
22⍀
VIN+
499⍀
AD8138
1k⍀
15pF
AD9235
523⍀
VIN–
1k⍀
AGND
15pF
499⍀
Figure 8. Differential Input Configuration Using
the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers will not be adequate to achieve
the true performance of the AD9235. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 9.
AVDD
22⍀
VIN+
2V p-p
15pF
49.9⍀
AD9235
22⍀
VIN–
15pF
1k⍀
0.1␮F
15pF
1k⍀
22⍀
1k⍀
15pF
+
10␮F
AD9235
VIN–
0.1␮F
AGND
AGND
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensitive to
clock duty cycle. Commonly a 5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics. The AD9235 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of the
AD9235. As shown in TPC 20, noise and distortion performance are nearly flat over a 30% range of duty cycle.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency will require approximately 100 clock cycles
to allow the DLL to acquire and lock to the new rate.
22⍀
0.1␮F
0.33␮F 1k⍀
49.9⍀
Figure 10. Single-Ended Input Configuration
As previously detailed, optimum performance will be achieved
while driving the AD9235 in a differential input configuration.
For baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen Key filter
topology to provide band limiting of the input signal.
49.9⍀
AVDD
VIN+
Differential Input Configurations
1Vp-p
22⍀
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated with the following equation.
SNR Degradation = 20 × log 10 [1 2 × π × f INPUT × t J ]
In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9235.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
1k⍀
Figure 9. Differential Transformer-Coupled Configuration
–14–
REV. B
AD9235
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode, and then must be recharged when returning
to normal operation. As a result, the wake-up time is related to the
time spent in standby mode and shorter standby cycles will result
in proportionally shorter wake-up times. With the recommended
0.1 µF and 10 µF decoupling capacitors on REFT and REFB, it
takes approximately 1 sec to fully discharge the reference buffer
decoupling capacitors and 3 ms to restore full operation.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 11, the power dissipated by the AD9235 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
I DRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits, 12 in the case of the
AD9235. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current will
be established by the average number of output bits switching,
which will be determined by the encode rate and the characteristics of the analog input signal.
DIGITAL OUTPUTS
The AD9235 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
325
300
AD9235-65
TOTAL POWER (mW)
275
225
As detailed in Table II, the data format can be selected for
either offset binary or twos complement.
200
Timing
250
175
The AD9235 provides latched data outputs with a pipeline delay of
seven clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 1 for a detailed timing diagram.
AD9235-40
150
125
100
AD9235-20
The length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD9235; these
transients can detract from the converter’s dynamic performance.
75
50
0.0
10
20
30
40
SAMPLE RATE (MSPS)
50
60
The lowest typical conversion rate of the AD9235 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
Figure 11. Total Power vs. Sample Rate with fIN = 10 MHz
VOLTAGE REFERENCE
For the AD9235-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the capacitive
load presented to the output drivers. The data in Figure 11 was
taken with a 5 pF load on each output driver.
A stable and accurate 0.5 V voltage reference is built into the
AD9235. The input range can be adjusted by varying the reference
voltage applied to the AD9235, using either the internal reference
or an externally applied reference voltage. The input span of the
ADC tracks reference voltage changes linearly.
The analog circuitry is optimally biased so that each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at
low sample rates that increases linearly with the clock frequency.
If the ADC is being driven differentially through a transformer, the
reference voltage can be used to bias the center tap (commonmode voltage).
By asserting the PDWN pin high, the AD9235 is placed in
standby mode. In this state, the ADC will typically dissipate 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9235 into its normal
operational mode.
A comparator within the AD9235 detects the potential at the
SENSE pin and configures the reference into one of four possible
states, which are summarized in Table I. If SENSE is grounded,
Internal Reference Connection
Table I. Reference Configuration Summary
Selected
Mode
SENSE
Voltage
Internal Switch
Position
Resulting
VREF (V)
Resulting Differential
Span (V p-p)
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
N/A
SENSE
SENSE
Internal Divider
N/A
0.5
0.5 × (1 + R2/R1)
1.0
2 × External Reference
1.0
2 × VREF (See Figure 13)
2.0
REV. B
–15–
AD9235
reference amplifier switch is connected to the internal resistor
divider (see Figure 12), setting VREF to 1 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V
reference output. If a resistor divider is connected as shown in
Figure 13, the switch will again be set to the SENSE pin. This
will put the reference amplifier in a noninverting mode with the
VREF output defined as follows.
External Reference Operation
The use of an external reference may be necessary to enhance the
gain accuracy of the ADC or improve thermal drift characteristics.
When multiple ADCs track one another, a single reference
(internal or external) may be necessary to reduce gain matching
errors to an acceptable level. A high precision external reference
may also be selected to provide lower gain and offset temperature
drift. Figure 14 shows the typical drift characteristics of the
internal reference in both 1 V and 0.5 V modes.
VREF = 0.5 × (1 + R 2 R 1)
1.2
VIN+
VIN–
1.0
REFT
VREF = 1.0V
VREF ERROR (%)
0.1F
ADC
CORE
10F
0.1F
REFB
0.1F
VREF
10F
0.8
VREF = 0.5V
0.6
0.4
0.5V
0.1F
0.2
SELECT
LOGIC
0.0
–40 –30 –20 –10
SENSE
AD9235
0
10 20 30 40 50
TEMPERATURE (C)
60
70
80
Figure 14. Typical VREF Drift
Figure 12. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
VIN+
VIN–
REFT
0.1F
ADC
CORE
10F
When the SENSE pin is tied to AVDD, the internal reference
will be disabled, allowing the use of an external reference. An
internal reference buffer will load the external reference with an
equivalent 7 kΩ load. The internal buffer will still generate the
positive and negative full-scale references, REFT and REFB, for
the ADC core. The input span will always be twice the value of
the reference voltage; therefore, the external reference must be
limited to a maximum of 1 V.
If the internal reference of the AD9235 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 15 depicts
how the internal reference voltage is affected by loading.
0.1F
REFB
0.05
0.1F
VREF
0.5V
0.1F
R2
–0.05
SELECT
LOGIC
ERROR (%)
10F
0.00
SENSE
R1
0.5V ERROR (%)
–0.10
1V ERROR (%)
–0.15
AD9235
–0.20
Figure 13. Programmable Reference Configuration
–0.25
0.0
0.5
1.0
1.5
LOAD (mA)
2.0
2.5
3.0
Figure 15. VREF Accuracy vs. Load
–16–
REV. B
AD9235
The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance (i.e., IF undersampling
characterization). It allows the user to apply a clock input signal that
is 4× the target sample rate of the AD9235. A low-jitter, differential
divide-by-4 counter, the MC100LVEL33D, provides a 1× clock
output that is subsequently returned back to the CLK input via
JP9. For example, a 260 MHz signal (sinusoid) will be divided
down to a 65 MHz signal for clocking the ADC. Note that R1 must
be removed with the AUXCLK interface. Lower jitter is often
achieved with this interface since many RF signal generators
display improved phase noise at higher output frequencies and the
slew rate of the sinusoidal output signal is 4× that of a 1× signal
of equal amplitude.
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9235 can output data in either
offset binary or twos complement format. There is also a provision
for enabling or disabling the clock duty cycle stabilizer (DCS).
The MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined below.
Table II. Mode Selection
MODE
Voltage
Data
Format
Duty Cycle
Stabilizer
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
Twos Complement
Twos Complement
Offset Binary
Offset Binary
Disabled
Enabled
Enabled
Disabled
Complete schematics and layout plots follow and demonstrate the
proper routing and grounding techniques that should be applied
at the system level.
The MODE pin is internally pulled down to AGND by a
20 kΩ resistor.
LFCSP EVALUATION BOARD
The typical bench setup used to evaluate the ac performance
of the AD9235 is similar to the TSSOP Evaluation Board
connections (refer to the schematics for connection details).
The AD9235 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various
jumpers (refer to the schematics).
TSSOP EVALUATION BOARD
The AD9235 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially,
through an AD8138 driver or a transformer, or single-ended.
Separate power pins are provided to isolate the DUT from the
support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 16 shows the typical bench characterization setup used to
evaluate the ac performance of the AD9235. It is critical that
signal sources with very low phase noise (<1 ps rms jitter) be used
to realize the ultimate performance of the converter. Proper
filtering of the input signal, to remove harmonics and lower the
integrated noise at the input, is also necessary to achieve the
specified noise performance.
An alternative differential analog input path using an AD8351
op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with
the ADC should remove C15, R12, and R3 and populate the
op amp circuit. The passive network between the AD8351
outputs and the AD9235 allows the user to optimize the frequency response of the op amp for the application.
3V
–
REFIN
HP8644, 2V p-p
SIGNAL SYNTHESIZER
BAND-PASS
FILTER
3V
+
–
3V
+
–
3V
+
–
AVDD GND DUT GND DUT
S4
AVDD
DRVDD
XFMR
INPUT
AD9235
+
DVDD
TSSOP EVALUATION BOARD
10MHz
HP8644, 2V p-p
REFOUT CLOCK SYNTHESIZER
CLOCK
DIVIDER
S1
CLOCK
Figure 16. TSSOP Evaluation Board Connections
REV. B
–17–
J1
DATA
CAPTURE
AND
PROCESSING
8
7
6
5
1 RP4 22
2 RP4 22
3 RP4 22
4 RP4 22
–18–
DVDDIN TB1 6
AGND TB1 4
DRVDDIN TB1 5
C6
22F
25V
L4
1
C14
0.1F
FBEAD
2
C53
0.1F
L3
1
D11O
L2
1
5
4 RP6 22
OTR
AVDD
D UTDRVDD
R27
5k
JP13
R17
1k
R20
1k
R4
10k
R3
10k
TP11 TP12 TP13 TP14
BLK BLK
BLK
BLK
R42
1k
TP4
RED
DVDD
TP10 TP15 TP16
TP9
BLK BLK
BLK
BLK
JP11
AVDD
AVDD
TP1
RED
D8
D9
D10
D11
DUTAVDD
8
7
6
1 RP6 22
2 RP6 22
3 RP6 22
JP12
5
4 RP5 22
8
7
6
1 RP5 22
2 RP5 22
3 RP5 22
TP2 RED
TP3
RED
OTRO
C52
0.1F
FBEAD
2
D8O
D9O
D10O
L1
1
C59
0.1F
FBEAD
2
D7
D4
D5
D6
D0
D1
D2
D3
FBEAD
2
C47
22F
25V
C48
22F
25V
AVDDIN TB1 1
AGND TB1 3
C58
22F
25V
5
4 RP3 22
8
7
6
1 RP3 22
2 RP3 22
3 RP3 22
DUTAVDDIN TB1 2
D4O
D5O
D6O
D7O
D3O
D2O
D0O
D1O
JP2
JP1
JP6
JP7
C21
10F
10V
C57
0.1F
C33
0.1F
JP24
JP25
JP23
C23
10F
10V
DUTAVDD
C32
0.1F
C20
10F
10V
C34
0.1F
C35
0.1F
WHT
TP5
C38
0.1F
C22
10F
10V
JP22
C41
0.001F
C50
0.1 F
SHEET 3
VIN–
VIN+
WHT
TP17
C36
0.1 F
C39
0.001F
DUTAVDD
C1
10F
10V
11
12
23
24
10
9
6
2
8
3
4
14
5
7
CLK
D1
D0
D2
D8O
D9O
D7O
D5O
D6O
D3O
D4O
D0O
D1O
D2O
OTRO
D10O
D11O
DUTCLK
WHT
TP6
DUTDRVDD
C40
0.001F
18
17
16
15
13
D4 20
D3 19
OTR
D11 1
28
D10
D9 27
26
D8
25
D7
22
D6
D5 21
C37
0.1F
DRVDD
DGND
AGND
AVDD
REFT
MODE U1
VIN+
VIN–
VREF
PDWN
REFB
AGND
SENSE
AVDD
AD9235
AD9235
Figure 17. TSSOP Evaluation Board Schematic, DUT
REV. B
–19–
C13
R1
49.9 0.1F
CW
R19
500
JP9
C27
0.1F
AVDD
R11
49.9
T2
2
3
R2
10
1
TP7
R18
500
2
C26
0.1F
74VHC04
U8
C24
0.1F
1
2
3
4
Figure 18. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering
74VHC04
8
11
U8
74VHC04
U8
10
9
74VHC04
U8
12
4
74VHC04
D5
D6
D7
D2
D3
D4
D0
D1
D8
D9
D10
D11
JP3
JP4
C10
0.1F
G1
G2
2 A1
3 A2
4 A3
5 A4
6 A5
7 A6
8 A7
9 A8
1
19
U8 DECOUPLING
AVDD
R9
22
R7
22 DUTCLK
OTR
C28
10F
10V
AVDD; 14
AVDD; 7
6
U8
D2
D1
R26
10k
13
3
5
U8
AVDD
U3 DECOUPLING
AVDD
WHT
R15
90
R13
113
AVDD
MC100LVEL33D
8
VCC
NC
7 OUT
INA
U3
6 REF
INB
5 VEE
INCOM
4
5
6 T1-1T 1
AVDD
1N5712
1
2
CLOCK
S1
R14
90
R12
113
AVDD
1
2
R25
10k
1N5712
REV. B
S5
AUXCLK
A1
A2
A3
A4
A5
A6
A7
A8
G1
G2
C3
10F
10V
2
3
4
5
6
7
8
9
1
19
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
2
18
17
16
15
14
13
12
11
C5
10F
10V 1
1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
DVDD
C4
10F
10V
18
17
16
15
14
13
12
11
20
VCC
GND 10
2
U7
74VHC541
C11
0.1F
U6
74VHC541
VCC 20
GND 10
C12
0.1F
RP2
RP2
RP2
RP2
22
22
22
22
RP2 22
RP2 22
RP2 22
8 RP2 22
1
2
3
4
5
6
7
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
DACLK
DOTR
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
1 RP2 22 16 DD0
2 RP2 22
3 RP2 22
4 RP2 22
5 RP2 22
6 RP2 22
7 RP2 22
8 RP2 22
HEADER RIGHT ANGLE MALE NO EJECTORS
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
J1
HDR40RAM
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
AD9235
–20–
S2
2
1
AMP INPUT
C19
10F
10V
1
R31
49.9
3
C2
6
R37
499
VAL
C17
R36
499
AD8138
VAL
2
0.1 F
C69
C15
10F
10V
1
-IN
1 VCC 4
2
U2 VO+
VO-VOC
8 +INVEE
5
ALT VEE
TP8
RED
2
A B
1
3
JP8
2
C18
0.1 F
R35
499
R34
523
AVDD
R10
40
R6
40
C8
0.1 F
XFMR INPUT
1
S4
2
R33
1k R32
1k
AVDD
SINGLE INPUT
1
S3
2
R24
49.9
C45
VAL
C42
VAL
C9
0.33F
R5
49.9
JP5
4
5
T2
2
3
6 T1-1T 1
R41
1k
R23
1k
AVDD
C7
0.1F
R8
1k
R16
1k
AVDD
C25
0.33F
C16
0.1F
JP43
JP41
JP46
JP45
JP40
JP42
R22
22
R21
22
C43
15pF
C44B
VIN–
VIN +
C44
15pF
AD9235
Figure 19. TSSOP Evaluation Board Schematic, Analog Inputs
REV. B
AD9235
DACLK
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB–DB11
CLOCK
DB10
DVDD
DB19
DCOM
DB8 AD9762 NC3
DB7
AVDD
DB6
COMP2
DB5
IOUTA
U4
DB4
IOUTB
DB3
ACOM
DB2
COMP1
DB1
FSADJ
DB0
REFIO
NC1
REFLO
NC2
SLEEP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DVDD
C30
C31
0.1F
0.01F
C29
C46
0.1F
0.01F
TP18
WHT
C56
R29
0.1F
C51
R30
2k
C55
0.1F
R28
49.9
22pF
49.9
C49
0.1F
C54
22pF
Figure 20. TSSOP Evaluation Board Schematic, Optional D/A Converter
Figure 21. TSSOP Evaluation Board Layout, Primary Side
REV. B
–21–
S6
AD9235
Figure 22. TSSOP Evaluation Board Layout, Secondary Side
Figure 23. TSSOP Evaluation Board Layout, Ground Plane
–22–
REV. B
AD9235
_
Figure 24. TSSOP Evaluation Board Power Plane
Figure 25. TSSOP Evaluation Board Layout, Primary Silkscreen
REV. B
–23–
AD9235
Figure 26. TSSOP Evaluation Board Layout, Secondary Silkscreen
–24–
REV. B
GND
J1
PRI SEC
Figure 27. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
PRI SEC
R11
36⍀
XOUTB
GND
C16
0.1␮F
R10
36⍀
E 45
XOUT
R18
25⍀
0.1␮F
C11
GND
R2
XX
GND
C21
10pF
R15
33⍀
AVDD
R13
1k⍀
C23
10pF
GND
P4
P3
R25
1k⍀
GND
AVDD
VIN–
3
2
4
P1
AVDD
GND
VIN+
R6
1k⍀
R7
1k⍀
R5
1k⍀
GND
GND
C19
15pF OR L1
FOR FILTER
R4
33⍀
R36
1k⍀
R26
1k⍀
C22
10␮F
GND GND
C13
0.10␮F
AVDD
GND
D
C18
0.1␮F
R SINGLE ENDED
GND
C5
0.1␮F
C26
10pF
R12
0⍀
R3
0⍀
C7
0.1␮F
GND
AMPINB
AMPIN
GND
p10
C29
10␮F
E
C
AVDD
GND
P11
P9 P8
P7 A B
C9
0.10␮F
R3, R17, R18
ONLY ONE SHOULD BE
ON BOARD AT A TIME
OPTIONAL XFR
T2
FT C1–1–13
5
1
XOUT
X FRIN
2
CT
3
4
GND
XOUTB
C15
AMP 0.1␮F
R42
0⍀
6
2 CT
4
T1
AD T 1–1 WT
GND
0.1␮F
C12
XFRIN1 1
5
NC
3
GND
C6
0.1␮F
L1 10nH
GND
R9
10k⍀
R1
10k⍀
MODE
2
P5
24
P6
GND
31 AGND
32 AVDD
28 AGND
29 VIN+
30 VIN-
25 REFB
26 REFT
27 AVDD
AVDD
P14
CLK
C8
0.1␮F
GND
U4
AD9235
D11 20
P13
R8
1k⍀
15
14
16
GND
D3 10
D2 9
13
D5 12
D4 11
DRVDD
DGND
D7
D6
6
5
4
GND
3
2.5V DRVDD
2
GND
1
AVDD
RP1 220⍀
11
6
EXTERNAL VOLTAGE DIVIDER
INTERNAL 1V REFERENCE (DEFAULT)
EXTERNAL REFERENCE
INTERNAL 0.5V REFERENCE
5
5
5
5
TO
TO
TO
TO
1
2
3
4
TWOS COMPLEMENT/DCS OFF
TWOS COMPLEMENT/DCS OFF
OFFSET BINARY/DCS ON
OFFSET BINARY/DCS OFF
MODE PIN SOLDERABLE JUMPER
E TO A
E TO B
E TO C
E TO D
10
9
12
7
8
13
5
15
14
4
16
2
3
10
9
7
8
1
11
12
6
5
13
15
14
4
16
D0X
D1X
D2X
D4X
D3X
D6X
D5X
D8X
D7X
D9X
D10X
D12X
D11X
DRX
D13X
H4
MTHOLE6
H3
MTHOLE6
H2
MTHOLE6
H1
MTHOLE6
2
3
RP2 220⍀
GND
1
P2
SENSE PIN SOLDERABLE JUMPER
(LSB)
DRVDD
GND
(MSB)
OVERRANGE BIT
3.0V
1
23
22
1 DNC
2 CLK
D10 19
D9 18
D8 17
VDL
AVDD
21
VREF
SENSE
MODE
OTR
3 DNC
4 PDWN
–25–
5 DNC
6 DNC
7 D0
8 D1
VAMP
2.5V
REV. B
5.0V
EXTREF
1V MAX E1
AD9235
LSB
–26–
R19
50
AMP
CC
GND
IN
1
CC
7
6
OUT
1Q3
5
GND
4
1Q2
3
1Q1
2
1OE
1
1Q4
GND
R35
25
C28
0.1F
R40
10k
GND
C35
0.10F
R41
10k
VAMP
POWER DOWN
USE R40 OR R41
42
1D4
43
1D3
44
GND
45
1D2
46
1D1
47
1CLK
48
24
23
2Q7
22
GND
21
2Q6
20
2Q5
19
VCC
18
2Q4
17
2Q3
16
GND
15
2Q2
14
2Q1
13
1Q8
12
1Q7
11
GND
10
1Q6
9
1Q5
8
V
2OE
2QB
25
2DB
26
2D7
27
GND
28
2D6
29
2D5
30
V
31 CC
2D4
32
2D3
33
GND
34
2D2
35
2D1
36
1D8
37
1D7
38
GND
39
1D6
40
1D5
41 V
U1
2CLK
AMP IN
CLKLAT/DAC
GND
D0X
DRVDD
D2X
D1X
D4X
D3X
GND
D5X
D7X
D6X
GND
D8X
D10X
D9X
DRVDD
D11X
GND
D12X
D13X
CLKAT/DAC
MSB
DRX
74LVTH162374
R33 RPG2 5
25
INLO 4
INHI 3
PWDN 1
RGP1 2
GND
GND
DRVDD
GND
GND
DRVDD
GND
GND
R34
1.2k
U3
AD8351
GND
VAMP
DRY
6 COMM
7 OPLO
9 VPOS
8 OPH1
10 VOCM
C44
0.1F
R38
1k
GND
R14
25
VAMP
R39
1k
C45
0.1F
C24
10F
R17
0
R16
0
GND
GND
GND
MSB
C17
0.1F
C27
0.1F
GND
DRY
GND
DR
GND
AMPINB
AMPIN
10
11
9
7
3
5
1
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
11
9
7
8
1
3
5
HEADER 40
4
6
2
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
12
10
8
4
6
2
GND
AD9235
Figure 28. LFCSP Evaluation Board Schematic, Digital Path
REV. B
REV. B
C4
10F
GND
–27–
J2
GND
R29
50
C43
0.1F
ENC
ENCX
GND
R30
1k
R31
1k
VDL
R27
0
R28
0
VDL
Figure 29. LFCSP Evaluation Board Schematic, Clock Input
VDL
E43
E44
E35
E51
E52
VDL
E31
VDL
E50
CLK
ENC
C33
C14
0.1F 0.001F
ANALOG BYPASSING
C32
0.001F
CLOCK TIMING ADJUSTMENTS
GND
ENCODE
C25
10F
GND
AVDD
FOR A BUFFERED ENCODE USE R28
FOR A DIRECT ENCODE USE R27
AVDD
C3
10F
DRVDD
DUT BYPASSING
C10
22F
VDL
R20
1k
GND
GND
R24
1k
GND
R21
1k
GND
E53
GND
R32
1k
C41
0.1F
DRVDD
C30
0.001F
5
9
10
12
13
3A
3B
4A
4B
2B
1 1A
2 1B
4 2A
U5
4Y
3Y
2Y
1Y
PWR
14
8
11
6
7
3
C34
0.1F
GND
C31
0.1F
74VCX86
DIGITAL BYPASSING
C2
22F
VDL
GND
ENCX
C36
0.1F
C39
C1
0.001F 0.1F
C48
0.001F
R23
0
CLKAT/DAC
R37
25
Rx
DNP
DR
GND
C49
0.001F
LATCH BYPASSING
C47
0.1F
SCHEMATIC SHOWS TWO GATE DELAY SETUP
FOR ONE DELAY REMOVE R22 AND R37 AND
ATTACH Rx (Rx = 0)
C38
0.001F
VDL
R22
0
GND
VAMP
C20
10F
C46
10F
C37
0.1F
C40
0.001F
AD9235
AD9235
Figure 30. LFCSP Evaluation Board Layout, Primary Side
Figure 32. LFCSP Evaluation Board Layout, Ground Plane
Figure 31. LFCSP Evaluation Board Layout, Secondary Side
–28–
Figure 33. LFCSP Evaluation Board Layout, Power Plane
REV. B
AD9235
Figure 34. LFCSP Evaluation Board Layout,
Primary Silkscreen
REV. B
Figure 35. LFCSP Evaluation Board Layout,
Secondary Silkscreen
–29–
AD9235
Table III. LFCSP Evaluation Board Bill of Materials
Item
Qty.
1
18
Omit1
8
2
8
2
Reference Designator
Device
Package
Value
C1, C5, C7, C8, C9, C11,
C12, C13, C15, C16, C31,
C33, C34, C36, C37, C41,
C43, C47
C6, C18, C27, C17, C28,
C35, C45, C44
Chip Capacitor
0603
0.1 µF
C2, C3, C4, C10, C20,
C22, C25, C29
C46, C24
Tantalum Capacitor
TAJD
10 µF
3
8
C14, C30, C32, C38, C39,
C40, C48, C49
Chip Capacitor
0603
0.001 µF
4
3
C19, C21, C23
Chip Capacitor
0603
10 pF
5
1
C26
Chip Capacitor
0603
10 pF
6
9
E31, E35, E43, E44, E50,
E51, E52, E53
E1, E45
Header
EHOLE
J1, J2
SMA Connector/50 Ω
SMA
L1
Inductor
0603
2
7
2
8
1
Recommended
Vendor/Part Number
Jumper Blocks
10 nH
Coilcraft/0603CS10NXGBU
9
1
P2
Terminal Block
TB6
Wieland/25.602.2653.0,
z5-530-0625-0
10
1
P12
Header Dual 20-Pin
RT Angle
HEADER40
Digi-Key S2131-20-ND
11
5
R3, R12, R23, R28, RX
R37, R22, R42, R16, R17,
R27
Chip Resistor
0603
0Ω
6
12
2
R4, R15
Chip Resistor
0603
33 Ω
13
14
R5, R6, R7, R8, R13, R20,
R21, R24, R25, R26, R30,
R31, R32, R36
Chip Resistor
0603
1 kΩ
14
2
R10, R11
Chip Resistor
0603
36 Ω
15
1
R29
R19
Chip Resistor
0603
50 Ω
220 Ω
1
Supplied
by ADI
16
2
RP1, RP2
Resistor Pack
R_742
17
1
T1
ADT1-1WT
AWT1-1T
18
1
U1
74LVTH162374
CMOS Register
TSSOP-48
19
1
U4
AD9235BCP ADC (DUT)
CSP-32
Analog Devices, Inc.
20
1
U5
74VCX86M
SOIC-14
Fairchild
21
1
PCB
AD92XXBCP/PCB
PCB
Analog Devices, Inc.
X
Analog Devices, Inc.
X
Mini-Circuits
22
1
U3
AD8351 Op Amp
MSOP-8
23
1
T2
MACOM Transformer
ETC1-1-13
1-1 TX
24
5
R9, R1, R2, R38, R39
Chip Resistor
0603
SELECT
25
3
R18, R14, R35
Chip Resistor
0603
25 Ω
–30–
Digi-Key
CTS/742C163220JTR
X
MACOM/ETC1-1-13
REV. B
AD9235
Table III. LFCSP Evaluation Board Bill of Materials (continued)
Omit1
Reference Designator
Device
Package
Value
26
2
R40, R41
Chip Resistor
0603
10 kΩ
27
1
R34
Chip Resistor
1.2 kΩ
28
1
R33
Chip Resistor
100 Ω
Item
Total
1
Qty.
82
Recommended
Vendor/Part Number
34
These items are included in the PCB design but are omitted at assembly.
OUTLINE DIMENSIONS
28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
9.80
9.70
9.60
28
15
4.50
4.40
4.30
1
6.40 BSC
14
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
8
0
0.20
0.09
COMPLIANT TO JEDEC STANDARDS MO-153AE
32-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
5.00
BSC SQ
0.60 MAX
25
24
PIN 1
INDICATOR
17
16
9
3.50
REF
0.80 MAX
0.65 NOM
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
REV. B
3.25
3.10 SQ
2.95
BOTTOM
VIEW
0.50
0.40
0.30
12 MAX
32 1
0.50
BSC
4.75
BSC SQ
TOP
VIEW
1.00
0.90
0.80
PIN 1
INDICATOR
0.60 MAX
–31–
8
Supplied
by ADI
AD9235
Revision History
Location
Page
5/03—Data Sheet changed from REV. A to REV. B.
Changes to Several Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Replaced Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
New DEFINITIONS OF SPECIFICATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to TPCs 1–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to THEORY OF OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to ANALOG INPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to Single-ended Input Configuration section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Replaced Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Changes to CLOCK INPUT CONSIDERATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to POWER DISSIPATION AND STANDBY MODE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to DIGITAL OUTPUTS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Timing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Changes to Figures 16–26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Added LFCSP Evaluation Board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inserted Figures 27–35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Added Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8/02—Data Sheet changed from REV. 0 to REV. A.
Updated RU-28 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
–32–
REV. B
C02461–0–5/03(B)
Added CP-32 Package (LFCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL