Fujitsu MBM29PL160BD-90PFTR 16m (2m x 8/1m x 16) bit Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20872-1E
PAGE MODE FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ FEATURES
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with MASK ROM pinouts
48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 program/erase cycles
• High performance
25 ns maximum page access time (75ns maximum random access time)
• An 8 words page read mode function
• Sector erase architecture
One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode
One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded programTM Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
(Continued)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
(Continued)
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Temporary sector unprotection
Temporary sector unprotection with the software command
• 5V tolerant (Data, Address, and Control Signals)
• In accordance with CFI (Common Flash Memory Interface)
■ PACKAGE
48-pin plastic TSOP (I)
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
44-pin plastic SOP
(FPT-44P-M16)
2
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ GENERAL DESCRIPTION
The MBM29PL160TD/BD is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M
words of 16 bits each. The MBM29PL160TD/BD is offered in a 48-pin TSOP (I), and 44-pin SOP packages. The
device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0
V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM
programmers.
The standard MBM29PL160TD/BD offers access times of 75 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29PL160TD/BD is pin and command set compatible with JEDEC standard E2PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29PL160TD/BD is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.0 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 4.8 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29PL160TD/BD is erased when shipped from the
factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7
or by the Toggle Bit feature on DQ6 output pin. Once the end of a program or erase cycle has been comleted,
the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29PL160TD/BD memory electrically erases all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
3
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
•
•
•
•
One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode.
One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode.
Individual-sector, multiple-sector, or bulk-erase capability.
Individual or multiple-sector protection is user definable.
Sector
Sector Size
(× 8) Address Range
(× 16) Address Range
SA0
256 Kbytes or 128 Kwords
000000H to 03FFFFH
00000H to 1FFFFH
SA1
256 Kbytes or 128 Kwords
040000H to 07FFFFH
20000H to 3FFFFH
SA2
256 Kbytes or 128 Kwords
080000H to 0BFFFFH
40000H to 5FFFFH
SA3
256 Kbytes or 128 Kwords
0C0000H to 0FFFFFH
60000H to 7FFFFH
SA4
256 Kbytes or 128 Kwords
100000H to 13FFFFH
80000H to 9FFFFH
SA5
256 Kbytes or 128 Kwords
140000H to 16FFFFH
A0000H to BFFFFH
SA6
256 Kbytes or 128 Kwords
180000H to 1BFFFFH
C0000H to DFFFFH
SA7
224 Kbytes or 112 Kwords
1C0000H to 1F7FFFH
E0000H to FBFFFH
SA8
8 Kbytes or 4 Kwords
1F8000H to 1F9FFFH
FC000H to FCFFFH
SA9
8 Kbytes or 4 Kwords
1FA000H to 1FBFFFH
FD000H to FDFFFH
SA10
16 Kbytes or 8 Kwords
1FC000H to 1FFFFFH
FE000H to FFFFFH
MBM29PL160TD Top Boot Sector Architecture
Sector
Sector Size
(× 8) Address Range
(× 16) Address Range
SA0
16 Kbytes or 8 Kwords
000000H to 003FFFH
00000H to 01FFFH
SA1
8 Kbytes or 4 Kwords
004000H to 005FFFH
02000H to 02FFFH
SA2
8 Kbytes or 4 Kwords
006000H to 007FFFH
03000H to 03FFFH
SA3
224 Kbytes or 112 Kwords
008000H to 03FFFFH
04000H to 1FFFFH
SA4
256 Kbytes or 128 Kwords
040000H to 07FFFFH
20000H to 3FFFFH
SA5
256 Kbytes or 128 Kwords
080000H to 0BFFFFH
40000H to 5FFFFH
SA6
256 Kbytes or 128 Kwords
0C0000H to 0FFFFFH
60000H to 7FFFFH
SA7
256 Kbytes or 128 Kwords
100000H to 13FFFFH
80000H to 9FFFFH
SA8
256 Kbytes or 128 Kwords
140000H to 17FFFFH
A0000H to BFFFFH
SA9
256 Kbytes or 128 Kwords
180000H to 1BFFFFH
C0000H to DFFFFH
SA10
256 Kbytes or 128 Kwords
1C0000H to 1FFFFFH
E0000H to FFFFFH
MBM29PL160BD Bottom Boot Sector Architecture
4
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ PRODUCT LINE UP
Part No.
MBM29PL160TD/160BD
+0.6 V
–0.3 V
-75
-90
Max. Address Access Time (ns)
75
90
Max. Page Address Access Time (ns)
25
35
Max. CE Access Time (ns)
75
90
Max. OE Access Time (ns)
25
35
Ordering Part No.
VCC = 3.0 V
■ BLOCK DIAGRAM
DQ0 to DQ15
VCC
VSS
WE
Input/Output
Buffers
Erase Voltage
Generator
State
Control
BYTE
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
OE
STB
Low VCC Detector
Timer for
Program/Erase
Address
Latch
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0 to A19
A-1
5
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ CONNECTION DIAGRAMS
SOP
TSOP(I)
(Marking Side)
WE
1
44
N.C.
A18
2
43
A19
A17
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
A0
11
34
A16
CE
12
33
BYTE
VSS
13
32
VSS
OE
14
31
DQ15/A-1
DQ0
15
30
DQ7
DQ8
16
29
DQ14
DQ1
17
28
DQ6
DQ9
18
27
DQ13
DQ2
19
26
DQ5
DQ10
20
25
DQ12
DQ3
21
24
DQ4
DQ11
22
23
VCC
FPT-44P-M16
BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
WE
N.C.
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
Standard Pinout
N.C.
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
VCC
VSS
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
N.C.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
N.C.
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VSS
VCC
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
N.C.
FPT-48P-M19
CE
A0
A1
A2
A3
A4
A5
A6
A7
A17
A18
N.C.
WE
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Reverse Pinout
FPT-48P-M20
6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ LOGIC SYMBOL
Table 1 MBM29PL160TD/BD Pin Configuration
Pin
A-1
20
A0 to A19
OE
A-1, A0 to A19
Address Inputs
DQ0 to DQ15
Data Inputs/Outputs
16 or 8
DQ0 to DQ15
CE
Function
CE
Chip Enable
OE
Output Enable
WE
Write Enable
WE
BYTE
BYTE
Selects 8-bit or 16-bit mode
N.C.
Pin Not Connected Internally
VSS
Device Ground
VCC
Device Power Supply
7
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ DEVICE BUS OPERATIONS
Table 2
MBM29PL160TD/BD User Bus Operation (BYTE = VIH)
CE
OE
WE
A0
A1
A6
A9
DQ0 to DQ15
Auto-Select Manufacture Code (1)
L
L
H
L
L
L
VID
Code
Auto-Select Device Code (1)
L
L
H
H
L
L
VID
Code
Read (3)
L
L
H
A0
A1
A6
A9
DOUT
Standby
H
X
X
X
X
X
X
HIGH-Z
Output Disable
L
H
H
X
X
X
X
HIGH-Z
Write (Program/Erase)
L
H
L
A0
A1
A6
A9
DIN
Enable Sector Protection (2), (4)
L
VID
L
H
L
VID
X
Verify Sector Protection (2), (4)
L
L
L
H
L
VID
Code
Operation
Table 3
H
MBM29PL160TD/BD User Bus Operation (BYTE = VIL)
CE
OE
WE
DQ15/
A-1
A0
A1
A6
A9
DQ0 to DQ7
Auto-Select Manufacture Code (1)
L
L
H
L
L
L
L
VID
Code
Auto-Select Device Code (1)
L
L
H
L
H
L
L
VID
Code
Read (3)
L
L
H
A-1
A0
A1
A6
A9
DOUT
Standby
H
X
X
X
X
X
X
X
HIGH-Z
Output Disable
L
H
H
X
X
X
X
X
HIGH-Z
Write (Program/Erase)
L
H
L
A-1
A0
A1
A6
A9
DIN
Enable Sector Protection (2), (4)
L
VID
L
L
H
L
VID
X
Verify Sector Protection (2), (4)
L
L
L
L
H
L
VID
Code
Operation
Legend: L = VIL, H = VIH, X = VIL or VIH.
H
= pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 7.
2. Refer to the section on Sector Protection.
3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. VCC = 3.3 V ±10%
8
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ FUNCTIONAL DESCRIPTION
Random Read Mode
The MBM29PL160TD/BD has two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC - tOE time.) See Figure 5.1 for timing specifications. When reading
out a data without changing addresses after powe-up, it is necessary to input hardware reset or to change CE
pin from "H" to "L".
Page Read Mode
The MBM29PL160TD/BD is capable of fast Page read mode and is compatible with the Page mode MASK ROM
read operation. This mode provides faster read access speed for random locations within a page. The Page size
of the MBM29PL160TD/BD device is 8 words, or 16 bytes, within the appropriate Page being selected by the
higheraddress bits A0 to A2 (in the word mode) and A-1 to A2 (in the byte mode) determining the specific word/
bytewithin that page. This is an asynchronous operation with the microprocessor supplying the specific word or
byte location.
The rondom or initial page access is equal to tACC and subsequent Page read access (as long as the locations
specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device
and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast
Page mode accesses are obtained by keeping A3 to A19 constant and changing A0 to A2 to select the specific
word, or changing A-1 to A2 to select the specific byte, within that page. See Figure 5.2 for timing specifications.
Standby Mode
The MBM29PL160TD/BD has a standby mode, a CMOS standby mode (CE input hel at VCC ±0.3 V.), when the
current consumed is less than 50 µA. During Embedded Algorithm operation, VCC Active current (ICC2) is required
even CE = “H”. The device can be read with standard access time (tCE) from standby modes.
In the standby mode, the outputs are in the high-impedance state, independent of the OE input. If the device
is deselected during erasure or programming, the device will draw active current until the operation is completed.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29PL160TD/BD data. This mode can be used effectively with an application requesting low power
consumption such as handy terminals.
To activate this mode, MBM29PL160TD/BD automatically switches itself to low power mode when addresses
remain stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the
current consumed is typically 50 µA (CMOS Level).
Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Output Disable
If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to
be in a high-impedance state.
9
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Autoselect
The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. The intent is to allow programming equipment to automatically match the device to be programmed
with its corresponding programming algorithm. The Autoselect command may also be used to check the status
of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional over the entire temperature range
of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Table 2 or Table 3.) (Recomend to set VIL for
the other addresses pins.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29PL160TD/BD is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 7, Command Definitions.
Word 0 (A0 = VIL) represents the manufacture’s code and word 1 (A0 = VIH) represents the device identifier code.
For the MBM29PL160TD/BD these two bytes are given in the Table 4.2. All identifiers for manufactures and
device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when
executing the Autoselect, A1 must be VIL. (See Tables 2 or 3.)
If BYTE = VIL (for byte mode), the device code is 27H (for top boot block) or 45H (for bottom boot block). If BYTE
= VIH (for word mode), the device code is 2227H (for top boot block) or 2245H (for bottom boot block).
In order to determine which sectors are write protected, A1 must be at VIH while running through the sector
addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 =1).
10
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Table 4.1 MBM29PL160TD/BD Sector Protection Verify Autoselect Code
Type
A12 to A19
A6
A1
A0
A-1*1
Code
(HEX)
X
VIL
VIL
VIL
VIL
04H
VIL
27H
X
VIL
VIL
VIH
X
2227H
VIL
45H
X
2245H
Manufacture’s Code
Byte
MBM29PL160TD
Word
Device Code
Byte
MBM29PL160BD
X
VIL
VIL
VIH
Word
Sector Protection
Sector
Addresses
VIL
VIH
VIL
VIL
01H*2
X
VIL
VIH
VIH
VIL
01H*3
Temporary Sector Unprotection
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
*3: Outputs 01H at Temporary Sector Unprotect and outputs 00H at Non Temporary Sector Unprotect.
Table 4.2 Expanded Autoselect Code Table
Type
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacture’s Code
04H A-1/0
(B)
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
27H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
45H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
1
0
0
0
1
0
1
MBM29PL160TD
(W) 2227H
Device
Code
(B)
0
0
1
0
0
0
1
0
MBM29PL160BD
(W) 2245H
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
Sector Protection
01H A-1/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Temporary Sector
Unprotection
01H A-1/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
(B): Byte mode
(W): Word mode
11
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Table 5
Sector
Address
A19
A18
A17
A16
A15
A14
A13
A12
(× 8) Address Range
(× 16) Address Range
SA0
0
0
0
X
X
X
X
X
000000H to 03FFFFH
00000H to 1FFFFH
SA1
0
0
1
X
X
X
X
X
040000H to 07FFFFH
20000H to 3FFFFH
SA2
0
1
0
X
X
X
X
X
080000H to 0BFFFFH
40000H to 5FFFFH
SA3
0
1
1
X
X
X
X
X
0C0000H to 0FFFFFH
60000H to 7FFFFH
SA4
1
0
0
X
X
X
X
X
100000H to 13FFFFH
80000H to 9FFFFH
SA5
1
0
1
X
X
X
X
X
140000H to 17FFFFH
A0000H to BFFFFH
SA6
1
1
0
X
X
X
X
X
180000H to 1BFFFFH
C0000H to DFFFFH
SA7
1
1
1
1C0000H to 1F7FFFH
E0000H to FBFFFH
SA8
1
1
1
1
1
1
0
0
1F8000H to 1F9FFFH
FC000H to FCFFFH
SA9
1
1
1
1
1
1
0
1
1FA000H to 1FBFFFH
FD000H to FDFFFH
SA10
1
1
1
1
1
1
1
X
1FC000H to 1FFFFFH
FE000H to FFFFFH
00000 - 11011
Table 6
12
Sector Address Tables (MBM29PL160TD)
Sector Address Tables (MBM29PL160BD)
Sector
Address
A19
A18
A17
A16
A15
A14
A13
A12
(× 8) Address Range
(× 16) Address Range
SA0
0
0
0
0
0
0
0
X
000000H to 003FFFH
00000H to 01FFFH
SA1
0
0
0
0
0
0
1
0
004000H to 005FFFH
02000H to 02FFFH
SA2
0
0
0
0
0
0
1
1
006000H to 007FFFH
03000H to 03FFFH
SA3
0
0
0
008000H to 03FFFFH
04000H to 1FFFFH
SA4
0
0
1
X
X
X
X
X
040000H to 07FFFFH
20000H to 3FFFFH
SA5
0
1
0
X
X
X
X
X
080000H to 0BFFFFH
40000H to 5FFFFH
SA6
0
1
1
X
X
X
X
X
0C0000H to 0FFFFFH
60000H to 7FFFFH
SA7
1
0
0
X
X
X
X
X
100000H to 13FFFFH
80000H to 9FFFFH
SA8
1
0
1
X
X
X
X
X
140000H to 17FFFFH
A0000H to BFFFFH
SA9
1
1
0
X
X
X
X
X
180000H to 1BFFFFH
C0000H to DFFFFH
SA10
1
1
1
X
X
X
X
X
1C0000H to 1FFFFFH
E0000H to FFFFFH
00100 - 11111
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Write
Device erasure and programming are accomplished via the command register. The command register is written
by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of CE or
WE, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first.
Standard microprocessor write timings are used. See Figures 6 to 8.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29PL160TD/BD features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 10). The sector protection feature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE =
VIL, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to
the sector to be protected. Tables 5 and 6 define the sector address for each of the eleven (11) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the
rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 14 and 20
for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)
while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. Otherwise the
device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A0, A1, and
A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device
codes. A-1 requires to VIL in byte mode.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses pins (A19, A18, A17, A16, A15,
A14, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See
Tables 4.1 and 4.2 for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29PL160TD/BD devices
in order to change data. The Temporary Sector Unprotection mode is activated by command register. During
this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once
the mode is taken away using command register, all the previously protected sectors will be protected again.
(See Figures 20.)
13
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Table 7
Command
Sequence
(Notes 1, 2, 3, 5)
Read/Reset
(Note 6)
Read/Reset
(Note 6)
Word
/Byte
Word
Byte
Word
Autoselect
Byte
Byte/Word
Program
(Notes 3, 4)
1
3
3
Word
Byte
Word
Chip Erase
Byte
Sector Erase
(Note 3)
Bus
Write
Cycles
Req'd
Word
Byte
MBM29PL160TD/BD Standard Command Definitions
Second
Bus Fifth Bus
First Bus
Third Bus Fourth
Sixth Bus
Bus
Read/Write
Write Cycle Write Cycle Write Cycle
Write Cycle Write Cycle
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
XXXH F0H
555H
AAAH
555H
AAAH
AAH
AAH
555H
4
6
6
AAAH
555H
AAAH
555H
AAAH
—
2AAH
555H
2AAH
555H
—
55H
55H
2AAH
AAH
AAH
AAH
555H
2AAH
555H
2AAH
555H
—
555H
AAAH
555H
AAAH
—
—
—
—
—
—
—
F0H
RA
RD
—
—
—
—
90H
—
—
—
—
—
—
A0H
PA
PD
—
—
—
—
555H
55H
55H
55H
AAAH
555H
AAAH
555H
AAAH
80H
80H
555H
AAAH
555H
AAAH
AAH
AAH
2AAH
555H
2AAH
555H
55H
555H
AAAH
10H
55H
SA
30H
Sector Erase
Suspend
Word
/Byte
1
XXXH B0H
—
—
—
—
—
—
—
—
—
—
Sector Erase
Resume
Word
/Byte
1
XXXH 30H
—
—
—
—
—
—
—
—
—
—
Temporary
Unprotect
Enable
Word
E0H XXXH 01H
—
—
—
—
Temporary
Unprotect
Disable
Word
E0H XXXH 00H
—
—
—
—
Byte
Byte
555H
4
AAAH
2AAH
AAH
555H
4
AAAH
555H
555H
55H
2AAH
AAH
555H
AAAH
555H
55H
AAAH
Notes: 1. Address bits A11 to A19 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA).
2. Bus operations are defined in Tables 2 and 3.
3. RA =Address of the memory location to be read.
PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA =Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
4. RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA. Data is latched on the rising edge of WE.
5. The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A0 to A10
Byte Mode: AAAH or 555H to addresses A-1 to A10
6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
14
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Table 8
Bus
Write
Cycles
Req'd
Command
Sequence
Set to Fast
Mode
Fast Program *1
MBM29PL160TD/BD Extended Command Definitions
Word
Byte
Word
Byte
Reset from Fast
Mode *1
Word
Query
Command *2
Word
Byte
Byte
3
2
2
2
First Bus
Write Cycle
Addr
555H
AAAH
XXXH
XXXH
XXXH
XXXH
55H
AAH
Data
AAH
A0H
90H
98H
Second Bus
Write Cycle
Addr
2AAH
555H
PA
XXXH
XXXH
—
Data
55H
Third Bus
Write Cycle
Addr
555H
AAAH
Fourth Bus
Read Cycle
Data
Addr
Data
20H
—
—
PD
—
—
—
—
F0H *3
—
—
—
—
—
—
—
—
—
SPA : Sector Address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector
addresses.
*1.
This command is valid while fast mode.
*2.
Addresses from system set to A0 to A6. The other addresses are “Don’t care”.
*3.
The data" 00H" is also acceptable.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in an improper sequence will reset the device to the
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The device remains enabled for reads until the command
register contents are altered.
The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters. (See Figure 5.1 and 5.2.)
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufactures and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A
read cycle from address XX01H for ×16 (XX02H for ×8) retrieves the device code (MBM29PL160TD = 27H and
15
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
MBM29PL160BD = 45H for ×8 mode; MBM29PL160TD = 2227H and MBM29PL160BD = 2245H for ×16 mode).
(See Tables 4.1 and 4.2.)
All manufactures and device codes will exhibit odd parity with DQ7 defined as the parity bit.
The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8).
Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce
a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin
mode verification on the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,
also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command
sequence.
Word/Byte Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens
first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the device return to the read mode and addresses are no longer latched. (See Table 9, Hardware
Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.
Hence, Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee whether the data being written is correct or not.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 16 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls
or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read mode.
(See Figure 8.)
Figure 17 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”
command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address
(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data
= 30H) is latched on the rising edge of WE. After a time-out of 50 µs from the rising edge of the last sector erase
command, the sector erase operation will begin.
16
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Multiple sectors may be erased concurrently by writing six-bus cycle operations on Table 7. This sequence is
followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs
from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling
edge of the WE occurs within the 50 µs time-out window the timer is reset. Monitor DQ3 to determine if the sector
erase timer window is still open. (See section DQ3, Sector Erase Timer.) Any command other than Sector Erase
or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous
command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case,
restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for
Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any
number of sectors (0 to 10).
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations. (See Figure 8.)
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase
Time] × Number of Sector Erase.
Figure 17 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when
writing the Erase Suspend or Erase Resume commands.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of
the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by Data polling of DQ7 and the Toggle Bit (DQ6) which is the same
as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read
from any address.
17
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Extended Command
(1) Fast Mode
MBM29PL160TD/BD has Fast Mode function. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence writing Fast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register.
(Refer to the Figure 22 Extended algorithm.) The VCC active current is required even CE = VIH during Fast
Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 22 Extended algorithm.)
(3) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98H) into the command register. Following the
command write, a read cycle from specific address retrives device information. Please note that output data
of upper byte (DQ8 to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate
operation, it is necessary to write the read/reset command sequence into the register.
18
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Write Operation Status
Table 9
Hardware Sequence Flags
Status
DQ7
DQ6
DQ5
DQ3
DQ2
Embedded Program Algorithm
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle
Data
Data
Data
Data
Data
DQ7
Toggle
(Note 1)
0
0
1
(Note 2)
DQ7
Toggle
1
0
1
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Embedded/Erase Algorithm
In
Progress
Erase Suspend Read
(Erase Suspended Sector)
Erase
Erase Suspend Read
Suspend
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Embedded Program Algorithm
Exceeded
Time
Limits
Embedded/Erase Algorithm
Erase Suspend Program
(Non-Erase Suspended Sector)
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
3. DQ0 and DQ1 are reserve pins for future use.
4. DQ4 is Fujitsu internal use only.
DQ7
Data Polling
The MBM29PL160TD/BD device features Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 18.
For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write
pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and
not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29PL160TD/BD data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm
operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0
to DQ7 will be read on successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out.
See Figure 9 for the Data Polling timing specifications and diagrams.
19
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
DQ6
Toggle Bit I
The MBM29PL160TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data can be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the sixwrite pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100 µs and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See Figure 10 and Figure 19 for the Toggle Bit I timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will
control the output disable functions as described in Tables 2 and 3.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the
second status check, the command may not have been accepted.
See Table 9: Hardware Sequence Flags.
20
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
DQ2
Toggle Bit II
This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address
of the non-erase suspended sector will indicate a logic “1” at DQ2.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress.
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 10 and Figure 15.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
Table 10
Toggle Bit Status
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle
Erase Suspend Read
(Erase Suspended Sector)
(Note 1)
1
1
Toggle
DQ7
Toggle (Note 1)
1 (Note 2)
Mode
Program
Erase-Suspend Program
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
Word/Byte Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29PL160TD/BD device. When
this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ0
to DQ15. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored. Refer to
Figures 11 to 13 for the timing diagrams.
Data Protection
The MBM29PL160TD/BD is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
21
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must
be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
22
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Table 11 Common Flash Memory Interface Code
A0 to A6
DQ0 to DQ15
Erase Block Region 2
Information
31h
32h
33h
34h
0001h
0000h
0020h
0000h
Erase Block Region 3
Information
35h
36h
37h
38h
0000h
0000h
0080h
0003h
Erase Block Region 4
Information
39h
3Ah
3Bh
3Ch
0006h
0000h
0000h
0004h
Query-unique ASCII string
“PRI”
40h
41h
42h
0050h
0052h
0049h
Major version number, ASCII
43h
0031h
Minor version number, ASCII
44h
0030h
Address Sensitive Unlock
0 = Required
1 = Not Required
45h
0000h
Erase Suspend
0 = Not Supported
1 = To Read Only
2 = To Read & Write
46h
0002h
Sector Protect
0 = Not Supported
X = Number of sectors in per
group
47h
0001h
Sector Temporary Unprotect
00 = Not Supported
01 = Supported
48h
0001h
0000h
25h
0004h
Sector Protection Algorithm
49h
0004h
Number of Sector for Bank2
4Ah
00h
Max. timeout for full chip
erase 2N times typical
26h
0000h
Burst Mode Type
00 = Not supported
4Bh
00h
Device Size = 2N byte
27h
0015h
02h
28h
29h
0002h
0000h
Max. number of byte in
multi-byte write = 2N
2Ah
2Bh
0000h
0000h
Page Mode Type
00 = Not supported
01 = 4 word Page
02 = 8 word Page
4Ch
Flash Device Interface
description
Number of Erase Block
Regions within device
2Ch
0004h
Erase Block Region 1
Information
2Dh
2Eh
2Fh
30h
0000h
0000h
0040h
0000h
Description
A0 to A6
DQ0 to DQ15
Query-unique ASCII string
“QRY”
10h
11h
12h
0051h
0052h
0059h
Primary OEM Command Set
2h: AMD/FJ standard type
13h
14h
0002h
0000h
Address for Primary
Extended Table
15h
16h
0040h
0000h
Alternate OEM Command
Set (00h = not applicable)
17h
18h
0000h
0000h
Address for Alternate OEM
Extended Table
19h
1Ah
0000h
0000h
VCC Min. (write/erase)
D7-4: volt, D3-0: 100 mvolt
1Bh
0027h
VCC Max. (write/erase)
D7-4: volt, D3-0: 100 mvolt
1Ch
0036h
VPP Min. voltage
1Dh
0000h
VPP Max. voltage
1Eh
0000h
Typical timeout per single
byte/word write 2N µs
1Fh
0004h
Typical timeout for Min. size
buffer write 2N µs
20h
0000h
Typical timeout per individual
block erase 2N ms
21h
000Ah
Typical timeout for full chip
erase 2N ms
22h
0000h
Max. timeout for byte/word
write 2N times typical
23h
0005h
Max. timeout for buffer write
2N times typical
24h
Max. timeout per individual
block erase 2N times typical
Description
23
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. –55°C to +125°C
Ambient Temperature with Power Applied .................................................................. –40°C to +85°C
Voltage with respect to Ground All pins except A9, OE, and RESET (Note 1) ............ –0.5 V to +5.5 V
VCC (Note 1) ................................................................................................................ –0.5 V to +4.0 V
A9, OE, and RESET (Note 2) ...................................................................................... –0.5 V to +13.0 V
Notes: 1. Minimum DC voltage on input or l/O pins are –0.5 V. During voltage transitions, inputs may negative
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are 6.0V.
During voltage transitions,outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE, and RESET pins are –0.5 V. During voltage transitions, A9, OE,
and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A9, OE, and RESET pins are +13.0 V which may positive overshoot to 13.5 V for periods of
up to 20 ns. Voltage difference between input voltage and supply voltage (VIN – VCC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Ambient Temperature (TA)
MBM29PL160TD/BD-75 ...........................................................................–20°C to +70°C
MBM29PL160TD/BD-90 ...........................................................................–40°C to +85°C
VCC Supply Voltages
MBM29PL160TD/BD-75/90 ......................................................................+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is quaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
24
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ MAXIMUM OVERSHOOT
20 ns
20 ns
+0.6 V
–0.5 V
–2.0 V
20 ns
Figure 1
Maximum Negative Overshoot Waveform
20 ns
6.0 V
VCC +0.5 V
+2.0 V
20 ns
20 ns
Figure 2
Maximum Positive Overshoot Waveform 1
20 ns
+13.5 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE, and RESET.
Figure 3
Maximum Positive Overshoot Waveform 2
25
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
VIN = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
ILIT
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max.,
A9, OE = 12.5 V
—
35
µA
CE = VIL, OE = VIH
f = 10 MHz
—
70
mA
CE = VIL, OE = VIH
f = 5 MHz
—
40
mA
ICC1
VCC Active Current (Note 1)
ICC2
VCC Active Current (Note 2)
CE = VIL, OE = VIH
—
35
mA
ICC3
VCC Current (Standby)
VCC = VCC Max., CE = VCC ±0.3 V,
—
5
µA
ICC4
VCC Current
VCC = VCC Max., CE = VSS ±0.3 V,
(Automatic Sleep Mode) (Note 3) VIN = VCC ±0.3 V or VSS ±0.3 V
—
5
µA
VCC Active Current
(Page Read Mode)
30MHz
—
12
mA
ICC5
40MHz
—
15
mA
CE = VIL, OE = VIH
VIL
Input Low Level
—
–0.5
0.8
V
VIH
Input High Level (Note 5)
—
2.0
5.5
V
VID
Voltage for Autoselect,Sector
Protection (A9, OE) (Note 4, 5)
—
11.5
12.5
V
VOL
Output Low Voltage Level
IOL = 4.0 mA, VCC = VCC Min.
—
0.45
V
IOH = –2.0 mA, VCC = VCC Min.
2.4
—
V
VCC – 0.4
—
V
2.3
2.5
V
VOH1
Output High Voltage Level
VOH2
VLKO
Notes: 1.
2.
3.
4.
5.
26
IOH = –100 µA
Low VCC Lock-Out Voltage
—
The lCC current listed includes both the DC operating current and the frequency dependent component.
lCC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
Applicable for only sector protection.
The input voltage must be input after Vcc is valid.
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
Symbols
Description
-75
(Note)
-90
(Note)
Unit
Min.
75
90
ns
Max.
75
90
ns
Min.
25
35
ns
Test Setup
JEDEC
Standard
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
—
tPRC
Page Read Cycle Time
—
tPACC
Page Address to Output Delay
CE = VIL
OE = VIL
Max.
25
35
ns
tELQV
tCE
Chip Enable to Output Delay
OE = VIL
Max.
75
90
ns
tGLQV
tOE
Output Enable to Output Delay
—
Max.
25
35
ns
tEHQZ
tDF
Chip Enable to Output HIGH-Z
—
Max.
20
30
ns
tGHQZ
tDF
Output Enable to Output HIGH-Z
—
Max.
20
30
ns
tAXQX
tOH
Output Hold Time From Address, CE
or OE, Whichever Occurs First
—
Min.
4
5
ns
—
tELFL
tELFH
CE or BYTE Switching Low or High
—
Max.
4
5
ns
—
CE = VIL
OE = VIL
—
Note: Test Conditions: Output Load:
1 TTL gate and 30 pF (MBM29PL160TD/BD-75)
1 TTL gate and 100 pF (MBM29PL160TD/BD-90)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29PL160TD/BD-75)
CL = 100 pF including jig capacitance (MBM29PL160TD/BD-90)
Figure 4
Test Conditions
27
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
• Write (Erase/Program) Operations
Parameter Symbols
MBM29PL160TD/BD
Description
JEDEC
Standard
tAVAV
tWC
Write Cycle Time
tAVWL
tAS
tWLAX
-90
Min.
75
90
ns
Address Setup Time
Min.
0
0
ns
tAH
Address Hold Time
Min.
45
45
ns
tDVWH
tDS
Data Setup Time
Min.
35
45
ns
tWHDX
tDH
Data Hold Time
Min.
0
0
ns
—
tOES
Output Enable Setup Time
Min.
0
0
ns
—
tOEH
Output Enable
Hold Time
Read
Min.
0
0
ns
Toggle and Data Polling
Min.
10
10
ns
tGHWL
tGHWL
Read Recover Time Before Write
Min.
0
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
(OE High to CE Low)
Min.
0
0
ns
tELWL
tCS
CE Setup Time
Min.
0
0
ns
tWLEL
tWS
WE Setup Time
Min.
0
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
0
ns
tWLWH
tWP
Write Pulse Width
Min.
35
35
ns
tELEH
tCP
CE Pulse Width
Min.
35
35
ns
tWHWL
tWPH
Write Pulse Width High
Min.
20
30
ns
tEHEL
tCPH
CE Pulse Width High
Min.
20
30
ns
tWHWH1
tWHWH1
Programming Operation
8.6
8.6
12.6
12.6
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
Typ.
4.8
4.8
sec
—
tEOE
Delay Time from Embedded Output Enable
Max.
75
90
ns
—
tVCS
VCC Setup Time
Min.
50
50
µs
—
tVLHT
Voltage Transition Time (Note 2)
Min.
4
4
µs
—
tWPP
Write Pulse Width (Note 2)
Min.
100
100
µs
—
tOESP
OE Setup Time to WE Active (Note 2)
Min.
4
4
µs
—
tCSP
CE Setup Time to WE Active (Note 2)
Min.
4
4
µs
—
tRB
Recover Time From RY/BY
Min.
0
0
ns
—
tFLQZ
BYTE Switching Low to Output HIGH-Z
Max.
30
30
ns
—
tFHQV
BYTE Switching High to Output Active
Min.
40
30
ns
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Protection operation.
28
Unit
-75
Byte
Word
Typ.
µs
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ SWITCHING WAVEFORMS
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Change
from H to L
May
Change
from L to H
Will Be
Change
from L to H
“H” or “L”:
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
tRC
Addresses
Addresses Stable
tACC
CE
tOE
tDF
OE
tOEH
WE
tCE
Outputs
HIGH-Z
Figure 5.1
tOH
Output Valid
HIGH-Z
AC Waveforms for Read Operations
29
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
A13 to A19
Addresses Valid
A0 to A2
(A-1)
Aa
Ab
tRC
tPRC
Ac
tACC
tCE
CE
tOE
OE
tOEH
WE
Outputs
HIGH-Z
Figure 5.2
30
Da
tPACC
tPACC
tOH
tOH
Db
tDF
tOH
Dc
AC Waveforms for Page Read Mode Operations
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
3rd Bus Cycle
Data Polling
555H
Addresses
PA
tWC
tAS
PA
tRC
tAH
CE
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
tDS
A0H
Data
Notes: 1.
2.
3.
4.
5.
6.
tOH
tDH
PD
DQ7
DOUT
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at word address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 6
AC Waveforms for Alternate WE Controlled Program Operations
31
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
3rd Bus Cycle
Addresses
Data Polling
PA
555H
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
Data
Notes: 1.
2.
3.
4.
5.
6.
PD
DQ7
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at word address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 7
32
A0H
tDH
AC Waveforms for Alternate CE Controlled Program Operations
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Addresses
2AAH
555H
tWC
tAS
555H
555H
2AAH
SA*
tAH
CE
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAH
Data
30H for Sector Erase
55H
80H
AAH
55H
10H
tVCS
VCC
* : 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAAH (Byte) for Chip
Erase.
2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 8
AC Waveforms for Chip/Sector Erase Operations
33
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
CE
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7
Data
DQ7 =
Valid Data
DQ7
High-Z
tWHWH1 or 2
DQ0 to DQ6 = Output Flag
Data
DQ0 to DQ6
DQ0 to DQ6
High-Z
Valid Data
(tEOE)
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 9
AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tOEH
WE
tOEH
tOES
OE
*
tDH
DQ6
Data
DQ6 = Toggle
DQ6 = Toggle
DQ6 =
Stop Toggling
DQ0 to DQ7
Data Valid
tOE
* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)
Figure 10
34
AC Waveforms for Taggle Bit I during Embedded Algorithm Operations
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
CE
BYTE
DQ0 to DQ14
DQ0 to DQ7
tELFH
DQ15/A-1
tFHQV
A-1
Figure 11
DQ0 to DQ14
DQ15
Timing Diagram for Word Mode Configuration
CE
BYTE
tELFL
DQ0 to DQ14
DQ0 to DQ14
DQ15/A-1
DQ15
DQ0 to DQ7
A-1
tFLQZ
Figure 12
Timing Diagram for Byte Mode Configuration
35
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
CE
The falling edge of the last WE signal
WE
Input
Valid
BYTE
tSET
(tAS)
Figure 13
36
tHOLD
(tAH)
BYTE Timing Diagram for Write Operations
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
A19, A18, A17
A16, A15, A14
A13, A12
SAX
SAY
A0
A1
A6
VID
3V
A9
tVLHT
VID
3V
OE
tVLHT
tVLHT
tWPP
WE
tOESP
tVLHT
tCSP
CE
01H
Data
tVCS
tOE
VCC
SAX = Sector Address for initial sector
SAY = Sector Address for next sector
Note: A-1 is VIL on byte mode.
Figure 14
AC Waveforms for Sector Protection Timing Diagram
37
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE
Note: DQ2 is read from the erase-suspended sector.
Figure 15
38
DQ2 vs. DQ6
Erase
Erase
Complete
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ FLOW CHART
Start
Write Program Command
Sequence
(See Below)
Data Polling Device
No
Verify Byte
?
Yes
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
* : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
Figure 16
Embedded ProgramTM Algorithm
39
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Start
Write Erase Command
Sequece
(See Below)
Data Polling or Toggle Bit
from Device
No
Data = FFH
?
Yes
Erasure Completed
Chip Erase Command Sequence*
(Address/Command):
Individual Sector/Multiple Sector*
Erase Command Sequence
(Address/Command):
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
Sector Address/30H
* : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
Figure 17
40
Embedded EraseTM Algorithm
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Start
Read Byte
(DQ0 to DQ7)
Addr. = VA
DQ7 = Data?
Yes
VA =Address for programming
=Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
=Any of the sector addresses
within the sector not being
protected during sector erase or
multiple sector erases
operation.
No
No
DQ5 = 1?
Yes
Read Byte
(DQ0 to DQ7)
Addr. = VA
DQ7 = Data?
*
Yes
No
Fail
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 18
Data Polling Algorithm
41
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Start
Read
(DQ0 to DQ7)
Addr. = “H” or “L”
No
DQ6 = Toggle
?
Yes
No
DQ5 = 1?
Yes
Read Byte
(DQ0 to DQ7)
Addr. = “H” or “L”
DQ6 = Toggle
?*
No
Yes
Fail
Pass
* : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ5 changing to “1”.
Figure 19
42
Toggle Bit Algorithm
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Start
Setup Sector Addr.
(A19, A18, A17, A16,
A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID
A6 = CE = VIL
A0 = VIL, A1 = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector
( A1 = VIH, A0 = VIL,
Addr. = SA, A6 = VIL)*
No
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
Data = 01H?
Yes
Protect Another Sector?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Protection
Completed
* : A-1 is VIL on byte mode.
Figure 20
Sector Protection Algorithm
43
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Start
Temporary Unprotect Enable
Command Write (Note 1)
Perform Erase or
Program Operations
Temporary Unprotect Disable
Command Write
Temporary Sector
Unprotection Completed
(Note 2)
Notes: 1. All protected sectors are unprotected.
2. All previously protected sectors are protected once again.
Figure 21
44
Temporary Sector Unprotection Algorithm
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
Start
555H/AAH
Set Fast Mode
2AAH/55H
555H/20H
XXXXH/A0H
Program Address/Program Data
In Fast Program
Data Polling Device
Verify Byte?
No
Yes
No
Increment Address
Last Address
?
Yes
Programming Completed
XXXH/90H
Reset Fast Mode
XXXH/F0H
* : The sequence is applied for ×16 mode.
* : The addresses differ from ×8 mode.
Figure 22
Embedded Programming Algorithm for Fast Mode
45
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Min.
Typ.
Max.
Sector Erase Time
—
4.8
60
Byte Programming Time
—
8.6
300
Unit
Comments
sec
Excludes programming time
prior to erasure
µs
Excludes system-level
overhead
Excludes system-level
overhead
Word Programming Time
—
12.6
360
Chip Programming Time
—
18
140
sec
100,000
—
—
cycles
Erase/Program Cycle
—
■ PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
6.0
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12.0
pF
CIN2
Control Pin Capacitance
VIN = 0
8.0
11.5
pF
Note: Test conditions TA = 25°C, f = 1.0 MHz
46
Test Setup
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29PL160
T
D
-80
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
PF
=44-Pin Small Outline Package (SOP)
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29PL160
16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Page Mode Flash Memory
3.0 V-only Read, Write, and Erase
47
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
■ PACKAGE DIMENSIONS
48-pin plastic TSOP (I)
(FPT-48P-M19)
*: Resin protruction. (Each side: 0.15(.006) Max)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
24
25
* 12.00±0.20
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
0.10(.004)
(.472±.008)
11.50REF
(.460)
19.00±0.20
(.748±.008)
1996 FUJITSU LIMITED F48029S-2C-2
+0.10
1.10 –0.05
+.004
.043 –.002
(Mounting height)
0.50(.0197)
TYP
0.15±0.05
(.006±.002)
C
0.25(.010)
0.05(0.02)MIN
(STAND OFF)
0.20±0.10
(.008±.004)
0.10(.004)
M
0.50±0.10
(.020±.004)
Dimensions in mm (inches)
(Continued)
48
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
48-pin plastic TSOP (I)
(FPT-48P-M20)
*: Resin protrusion. (Each side: 0.15(.006) Max)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
24
0.25(.010)
25
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
0.15±0.10
(.006±.002)
0.10(.004)
0.20±0.10
(.008±.004)
0.50(.0197)
TYP
0.10(.004)
M
0.05(0.02)MIN
(STAND OFF)
+0.10
1.10 –0.05
* 18.40±0.20
(.724±.008)
20.00±0.20
(.787±.008)
C
1996 FUJITSU LIMITED F48030S-2C-2
+.004
11.50(.460)REF
.043 –.002
(Mounting height)
* 12.00±0.20(.472±.008)
Dimensions in mm (inches)
(Continued)
49
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
44-pin plastic SOP
(FPT-44P-M16)
+0.25
+.010
28.45 –0.20 1.120 –.008
2.35±0.15(.093±.006)
(Mounting height)
44
0.80±0.20
(.031±.008)
23
13.00±0.10 16.00±0.20
(.512±.004) (.630±.008)
14.40±0.20
(.567±.008)
INDEX
LEAD No.
1
22
1.27(.050)TYP
0.10(.004)
+0.10
0.40 –0.05
+.004
.016 –.002
0.15±0.05
(.006±.002)
+0.10
Ø0.13(.005)
M
+.004
0.20 –0.15 .008 –.006
(Stand off)
26.67(1.050)REF
C
50
1998 FUJITSU LIMITED F44023S-4C-4
Dimensions in mm (inches)
MBM29PL160TD-75/-90/MBM29PL160BD-75/-90
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
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equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
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or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
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Any semiconductor devices have an inhereut chance inherently
a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
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F9907
 FUJITSU LIMITED Printed in Japan
51
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