TECHNICAL DATA IN82C55 CHMOS PROGRAMMABLE PERIPHERAL INTERFACE The Integral IN82C55AN is a high-performance, CHMOS version of the industry standard IN82C55AN general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bidirectional bus configuration. FEATURES • • • • • • • • • • Compatible with all Intel and Most Other Microprocessors High Speed, «Zero Wait State» Operation with 8MHz 8086/88 and 80186/188 24 Programmable I/O Pins Low Power CHMOS Completely TTL Compatible Control Word Read-Back Capability Direct Bit Set/Reset Capability 2.5mA DC Drive Capability on all I/O Port Outputs Available in 40-Pin DIP Available in EXPRESS Standard Temperature Range Extended Temperature Range GROUP A CONTROL GROUP A PORT C UPPER (4) DATA BUS BUFFER D7-D0 8 BIT INTERNAL DATA BUS RD WR A1 A0 READ/ WRITE CONTROL LOGIC GROUP A PORT A (8) GROUP B CONTROL Reset CS PA7-PA0 PC7-PC4 GROUP B PORT C LOWER (4) PC3-PC0 GROUP B PORT B (8) PB7-PB0 PA3 PA2 PA1 PA0 RD CS VSS A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA4 PA5 PA6 PA7 WR Reset D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3 Figure 1 Figure 2 Rev. 00 IN82C55A Symbol PA3-0 Pin number 1-4 Type I/O RD CS 5 6 I I GND A1-0 7 8-9 I Name and Function PORT A, PINS 0-3: Lower nibble of an 8-bit data output latch buffer and an 8-bit data input latch. READ CONTROL: This input is low during CPU read operations. CHIP SELECT: A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise. System Ground. ADDRESS: These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers. Input Operation (Read) A1 A0 CS WR RD Port A - Data Bus 0 0 0 1 0 Port B - Data Bus 0 1 0 1 0 Port C - Data Bus 1 0 0 1 0 Control Word - Data Bus 1 1 0 1 0 Output Operation (Write) 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 Data Bus - Port A Data Bus - Port B Data Bus - Port C Data Bus – Control Disable Function PC7-4 10-13 I/O PC0-3 PB0-7 14-17 18-25 I/O I/O VCC D7-0 26 27-34 I/O RESET 35 I WR PA7-4 36 37-40 I I/O Data Bus-3-State x x x x 1 Data Bus-3-State x x 1 1 0 PORT C, PINS 4-7: Upper nibble of an 8-bit data output latch/buffer and an 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. PORT C, PINS 0-3: Lower nibble of Port C. PORT B, PINS 0-7: An 8-bit data output latch/buffer and an 8-bit data input buffer SYSTEM POWER: +5V Power Supply DATA BUS: Bi-directional, tri-state data bus lines, connected to system data bus RESET: A high on this input clears the control register and all ports are set to the input mode WRITE CONTROL: This input is low during CPU write operations PORT A PINS 4-7: Upper nibble of an 8-bit data output latch/buffer and an 8-bit data input latch Rev. 00 IN82C55A IN82C55AN FUNCTIONAL DESCRIPTION General The IN82C55AN is a programmable peripheral interface device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configuration of the IN82C55AN is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures. Data Bus Buffer This 3-state bidirectional 8-bit buffer is used to interface the IN82C55AN to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the IN82C55AN. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control Logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0) The control word register can be both written and read as shown in the address decode table in the pin descriptions. Figure 6 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic “1”, as this implies control word mode information. Ports A, B, and C The IN82C55AN contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the IN82C55AN. Port A. One 8-bit data output latch/buffer and one 8-bit input latch/buffer. Both “pull-up” and “pull-down” bus hold devices are present on Port A. Port B. One 8-bit data input/output latch/buffer. Only “pull-up” bus hold devices are present on Port B. Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. Only “pull-up” bus hold devices are present on Port C. See Figure 4 for the bus-hold circuit configuration for Port A, B, and C. Rev. 00 IN82C55A GROUP A CONTROL GROUP A PORT A (8) GROUP A PORT C UPPER (4) DATA BUS BUFFER D7-D0 8 BIT INTERNAL DATA BUS RD WR A1 A0 READ/ WRITE CONTROL LOGIC GROUP B CONTROL PA7-PA0 PC7-PC4 GROUP B PORT C LOWER (4) PC3-PC0 GROUP B PORT B (8) PB7-PB0 Reset CS Figure 3. IN82C55AN Block Diagram Showing Data Bus Buffer and Read Write Control Logic Functions * RESET EXTERNAL INTERNAL PORT A DATA OUT PIN INTERNAL DATA IN INTERNAL DATA OUT VCC WR RESET P* EXTERNAL PORT B,C PIN INTERNAL DATA OUT WR *NOTE: Port pins loaded with more than 20pF capacitance may not have their logic level guaranteed following a hardware reset. Figure 4. Port A, B, C, Bus-hold Configuration Rev. 00 IN82C55A IN82C55AN OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software: Mode 0 - Basic input/output Mode 1 - Strobed Input/output Mode 2 - Bi-directional Bus When the reset input goes “high” all ports will be set to the input mode with all 24 port lines held at a logic “one” level by the internal bus hold devices (see Figure 4 Note). After the reset is removed the IN82C55AN can remain in the input mode with no additional initialization required. This eliminates the need for pullup or pulldown devices in “all CMOS” designs. During the execution of the system program, any of the other modes may be selected by using a single output instruction. This allows a single IN82C55AN to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be “tailored” to almost any I/O structure. For instance; Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interruptdriven basis. ADRESS BUS CONTROL BUS DATA BUS 8 RD, WR B MODE 0 8 A0, A1 C A 4 PB7-PB0 4 PC7-PC4 PC3-PC0 B MODE 1 D7-D0 C PA7-PA0 A 8 8 PB7-PB0 MODE 2 8 CONTROL OR I/O B CONTROL OR I/O C PA7-PA0 A 8 PB7-PB0 8 I/O CONTROL PA7-PA0 Figure 5. Basic Mode Definitions and Bus Interface Rev. 00 IN82C55A D7 D6 D5 D4 D3 D2 D1 D0 GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 0 = MODE 0 1 = MODE 1 GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2 MODE SET FLAG 1 = ACTIVE Figure 6. Mode Definition Format The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. Single Bit Set/Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. This feature reduces software requirements in Control-based applications. When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports. D7 D6 D5 D4 D3 D2 D1 D0 BIT SET/RESET 1 = SET 0 =RESET DON’T CARE BIT SELECT 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 B0 0 0 1 1 0 0 1 1 B1 0 0 0 0 1 1 1 1 B2 BIT SET/RESET FLAG 0 = ACTIVE Figure 7. Bit Set/Reset Format Rev. 00 IN82C55A Interrupt Control Functions When the IN82C55AN is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. This function allows the Programmer to disallow or allow a specific I/O device to interrupt the CPU without affecting any other device in the interrupt structure. INTE flip-flop definition: (BIT-SET) - INTE is SET - Interrupt enable (BIT-RESET) – INTE is RESET - Interrupt disable Note: All Mask flip-flops are automatically reset during mode selection and device Reset. Operating Modes Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No “handshaking” is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions: • • • • • Two 8-bit ports and two 4-bit ports. Any port can be input or output. Outputs are latched. Inputs are not latched. 16 different Input/Output configurations are possible in this Mode. MODE 0 (BASIC INPUT) tRR RD tIR tHR INPUT tAR tRA CS, A 1 , A 0 D 7 -D 0 tRD tDF Rev. 00 IN82C55A MODE 0 (BASIC OUTPUT) tWW WR tDW tWD D7-D0 tWA tAW CS ,A1,A0 OUTPUT tWB MODE 0 Port Definition A B GROUP A D4 D3 D1 D0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GROUP B PORT A PORT C (UPPER) # PORT B PORT C (LOWER) OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT MODE 0 Configurations CONTROL WORD #0 D7 D6 D5 D4 1 0 0 0 D3 0 A D2 0 D1 0 D0 0 CONTROL WORD #1 D7 D6 D5 D4 1 0 0 0 D3 0 8 PA7-PA0 A 4 D2 0 C… PA7-PA0 4 4 PC7-PC4 D7-D0 C… 4 PC3-PC0 PC3-PC0 8 B D0 1 8 PC7-PC4 D7-D0 D1 0 8 PB7-PB0 B PB7-PB0 Rev. 00 IN82C55A CONTROL WORD #2 D7 D6 D5 D4 1 0 0 0 D3 0 A D2 0 D1 1 D0 0 CONTROL WORD #3 D7 D6 D5 D4 1 0 0 0 D3 0 8 PA7-PA0 A 4 D2 0 C… PA7-PA0 4 4 PC7-PC4 D7-D0 C… 4 PC3-PC0 PC3-PC0 8 CONTROL WORD #4 D7 D6 D5 D4 1 0 0 0 D3 1 A 8 PB7-PB0 B D2 0 D1 0 D0 0 PB7-PB0 B CONTROL WORD #5 D7 D6 D5 D4 1 0 0 0 D3 1 8 PA7-PA0 A 4 D2 0 C… PA7-PA0 PC7-PC4 D7-D0 C… 4 PC3-PC0 PC3-PC0 8 CONTROL WORD #6 D7 D6 D5 D4 1 0 0 0 D3 1 A 8 PB7-PB0 D2 0 D1 1 D0 0 PB7-PB0 B CONTROL WORD #7 D7 D6 D5 D4 1 0 0 0 D3 1 8 PA7-PA0 A 4 D2 0 C… PA7-PA0 PC7-PC4 D7-D0 C… 4 PC3-PC0 PC3-PC0 8 CONTROL WORD #8 D7 D6 D5 D4 1 0 0 1 D3 0 A 8 PB7-PB0 D2 0 D1 0 D0 0 PB7-PB0 B CONTROL WORD #9 D7 D6 D5 D4 1 0 0 1 D3 0 8 PA7-PA0 A 4 D2 0 C… D0 1 PA7-PA0 4 4 PC7-PC4 D7-D0 C… 4 PC3-PC0 PC3-PC0 8 B D1 0 8 PC7-PC4 D7-D0 D0 1 4 4 B D1 1 8 PC7-PC4 D7-D0 D0 1 4 4 B D1 0 8 PC7-PC4 D7-D0 D0 1 8 PC7-PC4 D7-D0 D1 1 8 PB7-PB0 B PB7-PB0 Rev. 00 IN82C55A CONTROL WORD #10 D7 D6 D5 D4 1 0 0 1 D3 0 A D2 0 D1 1 D0 0 CONTROL WORD #11 D7 D6 D5 D4 1 0 0 1 D3 0 8 PA7-PA0 A 4 D2 0 C… PA7-PA0 4 4 PC7-PC4 D7-D0 C… 4 PC3-PC0 PC3-PC0 8 CONTROL WORD #12 D7 D6 D5 D4 1 0 0 1 D3 1 A 8 PB7-PB0 B D2 0 D1 0 D0 0 PB7-PB0 B CONTROL WORD #13 D7 D6 D5 D4 1 0 0 1 D3 1 8 PA7-PA0 A 4 D2 0 C… PA7-PA0 PC7-PC4 D7-D0 C… 4 PC3-PC0 PC3-PC0 8 CONTROL WORD #14 D7 D6 D5 D4 1 0 0 1 D3 1 A 8 PB7-PB0 D2 0 D1 1 D0 0 PB7-PB0 B CONTROL WORD #15 D7 D6 D5 D4 1 0 0 1 D3 1 8 PA7-PA0 A 4 D2 0 D7-D0 D0 1 PA7-PA0 4 4 PC7-PC4 D7-D0 C… 4 PC3-PC0 PC3-PC0 8 B D1 1 8 PC7-PC4 C… D0 1 4 4 B D1 0 8 PC7-PC4 D7-D0 D0 1 8 PC7-PC4 D7-D0 D1 1 8 PB7-PB0 B PB7-PB0 Operating Modes MODE 1 (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “handshaking” signals. In mode 1, Port A and Port B use the lines on Port C to generate or accept these “handshaking” signals. Mode 1 Basic functional Definitions: • Two Groups (Group A and Group B). • Each group contains one 8-bit data port and one 4-bit control/data port. • The 8-bit data port can be either input or output • Both inputs and outputs are latched. • The 4-bit port is used for control and status of the Rev. 00 IN82C55A • 8-bit data port. Input Control Signal Definition STB (Strobe Input). A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F) A “high” on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgement. IBF is set by STB input being low and is reset by the rising edge of the RD input. INTR (Interrupt Request) A “high” on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the STB is a “one”, IBF is a “one” and INTE is a “one”. It is reset by the falling edge of RD . This procedure allows an input device to request service from the CPU by simply strobing its data into the port. INTE A Controlled by bit set/reset of PC4. INTE B Controlled by bit set/reset of PC2 MODE 1 (PORT A) CONTROL WORD D7 D6 D5 D4 1 0 1 1 D3 1/0 D2 X D1 X D0 X PA7-PA0 INTE A 8 PC4 STBA PC5 IBFA PC3 INTRA PC6,7 1 = INPUT 0 = OUTPUT 2 RD PC6,7 MODE 1 (PORT B) CONTROL WORD D6 D5 D4 D7 1 X X X D3 X D2 1 D1 1 D0 X PB7-PB0 INTE B RD 8 PC2 STBB PC1 IBFB PC0 INTRB Figure 8. MODE 1 Input Rev. 00 IN82C55A tST STB tSIB IBF tSIT tRIB INTR tRIT RD tPH INPUT FROM PERIPHERAL tPS Figure 9. MODE 1 (Strobed Input) Output Control Signal Definition OBF (Output Buffer Full F/F). The OBF output will go “low” to indicate that the CPU has written data out to the specified port. The OBF F/F will be set by the rising edge of the WR input and reset by ACK Input being low. ACK (Acknowledge Input). A “low” on this input informs the IN82C55AN that the data from Port A or Port B has been accepted. In essence, a response from the peripheral device indicating that it has received the data output by the CPU. INTR (Interrupt Request). A “high” on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set when ACK is a “one”, OBF is a “one” and INTE is a “one”. It is reset by the falling edge of WR . INTE A Controlled by bit set/reset of PC6. INTE B Controlled by bit set/reset of PC2. MODE 1 (PORT A) CONTROL WORD D7 D6 D5 D4 1 0 1 0 D3 1/0 D2 X D1 X D0 X PA7-PA0 INTE A 8 PC6 ACKA PC7 OBFA PC3 INTRA PC6,7 1 = INPUT 0 = OUTPUT 2 WR PC4,5 MODE 1 (PORT B) CONTROL WORD D7 D6 D5 D4 1 X X X D3 X D2 1 D1 0 D0 X PB7-PB0 INTE B WR 8 PC2 ACKB PC1 OBFB PC0 INTRB Figure 10. MODE 1 Output Rev. 00 IN82C55A WR tAOB OBF tWOB INTR tWIT ACK tAIT tAK OUTPUT tWB Figure 11. MODE 1 (Strobed Output) Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications. PA7-PA0 CONTROL WORD D7 D6 D5 D4 1 0 1 1 D3 1/0 D2 1 D1 0 PC6,7 1 = INPUT 0 = OUTPUT WR PORT A – STROBED INPUT PORT B – STROBED OUTPUT RD D0 X 8 PA7-PA0 PC4 STBA PC5 IBFA PC3 INTRA PC6,7 PB7-PB0 2 CONTROL WORD D7 D6 D5 D4 1 0 1 0 D3 1/0 D2 1 D1 1 D0 X OBFB PC2 ACKB PC0 INTRB PC7 OBFA PC6 PC4,5 1 = INPUT 0 = OUTPUT 8 PC1 8 WR PORT A – STROBED OUTPUT PORT B – STROBED INPUT RD ACKA PC3 PC4,5 PB7-PB0 2 INTRA 8 PC2 STBB PC1 IBFB PC0 INTRB Figure 12. Combinations of MODE 1 Operating Modes MODE 2 (Strobed Bidirectional Bus I/O).This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). “Handshaking” signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions: • • • Used in Group A only. One 8-bit, bi-directional bus port (Port A) and a 5- bit control port (Port C). Both inputs and outputs are latched. • The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A). Rev. 00 IN82C55A Bidirectional Bus I/O Control Signal Definition INTR (Interrupt Request). A high on this output can be used to interrupt the CPU for input or output operations. Output Operations OBF (Output Buffer Full). The OBF output will go “low” to indicate that the CPU has written data out to port A. ACK (Acknowledge). A “low” on this input enables the tri-state output buffer of Port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 (The INTE Flip-Flop Associated with OBF ). Controlled by bit set/reset of PC6. Input Operations STB (Strobe Input). A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F). A “high” on this output indicates that data has been loaded into the input latch. INTE 2 (The INTE Flip-Flop Associated with IBF). Controlled by bit set/reset of PC4. CONTROL WORD D7 D6 D5 D4 1 1 X X D3 X D2 1/0 D1 1/0 PC3 D0 1/0 INTRA PA7-PA0 PC2-0 1 – INPUT 0 – OUTPUT INTE 1 PORT B 1 – INPUT 0 – OUTPUT GROUP B 1 – INPUT 0 – OUTPUT WR RD INTE 2 PC7 OBFA PC6 ACKA PC4 STBA PC5 IBFA 3 PC2-0 Figure 13. MODE Control Word Figure 14. MODE 2 Rev. 00 IN82C55A DATA FROM CPU TO IN82C55AN WR tAOB OBF tWOB INTR tAK ACK tST STB tSIB IBF tAD tKD tPS PERIPHERAL BUS tRIB tPH RD DATA FROM PERIPHERAL TO IN82C55AN DATA FROM IN82C55AN TO PERIPHERAL DATA FROM IN82C55AN TO 8080 Figure 15. MODE 2 (Bidirectional) NOTE: Any sequence where WR occurs before ACK , and STB occurs before ( INTR = IBF ∗ MASK ∗ STB ∗ RD + OBF ∗ MASK ∗ ACK ∗ WR ) RD is permissible. Rev. 00 IN82C55A INTRA PC3 CONTROL WORD D7 D6 D5 D4 1 1 X X D3 X D2 0 D1 1 PA7-PA0 D0 1/0 PC2-0 1 = INPUT 0 = OUTPUT MODE 2 AND MODE 0 (INPUT) PC7 OBFA PC6 ACKA PC4 STBA PC5 WR PC2-0 D3 X D2 0 MODE 2 AND MODE 0 (OUTPUT) D1 0 PA7-PA0 PC7 OBFA PC6 ACKA PC4 STBA PC2-0 D0 X WR IBFA 3 8 INTRA PC3 INTRA CONTROL WORD D7 D6 D5 D4 1 1 X X D3 X D2 1 D1 1 D0 X PA7-PA0 8 PC7 PC7 OBFA PC6 ACKA PC6 ACKA PC4 STBA PC4 STBA PB7-PB0 RD PB7-PB0 8 PC5 MODE 2 AND MODE 1 (OUTPUT) 8 PC5 WR 8 PC3 D2 1 PA7-PA0 RD PB7-PB0 D3 X D0 1/0 PC2-0 1 = INPUT 0 = OUTPUT RD CONTROL WORD D7 D6 D5 D4 1 1 X X D1 0 IBFA 3 INTRA PC3 CONTROL WORD D7 D6 D5 D4 1 1 X X 8 OBFA PC5 IBFA 8 MODE 2 AND MODE 1 (INPUT) WR RD PB7-PB0 IBFA 8 PC1 OBFB PC1 STBB PC2 ACKB PC2 IBFB PC0 INTRB PC0 INTRB Figure 16. MODE 1/4 Combinations Mode Definition Summary PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 IN MODE0 OUT IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT MODE1 OUT IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN INTRB IBFB STB B INTRA STB A IBFA I/O I/O B B B INTRA I/O I/O MODE2 GROUP A ONLY ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ I/0 I/O I/O INTRA STB A IBFA ACK A OBF A ACK A OBF A OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT INTRB B OBF B ACK B B B MODE 0 OR MODE1 ONLY Rev. 00 IN82C55A Special Mode Combination Considerations There are several combinations of modes possible. For any combination, some or all of the Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a “Set Mode” command. During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 18. Through a “Write Port C” command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a “Write Port C” command, nor can the interrupt enable flags be accessed. To write to any Port C output programmed as an output in a Mode 1 group or to change an interrupt enable flag, the “Set/Reset Port C Bit” command must be used. With a “Set/Reset Port C Bit” command, any Port C line programmed as an output (including INTR, IBF and OBF ) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C are not affected by a “Set/Reset Port C Bit” command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the “Set/Reset Port C Bit” command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 18. Current Drive Capability Any output on Port A, B or C can sink or source 2.5mA. This feature allows the IN82C55AN to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. Reading Port C Status In Mode 0, Port C transfers data to or from the peripheral device. When the IN82C55AN is programmed to function in Modes 1 or 2, Port C generates or accepts “hand-shaking” signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the “status” of each peripheral device and change the program flow accordingly. There is no special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function. D7 I/O D7 OBFA D6 I/O INPUT CONFIGURATION D5 D4 D3 D2 D1 D0 IBFA INTEA INTRA INTEB IBFB INTRB GROUP A GROUP B OUTPUT CONFIGURATION D6 D5 D4 D3 D2 D1 D0 INTEA I/O I/O INTRA INTEB OBFB INTRB GROUP A GROUP B Figure 17a. MODE 1 Status Word Format D7 OBFA D6 INTE1 D5 D4 D3 IBFA INTE2 INTRA GROUP A (Defined by mode 0 or mode 1 selektion) D2 D1 D0 GROUP B Figure 17b. MODE 2 Status Word Format Rev. 00 IN82C55A Interrupt Enable Flag INTEB INTEA2 INTEA1 Position PC2 PC4 PC6 Alternate ACKB (Output Mode 1) or STBB (Input Mode 1) STBA (Input Mode 1 or Mode 2) ACKA (Output Mode 1 or Mode 2) Figure 18. Interrupt Enable Flags in Modes 1 and 2 ABSOLUTE MAXIMUM RATINGS* 0OC to + 70OC - 65OC to + 150OC - 0.5 to + 8.0V + 4V to + 7V GND-2V to + 6.5V GND-0.5V to VCC + 0.5V 1Watt Ambient Temperature Under Bias Storage Temperature Supply Voltage Operating Voltage Voltage on any Input Voltage on any Output Power Dissipation NOTICE: This is a production data sheet. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. D.C. CHARACTERISTICS TA = 0OCto70OC, VCC =+5V ±10%, GND = 0V (TA =-40OC to +85OC for Extended Temperature) Symbol VIL VIH VOL VOH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IIL IOFL Input Leakage Current Output Float Leakage Current Darlington Drive Current IDAR IPHL IPHH IPHLO IPHHO ICC ICCSB Port Hold Low Leakage Current Port Hold High Leakage Current Port Hold Low Overdrive Current Port Hold High Overdrive Current VCC Supply Current VCC Supply Current-Standby Min -0.5 2.0 Max 0.8 VCC 0.4 3.0 VCC - 0.4 ±1 ±10 Units V V V V V μA μA ±2.5 (Note 4) mA +50 +300 μA -50 -300 μA Test Conditions IOL = 2.5mA IOH =-2.5mA IOH =-100μA VIN = VCC to 0V (Note 1) IN = VCC to 0V (Note 2) -350 μA Ports A,B,C Rext = 500Ω Vext = 1.7V VOUT = 1.0V Port A only VOUT = 3.0V Ports A,B,C VOUT = 0.8V +350 μA VOUT = 3.0V mA μA (Note 3) VCC = 5.5V VIN = VCC or GND Port Conditions If I/P = Open/High O/P = Open Only With Data Bus = High/Low CS = High Reset = Low Pure Inputs = Low/High 10 10 Rev. 00 IN82C55A NOTES: 1. 2. 3. 4. Pins A1, A0, CS, WR, RD, Reset Data Bus; Ports B, C Outputs open. Limit output current to 4.0mA. CAPACITANCE TA = 25OC, VCC = GND = 0V Symbol Parameter CIN Input Capacitance CI/O I/O Capacitance Min Max 10 20 Units pF pF TestConditions Unmeasured pins returned to GND fC = 1MHz(5) NOTE: 5. Sampled not 100% tested. A.C. CHARACTERISTICS TA = 0O to 70OC, VCC = +5V ±10%, GND = 0V TA = -40OC to +85OC for Extended Temperature BUS PARAMETERS READ CYCLE Symbol tAR tRA tRR tRD tDF tRV Parameter Address Stable Before RD _ Address Hold Time After RD _ RD Pulse Width Data Delay from RD _ RD _ to Data Floating Recovery Time between RD / WR Min Max Units 0 0 150 10 200 Test Conditions ns ns ns ns ns ns 120 75 WRITE CYCLE Symbol Parameter tAW tWA Address Stable Before WR _ Address Hold Time After WR _ tWW tDW tWD WR Pulse Width Data Setup Time Before WR _ Data Hold Time After WR _ Min 0 20 20 100 100 30 30 Max Units ns ns ns ns ns ns ns Test Conditions PortsAB PortC PortsAB PortC Rev. 00 IN82C55A OTHER TIMINGS Symbol tWB tlR tHR tAK tST tPS tPH tAD tKD tWOB tAOB tSIB tRIB tRIT tSIT tAIT tWIT tRES Parameter WR = 1 to Output Peripheral Data Before RD Peripheral Data After RD ACK Pulse Width STB Pulse Width Per. Data Before STB High Per. Data After STB High ACK = 0 to Output ACK = 1 to Output Float WR = 1 to OBF = 0 ACK = 0 to OBF = 1 STB = 0 to IBF = 1 RD = 1 to IBF = 0 RD = 0 to INTR = 0 STB = 1 to INTR = 1 ACK = 1 to INTR = 1 WR = 0 to INTR = 0 Reset Pulse Width Min Max 350 0 0 200 100 20 50 20 175 250 150 150 150 150 200 150 150 200 500 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions see note1 see note2 NOTE 1. INTR_ may occur as early as WR _. 2. Pulse width of initial Reset pulse after power on must be at least 50μSec. Subsequent Reset pulses may be 500ns minimum. The output Ports A B or C may glitch low during the reset pulse but all port pins will be held at a logic “one” level after the reset pulse. WRITE TIMING A0-1,CS tAW tWA DATA BUS tDW tWD WR tWW Rev. 00 IN82C55A READ TIMING A0-1,CS tAR DATA BUS tRA VALID HIGH IMPEDANCE HIGH IMPEDANCE tRD tDR RD tRR A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 2.4 2.0 2.0 CL=150pF TEST POINTS 0.8 0.8 0.45 A.C. Testing Inputs Are Driven At 2.4V For A Logic 1 And 0.45V For A Logic 0 Timing Measurements Are Made At 2.0V For A Logic 1 And 0.8 For A Logic 0. A.C. TESTING LOAD CIRCUIT DEVICE UNDER TEST VEXT* CL=150pF *VEXT Is Set At Various Voltages During Testing To Guarantee The Specification. C L Includes Jig Capacitance. Rev. 00 IN82C55A 40-Pin Plastic Dual-in-Line Dimension, mm A Aı A2 B B2 C D E E1 e e2 L α max min min max min max min max min max min max min max min max nom nom 6.35 0.38 3.18 4.95 0.36 0.56 0.77 1.78 0.20 0.38 50.30 53.20 15.24 15.87 12.32 14.73 2.54 15.24 min max min max 2.92 5.08 0º 10º Rev. 00