ISSI IS25C08B 8k-bit spi serial electrically erasable prom Datasheet

IS25C08B
8K-BIT SPI SERIAL
ELECTRICALLY ERASABLE PROM
Preliminary Information
September 2009
DESCRIPTION
FEATURES
• Serial Peripheral Interface (SPI) Compatible
— Supports SPI Modes 0 (0,0) and 3 (1,1)
• Wide-voltage Operation
— Vcc = 1.8V to 5.5V
• Low power CMOS
— Operating current less than 1 mA (1.8V)
— Standby current less than 1 µA (1.8V)
• Block Write Protection
— Protect 1/4, 1/2, or Entire Array
• 32-byte page write mode
— Partial page writes allowed
• 20 MHz Clock Rate (5V)
• Self timed write cycles (5 ms Typical)
• High-reliability
— Endurance: 1 million cycles per byte
— Data retention: 100 years
• Industrial grade
• Packages: SOIC/SOP, TSSOP, UDFN and CSP
The IS25C08B is an 8Kbit (1024x 8) electrically
erasable PROM devices that use the Serial Peripheral
Interface (SPI) for communications.
This EEPROM operates in a wide voltage range of 1.8V
to 5.5V to be compatible with most application voltages.
ISSI designed this device to be a practical, low-power SPI
EEPROM solution. The devices are offered in lead-free,
RoHS, halogen free or Green. The available package types
are 8-pin SOIC, TSSOP, UDFN and CSP.
The functional features of the IS25C08B allow them to
be among the most advanced serial non-volatile memories available. Each device has a Chip-Select (CS) pin,
and a 3-wire interface of Serial Data In (SI), Serial Data
Out (SO), and Serial Clock (SCK). While the 3-wire
interface of the IS25C08B provides for high-speed access, a HOLD pin allows the memories to ignore the
interface in a suspended state; later the HOLD pin reactivates communication without re-initializing the serial
sequence. A Status Register facilitates a flexible write
protection mechanism, and a device-ready bit (RDY).
Copyright © 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace systems, or for other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best
performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services described
herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
Rev. 00A
1
IS25C08B
PIN CONFIGURATION
8-pad UDFN
8-Pin SOIC and TSSOP
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
(Top View)
PIN DESCRIPTIONS
CS
SCK
SI
SO
GND
Vcc
WP
HOLD
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power
Write Protect
Suspends Serial Input
PIN DESCRIPTIONS
Serial Clock (SCK): This timing signal provides
synchronization between the microcontroller and
IS25C08B. Op-Codes, byte addresses, and data are
latched on SI with a rising edge of the SCK. Data on
SO is refreshed on the falling edge of SCK for SPI
modes (0,0) and (1,1).
Serial Data Input (SI): This is the input pin for all data
that the IS25C08B is required to receive.
Serial Data Output (SO): This is the output pin for all
data transmitted from the IS25C08B.
2
Chip Select (CS): The CS pin activates the device.
Upon power-up, CS should follow Vcc. When the device is to be enabled for instruction input, the signal requires a High-to-Low transition. While CS is stable Low,
the master and slave will communicate via SCK, SI, and
SO signals. Upon completion of communication, CS
must be driven High. At this moment, the slave device
may start its internal write cycle. When CS is high, the
device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.
Write Protect (WP): The purpose of this input signal is
to initiate Hardware Write Protection mode. This mode
prevents the Block Protection bits and the WPEN bit in
the Status Register from being altered. To cause Hardware Write Protection, WP must be Low at the same
time WPEN is 1. WP may be hardwired to Vcc or GND.
HOLD (HOLD): This input signal is used to suspend
the device in the middle of a serial sequence and temporarily ignore further communication on the bus (SI,
SO, SCK). Together with Chip Select, the HOLD signal
allows multiple slaves to share the bus. The HOLD
signal transitions must occur only when SCK is Low,
and be held stable during SCK transitions. (See Figure
8 for Hold timing) To disable this feature, HOLD may be
hardwired to Vcc.
Integrated Silicon Solution, Inc.
Preliminary Information Rev. 00A
08/25/09
IS25C08B
SERIAL INTERFACE DESCRIPTION
MASTER: The device that provides a clock signal.
SLAVE: The IS25C08B is a slave because the clock
signal is an input.
TRANSMITTER/RECEIVER: The IS25C08B has both
data input (SI) and data output (SO).
MSB: The most significant bit. It is always the first bit
transmitted or received.
OP-CODE: The first byte transmitted to the slave following CS transition to LOW. If the OP-CODE is a valid
member of the IS25C08B instruction set (Table 3), then
it is decoded appropriately. If the OP-CODE is not valid,
and the SO pin remains in high impedance.
Block Diagram
VCC
STATUS
REGISTER
GND
1024 x 8
MEMORY ARRAY
DATA
REGISTER
ADDRESS
DECODER
SI
CS
WP
SCK
OUTPUT
BUFFER
MODE
DECODE
LOGIC
CLOCK
SO
HOLD
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
Rev. 00A
3
IS25C08B
STATUS REGISTER
The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is accessible by the user.
Table 1. Status Register Format
Bit 7
WPEN
Bit 6 Bit 5 Bit 4
X
X
X
Bit 3 Bit 2 Bit1 Bit 0
BP1 BP0 WEN RDY
Notes:
1. X = Don't care bit.
Block Protect (BP1, BP0), Bits 2-3: Together, these
bits represent one of four block protection configurations implemented for the memory array. (See Table 2
for details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block
of memory defined by these bits is always protected,
regardless of the setting of WPEN, WP , or WEN.
Table 2. Block Protection
Status
Register
Bits
Array Addresses Protected
2. During internal write cycles, bits 0 to 7 are temporarily 1's.
The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 0. If
neither is true, it can be modified by a valid instruction.
Ready (RDY), Bit 0: When RDY = 1, it indicates that
the device is busy with a write cycle. RDY = 0 indicates
that the device is ready for an instruction. If RDY = 1,
the only command that will be handled by the device is
Read Status Register.
Write Enable (WEN), Bit 1: This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modification, regardless of the setting of WPEN, WP pin, or
block protection. The only way to set WEN to 1 is via
the Write Enable command (WREN). WEN is reset to 0
upon power-up.
4
Level
0
1(1/4)
BP1
0
0
BP0
0
1
2(1/2)
1
0
3(All)
1
1
IS25C08B
None
0300h
-03FFh
0200h
-03FFh
0000h
-03FFh
Don’t Care, Bits 4-6: Each of these bits can receive either 0 or 1, but values will not be retained. When these
bits are read from the register, they are always 0.
Write Protect Enable (WPEN), Bit 7: This bit can be
used in conjunction with WP pin to enable Hardware
Write Protection, which causes the Status Register to
be read-only. The memory array is not protected by this
mode. Hardware Write Protection requires that WP = 0
and WPEN = 1; it is disabled otherwise. Note: WPEN
cannot be changed from 1 to 0 if the WP pin is already
set to Low. (See Table 4 for data protection relationship)
Integrated Silicon Solution, Inc.
Preliminary Information Rev. 00A
08/25/09
IS25C08B
DEVICE OPERATION
The operations of the IS25C08B are controlled by a set of instructions that are clocked-in serially SI pin. (See Table
3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition
of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to
input an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of
SK. All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-to-High
transition of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no
internal programming were underway.
Table 3. Instruction Set
Name
Op-code
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
RDSR
WRSR
READ
WRITE
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Array
Write Data to Array
Address
Data(SI)
Data (SO)
-
-
-
A15-A0
A15-A0
D7-D0
D7-D0,...
D7-D0,...
D7-D0,...
-
1. X = Don’t care bit. For consistency, it is best to use “0”.
2. Some address bits are don’t care. See Table 5.
3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no
affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify
the array or Status Register to be ignored.
WRITE ENABLE (WREN)
When Vcc is initially applied, the device powers up with
both status register and entire array in a write-disabled
state. Upon completion of Write Disable (WRDI),
Write Status Register (WRSR), or Write Data to Array
(WRITE), the device resets the WEN bit in the Status
Register to 0. Prior to any data modification, a WREN
instruction is necessary to set WEN to 1. (See Figure 2
for timing).
WRITE DISABLE (WRDI)
The device can be completely protected from modification by resetting WEN to 0 through the WRDI instruction. (See Figure 3 for timing).
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
Rev. 00A
READ STATUS REGISTER (RDSR)
The Read Status instruction tells the user the status of
Write Protect Enable, the Block Protection setting (see
Table 2), the Write Enable state, and the RDY status.
RDSR is the only instruction accepted when a write
cycle is underway. It is recommended that the status
of Write Enable and RDY be checked, especially prior
to an attempted modification of data. The 8 bits of the
Status Register can be repeatedly output on SO after
the initial Op-code. (See Figure 4 for timing).
5
IS25C08B
WRITE STATUS REGISTER (WRSR)
This instruction lets the user choose a Block Protection
setting, and set or reset the WPEN bit. The values of
the other data bits incorporated into WRSR can be 0 or
1, and are not stored in the Status Register. WRSR will
be ignored unless both the following are true: a) WEN
= 1, due to a prior WREN instruction; and b) Hardware
Write Protection is not enabled. (See Table 4 for details). Except for the RDY status, the values in the Status Register remain unchanged until the moment when
the write cycle is complete and the register is updated.
Note: WPEN can be changed from 1 to 0 only if WP
is already set High. Once completed, WEN is reset for
complete chip write protection. (See Figure 5 for timing).
READ DATA (READ)
This instruction begins with the op-code and the 16bit address, and causes the selected data byte to be
shifted out on SO. Following this first data byte, additional sequential bytes are output. If the data byte in the
highest address is output, the address rolls-over to the
lowest address in the array, and the output could loop
indefinitely. At any time, a rising CS signal completes
the operation. (See Figure 6 for timing).
WRITE DATA (WRITE)
The WRITE instruction begins with the op-code, the
16-bit address of the first byte to be modified, and the
first data byte. Additional data bytes may be written sequentially to the array after the first byte. Each WRITE
instruction can affect the contents of a 32-byte page,
but no more. The page begins at address XXXXXXXX
XXXX0000, and ends with XXXXXXXX XXXX1111.
If the last byte of the page is input, the address rolls
over to the beginning of the same page. More than 32
data bytes can be input during the same instruction,
but upon a completed write cycle, a page would only
contain the last 32 bytes.
The region of the array defined within Block Protection
cannot be modified as long as that block configuration
is selected. The region of the array outside the Block
Protection can only be modified if Write Enable (WEN)
is set to 1. Therefore, it may be necessary that a WREN
instruction occur prior to WRITE. Hardware Write Protection has no affect on the memory array. Once Write is
completed, WEN is reset for complete chip write protection. (See Figure 7 for timing).
Table 5. Address Key
Name
IS25C08B
AN
Don't
Care Bits
A9-A0
A15-A10
Table 4. Write Protection
WPEN
WP
Hardware Write
WEN
Inside Block
Outside Block
Protection
Status Register
(WPEN, BP1, BP0)
0
X
Not Enabled
0
Read-only
Read-only
Read-only
0
1
1
X
0
0
Not Enabled
Enabled
Enabled
1
0
1
Read-only
Read-only
Read-only
Unprotected
Read-only
Unprotected
Unprotected
Read-only
Read-only
X
1
Not Enabled
0
Read-only
Read-only
Read-only
X
1
Not Enabled
1
Read-only
Unprotected
Unprotected
Note: X = Don't care bit.
6
Integrated Silicon Solution, Inc.
Preliminary Information Rev. 00A
08/25/09
IS25C08B
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vs
Vp
Tbias
Tstg
Iout
Parameter
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
Value
-0.5 to + 6.5
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
5
Unit
V
V
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions outside those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING RANGE (IS25C08B-2)
Range
Industrial
Ambient Temperature
–40°C to +85°C
Vcc
1.8V to 5.5V
Note: ISSI offers Industrial grade for Commercial applications (0oC to +70oC).
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters and
not 100% tested.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
Rev. 00A
7
IS25C08B
DC ELECTRICAL CHARACTERISTICS
Ta = –40°C to +85°C (Industrial)
Symbol
Icc
Parameter1
Vcc
Test Conditions
Operating Current 1.8V
Read/Write at 5 MHz
2.5V
Read/Write at 10 MHz
5V
Read/Write at 20 MHz
Isb
Standby Current
1.8V
Vin = Vcc or GND
CS = Vcc
2.5V
Vin = Vcc or GND
CS = Vcc
5V
Vin = Vcc or GND
CS = Vcc
Vol
Output LOW Voltage
1.8V
Iol = 0.15 mA
2.5V
Iol = 1.5 mA
5V
Iol = 2 mA
VoH
Output HIGH Voltage
1.8V
Ioh = -0.1mA
2.5V
Ioh = -0.4mA
5V
Ioh = -2mA
Vih
Input HIGH Voltage
Vil
Input LOW Voltage
Ili
Input Leakage Current
Vin = 0V to Vcc
Ilo
Output Leakage Current
Vout = 0V to Vcc, CS = Vcc
Min.
—
—
—
—
Max.
1.0
3.0
5.0
1.0
Unit
mA
mA
mA
µA
—
2.0
µA
—
3.0
µA
—
0.2
—
0.4
—
0.4
0.8 x Vcc
—
0.8 x Vcc
—
0.8 x Vcc
—
0.7x Vcc Vcc + 1
-0.3
0.3 x Vcc
-2
2
-2
2
V
V
V
V
V
V
V
V
µA
µA
Note:
1. The parameters are characterized but not 100% tested.
8
Integrated Silicon Solution, Inc.
Preliminary Information Rev. 00A
08/25/09
IS25C08B
AC Characteristics - Industrial
Ta = –40°C to +85°C Supply voltage = 1.8V to 5.5V
Symbol
Parameter1
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fSCK
SCK Clock Frequency
0
5
0
10
0
20
MHz
tRI
Input Rise Time
—
1
—
1
—
1
μs
tFI
Input Fall Time
—
1
—
1
—
1
μs
tWH
SCK High Time
80
—
40
—
20
—
ns
tWL
SCK Low Time
80
—
40
—
20
—
ns
tCS
CS High Time
100
—
50
—
25
—
ns
tCSS
CS Setup Time
100
—
50
—
25
—
ns
tCSH
CS Hold Time
100
—
50
—
25
—
ns
tSU
Data In Setup Time
20
—
10
—
5
—
ns
tH
Data In Hold Time
20
—
10
—
5
—
ns
tHD
HOLD Setup Time
20
—
10
—
5
—
ns
tCD
HOLD Hold Time
20
—
10
—
5
—
ns
tV
Output Valid
0
80
0
40
0
20
ns
tHO
Output Hold Time
0
—
0
—
0
—
ns
tLZ
HOLD to Output Low Z
0
100
0
50
0
25
ns
tHZ (ori)
HOLD to Output High Z
—
200
—
80
—
40
ns
tDIS
Output Disable Time
—
200
—
80
—
40
ns
tWC
Write Cycle Time
—
5
—
5
—
5
ms
Note:
1. The parameters are characterized but not 100% tested.
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
Rev. 00A
9
IS25C08B
TIMING DIAGRAMS
Figure 1. Synchronous Data Timing
CS
tCS
VIH
VIL
tCSH
tCSS
SK
VIH
VIL
DIN
VIH
VIL
DOUT
VOH
VOL
tWH
tSU
tWL
tH
VALID IN
tV
HIGH-Z
tHO
tDIS
HIGH-Z
Figure 2. WREN Timing
CS
SK
DIN
DOUT
WREN OP-CODE
HIGH-Z
Figure 3. WRDI Timing
CS
SK
DIN
DOUT
10
WRDI OP-CODE
HIGH-Z
Integrated Silicon Solution, Inc.
Preliminary Information Rev. 00A
08/25/09
IS25C08B
Figure 4. RDSR Timing
CS
SK
Din
Instruction
DATA OUT
7 6 5 4 3 2 1 0
Dout
Figure 5. WRSR Timing
CS
SK
Din
Instruction
DATA IN
7 6 5 4 3 2 1 0
Dout
Figure 6. READ Timing
CS
SK
Instruction
Din
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA OUT
7 6 5 4 3 2 1 0
Dout
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
BYTE Address
Rev. 00A
11
IS25C08B
Figure 7. WRITE Timing
CS
SK
Instruction
BYTE Address
Din
DATA IN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Dout
Figure 8. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
DOUT
12
tLZ
Integrated Silicon Solution, Inc.
Preliminary Information Rev. 00A
08/25/09
IS25C08B
ORDERING INFORMATION
Industrial Range: -40°C to +85°C, Lead-free
Voltage
Range
1.8V
to 5.5V
Part Number*
IS25C08B-2GLI-TR
IS25C08B-2ZLI-TR
IS25C08B-2UDLI-TR
IS25C08B-2CLI-TR
Package* (8-pin)
150-mil SOIC (JEDEC)
3 x 4.4 mm TSSOP
2 x 3 x 0.55 mm Ultra DFN
CSP
*
1. Contact ISSI Sales Representatives for availability and other package information.
2. The listed part numbers are packed in tape and reel “-TR” (4K per reel). UDFN/DFN is 5K per reel.
3. For tube/bulk packaging, remove “-TR” at the end of the P/N.
4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable.
5. ISSI offers Industrial grade for Commercial applications (0oC to +70oC).
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
Rev. 00A
13
IS25C08B
14
Integrated Silicon Solution, Inc.
Preliminary Information Rev. 00A
08/25/09
IS25C08B
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
Rev. 00A
15
IS25C08B
16
Integrated Silicon Solution, Inc.
Preliminary Information Rev. 00A
08/25/09
IS25C08B
CSP
180 um
Bottom View
(Ball Side)
Integrated Silicon Solution, Inc.
Preliminary Information
08/25/09
Rev. 00A
17