TI ISO7241CDW Quad digital isolator Datasheet

ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
QUAD DIGITAL ISOLATORS
FEATURES
1
•
•
•
•
•
•
1, 25, and 150-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew;
1 ns Max
– Low Pulse-Width Distortion (PWD);
2 ns Max
– Low Jitter Content; 1 ns Typ at 150 Mbps
Typical 25-Year Life at Rated Working Voltage
(see application note SLLA197 and Figure 15)
4000-Vpeak Isolation, 560-Vpeak Working Voltage
UL 1577 Certified
4 kV ESD Protection
Operate With 3.3-V or 5-V Supplies
•
•
High Electromagnetic Immunity
(see application report SLLA181)
–40°C to 125°C Operating Range
APPLICATIONS
•
•
•
•
Industrial Fieldbus
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
DESCRIPTION
The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations and
output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,
isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging
sensitive circuitry.
The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same
direction and one channel in opposition. The ISO7242 has two channels in each direction.
The A and C option devices have TTL input thresholds and a noise-filter at the input that prevents transient
pulses from being passed to the output of the device. The M option devices have CMOS Vcc/2 input thresholds
and do not have the input noise-filter or the additional propagation delay.
A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh
pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit
drives the output to a logic high state. (Contact TI for a logic low failsafe option).
These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V,
5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage
supply level being used.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
ISO7240
VCC1
GND1
INA
INB
INC
IND
NC
GND1
1
2
3
4
5
6
7
8
ISO7241
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
OUTD
EN
GND2
VCC1
GND1
INA
INB
INC
OUTD
EN1
GND1
1
2
3
4
5
6
7
8
ISO7242
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
IND
EN2
GND2
VCC1
GND1
INA
INB
OUTC
OUTD
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
IND
EN2
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
EN
IN
Input
+
Filter
Data MUX
AC Detect
Vref
OUT
Output Buffer
AC Channel
Table 1. Device Function Table ISO724x
VCC1
PU
(1)
2
VCC2
PU
(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
H or Open
H
L
H or Open
L
X
L
Z
Open
H or Open
H
PD
PU
X
H or Open
H
PD
PU
X
L
Z
PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
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Product Folder Link(s): ISO7240 ISO7241 ISO7242
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
AVAILABLE OPTIONS
(1)
PRODUCT
SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
MARKED
AS
ISO7240ADW
1 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7240CDW
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7240MDW
150 Mbps
Vcc/2 (CMOS)
ISO7240M
ISO7241ADW
1 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7241A
ISO7241CDW
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7241MDW
150 Mbps
Vcc/2 (CMOS)
ISO7241M
ISO7242ADW
1 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7242A
ISO7242CDW
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7242MDW
150 Mbps
Vcc/2 (CMOS)
ISO7240A
4/0
3/1
2/2
ISO7240C
ISO7241C
ISO7242C
ISO7242M
ORDERING
NUMBER (1)
ISO7240ADW (rail)
ISO7240ADWR (reel)
ISO7240CDW (rail)
ISO7240CDWR (reel)
ISO7240MDW (rail)
ISO7240MDWR (reel)
ISO7241ADW (rail)
ISO7241ADWR (reel)
ISO7241CDW (rail)
ISO7241CDWR (reel)
ISO7241MDW (rail)
ISO7241MDWR (reel)
ISO7242ADW (rail)
ISO7242ADWR (reel)
ISO7242CDW (rail)
ISO7242CDWR (reel)
ISO7242MDW (rail)
ISO7242MDWR (reel)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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3
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
ABSOLUTE MAXIMUM RATINGS (1)
(2)
VCC
Supply voltage
VI
Voltage at IN, OUT, EN
, VCC1, VCC2
IO
Output current
ESD
Electrostatic Field-Induced-Charged Device
discharge
Model
TJ
Maximum junction temperature
Human Body Model
JEDEC Standard 22, Test Method A114-C.01
Machine Model
(1)
(2)
JEDEC Standard 22, Test Method C101
VALUE
UNIT
–0.5 to 6
V
–0.5 to 6
V
±15
mA
±4
All pins
kV
±1
ANSI/ESDS5.2-1996
±200
V
170
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage, VCC1, VCC2
IOH
High-level output current
IOL
Low-level output current
tui
1/tui
4.5
5.5
3.15
3.45
Input pulse width
Signaling rate
UNIT
V
mA
–4
mA
ISO724xA
1
µs
ISO724xC
40
ISO724xM
6.67
5
ISO724xA
0
1500 (1)
1000
ISO724xC
0
30 (1)
25
ISO724xM
0
200 (1)
150
High-level input voltage (IN)
VIL
Low-level input voltage (IN)
VIH
High-level input voltage (IN) (EN on all devices)
VIL
Low-level input voltage (IN) (EN on all devices)
TJ
Junction temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
certification
4
MAX
4
VIH
(1)
TYP
ISO724xM
ISO724xA, ISO724xC
ns
kbps
Mbps
0.7 VCC
VCC
V
0
0.3 VCC
V
2
VCC
V
0
0.8
V
150
°C
1000
A/m
Typical value at room temperature and well-regulated power supply.
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ISO7240
ISO7241
ISO7242
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SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
3
UNIT
SUPPLY CURRENT
ISO7240A/C/M
ICC1
ICC2
Quiescent
ISO7240A
1 Mbps
ISO7240C/M
25 Mbps
ISO7241A/C/M
Quiescent
ISO7241A
1 Mbps
ISO7241C/M
25 Mbps
ISO7242A/C/M
Quiescent
ISO7242A
1 Mbps
ISO7242C/M
25 Mbps
ISO7240A/C/M
Quiescent
ISO7240A
1 Mbps
ISO7240C/M
25 Mbps
ISO7241A/C/M
Quiescent
ISO7241A
1 Mbps
ISO7241C/M
25 Mbps
ISO7242A/C/M
Quiescent
ISO7242A
1 Mbps
ISO7242C/M
25 Mbps
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
1
3
7
10.5
6.5
10
6.5
10
12
18
10
16
10
16
15
24
15
22
16
22
17
25
13
20
13
20
18
28
10
16
10
16
15
24
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at VCC, Single channel
VCC – 0.8
IOH = –20 µA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
µA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
150
IN from 0 V to VCC
mV
10
–10
25
Product Folder Link(s): ISO7240 ISO7241 ISO7242
µA
2
pF
50
kV/µs
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V
5
ISO7240
ISO7241
ISO7242
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SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
(1)
MAX
10
18
See Figure 1
42
ISO724xM
23
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
tjit(pp)
Peak-to-peak eye-pattern jitter
150 Mbps NRZ data input, Same
polarity input on all channels, See
Figure 5
6
1
ISO724xA/C
2
2
ISO724xM
0
ns
ns
2
See Figure 2
ns
1
2
See Figure 1
ISO724xM
ns
2.5
10
Pulse-width distortion
(2)
UNIT
95
PWD
(1)
(2)
|tPHL – tPLH|
TYP
40
ISO724xA
ISO724xC
MIN
ns
12
µs
1
ns
Also referred to as pulse skew.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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Product Folder Link(s): ISO7240 ISO7241 ISO7242
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS
VCC1 at 5-V, VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
3
UNIT
SUPPLY CURRENT
ICC1
ICC2
ISO7240A/C/M
Quiescent
ISO7240A
1 Mbps
ISO7240C/M
25 Mbps
ISO7241A/C/M
Quiescent
ISO7241A
1 Mbps
ISO7241C/M
25 Mbps
ISO7242A/C/M
Quiescent
ISO7242A
1 Mbps
ISO7242C/M
25 Mbps
ISO7240A/C/M
Quiescent
ISO7240A
1 Mbps
ISO7240C/M
25 Mbps
ISO7241A/C/M
Quiescent
ISO7241A
1 Mbps
ISO7241C/M
25 Mbps
ISO7242A/C/M
Quiescent
ISO7242A
1 Mbps
ISO7242C/M
25 Mbps
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
1
3
7
10.5
6.5
10
6.5
10
12
18
10
16
10
16
15
24
9.5
15
10
15
10.5
17
8
13
8
13
11.5
18
6
10
6
10
9
14
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
VOH
Sleep mode output current
High-level output voltage
EN at VCC, Single channel
IOH = –4 mA, See Figure 1
µA
0
ISO7240
VCC – 0.4
ISO724x
(5-V side)
VCC – 0.8
IOH = –20 µA, See Figure 1
V
VCC – 0.1
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
CMTI
Common-mode transient immunity VI = VCC or 0 V, See Figure 4
150
IN from 0 V to VCC
mV
10
–10
IN at VCC, VI = 0.4 sin (4E6πt)
25
Product Folder Link(s): ISO7240 ISO7241 ISO7242
µA
2
pF
50
kV/µs
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V
7
ISO7240
ISO7241
ISO7242
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SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
SWITCHING CHARACTERISTICS
VCC1 at 5-V, VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
40
100
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
tjit(pp)
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input,
Same polarity input on all
channels, See Figure 5
(1)
(2)
8
ISO724xA
ISO724xC
11
See Figure 1
50
12
29
1
ISO724xA/C
2
3
ISO724xM
0
ns
ns
2
See Figure 2
ns
1
2
See Figure 1
ISO724xM
ns
3
ISO724xM
(2)
20
UNIT
ns
18
µs
1
ns
Also known as pulse skew
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS
VCC1 at 3.3-V, VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
1
2
3
5
4
7
UNIT
SUPPLY CURRENT
ICC1
ICC2
ISO7240A/C/M
Quiescent
ISO7240A
1 Mbps
ISO7240C/M
25 Mbps
ISO7241A/C/M
Quiescent
ISO7241A
1 Mbps
ISO7241C/M
25 Mbps
ISO7242A/C/M
Quiescent
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
4
7
6.5
11
6
10
6
10
9
14
15
22
16
22
ISO7242A
1 Mbps
ISO7242C/M
25 Mbps
ISO7240A/C/M
Quiescent
ISO7240A
1 Mbps
ISO7240C/M
25 Mbps
17
25
ISO7241A/C/M
Quiescent
13
20
ISO7241A
1 Mbps
13
20
ISO7241C/M
25 Mbps
18
28
ISO7242A/C/M
Quiescent
10
16
ISO7242A
1 Mbps
10
16
ISO7242C/M
25 Mbps
15
24
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
VOH
Sleep mode output current
High-level output voltage
EN at VCC, Single channel
IOH = –4 mA, See Figure 1
µA
0
ISO7240
VCC – 0.4
ISO724x
(5-V side)
VCC – 0.8
IOH = –20 µA, See Figure 1
V
VCC – 0.1
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
150
IN from 0 V to VCC
mV
10
–10
25
Product Folder Link(s): ISO7240 ISO7241 ISO7242
µA
2
pF
50
kV/µs
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9
ISO7240
ISO7241
ISO7242
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SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
SWITCHING CHARACTERISTICS
VCC1 at 3.3-V and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
Peak-to-peak eye-pattern jitter
150 Mbps NRZ data input, Same polarity
input on all channels, See Figure 5
tjit(pp)
(1)
(2)
10
(2)
40
MAX
tPLH, tPHL
ISO724xA
ISO724xC
11
22
51
12
30
See Figure 1
ns
3
ISO724xM
1
ISO724xA/C
2
2.5
ISO724xM
0
1
2
See Figure 1
ISO724xM
UNIT
100
ns
ns
2
See Figure 2
ns
ns
12
µs
1
ns
Also known as pulse skew
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Submit Documentation Feedback
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Product Folder Link(s): ISO7240 ISO7241 ISO7242
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
1
2
3
5
4
7
UNIT
SUPPLY CURRENT
ICC1
ICC2
ISO7240A/C/M
Quiescent
ISO7240A
1 Mbps
ISO7240C/M
25 Mbps
ISO7241A/C/M
Quiescent
ISO7241A
1 Mbps
ISO7241C/M
25 Mbps
ISO7242A/C/M
Quiescent
ISO7242A
1 Mbps
ISO7242C/M
25 Mbps
ISO7240A/C/M
Quiescent
ISO7240A
1 Mbps
ISO7240C/M
25 Mbps
ISO7241A/C/M
Quiescent
ISO7241A
1 Mbps
ISO7241C/M
25 Mbps
ISO7242A/C/M
Quiescent
ISO7242A
1 Mbps
ISO7242C/M
25 Mbps
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
4
7
6.5
11
6
10
6
10
9
14
9.5
15
10
15
10.5
17
8
13
8
13
11.5
18
6
10
6
10
9
14
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at VCC, single channel
VCC – 0.4
IOH = –20 µA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
µA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
150
IN from 0 V or VCC
mV
10
–10
25
Product Folder Link(s): ISO7240 ISO7241 ISO7242
µA
2
pF
50
kV/µs
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V
11
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input, same
polarity input on all channels, See Figure 5
tjit(pp)
(1)
(2)
12
(2)
45
MAX
tPLH, tPHL
ISO724xA
ISO724xC
12
See Figure 1
25
56
12
34
ns
4
ISO724xM
1
ISO724xA/C
2
3.5
ISO724xM
0
1
ns
ns
2
See Figure 1
ISO724xM
UNIT
110
2
See Figure 2
ns
18
µs
1
ns
Also referred to as pulse skew.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
VI
50 W
NOTE A
VCC1
VI
VCC1/2
VCC1/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
Vcc
ISOLATION BARRIER
0V
RL = 1 kW ±1%
IN
Input
Generator
VI
OUT
EN
Vcc/2
VI
t PZL
VO
VO
CL
Vcc/2
0V
t PLZ
Vcc
0.5 V
50%
NOTE
B
50 W
VOL
3V
ISOLATION BARRIER
NOTE A
IN
Input
Generator
VI
Vcc
OUT
VO
Vcc/2
VI
Vcc/2
0V
EN
50 W
t PZH
CL
NOTE
B
RL = 1 kW ±1%
VO
VOH
50%
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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13
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VI
0V
or
VCC1
ISOLATION BARRIER
VCC1
IN
VCC1
VI
OUT
2.7 V
VO
0V
VOH
tfs
CL
NOTE B
VO
50%
VOL
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCC1
VCC2
ISOLATION BARRIER
C = 0.1 mF± 1%
IN
S1
GND1
C = 0.1 mF± 1%
OUT
NOTE B
Pass-fail criteria:
Output must
remain stable
VOH or VOL
GND2
VCM
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
VCC1
DUT
Tektronix
HFS9009
IN
OUT
0V
Tektronix
784D
PATTERN
GENERATOR
VCC/2
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 5. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
14
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ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
L(I01)
Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
7.7
mm
L(I02)
Minimum external tracking (Creepage)
Shortest terminal-to-terminal distance across the
package surface
8.1
mm
0.008
mm
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device
CIO
Barrier capacitance Input to output
CI
Input capacitance to ground
>1012
Ω
VI = 0.4 sin (4E6πt)
2
pF
VI = 0.4 sin (4E6πt)
2
pF
DEVICE I/O SCHEMATICS
Enable
VCC
Output
Input
VCC
VCC
VCC
VCC
VCC
1 MW
500 W
EN
IN
8W
500 W
OUT
13 W
1 MW
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15
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC
60747-5-2
Approved under CSA Component
Acceptance Notice
Recognized under 1577
Component Recognition
Program (1)
File Number: Pending
File Number: Pending
File Number: E181974
(1)
Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Low-K Thermal Resistance (1)
168
High-K Thermal Resistance
96.1
UNIT
θJA
Junction-to-air
θJB
Junction-to-Board Thermal Resistance
61
°C/W
θJC
Junction-to-Case Thermal Resistance
48
°C/W
PD
(1)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
Device Power Dissipation
°C/W
220
mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
TYPICAL CHARACTERISTIC CURVES
ISO7240C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
ISO7241C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
45
45
TA = 25°C,
Load = 15 pF,
All Channels
40
ICC - Supply Current - mA/RMS
ICC - Supply Current - mA/RMS
40
35
5-V ICC2
30
3.3-V ICC2
25
20
5-V ICC1
15
10
5
0
25
50
75
100
Signaling Rate - Mbps
125
35
5-V ICC2
30
5-V ICC1
25
20
3.3-V ICC2
15
3.3-V ICC1
10
5
3.3-V ICC1
0
TA = 25°C,
Load = 15 pF,
All Channels
150
0
0
25
Figure 6.
16
50
75
100
125
150
Signaling Rate - Mbps
Figure 7.
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ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
TYPICAL CHARACTERISTIC CURVES (continued)
ISO7242C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
45
45
40
C 3.3-V tpLH, tpHL
35
35
30
Propagation Delay - ns
ICC - Supply Current - mA/RMS
40
TA = 25°C,
Load = 15 pF,
All Channels
5-V ICC1,ICC2
25
20
15
3.3-V ICC1,ICC2
25
M 3.3-V tpLH, tpHL
20
15
M 5-V tpLH, tpHL
10
10
5
5
0
0
TA = 25°C,
Load = 15 pF,
All Channels
0
25
50
75
100
125
150
Signaling Rate - Mbps
80
65
35
20
50
TA - Free-Air Temperature - °C
Figure 8.
Figure 9.
INPUT VOLTAGE THRESHOLD
vs
FREE-AIR TEMPERATURE
VCC1 FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
-40
1.4
-25
-10
5
95
110
125
95
110
125
3
5 V Vth+
1.3
2.9
VCC1 - Failsafe Threshold - V
1.35
Input Voltage Threshold - V
C 5-V tpLH, tpHL
30
3.3 V Vth+
1.25
1.2
Air Flow at 7 cf/m,
Low_K Board
1.15
5 V Vth1.1
2.8
VCC at 5 V or 3.3 V,
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
2.7
Vfs+
2.6
2.5
Vfs-
2.4
2.3
2.2
1.05
1
-40
3.3 V Vth-25
-10
2.1
5
20
35
50
65
80
TA - Free-Air Temperature - °C
95
110
125
2
-40
-25
-10
Figure 10.
5
20
35
50
65
80
TA - Free-Air Temperature - °C
Figure 11.
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ISO7240
ISO7241
ISO7242
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SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
TYPICAL CHARACTERISTIC CURVES (continued)
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
50
Load = 15 pF,
TA = 25°C
VCC = 5 V
40
IO - Output Current - mA
40
IO - Output Current - mA
Load = 15 pF,
TA = 25°C
45
VCC = 3.3 V
30
20
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
10
5
0
0
0
2
4
VO - Output Voltage - V
6
0
1
Figure 12.
18
2
3
VO - Output Voltage - V
4
5
Figure 13.
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ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007
APPLICATION INFORMATION
VCC1
20 mm
Max From
20 mm
Max From
VCC1
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUTA
IN B
4
13
OUTB
IN C
5
12
OUTC
IN D
6
11
OUTD
7
10
8
9
GND1
NC
GND1
ISO7240x
GND2
EN
GND2
Figure 14. Typical ISO724x Application Circuit
LIFE EXPECTANCY vs. WORKING VOLTAGE
WORKING LIFE -- YEARS
100
VIORM at 560-V
28 Years
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (VIORM) -- V
Figure 15. Time-Dependant Dielectric Breakdown Testing Results
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19
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2007
PACKAGING INFORMATION
(1)
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ISO7240ADW
ACTIVE
SOIC
DW
16
49
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240ADWG4
ACTIVE
SOIC
DW
16
49
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240ADWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240ADWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240CDW
ACTIVE
SOIC
DW
16
49
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240CDWG4
ACTIVE
SOIC
DW
16
49
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240CDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240CDWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240MDW
ACTIVE
SOIC
DW
16
49
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240MDWG4
ACTIVE
SOIC
DW
16
49
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240MDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7240MDWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7241ADW
ACTIVE
SOIC
DW
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7241ADWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7241CDW
ACTIVE
SOIC
DW
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7241CDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7241MDW
ACTIVE
SOIC
DW
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7241MDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7242ADW
ACTIVE
SOIC
DW
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7242ADWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7242CDW
ACTIVE
SOIC
DW
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7242CDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7242MDW
ACTIVE
SOIC
DW
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7242MDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
49
49
49
49
49
49
The marketing status values are defined as follows:
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7240ADWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
ISO7240CDWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
ISO7240MDWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
ISO7241ADWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
ISO7241CDWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
ISO7241MDWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
ISO7242ADWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
ISO7242CDWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
ISO7242MDWR
DW
16
SITE 35
330
16
10.9
10.78
3.0
12
16
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
ISO7240ADWR
DW
16
SITE 35
406.0
348.0
63.0
ISO7240CDWR
DW
16
SITE 35
406.0
348.0
63.0
ISO7240MDWR
DW
16
SITE 35
406.0
348.0
63.0
ISO7241ADWR
DW
16
SITE 35
406.0
348.0
63.0
ISO7241CDWR
DW
16
SITE 35
406.0
348.0
63.0
ISO7241MDWR
DW
16
SITE 35
406.0
348.0
63.0
ISO7242ADWR
DW
16
SITE 35
406.0
348.0
63.0
ISO7242CDWR
DW
16
SITE 35
406.0
348.0
63.0
ISO7242MDWR
DW
16
SITE 35
406.0
348.0
63.0
Pack Materials-Page 2
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